Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
| 2 | * |
| 3 | * This driver supports the memory controllers found on the Intel |
| 4 | * processor family Sandy Bridge. |
| 5 | * |
| 6 | * This file may be distributed under the terms of the |
| 7 | * GNU General Public License version 2 only. |
| 8 | * |
| 9 | * Copyright (c) 2011 by: |
| 10 | * Mauro Carvalho Chehab <mchehab@redhat.com> |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/pci_ids.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/edac.h> |
| 20 | #include <linux/mmzone.h> |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 21 | #include <linux/smp.h> |
| 22 | #include <linux/bitmap.h> |
| 23 | #include <asm/processor.h> |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 24 | #include <asm/mce.h> |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 25 | |
| 26 | #include "edac_core.h" |
| 27 | |
| 28 | /* Static vars */ |
| 29 | static LIST_HEAD(sbridge_edac_list); |
| 30 | static DEFINE_MUTEX(sbridge_edac_lock); |
| 31 | static int probed; |
| 32 | |
| 33 | /* |
| 34 | * Alter this version for the module when modifications are made |
| 35 | */ |
| 36 | #define SBRIDGE_REVISION " Ver: 1.0.0 " |
| 37 | #define EDAC_MOD_STR "sbridge_edac" |
| 38 | |
| 39 | /* |
| 40 | * Debug macros |
| 41 | */ |
| 42 | #define sbridge_printk(level, fmt, arg...) \ |
| 43 | edac_printk(level, "sbridge", fmt, ##arg) |
| 44 | |
| 45 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ |
| 46 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) |
| 47 | |
| 48 | /* |
| 49 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> |
| 50 | */ |
| 51 | #define GET_BITFIELD(v, lo, hi) \ |
| 52 | (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo)) |
| 53 | |
| 54 | /* |
| 55 | * sbridge Memory Controller Registers |
| 56 | */ |
| 57 | |
| 58 | /* |
| 59 | * FIXME: For now, let's order by device function, as it makes |
| 60 | * easier for driver's development proccess. This table should be |
| 61 | * moved to pci_id.h when submitted upstream |
| 62 | */ |
| 63 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */ |
| 64 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */ |
| 65 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */ |
| 66 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */ |
| 67 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */ |
| 68 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */ |
| 69 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */ |
| 70 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */ |
| 71 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */ |
| 72 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */ |
| 73 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */ |
| 74 | |
| 75 | /* |
| 76 | * Currently, unused, but will be needed in the future |
| 77 | * implementations, as they hold the error counters |
| 78 | */ |
| 79 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */ |
| 80 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */ |
| 81 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */ |
| 82 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */ |
| 83 | |
| 84 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
| 85 | static const u32 dram_rule[] = { |
| 86 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
| 87 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, |
| 88 | }; |
| 89 | #define MAX_SAD ARRAY_SIZE(dram_rule) |
| 90 | |
| 91 | #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) |
| 92 | #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) |
| 93 | #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) |
| 94 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) |
| 95 | |
| 96 | static char *get_dram_attr(u32 reg) |
| 97 | { |
| 98 | switch(DRAM_ATTR(reg)) { |
| 99 | case 0: |
| 100 | return "DRAM"; |
| 101 | case 1: |
| 102 | return "MMCFG"; |
| 103 | case 2: |
| 104 | return "NXM"; |
| 105 | default: |
| 106 | return "unknown"; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | static const u32 interleave_list[] = { |
| 111 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
| 112 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, |
| 113 | }; |
| 114 | #define MAX_INTERLEAVE ARRAY_SIZE(interleave_list) |
| 115 | |
| 116 | #define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2) |
| 117 | #define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5) |
| 118 | #define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10) |
| 119 | #define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13) |
| 120 | #define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18) |
| 121 | #define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21) |
| 122 | #define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26) |
| 123 | #define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29) |
| 124 | |
| 125 | static inline int sad_pkg(u32 reg, int interleave) |
| 126 | { |
| 127 | switch (interleave) { |
| 128 | case 0: |
| 129 | return SAD_PKG0(reg); |
| 130 | case 1: |
| 131 | return SAD_PKG1(reg); |
| 132 | case 2: |
| 133 | return SAD_PKG2(reg); |
| 134 | case 3: |
| 135 | return SAD_PKG3(reg); |
| 136 | case 4: |
| 137 | return SAD_PKG4(reg); |
| 138 | case 5: |
| 139 | return SAD_PKG5(reg); |
| 140 | case 6: |
| 141 | return SAD_PKG6(reg); |
| 142 | case 7: |
| 143 | return SAD_PKG7(reg); |
| 144 | default: |
| 145 | return -EINVAL; |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | /* Devices 12 Function 7 */ |
| 150 | |
| 151 | #define TOLM 0x80 |
| 152 | #define TOHM 0x84 |
| 153 | |
| 154 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) |
| 155 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) |
| 156 | |
| 157 | /* Device 13 Function 6 */ |
| 158 | |
| 159 | #define SAD_TARGET 0xf0 |
| 160 | |
| 161 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) |
| 162 | |
| 163 | #define SAD_CONTROL 0xf4 |
| 164 | |
| 165 | #define NODE_ID(reg) GET_BITFIELD(reg, 0, 2) |
| 166 | |
| 167 | /* Device 14 function 0 */ |
| 168 | |
| 169 | static const u32 tad_dram_rule[] = { |
| 170 | 0x40, 0x44, 0x48, 0x4c, |
| 171 | 0x50, 0x54, 0x58, 0x5c, |
| 172 | 0x60, 0x64, 0x68, 0x6c, |
| 173 | }; |
| 174 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) |
| 175 | |
| 176 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) |
| 177 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) |
| 178 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) |
| 179 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) |
| 180 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) |
| 181 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) |
| 182 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) |
| 183 | |
| 184 | /* Device 15, function 0 */ |
| 185 | |
| 186 | #define MCMTR 0x7c |
| 187 | |
| 188 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) |
| 189 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) |
| 190 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) |
| 191 | |
| 192 | /* Device 15, function 1 */ |
| 193 | |
| 194 | #define RASENABLES 0xac |
| 195 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) |
| 196 | |
| 197 | /* Device 15, functions 2-5 */ |
| 198 | |
| 199 | static const int mtr_regs[] = { |
| 200 | 0x80, 0x84, 0x88, |
| 201 | }; |
| 202 | |
| 203 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) |
| 204 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) |
| 205 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) |
| 206 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) |
| 207 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) |
| 208 | |
| 209 | static const u32 tad_ch_nilv_offset[] = { |
| 210 | 0x90, 0x94, 0x98, 0x9c, |
| 211 | 0xa0, 0xa4, 0xa8, 0xac, |
| 212 | 0xb0, 0xb4, 0xb8, 0xbc, |
| 213 | }; |
| 214 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) |
| 215 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) |
| 216 | |
| 217 | static const u32 rir_way_limit[] = { |
| 218 | 0x108, 0x10c, 0x110, 0x114, 0x118, |
| 219 | }; |
| 220 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) |
| 221 | |
| 222 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) |
| 223 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) |
| 224 | #define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff) |
| 225 | |
| 226 | #define MAX_RIR_WAY 8 |
| 227 | |
| 228 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { |
| 229 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, |
| 230 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, |
| 231 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, |
| 232 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, |
| 233 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, |
| 234 | }; |
| 235 | |
| 236 | #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) |
| 237 | #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) |
| 238 | |
| 239 | /* Device 16, functions 2-7 */ |
| 240 | |
| 241 | /* |
| 242 | * FIXME: Implement the error count reads directly |
| 243 | */ |
| 244 | |
| 245 | static const u32 correrrcnt[] = { |
| 246 | 0x104, 0x108, 0x10c, 0x110, |
| 247 | }; |
| 248 | |
| 249 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) |
| 250 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) |
| 251 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) |
| 252 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) |
| 253 | |
| 254 | static const u32 correrrthrsld[] = { |
| 255 | 0x11c, 0x120, 0x124, 0x128, |
| 256 | }; |
| 257 | |
| 258 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) |
| 259 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) |
| 260 | |
| 261 | |
| 262 | /* Device 17, function 0 */ |
| 263 | |
| 264 | #define RANK_CFG_A 0x0328 |
| 265 | |
| 266 | #define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11) |
| 267 | |
| 268 | /* |
| 269 | * sbridge structs |
| 270 | */ |
| 271 | |
| 272 | #define NUM_CHANNELS 4 |
| 273 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
| 274 | |
| 275 | struct sbridge_info { |
| 276 | u32 mcmtr; |
| 277 | }; |
| 278 | |
| 279 | struct sbridge_channel { |
| 280 | u32 ranks; |
| 281 | u32 dimms; |
| 282 | }; |
| 283 | |
| 284 | struct pci_id_descr { |
| 285 | int dev; |
| 286 | int func; |
| 287 | int dev_id; |
| 288 | int optional; |
| 289 | }; |
| 290 | |
| 291 | struct pci_id_table { |
| 292 | const struct pci_id_descr *descr; |
| 293 | int n_devs; |
| 294 | }; |
| 295 | |
| 296 | struct sbridge_dev { |
| 297 | struct list_head list; |
| 298 | u8 bus, mc; |
| 299 | u8 node_id, source_id; |
| 300 | struct pci_dev **pdev; |
| 301 | int n_devs; |
| 302 | struct mem_ctl_info *mci; |
| 303 | }; |
| 304 | |
| 305 | struct sbridge_pvt { |
| 306 | struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; |
| 307 | struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0; |
| 308 | struct pci_dev *pci_br; |
| 309 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
| 310 | |
| 311 | struct sbridge_dev *sbridge_dev; |
| 312 | |
| 313 | struct sbridge_info info; |
| 314 | struct sbridge_channel channel[NUM_CHANNELS]; |
| 315 | |
| 316 | int csrow_map[NUM_CHANNELS][MAX_DIMMS]; |
| 317 | |
| 318 | /* Memory type detection */ |
| 319 | bool is_mirrored, is_lockstep, is_close_pg; |
| 320 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 321 | /* Fifo double buffers */ |
| 322 | struct mce mce_entry[MCE_LOG_LEN]; |
| 323 | struct mce mce_outentry[MCE_LOG_LEN]; |
| 324 | |
| 325 | /* Fifo in/out counters */ |
| 326 | unsigned mce_in, mce_out; |
| 327 | |
| 328 | /* Count indicator to show errors not got */ |
| 329 | unsigned mce_overrun; |
| 330 | |
| 331 | /* Memory description */ |
| 332 | u64 tolm, tohm; |
| 333 | }; |
| 334 | |
| 335 | #define PCI_DESCR(device, function, device_id) \ |
| 336 | .dev = (device), \ |
| 337 | .func = (function), \ |
| 338 | .dev_id = (device_id) |
| 339 | |
| 340 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { |
| 341 | /* Processor Home Agent */ |
| 342 | { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) }, |
| 343 | |
| 344 | /* Memory controller */ |
| 345 | { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) }, |
| 346 | { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) }, |
| 347 | { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) }, |
| 348 | { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) }, |
| 349 | { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) }, |
| 350 | { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) }, |
| 351 | { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) }, |
| 352 | |
| 353 | /* System Address Decoder */ |
| 354 | { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) }, |
| 355 | { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) }, |
| 356 | |
| 357 | /* Broadcast Registers */ |
| 358 | { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) }, |
| 359 | }; |
| 360 | |
| 361 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } |
| 362 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { |
| 363 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), |
| 364 | {0,} /* 0 terminated list. */ |
| 365 | }; |
| 366 | |
| 367 | /* |
| 368 | * pci_device_id table for which devices we are looking for |
| 369 | */ |
| 370 | static const struct pci_device_id sbridge_pci_tbl[] __devinitdata = { |
| 371 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)}, |
| 372 | {0,} /* 0 terminated list. */ |
| 373 | }; |
| 374 | |
| 375 | |
| 376 | /**************************************************************************** |
| 377 | Anciliary status routines |
| 378 | ****************************************************************************/ |
| 379 | |
| 380 | static inline int numrank(u32 mtr) |
| 381 | { |
| 382 | int ranks = (1 << RANK_CNT_BITS(mtr)); |
| 383 | |
| 384 | if (ranks > 4) { |
| 385 | debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)", |
| 386 | ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr); |
| 387 | return -EINVAL; |
| 388 | } |
| 389 | |
| 390 | return ranks; |
| 391 | } |
| 392 | |
| 393 | static inline int numrow(u32 mtr) |
| 394 | { |
| 395 | int rows = (RANK_WIDTH_BITS(mtr) + 12); |
| 396 | |
| 397 | if (rows < 13 || rows > 18) { |
| 398 | debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)", |
| 399 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); |
| 400 | return -EINVAL; |
| 401 | } |
| 402 | |
| 403 | return 1 << rows; |
| 404 | } |
| 405 | |
| 406 | static inline int numcol(u32 mtr) |
| 407 | { |
| 408 | int cols = (COL_WIDTH_BITS(mtr) + 10); |
| 409 | |
| 410 | if (cols > 12) { |
| 411 | debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)", |
| 412 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); |
| 413 | return -EINVAL; |
| 414 | } |
| 415 | |
| 416 | return 1 << cols; |
| 417 | } |
| 418 | |
| 419 | static struct sbridge_dev *get_sbridge_dev(u8 bus) |
| 420 | { |
| 421 | struct sbridge_dev *sbridge_dev; |
| 422 | |
| 423 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
| 424 | if (sbridge_dev->bus == bus) |
| 425 | return sbridge_dev; |
| 426 | } |
| 427 | |
| 428 | return NULL; |
| 429 | } |
| 430 | |
| 431 | static struct sbridge_dev *alloc_sbridge_dev(u8 bus, |
| 432 | const struct pci_id_table *table) |
| 433 | { |
| 434 | struct sbridge_dev *sbridge_dev; |
| 435 | |
| 436 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); |
| 437 | if (!sbridge_dev) |
| 438 | return NULL; |
| 439 | |
| 440 | sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, |
| 441 | GFP_KERNEL); |
| 442 | if (!sbridge_dev->pdev) { |
| 443 | kfree(sbridge_dev); |
| 444 | return NULL; |
| 445 | } |
| 446 | |
| 447 | sbridge_dev->bus = bus; |
| 448 | sbridge_dev->n_devs = table->n_devs; |
| 449 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); |
| 450 | |
| 451 | return sbridge_dev; |
| 452 | } |
| 453 | |
| 454 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) |
| 455 | { |
| 456 | list_del(&sbridge_dev->list); |
| 457 | kfree(sbridge_dev->pdev); |
| 458 | kfree(sbridge_dev); |
| 459 | } |
| 460 | |
| 461 | /**************************************************************************** |
| 462 | Memory check routines |
| 463 | ****************************************************************************/ |
| 464 | static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot, |
| 465 | unsigned func) |
| 466 | { |
| 467 | struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus); |
| 468 | int i; |
| 469 | |
| 470 | if (!sbridge_dev) |
| 471 | return NULL; |
| 472 | |
| 473 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 474 | if (!sbridge_dev->pdev[i]) |
| 475 | continue; |
| 476 | |
| 477 | if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot && |
| 478 | PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) { |
| 479 | debugf1("Associated %02x.%02x.%d with %p\n", |
| 480 | bus, slot, func, sbridge_dev->pdev[i]); |
| 481 | return sbridge_dev->pdev[i]; |
| 482 | } |
| 483 | } |
| 484 | |
| 485 | return NULL; |
| 486 | } |
| 487 | |
| 488 | /** |
| 489 | * sbridge_get_active_channels() - gets the number of channels and csrows |
| 490 | * bus: Device bus |
| 491 | * @channels: Number of channels that will be returned |
| 492 | * @csrows: Number of csrows found |
| 493 | * |
| 494 | * Since EDAC core needs to know in advance the number of available channels |
| 495 | * and csrows, in order to allocate memory for csrows/channels, it is needed |
| 496 | * to run two similar steps. At the first step, implemented on this function, |
| 497 | * it checks the number of csrows/channels present at one socket, identified |
| 498 | * by the associated PCI bus. |
| 499 | * this is used in order to properly allocate the size of mci components. |
| 500 | * Note: one csrow is one dimm. |
| 501 | */ |
| 502 | static int sbridge_get_active_channels(const u8 bus, unsigned *channels, |
| 503 | unsigned *csrows) |
| 504 | { |
| 505 | struct pci_dev *pdev = NULL; |
| 506 | int i, j; |
| 507 | u32 mcmtr; |
| 508 | |
| 509 | *channels = 0; |
| 510 | *csrows = 0; |
| 511 | |
| 512 | pdev = get_pdev_slot_func(bus, 15, 0); |
| 513 | if (!pdev) { |
| 514 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " |
| 515 | "%2x.%02d.%d!!!\n", |
| 516 | bus, 15, 0); |
| 517 | return -ENODEV; |
| 518 | } |
| 519 | |
| 520 | pci_read_config_dword(pdev, MCMTR, &mcmtr); |
| 521 | if (!IS_ECC_ENABLED(mcmtr)) { |
| 522 | sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); |
| 523 | return -ENODEV; |
| 524 | } |
| 525 | |
| 526 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 527 | u32 mtr; |
| 528 | |
| 529 | /* Device 15 functions 2 - 5 */ |
| 530 | pdev = get_pdev_slot_func(bus, 15, 2 + i); |
| 531 | if (!pdev) { |
| 532 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " |
| 533 | "%2x.%02d.%d!!!\n", |
| 534 | bus, 15, 2 + i); |
| 535 | return -ENODEV; |
| 536 | } |
| 537 | (*channels)++; |
| 538 | |
| 539 | for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { |
| 540 | pci_read_config_dword(pdev, mtr_regs[j], &mtr); |
| 541 | debugf1("Bus#%02x channel #%d MTR%d = %x\n", bus, i, j, mtr); |
| 542 | if (IS_DIMM_PRESENT(mtr)) |
| 543 | (*csrows)++; |
| 544 | } |
| 545 | } |
| 546 | |
| 547 | debugf0("Number of active channels: %d, number of active dimms: %d\n", |
| 548 | *channels, *csrows); |
| 549 | |
| 550 | return 0; |
| 551 | } |
| 552 | |
| 553 | static int get_dimm_config(const struct mem_ctl_info *mci) |
| 554 | { |
| 555 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 556 | struct csrow_info *csr; |
| 557 | int i, j, banks, ranks, rows, cols, size, npages; |
| 558 | int csrow = 0; |
| 559 | unsigned long last_page = 0; |
| 560 | u32 reg; |
| 561 | enum edac_type mode; |
Mark A. Grondona | c6e13b5 | 2011-10-18 11:02:58 -0200 | [diff] [blame] | 562 | enum mem_type mtype; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 563 | |
| 564 | pci_read_config_dword(pvt->pci_br, SAD_TARGET, ®); |
| 565 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); |
| 566 | |
| 567 | pci_read_config_dword(pvt->pci_br, SAD_CONTROL, ®); |
| 568 | pvt->sbridge_dev->node_id = NODE_ID(reg); |
| 569 | debugf0("mc#%d: Node ID: %d, source ID: %d\n", |
| 570 | pvt->sbridge_dev->mc, |
| 571 | pvt->sbridge_dev->node_id, |
| 572 | pvt->sbridge_dev->source_id); |
| 573 | |
| 574 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); |
| 575 | if (IS_MIRROR_ENABLED(reg)) { |
| 576 | debugf0("Memory mirror is enabled\n"); |
| 577 | pvt->is_mirrored = true; |
| 578 | } else { |
| 579 | debugf0("Memory mirror is disabled\n"); |
| 580 | pvt->is_mirrored = false; |
| 581 | } |
| 582 | |
| 583 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); |
| 584 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { |
| 585 | debugf0("Lockstep is enabled\n"); |
| 586 | mode = EDAC_S8ECD8ED; |
| 587 | pvt->is_lockstep = true; |
| 588 | } else { |
| 589 | debugf0("Lockstep is disabled\n"); |
| 590 | mode = EDAC_S4ECD4ED; |
| 591 | pvt->is_lockstep = false; |
| 592 | } |
| 593 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { |
| 594 | debugf0("address map is on closed page mode\n"); |
| 595 | pvt->is_close_pg = true; |
| 596 | } else { |
| 597 | debugf0("address map is on open page mode\n"); |
| 598 | pvt->is_close_pg = false; |
| 599 | } |
| 600 | |
| 601 | pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, ®); |
| 602 | if (IS_RDIMM_ENABLED(reg)) { |
| 603 | /* FIXME: Can also be LRDIMM */ |
| 604 | debugf0("Memory is registered\n"); |
Mark A. Grondona | c6e13b5 | 2011-10-18 11:02:58 -0200 | [diff] [blame] | 605 | mtype = MEM_RDDR3; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 606 | } else { |
| 607 | debugf0("Memory is unregistered\n"); |
Mark A. Grondona | c6e13b5 | 2011-10-18 11:02:58 -0200 | [diff] [blame] | 608 | mtype = MEM_DDR3; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 609 | } |
| 610 | |
| 611 | /* On all supported DDR3 DIMM types, there are 8 banks available */ |
| 612 | banks = 8; |
| 613 | |
| 614 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 615 | u32 mtr; |
| 616 | |
| 617 | for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { |
| 618 | pci_read_config_dword(pvt->pci_tad[i], |
| 619 | mtr_regs[j], &mtr); |
| 620 | debugf4("Channel #%d MTR%d = %x\n", i, j, mtr); |
| 621 | if (IS_DIMM_PRESENT(mtr)) { |
| 622 | pvt->channel[i].dimms++; |
| 623 | |
| 624 | ranks = numrank(mtr); |
| 625 | rows = numrow(mtr); |
| 626 | cols = numcol(mtr); |
| 627 | |
| 628 | /* DDR3 has 8 I/O banks */ |
| 629 | size = (rows * cols * banks * ranks) >> (20 - 3); |
| 630 | npages = MiB_TO_PAGES(size); |
| 631 | |
| 632 | debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
| 633 | pvt->sbridge_dev->mc, i, j, |
| 634 | size, npages, |
| 635 | banks, ranks, rows, cols); |
| 636 | csr = &mci->csrows[csrow]; |
| 637 | |
| 638 | csr->first_page = last_page; |
| 639 | csr->last_page = last_page + npages - 1; |
| 640 | csr->page_mask = 0UL; /* Unused */ |
| 641 | csr->nr_pages = npages; |
| 642 | csr->grain = 32; |
| 643 | csr->csrow_idx = csrow; |
| 644 | csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4; |
| 645 | csr->ce_count = 0; |
| 646 | csr->ue_count = 0; |
Mark A. Grondona | c6e13b5 | 2011-10-18 11:02:58 -0200 | [diff] [blame] | 647 | csr->mtype = mtype; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 648 | csr->edac_mode = mode; |
| 649 | csr->nr_channels = 1; |
| 650 | csr->channels[0].chan_idx = i; |
| 651 | csr->channels[0].ce_count = 0; |
| 652 | pvt->csrow_map[i][j] = csrow; |
| 653 | snprintf(csr->channels[0].label, |
| 654 | sizeof(csr->channels[0].label), |
| 655 | "CPU_SrcID#%u_Channel#%u_DIMM#%u", |
| 656 | pvt->sbridge_dev->source_id, i, j); |
| 657 | last_page += npages; |
| 658 | csrow++; |
| 659 | } |
| 660 | } |
| 661 | } |
| 662 | |
| 663 | return 0; |
| 664 | } |
| 665 | |
| 666 | static void get_memory_layout(const struct mem_ctl_info *mci) |
| 667 | { |
| 668 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 669 | int i, j, k, n_sads, n_tads, sad_interl; |
| 670 | u32 reg; |
| 671 | u64 limit, prv = 0; |
| 672 | u64 tmp_mb; |
| 673 | u32 rir_way; |
| 674 | |
| 675 | /* |
| 676 | * Step 1) Get TOLM/TOHM ranges |
| 677 | */ |
| 678 | |
| 679 | /* Address range is 32:28 */ |
| 680 | pci_read_config_dword(pvt->pci_sad1, TOLM, |
| 681 | ®); |
| 682 | pvt->tolm = GET_TOLM(reg); |
| 683 | tmp_mb = (1 + pvt->tolm) >> 20; |
| 684 | |
| 685 | debugf0("TOLM: %Lu.%03Lu GB (0x%016Lx)\n", |
| 686 | tmp_mb / 1000, tmp_mb % 1000, (u64)pvt->tolm); |
| 687 | |
| 688 | /* Address range is already 45:25 */ |
| 689 | pci_read_config_dword(pvt->pci_sad1, TOHM, |
| 690 | ®); |
| 691 | pvt->tohm = GET_TOHM(reg); |
| 692 | tmp_mb = (1 + pvt->tohm) >> 20; |
| 693 | |
| 694 | debugf0("TOHM: %Lu.%03Lu GB (0x%016Lx)", |
| 695 | tmp_mb / 1000, tmp_mb % 1000, (u64)pvt->tohm); |
| 696 | |
| 697 | /* |
| 698 | * Step 2) Get SAD range and SAD Interleave list |
| 699 | * TAD registers contain the interleave wayness. However, it |
| 700 | * seems simpler to just discover it indirectly, with the |
| 701 | * algorithm bellow. |
| 702 | */ |
| 703 | prv = 0; |
| 704 | for (n_sads = 0; n_sads < MAX_SAD; n_sads++) { |
| 705 | /* SAD_LIMIT Address range is 45:26 */ |
| 706 | pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads], |
| 707 | ®); |
| 708 | limit = SAD_LIMIT(reg); |
| 709 | |
| 710 | if (!DRAM_RULE_ENABLE(reg)) |
| 711 | continue; |
| 712 | |
| 713 | if (limit <= prv) |
| 714 | break; |
| 715 | |
| 716 | tmp_mb = (limit + 1) >> 20; |
| 717 | debugf0("SAD#%d %s up to %Lu.%03Lu GB (0x%016Lx) %s reg=0x%08x\n", |
| 718 | n_sads, |
| 719 | get_dram_attr(reg), |
| 720 | tmp_mb / 1000, tmp_mb % 1000, |
| 721 | ((u64)tmp_mb) << 20L, |
| 722 | INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]", |
| 723 | reg); |
| 724 | prv = limit; |
| 725 | |
| 726 | pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads], |
| 727 | ®); |
| 728 | sad_interl = sad_pkg(reg, 0); |
| 729 | for (j = 0; j < 8; j++) { |
| 730 | if (j > 0 && sad_interl == sad_pkg(reg, j)) |
| 731 | break; |
| 732 | |
| 733 | debugf0("SAD#%d, interleave #%d: %d\n", |
| 734 | n_sads, j, sad_pkg(reg, j)); |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | /* |
| 739 | * Step 3) Get TAD range |
| 740 | */ |
| 741 | prv = 0; |
| 742 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
| 743 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], |
| 744 | ®); |
| 745 | limit = TAD_LIMIT(reg); |
| 746 | if (limit <= prv) |
| 747 | break; |
| 748 | tmp_mb = (limit + 1) >> 20; |
| 749 | |
| 750 | debugf0("TAD#%d: up to %Lu.%03Lu GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
| 751 | n_tads, tmp_mb / 1000, tmp_mb % 1000, |
| 752 | ((u64)tmp_mb) << 20L, |
| 753 | (u32)TAD_SOCK(reg), |
| 754 | (u32)TAD_CH(reg), |
| 755 | (u32)TAD_TGT0(reg), |
| 756 | (u32)TAD_TGT1(reg), |
| 757 | (u32)TAD_TGT2(reg), |
| 758 | (u32)TAD_TGT3(reg), |
| 759 | reg); |
| 760 | prv = tmp_mb; |
| 761 | } |
| 762 | |
| 763 | /* |
| 764 | * Step 4) Get TAD offsets, per each channel |
| 765 | */ |
| 766 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 767 | if (!pvt->channel[i].dimms) |
| 768 | continue; |
| 769 | for (j = 0; j < n_tads; j++) { |
| 770 | pci_read_config_dword(pvt->pci_tad[i], |
| 771 | tad_ch_nilv_offset[j], |
| 772 | ®); |
| 773 | tmp_mb = TAD_OFFSET(reg) >> 20; |
| 774 | debugf0("TAD CH#%d, offset #%d: %Lu.%03Lu GB (0x%016Lx), reg=0x%08x\n", |
| 775 | i, j, |
| 776 | tmp_mb / 1000, tmp_mb % 1000, |
| 777 | ((u64)tmp_mb) << 20L, |
| 778 | reg); |
| 779 | } |
| 780 | } |
| 781 | |
| 782 | /* |
| 783 | * Step 6) Get RIR Wayness/Limit, per each channel |
| 784 | */ |
| 785 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 786 | if (!pvt->channel[i].dimms) |
| 787 | continue; |
| 788 | for (j = 0; j < MAX_RIR_RANGES; j++) { |
| 789 | pci_read_config_dword(pvt->pci_tad[i], |
| 790 | rir_way_limit[j], |
| 791 | ®); |
| 792 | |
| 793 | if (!IS_RIR_VALID(reg)) |
| 794 | continue; |
| 795 | |
| 796 | tmp_mb = RIR_LIMIT(reg) >> 20; |
| 797 | rir_way = 1 << RIR_WAY(reg); |
| 798 | debugf0("CH#%d RIR#%d, limit: %Lu.%03Lu GB (0x%016Lx), way: %d, reg=0x%08x\n", |
| 799 | i, j, |
| 800 | tmp_mb / 1000, tmp_mb % 1000, |
| 801 | ((u64)tmp_mb) << 20L, |
| 802 | rir_way, |
| 803 | reg); |
| 804 | |
| 805 | for (k = 0; k < rir_way; k++) { |
| 806 | pci_read_config_dword(pvt->pci_tad[i], |
| 807 | rir_offset[j][k], |
| 808 | ®); |
| 809 | tmp_mb = RIR_OFFSET(reg) << 6; |
| 810 | |
| 811 | debugf0("CH#%d RIR#%d INTL#%d, offset %Lu.%03Lu GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
| 812 | i, j, k, |
| 813 | tmp_mb / 1000, tmp_mb % 1000, |
| 814 | ((u64)tmp_mb) << 20L, |
| 815 | (u32)RIR_RNK_TGT(reg), |
| 816 | reg); |
| 817 | } |
| 818 | } |
| 819 | } |
| 820 | } |
| 821 | |
| 822 | struct mem_ctl_info *get_mci_for_node_id(u8 node_id) |
| 823 | { |
| 824 | struct sbridge_dev *sbridge_dev; |
| 825 | |
| 826 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
| 827 | if (sbridge_dev->node_id == node_id) |
| 828 | return sbridge_dev->mci; |
| 829 | } |
| 830 | return NULL; |
| 831 | } |
| 832 | |
| 833 | static int get_memory_error_data(struct mem_ctl_info *mci, |
| 834 | u64 addr, |
| 835 | u8 *socket, |
| 836 | long *channel_mask, |
| 837 | u8 *rank, |
| 838 | char *area_type) |
| 839 | { |
| 840 | struct mem_ctl_info *new_mci; |
| 841 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 842 | char msg[256]; |
| 843 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
| 844 | int sad_interl, idx, base_ch; |
| 845 | int interleave_mode; |
| 846 | unsigned sad_interleave[MAX_INTERLEAVE]; |
| 847 | u32 reg; |
| 848 | u8 ch_way,sck_way; |
| 849 | u32 tad_offset; |
| 850 | u32 rir_way; |
| 851 | u64 ch_addr, offset, limit, prv = 0; |
| 852 | |
| 853 | |
| 854 | /* |
| 855 | * Step 0) Check if the address is at special memory ranges |
| 856 | * The check bellow is probably enough to fill all cases where |
| 857 | * the error is not inside a memory, except for the legacy |
| 858 | * range (e. g. VGA addresses). It is unlikely, however, that the |
| 859 | * memory controller would generate an error on that range. |
| 860 | */ |
| 861 | if ((addr > (u64) pvt->tolm) && (addr < (1L << 32))) { |
| 862 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
| 863 | edac_mc_handle_ce_no_info(mci, msg); |
| 864 | return -EINVAL; |
| 865 | } |
| 866 | if (addr >= (u64)pvt->tohm) { |
| 867 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); |
| 868 | edac_mc_handle_ce_no_info(mci, msg); |
| 869 | return -EINVAL; |
| 870 | } |
| 871 | |
| 872 | /* |
| 873 | * Step 1) Get socket |
| 874 | */ |
| 875 | for (n_sads = 0; n_sads < MAX_SAD; n_sads++) { |
| 876 | pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads], |
| 877 | ®); |
| 878 | |
| 879 | if (!DRAM_RULE_ENABLE(reg)) |
| 880 | continue; |
| 881 | |
| 882 | limit = SAD_LIMIT(reg); |
| 883 | if (limit <= prv) { |
| 884 | sprintf(msg, "Can't discover the memory socket"); |
| 885 | edac_mc_handle_ce_no_info(mci, msg); |
| 886 | return -EINVAL; |
| 887 | } |
| 888 | if (addr <= limit) |
| 889 | break; |
| 890 | prv = limit; |
| 891 | } |
| 892 | if (n_sads == MAX_SAD) { |
| 893 | sprintf(msg, "Can't discover the memory socket"); |
| 894 | edac_mc_handle_ce_no_info(mci, msg); |
| 895 | return -EINVAL; |
| 896 | } |
| 897 | area_type = get_dram_attr(reg); |
| 898 | interleave_mode = INTERLEAVE_MODE(reg); |
| 899 | |
| 900 | pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads], |
| 901 | ®); |
| 902 | sad_interl = sad_pkg(reg, 0); |
| 903 | for (sad_way = 0; sad_way < 8; sad_way++) { |
| 904 | if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way)) |
| 905 | break; |
| 906 | sad_interleave[sad_way] = sad_pkg(reg, sad_way); |
| 907 | debugf0("SAD interleave #%d: %d\n", |
| 908 | sad_way, sad_interleave[sad_way]); |
| 909 | } |
| 910 | debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", |
| 911 | pvt->sbridge_dev->mc, |
| 912 | n_sads, |
| 913 | addr, |
| 914 | limit, |
| 915 | sad_way + 7, |
| 916 | INTERLEAVE_MODE(reg) ? "" : "XOR[18:16]"); |
| 917 | if (interleave_mode) |
| 918 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; |
| 919 | else |
| 920 | idx = (addr >> 6) & 7; |
| 921 | switch (sad_way) { |
| 922 | case 1: |
| 923 | idx = 0; |
| 924 | break; |
| 925 | case 2: |
| 926 | idx = idx & 1; |
| 927 | break; |
| 928 | case 4: |
| 929 | idx = idx & 3; |
| 930 | break; |
| 931 | case 8: |
| 932 | break; |
| 933 | default: |
| 934 | sprintf(msg, "Can't discover socket interleave"); |
| 935 | edac_mc_handle_ce_no_info(mci, msg); |
| 936 | return -EINVAL; |
| 937 | } |
| 938 | *socket = sad_interleave[idx]; |
| 939 | debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n", |
| 940 | idx, sad_way, *socket); |
| 941 | |
| 942 | /* |
| 943 | * Move to the proper node structure, in order to access the |
| 944 | * right PCI registers |
| 945 | */ |
| 946 | new_mci = get_mci_for_node_id(*socket); |
| 947 | if (!new_mci) { |
| 948 | sprintf(msg, "Struct for socket #%u wasn't initialized", |
| 949 | *socket); |
| 950 | edac_mc_handle_ce_no_info(mci, msg); |
| 951 | return -EINVAL; |
| 952 | } |
| 953 | mci = new_mci; |
| 954 | pvt = mci->pvt_info; |
| 955 | |
| 956 | /* |
| 957 | * Step 2) Get memory channel |
| 958 | */ |
| 959 | prv = 0; |
| 960 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
| 961 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], |
| 962 | ®); |
| 963 | limit = TAD_LIMIT(reg); |
| 964 | if (limit <= prv) { |
| 965 | sprintf(msg, "Can't discover the memory channel"); |
| 966 | edac_mc_handle_ce_no_info(mci, msg); |
| 967 | return -EINVAL; |
| 968 | } |
| 969 | if (addr <= limit) |
| 970 | break; |
| 971 | prv = limit; |
| 972 | } |
| 973 | ch_way = TAD_CH(reg) + 1; |
| 974 | sck_way = TAD_SOCK(reg) + 1; |
| 975 | /* |
| 976 | * FIXME: Is it right to always use channel 0 for offsets? |
| 977 | */ |
| 978 | pci_read_config_dword(pvt->pci_tad[0], |
| 979 | tad_ch_nilv_offset[n_tads], |
| 980 | &tad_offset); |
| 981 | |
| 982 | if (ch_way == 3) |
| 983 | idx = addr >> 6; |
| 984 | else |
| 985 | idx = addr >> (6 + sck_way); |
| 986 | idx = idx % ch_way; |
| 987 | |
| 988 | /* |
| 989 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? |
| 990 | */ |
| 991 | switch (idx) { |
| 992 | case 0: |
| 993 | base_ch = TAD_TGT0(reg); |
| 994 | break; |
| 995 | case 1: |
| 996 | base_ch = TAD_TGT1(reg); |
| 997 | break; |
| 998 | case 2: |
| 999 | base_ch = TAD_TGT2(reg); |
| 1000 | break; |
| 1001 | case 3: |
| 1002 | base_ch = TAD_TGT3(reg); |
| 1003 | break; |
| 1004 | default: |
| 1005 | sprintf(msg, "Can't discover the TAD target"); |
| 1006 | edac_mc_handle_ce_no_info(mci, msg); |
| 1007 | return -EINVAL; |
| 1008 | } |
| 1009 | *channel_mask = 1 << base_ch; |
| 1010 | |
| 1011 | if (pvt->is_mirrored) { |
| 1012 | *channel_mask |= 1 << ((base_ch + 2) % 4); |
| 1013 | switch(ch_way) { |
| 1014 | case 2: |
| 1015 | case 4: |
| 1016 | sck_xch = 1 << sck_way * (ch_way >> 1); |
| 1017 | break; |
| 1018 | default: |
| 1019 | sprintf(msg, "Invalid mirror set. Can't decode addr"); |
| 1020 | edac_mc_handle_ce_no_info(mci, msg); |
| 1021 | return -EINVAL; |
| 1022 | } |
| 1023 | } else |
| 1024 | sck_xch = (1 << sck_way) * ch_way; |
| 1025 | |
| 1026 | if (pvt->is_lockstep) |
| 1027 | *channel_mask |= 1 << ((base_ch + 1) % 4); |
| 1028 | |
| 1029 | offset = TAD_OFFSET(tad_offset); |
| 1030 | |
| 1031 | debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
| 1032 | n_tads, |
| 1033 | addr, |
| 1034 | limit, |
| 1035 | (u32)TAD_SOCK(reg), |
| 1036 | ch_way, |
| 1037 | offset, |
| 1038 | idx, |
| 1039 | base_ch, |
| 1040 | *channel_mask); |
| 1041 | |
| 1042 | /* Calculate channel address */ |
| 1043 | /* Remove the TAD offset */ |
| 1044 | |
| 1045 | if (offset > addr) { |
| 1046 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", |
| 1047 | offset, addr); |
| 1048 | edac_mc_handle_ce_no_info(mci, msg); |
| 1049 | return -EINVAL; |
| 1050 | } |
| 1051 | addr -= offset; |
| 1052 | /* Store the low bits [0:6] of the addr */ |
| 1053 | ch_addr = addr & 0x7f; |
| 1054 | /* Remove socket wayness and remove 6 bits */ |
| 1055 | addr >>= 6; |
| 1056 | addr /= sck_xch; |
| 1057 | #if 0 |
| 1058 | /* Divide by channel way */ |
| 1059 | addr = addr / ch_way; |
| 1060 | #endif |
| 1061 | /* Recover the last 6 bits */ |
| 1062 | ch_addr |= addr << 6; |
| 1063 | |
| 1064 | /* |
| 1065 | * Step 3) Decode rank |
| 1066 | */ |
| 1067 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { |
| 1068 | pci_read_config_dword(pvt->pci_tad[base_ch], |
| 1069 | rir_way_limit[n_rir], |
| 1070 | ®); |
| 1071 | |
| 1072 | if (!IS_RIR_VALID(reg)) |
| 1073 | continue; |
| 1074 | |
| 1075 | limit = RIR_LIMIT(reg); |
| 1076 | |
| 1077 | debugf0("RIR#%d, limit: %Lu.%03Lu GB (0x%016Lx), way: %d\n", |
| 1078 | n_rir, |
| 1079 | (limit >> 20) / 1000, (limit >> 20) % 1000, |
| 1080 | limit, |
| 1081 | 1 << RIR_WAY(reg)); |
| 1082 | if (ch_addr <= limit) |
| 1083 | break; |
| 1084 | } |
| 1085 | if (n_rir == MAX_RIR_RANGES) { |
| 1086 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", |
| 1087 | ch_addr); |
| 1088 | edac_mc_handle_ce_no_info(mci, msg); |
| 1089 | return -EINVAL; |
| 1090 | } |
| 1091 | rir_way = RIR_WAY(reg); |
| 1092 | if (pvt->is_close_pg) |
| 1093 | idx = (ch_addr >> 6); |
| 1094 | else |
| 1095 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ |
| 1096 | idx %= 1 << rir_way; |
| 1097 | |
| 1098 | pci_read_config_dword(pvt->pci_tad[base_ch], |
| 1099 | rir_offset[n_rir][idx], |
| 1100 | ®); |
| 1101 | *rank = RIR_RNK_TGT(reg); |
| 1102 | |
| 1103 | debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
| 1104 | n_rir, |
| 1105 | ch_addr, |
| 1106 | limit, |
| 1107 | rir_way, |
| 1108 | idx); |
| 1109 | |
| 1110 | return 0; |
| 1111 | } |
| 1112 | |
| 1113 | /**************************************************************************** |
| 1114 | Device initialization routines: put/get, init/exit |
| 1115 | ****************************************************************************/ |
| 1116 | |
| 1117 | /* |
| 1118 | * sbridge_put_all_devices 'put' all the devices that we have |
| 1119 | * reserved via 'get' |
| 1120 | */ |
| 1121 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) |
| 1122 | { |
| 1123 | int i; |
| 1124 | |
| 1125 | debugf0(__FILE__ ": %s()\n", __func__); |
| 1126 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1127 | struct pci_dev *pdev = sbridge_dev->pdev[i]; |
| 1128 | if (!pdev) |
| 1129 | continue; |
| 1130 | debugf0("Removing dev %02x:%02x.%d\n", |
| 1131 | pdev->bus->number, |
| 1132 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
| 1133 | pci_dev_put(pdev); |
| 1134 | } |
| 1135 | } |
| 1136 | |
| 1137 | static void sbridge_put_all_devices(void) |
| 1138 | { |
| 1139 | struct sbridge_dev *sbridge_dev, *tmp; |
| 1140 | |
| 1141 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { |
| 1142 | sbridge_put_devices(sbridge_dev); |
| 1143 | free_sbridge_dev(sbridge_dev); |
| 1144 | } |
| 1145 | } |
| 1146 | |
| 1147 | /* |
| 1148 | * sbridge_get_all_devices Find and perform 'get' operation on the MCH's |
| 1149 | * device/functions we want to reference for this driver |
| 1150 | * |
| 1151 | * Need to 'get' device 16 func 1 and func 2 |
| 1152 | */ |
| 1153 | static int sbridge_get_onedevice(struct pci_dev **prev, |
| 1154 | u8 *num_mc, |
| 1155 | const struct pci_id_table *table, |
| 1156 | const unsigned devno) |
| 1157 | { |
| 1158 | struct sbridge_dev *sbridge_dev; |
| 1159 | const struct pci_id_descr *dev_descr = &table->descr[devno]; |
| 1160 | |
| 1161 | struct pci_dev *pdev = NULL; |
| 1162 | u8 bus = 0; |
| 1163 | |
| 1164 | sbridge_printk(KERN_INFO, |
| 1165 | "Seeking for: dev %02x.%d PCI ID %04x:%04x\n", |
| 1166 | dev_descr->dev, dev_descr->func, |
| 1167 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1168 | |
| 1169 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1170 | dev_descr->dev_id, *prev); |
| 1171 | |
| 1172 | if (!pdev) { |
| 1173 | if (*prev) { |
| 1174 | *prev = pdev; |
| 1175 | return 0; |
| 1176 | } |
| 1177 | |
| 1178 | if (dev_descr->optional) |
| 1179 | return 0; |
| 1180 | |
| 1181 | if (devno == 0) |
| 1182 | return -ENODEV; |
| 1183 | |
| 1184 | sbridge_printk(KERN_INFO, |
| 1185 | "Device not found: dev %02x.%d PCI ID %04x:%04x\n", |
| 1186 | dev_descr->dev, dev_descr->func, |
| 1187 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1188 | |
| 1189 | /* End of list, leave */ |
| 1190 | return -ENODEV; |
| 1191 | } |
| 1192 | bus = pdev->bus->number; |
| 1193 | |
| 1194 | sbridge_dev = get_sbridge_dev(bus); |
| 1195 | if (!sbridge_dev) { |
| 1196 | sbridge_dev = alloc_sbridge_dev(bus, table); |
| 1197 | if (!sbridge_dev) { |
| 1198 | pci_dev_put(pdev); |
| 1199 | return -ENOMEM; |
| 1200 | } |
| 1201 | (*num_mc)++; |
| 1202 | } |
| 1203 | |
| 1204 | if (sbridge_dev->pdev[devno]) { |
| 1205 | sbridge_printk(KERN_ERR, |
| 1206 | "Duplicated device for " |
| 1207 | "dev %02x:%d.%d PCI ID %04x:%04x\n", |
| 1208 | bus, dev_descr->dev, dev_descr->func, |
| 1209 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1210 | pci_dev_put(pdev); |
| 1211 | return -ENODEV; |
| 1212 | } |
| 1213 | |
| 1214 | sbridge_dev->pdev[devno] = pdev; |
| 1215 | |
| 1216 | /* Sanity check */ |
| 1217 | if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || |
| 1218 | PCI_FUNC(pdev->devfn) != dev_descr->func)) { |
| 1219 | sbridge_printk(KERN_ERR, |
| 1220 | "Device PCI ID %04x:%04x " |
| 1221 | "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n", |
| 1222 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id, |
| 1223 | bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
| 1224 | bus, dev_descr->dev, dev_descr->func); |
| 1225 | return -ENODEV; |
| 1226 | } |
| 1227 | |
| 1228 | /* Be sure that the device is enabled */ |
| 1229 | if (unlikely(pci_enable_device(pdev) < 0)) { |
| 1230 | sbridge_printk(KERN_ERR, |
| 1231 | "Couldn't enable " |
| 1232 | "dev %02x:%d.%d PCI ID %04x:%04x\n", |
| 1233 | bus, dev_descr->dev, dev_descr->func, |
| 1234 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1235 | return -ENODEV; |
| 1236 | } |
| 1237 | |
| 1238 | debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n", |
| 1239 | bus, dev_descr->dev, |
| 1240 | dev_descr->func, |
| 1241 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1242 | |
| 1243 | /* |
| 1244 | * As stated on drivers/pci/search.c, the reference count for |
| 1245 | * @from is always decremented if it is not %NULL. So, as we need |
| 1246 | * to get all devices up to null, we need to do a get for the device |
| 1247 | */ |
| 1248 | pci_dev_get(pdev); |
| 1249 | |
| 1250 | *prev = pdev; |
| 1251 | |
| 1252 | return 0; |
| 1253 | } |
| 1254 | |
| 1255 | static int sbridge_get_all_devices(u8 *num_mc) |
| 1256 | { |
| 1257 | int i, rc; |
| 1258 | struct pci_dev *pdev = NULL; |
| 1259 | const struct pci_id_table *table = pci_dev_descr_sbridge_table; |
| 1260 | |
| 1261 | while (table && table->descr) { |
| 1262 | for (i = 0; i < table->n_devs; i++) { |
| 1263 | pdev = NULL; |
| 1264 | do { |
| 1265 | rc = sbridge_get_onedevice(&pdev, num_mc, |
| 1266 | table, i); |
| 1267 | if (rc < 0) { |
| 1268 | if (i == 0) { |
| 1269 | i = table->n_devs; |
| 1270 | break; |
| 1271 | } |
| 1272 | sbridge_put_all_devices(); |
| 1273 | return -ENODEV; |
| 1274 | } |
| 1275 | } while (pdev); |
| 1276 | } |
| 1277 | table++; |
| 1278 | } |
| 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | |
| 1283 | static int mci_bind_devs(struct mem_ctl_info *mci, |
| 1284 | struct sbridge_dev *sbridge_dev) |
| 1285 | { |
| 1286 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 1287 | struct pci_dev *pdev; |
| 1288 | int i, func, slot; |
| 1289 | |
| 1290 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1291 | pdev = sbridge_dev->pdev[i]; |
| 1292 | if (!pdev) |
| 1293 | continue; |
| 1294 | slot = PCI_SLOT(pdev->devfn); |
| 1295 | func = PCI_FUNC(pdev->devfn); |
| 1296 | switch (slot) { |
| 1297 | case 12: |
| 1298 | switch (func) { |
| 1299 | case 6: |
| 1300 | pvt->pci_sad0 = pdev; |
| 1301 | break; |
| 1302 | case 7: |
| 1303 | pvt->pci_sad1 = pdev; |
| 1304 | break; |
| 1305 | default: |
| 1306 | goto error; |
| 1307 | } |
| 1308 | break; |
| 1309 | case 13: |
| 1310 | switch (func) { |
| 1311 | case 6: |
| 1312 | pvt->pci_br = pdev; |
| 1313 | break; |
| 1314 | default: |
| 1315 | goto error; |
| 1316 | } |
| 1317 | break; |
| 1318 | case 14: |
| 1319 | switch (func) { |
| 1320 | case 0: |
| 1321 | pvt->pci_ha0 = pdev; |
| 1322 | break; |
| 1323 | default: |
| 1324 | goto error; |
| 1325 | } |
| 1326 | break; |
| 1327 | case 15: |
| 1328 | switch (func) { |
| 1329 | case 0: |
| 1330 | pvt->pci_ta = pdev; |
| 1331 | break; |
| 1332 | case 1: |
| 1333 | pvt->pci_ras = pdev; |
| 1334 | break; |
| 1335 | case 2: |
| 1336 | case 3: |
| 1337 | case 4: |
| 1338 | case 5: |
| 1339 | pvt->pci_tad[func - 2] = pdev; |
| 1340 | break; |
| 1341 | default: |
| 1342 | goto error; |
| 1343 | } |
| 1344 | break; |
| 1345 | case 17: |
| 1346 | switch (func) { |
| 1347 | case 0: |
| 1348 | pvt->pci_ddrio = pdev; |
| 1349 | break; |
| 1350 | default: |
| 1351 | goto error; |
| 1352 | } |
| 1353 | break; |
| 1354 | default: |
| 1355 | goto error; |
| 1356 | } |
| 1357 | |
| 1358 | debugf0("Associated PCI %02x.%02d.%d with dev = %p\n", |
| 1359 | sbridge_dev->bus, |
| 1360 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
| 1361 | pdev); |
| 1362 | } |
| 1363 | |
| 1364 | /* Check if everything were registered */ |
| 1365 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || |
| 1366 | !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta || |
| 1367 | !pvt->pci_ddrio) |
| 1368 | goto enodev; |
| 1369 | |
| 1370 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 1371 | if (!pvt->pci_tad[i]) |
| 1372 | goto enodev; |
| 1373 | } |
| 1374 | return 0; |
| 1375 | |
| 1376 | enodev: |
| 1377 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); |
| 1378 | return -ENODEV; |
| 1379 | |
| 1380 | error: |
| 1381 | sbridge_printk(KERN_ERR, "Device %d, function %d " |
| 1382 | "is out of the expected range\n", |
| 1383 | slot, func); |
| 1384 | return -EINVAL; |
| 1385 | } |
| 1386 | |
| 1387 | /**************************************************************************** |
| 1388 | Error check routines |
| 1389 | ****************************************************************************/ |
| 1390 | |
| 1391 | /* |
| 1392 | * While Sandy Bridge has error count registers, SMI BIOS read values from |
| 1393 | * and resets the counters. So, they are not reliable for the OS to read |
| 1394 | * from them. So, we have no option but to just trust on whatever MCE is |
| 1395 | * telling us about the errors. |
| 1396 | */ |
| 1397 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, |
| 1398 | const struct mce *m) |
| 1399 | { |
| 1400 | struct mem_ctl_info *new_mci; |
| 1401 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 1402 | char *type, *optype, *msg, *recoverable_msg; |
| 1403 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
| 1404 | bool overflow = GET_BITFIELD(m->status, 62, 62); |
| 1405 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); |
| 1406 | bool recoverable = GET_BITFIELD(m->status, 56, 56); |
| 1407 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); |
| 1408 | u32 mscod = GET_BITFIELD(m->status, 16, 31); |
| 1409 | u32 errcode = GET_BITFIELD(m->status, 0, 15); |
| 1410 | u32 channel = GET_BITFIELD(m->status, 0, 3); |
| 1411 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); |
| 1412 | long channel_mask, first_channel; |
| 1413 | u8 rank, socket; |
| 1414 | int csrow, rc, dimm; |
| 1415 | char *area_type = "Unknown"; |
| 1416 | |
| 1417 | if (ripv) |
| 1418 | type = "NON_FATAL"; |
| 1419 | else |
| 1420 | type = "FATAL"; |
| 1421 | |
| 1422 | /* |
| 1423 | * According with Table 15-9 of the Intel Archictecture spec vol 3A, |
| 1424 | * memory errors should fit in this mask: |
| 1425 | * 000f 0000 1mmm cccc (binary) |
| 1426 | * where: |
| 1427 | * f = Correction Report Filtering Bit. If 1, subsequent errors |
| 1428 | * won't be shown |
| 1429 | * mmm = error type |
| 1430 | * cccc = channel |
| 1431 | * If the mask doesn't match, report an error to the parsing logic |
| 1432 | */ |
| 1433 | if (! ((errcode & 0xef80) == 0x80)) { |
| 1434 | optype = "Can't parse: it is not a mem"; |
| 1435 | } else { |
| 1436 | switch (optypenum) { |
| 1437 | case 0: |
| 1438 | optype = "generic undef request"; |
| 1439 | break; |
| 1440 | case 1: |
| 1441 | optype = "memory read"; |
| 1442 | break; |
| 1443 | case 2: |
| 1444 | optype = "memory write"; |
| 1445 | break; |
| 1446 | case 3: |
| 1447 | optype = "addr/cmd"; |
| 1448 | break; |
| 1449 | case 4: |
| 1450 | optype = "memory scrubbing"; |
| 1451 | break; |
| 1452 | default: |
| 1453 | optype = "reserved"; |
| 1454 | break; |
| 1455 | } |
| 1456 | } |
| 1457 | |
| 1458 | rc = get_memory_error_data(mci, m->addr, &socket, |
| 1459 | &channel_mask, &rank, area_type); |
| 1460 | if (rc < 0) |
| 1461 | return; |
| 1462 | new_mci = get_mci_for_node_id(socket); |
| 1463 | if (!new_mci) { |
| 1464 | edac_mc_handle_ce_no_info(mci, "Error: socket got corrupted!"); |
| 1465 | return; |
| 1466 | } |
| 1467 | mci = new_mci; |
| 1468 | pvt = mci->pvt_info; |
| 1469 | |
| 1470 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); |
| 1471 | |
| 1472 | if (rank < 4) |
| 1473 | dimm = 0; |
| 1474 | else if (rank < 8) |
| 1475 | dimm = 1; |
| 1476 | else |
| 1477 | dimm = 2; |
| 1478 | |
| 1479 | csrow = pvt->csrow_map[first_channel][dimm]; |
| 1480 | |
| 1481 | if (uncorrected_error && recoverable) |
| 1482 | recoverable_msg = " recoverable"; |
| 1483 | else |
| 1484 | recoverable_msg = ""; |
| 1485 | |
| 1486 | /* |
| 1487 | * FIXME: What should we do with "channel" information on mcelog? |
| 1488 | * Probably, we can just discard it, as the channel information |
| 1489 | * comes from the get_memory_error_data() address decoding |
| 1490 | */ |
| 1491 | msg = kasprintf(GFP_ATOMIC, |
| 1492 | "%d %s error(s): %s on %s area %s%s: cpu=%d Err=%04x:%04x (ch=%d), " |
| 1493 | "addr = 0x%08llx => socket=%d, Channel=%ld(mask=%ld), rank=%d\n", |
| 1494 | core_err_cnt, |
| 1495 | area_type, |
| 1496 | optype, |
| 1497 | type, |
| 1498 | recoverable_msg, |
| 1499 | overflow ? "OVERFLOW" : "", |
| 1500 | m->cpu, |
| 1501 | mscod, errcode, |
| 1502 | channel, /* 1111b means not specified */ |
| 1503 | (long long) m->addr, |
| 1504 | socket, |
| 1505 | first_channel, /* This is the real channel on SB */ |
| 1506 | channel_mask, |
| 1507 | rank); |
| 1508 | |
| 1509 | debugf0("%s", msg); |
| 1510 | |
| 1511 | /* Call the helper to output message */ |
| 1512 | if (uncorrected_error) |
| 1513 | edac_mc_handle_fbd_ue(mci, csrow, 0, 0, msg); |
| 1514 | else |
| 1515 | edac_mc_handle_fbd_ce(mci, csrow, 0, msg); |
| 1516 | |
| 1517 | kfree(msg); |
| 1518 | } |
| 1519 | |
| 1520 | /* |
| 1521 | * sbridge_check_error Retrieve and process errors reported by the |
| 1522 | * hardware. Called by the Core module. |
| 1523 | */ |
| 1524 | static void sbridge_check_error(struct mem_ctl_info *mci) |
| 1525 | { |
| 1526 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 1527 | int i; |
| 1528 | unsigned count = 0; |
| 1529 | struct mce *m; |
| 1530 | |
| 1531 | /* |
| 1532 | * MCE first step: Copy all mce errors into a temporary buffer |
| 1533 | * We use a double buffering here, to reduce the risk of |
| 1534 | * loosing an error. |
| 1535 | */ |
| 1536 | smp_rmb(); |
| 1537 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) |
| 1538 | % MCE_LOG_LEN; |
| 1539 | if (!count) |
| 1540 | return; |
| 1541 | |
| 1542 | m = pvt->mce_outentry; |
| 1543 | if (pvt->mce_in + count > MCE_LOG_LEN) { |
| 1544 | unsigned l = MCE_LOG_LEN - pvt->mce_in; |
| 1545 | |
| 1546 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); |
| 1547 | smp_wmb(); |
| 1548 | pvt->mce_in = 0; |
| 1549 | count -= l; |
| 1550 | m += l; |
| 1551 | } |
| 1552 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); |
| 1553 | smp_wmb(); |
| 1554 | pvt->mce_in += count; |
| 1555 | |
| 1556 | smp_rmb(); |
| 1557 | if (pvt->mce_overrun) { |
| 1558 | sbridge_printk(KERN_ERR, "Lost %d memory errors\n", |
| 1559 | pvt->mce_overrun); |
| 1560 | smp_wmb(); |
| 1561 | pvt->mce_overrun = 0; |
| 1562 | } |
| 1563 | |
| 1564 | /* |
| 1565 | * MCE second step: parse errors and display |
| 1566 | */ |
| 1567 | for (i = 0; i < count; i++) |
| 1568 | sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); |
| 1569 | } |
| 1570 | |
| 1571 | /* |
| 1572 | * sbridge_mce_check_error Replicates mcelog routine to get errors |
| 1573 | * This routine simply queues mcelog errors, and |
| 1574 | * return. The error itself should be handled later |
| 1575 | * by sbridge_check_error. |
| 1576 | * WARNING: As this routine should be called at NMI time, extra care should |
| 1577 | * be taken to avoid deadlocks, and to be as fast as possible. |
| 1578 | */ |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1579 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
| 1580 | void *data) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1581 | { |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1582 | struct mce *mce = (struct mce *)data; |
| 1583 | struct mem_ctl_info *mci; |
| 1584 | struct sbridge_pvt *pvt; |
| 1585 | |
| 1586 | mci = get_mci_for_node_id(mce->socketid); |
| 1587 | if (!mci) |
| 1588 | return NOTIFY_BAD; |
| 1589 | pvt = mci->pvt_info; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1590 | |
| 1591 | /* |
| 1592 | * Just let mcelog handle it if the error is |
| 1593 | * outside the memory controller. A memory error |
| 1594 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. |
| 1595 | * bit 12 has an special meaning. |
| 1596 | */ |
| 1597 | if ((mce->status & 0xefff) >> 7 != 1) |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1598 | return NOTIFY_DONE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1599 | |
| 1600 | printk("sbridge: HANDLING MCE MEMORY ERROR\n"); |
| 1601 | |
| 1602 | printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
| 1603 | mce->extcpu, mce->mcgstatus, mce->bank, mce->status); |
| 1604 | printk("TSC %llx ", mce->tsc); |
| 1605 | printk("ADDR %llx ", mce->addr); |
| 1606 | printk("MISC %llx ", mce->misc); |
| 1607 | |
| 1608 | printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
| 1609 | mce->cpuvendor, mce->cpuid, mce->time, |
| 1610 | mce->socketid, mce->apicid); |
| 1611 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1612 | /* Only handle if it is the right mc controller */ |
| 1613 | if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc) |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1614 | return NOTIFY_DONE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1615 | |
| 1616 | smp_rmb(); |
| 1617 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { |
| 1618 | smp_wmb(); |
| 1619 | pvt->mce_overrun++; |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1620 | return NOTIFY_DONE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1621 | } |
| 1622 | |
| 1623 | /* Copy memory error at the ringbuffer */ |
| 1624 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); |
| 1625 | smp_wmb(); |
| 1626 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; |
| 1627 | |
| 1628 | /* Handle fatal errors immediately */ |
| 1629 | if (mce->mcgstatus & 1) |
| 1630 | sbridge_check_error(mci); |
| 1631 | |
| 1632 | /* Advice mcelog that the error were handled */ |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1633 | return NOTIFY_STOP; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1634 | } |
| 1635 | |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1636 | static struct notifier_block sbridge_mce_dec = { |
| 1637 | .notifier_call = sbridge_mce_check_error, |
| 1638 | }; |
| 1639 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1640 | /**************************************************************************** |
| 1641 | EDAC register/unregister logic |
| 1642 | ****************************************************************************/ |
| 1643 | |
| 1644 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) |
| 1645 | { |
| 1646 | struct mem_ctl_info *mci = sbridge_dev->mci; |
| 1647 | struct sbridge_pvt *pvt; |
| 1648 | |
| 1649 | if (unlikely(!mci || !mci->pvt_info)) { |
| 1650 | debugf0("MC: " __FILE__ ": %s(): dev = %p\n", |
| 1651 | __func__, &sbridge_dev->pdev[0]->dev); |
| 1652 | |
| 1653 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); |
| 1654 | return; |
| 1655 | } |
| 1656 | |
| 1657 | pvt = mci->pvt_info; |
| 1658 | |
| 1659 | debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n", |
| 1660 | __func__, mci, &sbridge_dev->pdev[0]->dev); |
| 1661 | |
Borislav Petkov | 3653ada | 2011-12-04 15:12:09 +0100 | [diff] [blame] | 1662 | mce_unregister_decode_chain(&sbridge_mce_dec); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1663 | |
| 1664 | /* Remove MC sysfs nodes */ |
| 1665 | edac_mc_del_mc(mci->dev); |
| 1666 | |
| 1667 | debugf1("%s: free mci struct\n", mci->ctl_name); |
| 1668 | kfree(mci->ctl_name); |
| 1669 | edac_mc_free(mci); |
| 1670 | sbridge_dev->mci = NULL; |
| 1671 | } |
| 1672 | |
| 1673 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev) |
| 1674 | { |
| 1675 | struct mem_ctl_info *mci; |
| 1676 | struct sbridge_pvt *pvt; |
| 1677 | int rc, channels, csrows; |
| 1678 | |
| 1679 | /* Check the number of active and not disabled channels */ |
| 1680 | rc = sbridge_get_active_channels(sbridge_dev->bus, &channels, &csrows); |
| 1681 | if (unlikely(rc < 0)) |
| 1682 | return rc; |
| 1683 | |
| 1684 | /* allocate a new MC control structure */ |
| 1685 | mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, sbridge_dev->mc); |
| 1686 | if (unlikely(!mci)) |
| 1687 | return -ENOMEM; |
| 1688 | |
| 1689 | debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n", |
| 1690 | __func__, mci, &sbridge_dev->pdev[0]->dev); |
| 1691 | |
| 1692 | pvt = mci->pvt_info; |
| 1693 | memset(pvt, 0, sizeof(*pvt)); |
| 1694 | |
| 1695 | /* Associate sbridge_dev and mci for future usage */ |
| 1696 | pvt->sbridge_dev = sbridge_dev; |
| 1697 | sbridge_dev->mci = mci; |
| 1698 | |
| 1699 | mci->mtype_cap = MEM_FLAG_DDR3; |
| 1700 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
| 1701 | mci->edac_cap = EDAC_FLAG_NONE; |
| 1702 | mci->mod_name = "sbridge_edac.c"; |
| 1703 | mci->mod_ver = SBRIDGE_REVISION; |
| 1704 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); |
| 1705 | mci->dev_name = pci_name(sbridge_dev->pdev[0]); |
| 1706 | mci->ctl_page_to_phys = NULL; |
| 1707 | |
| 1708 | /* Set the function pointer to an actual operation function */ |
| 1709 | mci->edac_check = sbridge_check_error; |
| 1710 | |
| 1711 | /* Store pci devices at mci for faster access */ |
| 1712 | rc = mci_bind_devs(mci, sbridge_dev); |
| 1713 | if (unlikely(rc < 0)) |
| 1714 | goto fail0; |
| 1715 | |
| 1716 | /* Get dimm basic config and the memory layout */ |
| 1717 | get_dimm_config(mci); |
| 1718 | get_memory_layout(mci); |
| 1719 | |
| 1720 | /* record ptr to the generic device */ |
| 1721 | mci->dev = &sbridge_dev->pdev[0]->dev; |
| 1722 | |
| 1723 | /* add this new MC control structure to EDAC's list of MCs */ |
| 1724 | if (unlikely(edac_mc_add_mc(mci))) { |
| 1725 | debugf0("MC: " __FILE__ |
| 1726 | ": %s(): failed edac_mc_add_mc()\n", __func__); |
| 1727 | rc = -EINVAL; |
| 1728 | goto fail0; |
| 1729 | } |
| 1730 | |
Borislav Petkov | 3653ada | 2011-12-04 15:12:09 +0100 | [diff] [blame] | 1731 | mce_register_decode_chain(&sbridge_mce_dec); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1732 | return 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1733 | |
| 1734 | fail0: |
| 1735 | kfree(mci->ctl_name); |
| 1736 | edac_mc_free(mci); |
| 1737 | sbridge_dev->mci = NULL; |
| 1738 | return rc; |
| 1739 | } |
| 1740 | |
| 1741 | /* |
| 1742 | * sbridge_probe Probe for ONE instance of device to see if it is |
| 1743 | * present. |
| 1744 | * return: |
| 1745 | * 0 for FOUND a device |
| 1746 | * < 0 for error code |
| 1747 | */ |
| 1748 | |
| 1749 | static int __devinit sbridge_probe(struct pci_dev *pdev, |
| 1750 | const struct pci_device_id *id) |
| 1751 | { |
| 1752 | int rc; |
| 1753 | u8 mc, num_mc = 0; |
| 1754 | struct sbridge_dev *sbridge_dev; |
| 1755 | |
| 1756 | /* get the pci devices we want to reserve for our use */ |
| 1757 | mutex_lock(&sbridge_edac_lock); |
| 1758 | |
| 1759 | /* |
| 1760 | * All memory controllers are allocated at the first pass. |
| 1761 | */ |
| 1762 | if (unlikely(probed >= 1)) { |
| 1763 | mutex_unlock(&sbridge_edac_lock); |
| 1764 | return -ENODEV; |
| 1765 | } |
| 1766 | probed++; |
| 1767 | |
| 1768 | rc = sbridge_get_all_devices(&num_mc); |
| 1769 | if (unlikely(rc < 0)) |
| 1770 | goto fail0; |
| 1771 | mc = 0; |
| 1772 | |
| 1773 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
| 1774 | debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc); |
| 1775 | sbridge_dev->mc = mc++; |
| 1776 | rc = sbridge_register_mci(sbridge_dev); |
| 1777 | if (unlikely(rc < 0)) |
| 1778 | goto fail1; |
| 1779 | } |
| 1780 | |
| 1781 | sbridge_printk(KERN_INFO, "Driver loaded.\n"); |
| 1782 | |
| 1783 | mutex_unlock(&sbridge_edac_lock); |
| 1784 | return 0; |
| 1785 | |
| 1786 | fail1: |
| 1787 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) |
| 1788 | sbridge_unregister_mci(sbridge_dev); |
| 1789 | |
| 1790 | sbridge_put_all_devices(); |
| 1791 | fail0: |
| 1792 | mutex_unlock(&sbridge_edac_lock); |
| 1793 | return rc; |
| 1794 | } |
| 1795 | |
| 1796 | /* |
| 1797 | * sbridge_remove destructor for one instance of device |
| 1798 | * |
| 1799 | */ |
| 1800 | static void __devexit sbridge_remove(struct pci_dev *pdev) |
| 1801 | { |
| 1802 | struct sbridge_dev *sbridge_dev; |
| 1803 | |
| 1804 | debugf0(__FILE__ ": %s()\n", __func__); |
| 1805 | |
| 1806 | /* |
| 1807 | * we have a trouble here: pdev value for removal will be wrong, since |
| 1808 | * it will point to the X58 register used to detect that the machine |
| 1809 | * is a Nehalem or upper design. However, due to the way several PCI |
| 1810 | * devices are grouped together to provide MC functionality, we need |
| 1811 | * to use a different method for releasing the devices |
| 1812 | */ |
| 1813 | |
| 1814 | mutex_lock(&sbridge_edac_lock); |
| 1815 | |
| 1816 | if (unlikely(!probed)) { |
| 1817 | mutex_unlock(&sbridge_edac_lock); |
| 1818 | return; |
| 1819 | } |
| 1820 | |
| 1821 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) |
| 1822 | sbridge_unregister_mci(sbridge_dev); |
| 1823 | |
| 1824 | /* Release PCI resources */ |
| 1825 | sbridge_put_all_devices(); |
| 1826 | |
| 1827 | probed--; |
| 1828 | |
| 1829 | mutex_unlock(&sbridge_edac_lock); |
| 1830 | } |
| 1831 | |
| 1832 | MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl); |
| 1833 | |
| 1834 | /* |
| 1835 | * sbridge_driver pci_driver structure for this module |
| 1836 | * |
| 1837 | */ |
| 1838 | static struct pci_driver sbridge_driver = { |
| 1839 | .name = "sbridge_edac", |
| 1840 | .probe = sbridge_probe, |
| 1841 | .remove = __devexit_p(sbridge_remove), |
| 1842 | .id_table = sbridge_pci_tbl, |
| 1843 | }; |
| 1844 | |
| 1845 | /* |
| 1846 | * sbridge_init Module entry function |
| 1847 | * Try to initialize this module for its devices |
| 1848 | */ |
| 1849 | static int __init sbridge_init(void) |
| 1850 | { |
| 1851 | int pci_rc; |
| 1852 | |
| 1853 | debugf2("MC: " __FILE__ ": %s()\n", __func__); |
| 1854 | |
| 1855 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
| 1856 | opstate_init(); |
| 1857 | |
| 1858 | pci_rc = pci_register_driver(&sbridge_driver); |
| 1859 | |
| 1860 | if (pci_rc >= 0) |
| 1861 | return 0; |
| 1862 | |
| 1863 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", |
| 1864 | pci_rc); |
| 1865 | |
| 1866 | return pci_rc; |
| 1867 | } |
| 1868 | |
| 1869 | /* |
| 1870 | * sbridge_exit() Module exit function |
| 1871 | * Unregister the driver |
| 1872 | */ |
| 1873 | static void __exit sbridge_exit(void) |
| 1874 | { |
| 1875 | debugf2("MC: " __FILE__ ": %s()\n", __func__); |
| 1876 | pci_unregister_driver(&sbridge_driver); |
| 1877 | } |
| 1878 | |
| 1879 | module_init(sbridge_init); |
| 1880 | module_exit(sbridge_exit); |
| 1881 | |
| 1882 | module_param(edac_op_state, int, 0444); |
| 1883 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |
| 1884 | |
| 1885 | MODULE_LICENSE("GPL"); |
| 1886 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); |
| 1887 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
| 1888 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - " |
| 1889 | SBRIDGE_REVISION); |