Krzysztof Halasa | dac2f83 | 2008-04-20 19:06:39 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Intel IXP4xx Ethernet driver for Linux |
| 3 | * |
| 4 | * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of version 2 of the GNU General Public License |
| 8 | * as published by the Free Software Foundation. |
| 9 | * |
| 10 | * Ethernet port config (0x00 is not present on IXP42X): |
| 11 | * |
| 12 | * logical port 0x00 0x10 0x20 |
| 13 | * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) |
| 14 | * physical PortId 2 0 1 |
| 15 | * TX queue 23 24 25 |
| 16 | * RX-free queue 26 27 28 |
| 17 | * TX-done queue is always 31, per-port RX and TX-ready queues are configurable |
| 18 | * |
| 19 | * |
| 20 | * Queue entries: |
| 21 | * bits 0 -> 1 - NPE ID (RX and TX-done) |
| 22 | * bits 0 -> 2 - priority (TX, per 802.1D) |
| 23 | * bits 3 -> 4 - port ID (user-set?) |
| 24 | * bits 5 -> 31 - physical descriptor address |
| 25 | */ |
| 26 | |
| 27 | #include <linux/delay.h> |
| 28 | #include <linux/dma-mapping.h> |
| 29 | #include <linux/dmapool.h> |
| 30 | #include <linux/etherdevice.h> |
| 31 | #include <linux/io.h> |
| 32 | #include <linux/kernel.h> |
| 33 | #include <linux/mii.h> |
| 34 | #include <linux/platform_device.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 35 | #include <mach/npe.h> |
| 36 | #include <mach/qmgr.h> |
Krzysztof Halasa | dac2f83 | 2008-04-20 19:06:39 +0200 | [diff] [blame] | 37 | |
| 38 | #define DEBUG_QUEUES 0 |
| 39 | #define DEBUG_DESC 0 |
| 40 | #define DEBUG_RX 0 |
| 41 | #define DEBUG_TX 0 |
| 42 | #define DEBUG_PKT_BYTES 0 |
| 43 | #define DEBUG_MDIO 0 |
| 44 | #define DEBUG_CLOSE 0 |
| 45 | |
| 46 | #define DRV_NAME "ixp4xx_eth" |
| 47 | |
| 48 | #define MAX_NPES 3 |
| 49 | |
| 50 | #define RX_DESCS 64 /* also length of all RX queues */ |
| 51 | #define TX_DESCS 16 /* also length of all TX queues */ |
| 52 | #define TXDONE_QUEUE_LEN 64 /* dwords */ |
| 53 | |
| 54 | #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) |
| 55 | #define REGS_SIZE 0x1000 |
| 56 | #define MAX_MRU 1536 /* 0x600 */ |
| 57 | #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) |
| 58 | |
| 59 | #define NAPI_WEIGHT 16 |
| 60 | #define MDIO_INTERVAL (3 * HZ) |
| 61 | #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ |
| 62 | #define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */ |
| 63 | #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ |
| 64 | |
| 65 | #define NPE_ID(port_id) ((port_id) >> 4) |
| 66 | #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) |
| 67 | #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) |
| 68 | #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) |
| 69 | #define TXDONE_QUEUE 31 |
| 70 | |
| 71 | /* TX Control Registers */ |
| 72 | #define TX_CNTRL0_TX_EN 0x01 |
| 73 | #define TX_CNTRL0_HALFDUPLEX 0x02 |
| 74 | #define TX_CNTRL0_RETRY 0x04 |
| 75 | #define TX_CNTRL0_PAD_EN 0x08 |
| 76 | #define TX_CNTRL0_APPEND_FCS 0x10 |
| 77 | #define TX_CNTRL0_2DEFER 0x20 |
| 78 | #define TX_CNTRL0_RMII 0x40 /* reduced MII */ |
| 79 | #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ |
| 80 | |
| 81 | /* RX Control Registers */ |
| 82 | #define RX_CNTRL0_RX_EN 0x01 |
| 83 | #define RX_CNTRL0_PADSTRIP_EN 0x02 |
| 84 | #define RX_CNTRL0_SEND_FCS 0x04 |
| 85 | #define RX_CNTRL0_PAUSE_EN 0x08 |
| 86 | #define RX_CNTRL0_LOOP_EN 0x10 |
| 87 | #define RX_CNTRL0_ADDR_FLTR_EN 0x20 |
| 88 | #define RX_CNTRL0_RX_RUNT_EN 0x40 |
| 89 | #define RX_CNTRL0_BCAST_DIS 0x80 |
| 90 | #define RX_CNTRL1_DEFER_EN 0x01 |
| 91 | |
| 92 | /* Core Control Register */ |
| 93 | #define CORE_RESET 0x01 |
| 94 | #define CORE_RX_FIFO_FLUSH 0x02 |
| 95 | #define CORE_TX_FIFO_FLUSH 0x04 |
| 96 | #define CORE_SEND_JAM 0x08 |
| 97 | #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ |
| 98 | |
| 99 | #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ |
| 100 | TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ |
| 101 | TX_CNTRL0_2DEFER) |
| 102 | #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN |
| 103 | #define DEFAULT_CORE_CNTRL CORE_MDC_EN |
| 104 | |
| 105 | |
| 106 | /* NPE message codes */ |
| 107 | #define NPE_GETSTATUS 0x00 |
| 108 | #define NPE_EDB_SETPORTADDRESS 0x01 |
| 109 | #define NPE_EDB_GETMACADDRESSDATABASE 0x02 |
| 110 | #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 |
| 111 | #define NPE_GETSTATS 0x04 |
| 112 | #define NPE_RESETSTATS 0x05 |
| 113 | #define NPE_SETMAXFRAMELENGTHS 0x06 |
| 114 | #define NPE_VLAN_SETRXTAGMODE 0x07 |
| 115 | #define NPE_VLAN_SETDEFAULTRXVID 0x08 |
| 116 | #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 |
| 117 | #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A |
| 118 | #define NPE_VLAN_SETRXQOSENTRY 0x0B |
| 119 | #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C |
| 120 | #define NPE_STP_SETBLOCKINGSTATE 0x0D |
| 121 | #define NPE_FW_SETFIREWALLMODE 0x0E |
| 122 | #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F |
| 123 | #define NPE_PC_SETAPMACTABLE 0x11 |
| 124 | #define NPE_SETLOOPBACK_MODE 0x12 |
| 125 | #define NPE_PC_SETBSSIDTABLE 0x13 |
| 126 | #define NPE_ADDRESS_FILTER_CONFIG 0x14 |
| 127 | #define NPE_APPENDFCSCONFIG 0x15 |
| 128 | #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 |
| 129 | #define NPE_MAC_RECOVERY_START 0x17 |
| 130 | |
| 131 | |
| 132 | #ifdef __ARMEB__ |
| 133 | typedef struct sk_buff buffer_t; |
| 134 | #define free_buffer dev_kfree_skb |
| 135 | #define free_buffer_irq dev_kfree_skb_irq |
| 136 | #else |
| 137 | typedef void buffer_t; |
| 138 | #define free_buffer kfree |
| 139 | #define free_buffer_irq kfree |
| 140 | #endif |
| 141 | |
| 142 | struct eth_regs { |
| 143 | u32 tx_control[2], __res1[2]; /* 000 */ |
| 144 | u32 rx_control[2], __res2[2]; /* 010 */ |
| 145 | u32 random_seed, __res3[3]; /* 020 */ |
| 146 | u32 partial_empty_threshold, __res4; /* 030 */ |
| 147 | u32 partial_full_threshold, __res5; /* 038 */ |
| 148 | u32 tx_start_bytes, __res6[3]; /* 040 */ |
| 149 | u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ |
| 150 | u32 tx_2part_deferral[2], __res8[2]; /* 060 */ |
| 151 | u32 slot_time, __res9[3]; /* 070 */ |
| 152 | u32 mdio_command[4]; /* 080 */ |
| 153 | u32 mdio_status[4]; /* 090 */ |
| 154 | u32 mcast_mask[6], __res10[2]; /* 0A0 */ |
| 155 | u32 mcast_addr[6], __res11[2]; /* 0C0 */ |
| 156 | u32 int_clock_threshold, __res12[3]; /* 0E0 */ |
| 157 | u32 hw_addr[6], __res13[61]; /* 0F0 */ |
| 158 | u32 core_control; /* 1FC */ |
| 159 | }; |
| 160 | |
| 161 | struct port { |
| 162 | struct resource *mem_res; |
| 163 | struct eth_regs __iomem *regs; |
| 164 | struct npe *npe; |
| 165 | struct net_device *netdev; |
| 166 | struct napi_struct napi; |
| 167 | struct net_device_stats stat; |
| 168 | struct mii_if_info mii; |
| 169 | struct delayed_work mdio_thread; |
| 170 | struct eth_plat_info *plat; |
| 171 | buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; |
| 172 | struct desc *desc_tab; /* coherent */ |
| 173 | u32 desc_tab_phys; |
| 174 | int id; /* logical port ID */ |
| 175 | u16 mii_bmcr; |
| 176 | }; |
| 177 | |
| 178 | /* NPE message structure */ |
| 179 | struct msg { |
| 180 | #ifdef __ARMEB__ |
| 181 | u8 cmd, eth_id, byte2, byte3; |
| 182 | u8 byte4, byte5, byte6, byte7; |
| 183 | #else |
| 184 | u8 byte3, byte2, eth_id, cmd; |
| 185 | u8 byte7, byte6, byte5, byte4; |
| 186 | #endif |
| 187 | }; |
| 188 | |
| 189 | /* Ethernet packet descriptor */ |
| 190 | struct desc { |
| 191 | u32 next; /* pointer to next buffer, unused */ |
| 192 | |
| 193 | #ifdef __ARMEB__ |
| 194 | u16 buf_len; /* buffer length */ |
| 195 | u16 pkt_len; /* packet length */ |
| 196 | u32 data; /* pointer to data buffer in RAM */ |
| 197 | u8 dest_id; |
| 198 | u8 src_id; |
| 199 | u16 flags; |
| 200 | u8 qos; |
| 201 | u8 padlen; |
| 202 | u16 vlan_tci; |
| 203 | #else |
| 204 | u16 pkt_len; /* packet length */ |
| 205 | u16 buf_len; /* buffer length */ |
| 206 | u32 data; /* pointer to data buffer in RAM */ |
| 207 | u16 flags; |
| 208 | u8 src_id; |
| 209 | u8 dest_id; |
| 210 | u16 vlan_tci; |
| 211 | u8 padlen; |
| 212 | u8 qos; |
| 213 | #endif |
| 214 | |
| 215 | #ifdef __ARMEB__ |
| 216 | u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; |
| 217 | u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; |
| 218 | u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; |
| 219 | #else |
| 220 | u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; |
| 221 | u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; |
| 222 | u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; |
| 223 | #endif |
| 224 | }; |
| 225 | |
| 226 | |
| 227 | #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ |
| 228 | (n) * sizeof(struct desc)) |
| 229 | #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) |
| 230 | |
| 231 | #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ |
| 232 | ((n) + RX_DESCS) * sizeof(struct desc)) |
| 233 | #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) |
| 234 | |
| 235 | #ifndef __ARMEB__ |
| 236 | static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) |
| 237 | { |
| 238 | int i; |
| 239 | for (i = 0; i < cnt; i++) |
| 240 | dest[i] = swab32(src[i]); |
| 241 | } |
| 242 | #endif |
| 243 | |
| 244 | static spinlock_t mdio_lock; |
| 245 | static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ |
| 246 | static int ports_open; |
| 247 | static struct port *npe_port_tab[MAX_NPES]; |
| 248 | static struct dma_pool *dma_pool; |
| 249 | |
| 250 | |
| 251 | static u16 mdio_cmd(struct net_device *dev, int phy_id, int location, |
| 252 | int write, u16 cmd) |
| 253 | { |
| 254 | int cycles = 0; |
| 255 | |
| 256 | if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { |
| 257 | printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name); |
| 258 | return 0; |
| 259 | } |
| 260 | |
| 261 | if (write) { |
| 262 | __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); |
| 263 | __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); |
| 264 | } |
| 265 | __raw_writel(((phy_id << 5) | location) & 0xFF, |
| 266 | &mdio_regs->mdio_command[2]); |
| 267 | __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, |
| 268 | &mdio_regs->mdio_command[3]); |
| 269 | |
| 270 | while ((cycles < MAX_MDIO_RETRIES) && |
| 271 | (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { |
| 272 | udelay(1); |
| 273 | cycles++; |
| 274 | } |
| 275 | |
| 276 | if (cycles == MAX_MDIO_RETRIES) { |
| 277 | printk(KERN_ERR "%s: MII write failed\n", dev->name); |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | #if DEBUG_MDIO |
| 282 | printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name, |
| 283 | cycles); |
| 284 | #endif |
| 285 | |
| 286 | if (write) |
| 287 | return 0; |
| 288 | |
| 289 | if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { |
| 290 | printk(KERN_ERR "%s: MII read failed\n", dev->name); |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | |
| 295 | (__raw_readl(&mdio_regs->mdio_status[1]) << 8); |
| 296 | } |
| 297 | |
| 298 | static int mdio_read(struct net_device *dev, int phy_id, int location) |
| 299 | { |
| 300 | unsigned long flags; |
| 301 | u16 val; |
| 302 | |
| 303 | spin_lock_irqsave(&mdio_lock, flags); |
| 304 | val = mdio_cmd(dev, phy_id, location, 0, 0); |
| 305 | spin_unlock_irqrestore(&mdio_lock, flags); |
| 306 | return val; |
| 307 | } |
| 308 | |
| 309 | static void mdio_write(struct net_device *dev, int phy_id, int location, |
| 310 | int val) |
| 311 | { |
| 312 | unsigned long flags; |
| 313 | |
| 314 | spin_lock_irqsave(&mdio_lock, flags); |
| 315 | mdio_cmd(dev, phy_id, location, 1, val); |
| 316 | spin_unlock_irqrestore(&mdio_lock, flags); |
| 317 | } |
| 318 | |
| 319 | static void phy_reset(struct net_device *dev, int phy_id) |
| 320 | { |
| 321 | struct port *port = netdev_priv(dev); |
| 322 | int cycles = 0; |
| 323 | |
| 324 | mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET); |
| 325 | |
| 326 | while (cycles < MAX_MII_RESET_RETRIES) { |
| 327 | if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) { |
| 328 | #if DEBUG_MDIO |
| 329 | printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n", |
| 330 | dev->name, cycles); |
| 331 | #endif |
| 332 | return; |
| 333 | } |
| 334 | udelay(1); |
| 335 | cycles++; |
| 336 | } |
| 337 | |
| 338 | printk(KERN_ERR "%s: MII reset failed\n", dev->name); |
| 339 | } |
| 340 | |
| 341 | static void eth_set_duplex(struct port *port) |
| 342 | { |
| 343 | if (port->mii.full_duplex) |
| 344 | __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, |
| 345 | &port->regs->tx_control[0]); |
| 346 | else |
| 347 | __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, |
| 348 | &port->regs->tx_control[0]); |
| 349 | } |
| 350 | |
| 351 | |
| 352 | static void phy_check_media(struct port *port, int init) |
| 353 | { |
| 354 | if (mii_check_media(&port->mii, 1, init)) |
| 355 | eth_set_duplex(port); |
| 356 | if (port->mii.force_media) { /* mii_check_media() doesn't work */ |
| 357 | struct net_device *dev = port->netdev; |
| 358 | int cur_link = mii_link_ok(&port->mii); |
| 359 | int prev_link = netif_carrier_ok(dev); |
| 360 | |
| 361 | if (!prev_link && cur_link) { |
| 362 | printk(KERN_INFO "%s: link up\n", dev->name); |
| 363 | netif_carrier_on(dev); |
| 364 | } else if (prev_link && !cur_link) { |
| 365 | printk(KERN_INFO "%s: link down\n", dev->name); |
| 366 | netif_carrier_off(dev); |
| 367 | } |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | |
| 372 | static void mdio_thread(struct work_struct *work) |
| 373 | { |
| 374 | struct port *port = container_of(work, struct port, mdio_thread.work); |
| 375 | |
| 376 | phy_check_media(port, 0); |
| 377 | schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL); |
| 378 | } |
| 379 | |
| 380 | |
| 381 | static inline void debug_pkt(struct net_device *dev, const char *func, |
| 382 | u8 *data, int len) |
| 383 | { |
| 384 | #if DEBUG_PKT_BYTES |
| 385 | int i; |
| 386 | |
| 387 | printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); |
| 388 | for (i = 0; i < len; i++) { |
| 389 | if (i >= DEBUG_PKT_BYTES) |
| 390 | break; |
| 391 | printk("%s%02X", |
| 392 | ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", |
| 393 | data[i]); |
| 394 | } |
| 395 | printk("\n"); |
| 396 | #endif |
| 397 | } |
| 398 | |
| 399 | |
| 400 | static inline void debug_desc(u32 phys, struct desc *desc) |
| 401 | { |
| 402 | #if DEBUG_DESC |
| 403 | printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" |
| 404 | " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", |
| 405 | phys, desc->next, desc->buf_len, desc->pkt_len, |
| 406 | desc->data, desc->dest_id, desc->src_id, desc->flags, |
| 407 | desc->qos, desc->padlen, desc->vlan_tci, |
| 408 | desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, |
| 409 | desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, |
| 410 | desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, |
| 411 | desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); |
| 412 | #endif |
| 413 | } |
| 414 | |
| 415 | static inline void debug_queue(unsigned int queue, int is_get, u32 phys) |
| 416 | { |
| 417 | #if DEBUG_QUEUES |
| 418 | static struct { |
| 419 | int queue; |
| 420 | char *name; |
| 421 | } names[] = { |
| 422 | { TX_QUEUE(0x10), "TX#0 " }, |
| 423 | { TX_QUEUE(0x20), "TX#1 " }, |
| 424 | { TX_QUEUE(0x00), "TX#2 " }, |
| 425 | { RXFREE_QUEUE(0x10), "RX-free#0 " }, |
| 426 | { RXFREE_QUEUE(0x20), "RX-free#1 " }, |
| 427 | { RXFREE_QUEUE(0x00), "RX-free#2 " }, |
| 428 | { TXDONE_QUEUE, "TX-done " }, |
| 429 | }; |
| 430 | int i; |
| 431 | |
| 432 | for (i = 0; i < ARRAY_SIZE(names); i++) |
| 433 | if (names[i].queue == queue) |
| 434 | break; |
| 435 | |
| 436 | printk(KERN_DEBUG "Queue %i %s%s %X\n", queue, |
| 437 | i < ARRAY_SIZE(names) ? names[i].name : "", |
| 438 | is_get ? "->" : "<-", phys); |
| 439 | #endif |
| 440 | } |
| 441 | |
| 442 | static inline u32 queue_get_entry(unsigned int queue) |
| 443 | { |
| 444 | u32 phys = qmgr_get_entry(queue); |
| 445 | debug_queue(queue, 1, phys); |
| 446 | return phys; |
| 447 | } |
| 448 | |
| 449 | static inline int queue_get_desc(unsigned int queue, struct port *port, |
| 450 | int is_tx) |
| 451 | { |
| 452 | u32 phys, tab_phys, n_desc; |
| 453 | struct desc *tab; |
| 454 | |
| 455 | if (!(phys = queue_get_entry(queue))) |
| 456 | return -1; |
| 457 | |
| 458 | phys &= ~0x1F; /* mask out non-address bits */ |
| 459 | tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); |
| 460 | tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); |
| 461 | n_desc = (phys - tab_phys) / sizeof(struct desc); |
| 462 | BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); |
| 463 | debug_desc(phys, &tab[n_desc]); |
| 464 | BUG_ON(tab[n_desc].next); |
| 465 | return n_desc; |
| 466 | } |
| 467 | |
| 468 | static inline void queue_put_desc(unsigned int queue, u32 phys, |
| 469 | struct desc *desc) |
| 470 | { |
| 471 | debug_queue(queue, 0, phys); |
| 472 | debug_desc(phys, desc); |
| 473 | BUG_ON(phys & 0x1F); |
| 474 | qmgr_put_entry(queue, phys); |
| 475 | BUG_ON(qmgr_stat_overflow(queue)); |
| 476 | } |
| 477 | |
| 478 | |
| 479 | static inline void dma_unmap_tx(struct port *port, struct desc *desc) |
| 480 | { |
| 481 | #ifdef __ARMEB__ |
| 482 | dma_unmap_single(&port->netdev->dev, desc->data, |
| 483 | desc->buf_len, DMA_TO_DEVICE); |
| 484 | #else |
| 485 | dma_unmap_single(&port->netdev->dev, desc->data & ~3, |
| 486 | ALIGN((desc->data & 3) + desc->buf_len, 4), |
| 487 | DMA_TO_DEVICE); |
| 488 | #endif |
| 489 | } |
| 490 | |
| 491 | |
| 492 | static void eth_rx_irq(void *pdev) |
| 493 | { |
| 494 | struct net_device *dev = pdev; |
| 495 | struct port *port = netdev_priv(dev); |
| 496 | |
| 497 | #if DEBUG_RX |
| 498 | printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); |
| 499 | #endif |
| 500 | qmgr_disable_irq(port->plat->rxq); |
| 501 | netif_rx_schedule(dev, &port->napi); |
| 502 | } |
| 503 | |
| 504 | static int eth_poll(struct napi_struct *napi, int budget) |
| 505 | { |
| 506 | struct port *port = container_of(napi, struct port, napi); |
| 507 | struct net_device *dev = port->netdev; |
| 508 | unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); |
| 509 | int received = 0; |
| 510 | |
| 511 | #if DEBUG_RX |
| 512 | printk(KERN_DEBUG "%s: eth_poll\n", dev->name); |
| 513 | #endif |
| 514 | |
| 515 | while (received < budget) { |
| 516 | struct sk_buff *skb; |
| 517 | struct desc *desc; |
| 518 | int n; |
| 519 | #ifdef __ARMEB__ |
| 520 | struct sk_buff *temp; |
| 521 | u32 phys; |
| 522 | #endif |
| 523 | |
| 524 | if ((n = queue_get_desc(rxq, port, 0)) < 0) { |
Krzysztof Halasa | dac2f83 | 2008-04-20 19:06:39 +0200 | [diff] [blame] | 525 | #if DEBUG_RX |
| 526 | printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n", |
| 527 | dev->name); |
| 528 | #endif |
| 529 | netif_rx_complete(dev, napi); |
| 530 | qmgr_enable_irq(rxq); |
| 531 | if (!qmgr_stat_empty(rxq) && |
| 532 | netif_rx_reschedule(dev, napi)) { |
| 533 | #if DEBUG_RX |
| 534 | printk(KERN_DEBUG "%s: eth_poll" |
| 535 | " netif_rx_reschedule successed\n", |
| 536 | dev->name); |
| 537 | #endif |
| 538 | qmgr_disable_irq(rxq); |
| 539 | continue; |
| 540 | } |
| 541 | #if DEBUG_RX |
| 542 | printk(KERN_DEBUG "%s: eth_poll all done\n", |
| 543 | dev->name); |
| 544 | #endif |
Krzysztof Halasa | 9076689 | 2008-07-09 13:10:32 +0200 | [diff] [blame] | 545 | return received; /* all work done */ |
Krzysztof Halasa | dac2f83 | 2008-04-20 19:06:39 +0200 | [diff] [blame] | 546 | } |
| 547 | |
| 548 | desc = rx_desc_ptr(port, n); |
| 549 | |
| 550 | #ifdef __ARMEB__ |
| 551 | if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { |
| 552 | phys = dma_map_single(&dev->dev, skb->data, |
| 553 | RX_BUFF_SIZE, DMA_FROM_DEVICE); |
Mikael Pettersson | 7144dec | 2008-08-13 21:08:14 +0200 | [diff] [blame] | 554 | if (dma_mapping_error(&dev->dev, phys)) { |
Krzysztof Halasa | dac2f83 | 2008-04-20 19:06:39 +0200 | [diff] [blame] | 555 | dev_kfree_skb(skb); |
| 556 | skb = NULL; |
| 557 | } |
| 558 | } |
| 559 | #else |
| 560 | skb = netdev_alloc_skb(dev, |
| 561 | ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); |
| 562 | #endif |
| 563 | |
| 564 | if (!skb) { |
| 565 | port->stat.rx_dropped++; |
| 566 | /* put the desc back on RX-ready queue */ |
| 567 | desc->buf_len = MAX_MRU; |
| 568 | desc->pkt_len = 0; |
| 569 | queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); |
| 570 | continue; |
| 571 | } |
| 572 | |
| 573 | /* process received frame */ |
| 574 | #ifdef __ARMEB__ |
| 575 | temp = skb; |
| 576 | skb = port->rx_buff_tab[n]; |
| 577 | dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, |
| 578 | RX_BUFF_SIZE, DMA_FROM_DEVICE); |
| 579 | #else |
| 580 | dma_sync_single(&dev->dev, desc->data - NET_IP_ALIGN, |
| 581 | RX_BUFF_SIZE, DMA_FROM_DEVICE); |
| 582 | memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], |
| 583 | ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); |
| 584 | #endif |
| 585 | skb_reserve(skb, NET_IP_ALIGN); |
| 586 | skb_put(skb, desc->pkt_len); |
| 587 | |
| 588 | debug_pkt(dev, "eth_poll", skb->data, skb->len); |
| 589 | |
| 590 | skb->protocol = eth_type_trans(skb, dev); |
| 591 | dev->last_rx = jiffies; |
| 592 | port->stat.rx_packets++; |
| 593 | port->stat.rx_bytes += skb->len; |
| 594 | netif_receive_skb(skb); |
| 595 | |
| 596 | /* put the new buffer on RX-free queue */ |
| 597 | #ifdef __ARMEB__ |
| 598 | port->rx_buff_tab[n] = temp; |
| 599 | desc->data = phys + NET_IP_ALIGN; |
| 600 | #endif |
| 601 | desc->buf_len = MAX_MRU; |
| 602 | desc->pkt_len = 0; |
| 603 | queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); |
| 604 | received++; |
| 605 | } |
| 606 | |
| 607 | #if DEBUG_RX |
| 608 | printk(KERN_DEBUG "eth_poll(): end, not all work done\n"); |
| 609 | #endif |
| 610 | return received; /* not all work done */ |
| 611 | } |
| 612 | |
| 613 | |
| 614 | static void eth_txdone_irq(void *unused) |
| 615 | { |
| 616 | u32 phys; |
| 617 | |
| 618 | #if DEBUG_TX |
| 619 | printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); |
| 620 | #endif |
| 621 | while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) { |
| 622 | u32 npe_id, n_desc; |
| 623 | struct port *port; |
| 624 | struct desc *desc; |
| 625 | int start; |
| 626 | |
| 627 | npe_id = phys & 3; |
| 628 | BUG_ON(npe_id >= MAX_NPES); |
| 629 | port = npe_port_tab[npe_id]; |
| 630 | BUG_ON(!port); |
| 631 | phys &= ~0x1F; /* mask out non-address bits */ |
| 632 | n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); |
| 633 | BUG_ON(n_desc >= TX_DESCS); |
| 634 | desc = tx_desc_ptr(port, n_desc); |
| 635 | debug_desc(phys, desc); |
| 636 | |
| 637 | if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ |
| 638 | port->stat.tx_packets++; |
| 639 | port->stat.tx_bytes += desc->pkt_len; |
| 640 | |
| 641 | dma_unmap_tx(port, desc); |
| 642 | #if DEBUG_TX |
| 643 | printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", |
| 644 | port->netdev->name, port->tx_buff_tab[n_desc]); |
| 645 | #endif |
| 646 | free_buffer_irq(port->tx_buff_tab[n_desc]); |
| 647 | port->tx_buff_tab[n_desc] = NULL; |
| 648 | } |
| 649 | |
| 650 | start = qmgr_stat_empty(port->plat->txreadyq); |
| 651 | queue_put_desc(port->plat->txreadyq, phys, desc); |
| 652 | if (start) { |
| 653 | #if DEBUG_TX |
| 654 | printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", |
| 655 | port->netdev->name); |
| 656 | #endif |
| 657 | netif_wake_queue(port->netdev); |
| 658 | } |
| 659 | } |
| 660 | } |
| 661 | |
| 662 | static int eth_xmit(struct sk_buff *skb, struct net_device *dev) |
| 663 | { |
| 664 | struct port *port = netdev_priv(dev); |
| 665 | unsigned int txreadyq = port->plat->txreadyq; |
| 666 | int len, offset, bytes, n; |
| 667 | void *mem; |
| 668 | u32 phys; |
| 669 | struct desc *desc; |
| 670 | |
| 671 | #if DEBUG_TX |
| 672 | printk(KERN_DEBUG "%s: eth_xmit\n", dev->name); |
| 673 | #endif |
| 674 | |
| 675 | if (unlikely(skb->len > MAX_MRU)) { |
| 676 | dev_kfree_skb(skb); |
| 677 | port->stat.tx_errors++; |
| 678 | return NETDEV_TX_OK; |
| 679 | } |
| 680 | |
| 681 | debug_pkt(dev, "eth_xmit", skb->data, skb->len); |
| 682 | |
| 683 | len = skb->len; |
| 684 | #ifdef __ARMEB__ |
| 685 | offset = 0; /* no need to keep alignment */ |
| 686 | bytes = len; |
| 687 | mem = skb->data; |
| 688 | #else |
| 689 | offset = (int)skb->data & 3; /* keep 32-bit alignment */ |
| 690 | bytes = ALIGN(offset + len, 4); |
| 691 | if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { |
| 692 | dev_kfree_skb(skb); |
| 693 | port->stat.tx_dropped++; |
| 694 | return NETDEV_TX_OK; |
| 695 | } |
| 696 | memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); |
| 697 | dev_kfree_skb(skb); |
| 698 | #endif |
| 699 | |
| 700 | phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); |
Mikael Pettersson | 7144dec | 2008-08-13 21:08:14 +0200 | [diff] [blame] | 701 | if (dma_mapping_error(&dev->dev, phys)) { |
Krzysztof Halasa | dac2f83 | 2008-04-20 19:06:39 +0200 | [diff] [blame] | 702 | #ifdef __ARMEB__ |
| 703 | dev_kfree_skb(skb); |
| 704 | #else |
| 705 | kfree(mem); |
| 706 | #endif |
| 707 | port->stat.tx_dropped++; |
| 708 | return NETDEV_TX_OK; |
| 709 | } |
| 710 | |
| 711 | n = queue_get_desc(txreadyq, port, 1); |
| 712 | BUG_ON(n < 0); |
| 713 | desc = tx_desc_ptr(port, n); |
| 714 | |
| 715 | #ifdef __ARMEB__ |
| 716 | port->tx_buff_tab[n] = skb; |
| 717 | #else |
| 718 | port->tx_buff_tab[n] = mem; |
| 719 | #endif |
| 720 | desc->data = phys + offset; |
| 721 | desc->buf_len = desc->pkt_len = len; |
| 722 | |
| 723 | /* NPE firmware pads short frames with zeros internally */ |
| 724 | wmb(); |
| 725 | queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); |
| 726 | dev->trans_start = jiffies; |
| 727 | |
| 728 | if (qmgr_stat_empty(txreadyq)) { |
| 729 | #if DEBUG_TX |
| 730 | printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name); |
| 731 | #endif |
| 732 | netif_stop_queue(dev); |
| 733 | /* we could miss TX ready interrupt */ |
| 734 | if (!qmgr_stat_empty(txreadyq)) { |
| 735 | #if DEBUG_TX |
| 736 | printk(KERN_DEBUG "%s: eth_xmit ready again\n", |
| 737 | dev->name); |
| 738 | #endif |
| 739 | netif_wake_queue(dev); |
| 740 | } |
| 741 | } |
| 742 | |
| 743 | #if DEBUG_TX |
| 744 | printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name); |
| 745 | #endif |
| 746 | return NETDEV_TX_OK; |
| 747 | } |
| 748 | |
| 749 | |
| 750 | static struct net_device_stats *eth_stats(struct net_device *dev) |
| 751 | { |
| 752 | struct port *port = netdev_priv(dev); |
| 753 | return &port->stat; |
| 754 | } |
| 755 | |
| 756 | static void eth_set_mcast_list(struct net_device *dev) |
| 757 | { |
| 758 | struct port *port = netdev_priv(dev); |
| 759 | struct dev_mc_list *mclist = dev->mc_list; |
| 760 | u8 diffs[ETH_ALEN], *addr; |
| 761 | int cnt = dev->mc_count, i; |
| 762 | |
| 763 | if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) { |
| 764 | __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, |
| 765 | &port->regs->rx_control[0]); |
| 766 | return; |
| 767 | } |
| 768 | |
| 769 | memset(diffs, 0, ETH_ALEN); |
| 770 | addr = mclist->dmi_addr; /* first MAC address */ |
| 771 | |
| 772 | while (--cnt && (mclist = mclist->next)) |
| 773 | for (i = 0; i < ETH_ALEN; i++) |
| 774 | diffs[i] |= addr[i] ^ mclist->dmi_addr[i]; |
| 775 | |
| 776 | for (i = 0; i < ETH_ALEN; i++) { |
| 777 | __raw_writel(addr[i], &port->regs->mcast_addr[i]); |
| 778 | __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); |
| 779 | } |
| 780 | |
| 781 | __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, |
| 782 | &port->regs->rx_control[0]); |
| 783 | } |
| 784 | |
| 785 | |
| 786 | static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) |
| 787 | { |
| 788 | struct port *port = netdev_priv(dev); |
| 789 | unsigned int duplex_chg; |
| 790 | int err; |
| 791 | |
| 792 | if (!netif_running(dev)) |
| 793 | return -EINVAL; |
| 794 | err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg); |
| 795 | if (duplex_chg) |
| 796 | eth_set_duplex(port); |
| 797 | return err; |
| 798 | } |
| 799 | |
| 800 | |
| 801 | static int request_queues(struct port *port) |
| 802 | { |
| 803 | int err; |
| 804 | |
| 805 | err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0); |
| 806 | if (err) |
| 807 | return err; |
| 808 | |
| 809 | err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0); |
| 810 | if (err) |
| 811 | goto rel_rxfree; |
| 812 | |
| 813 | err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0); |
| 814 | if (err) |
| 815 | goto rel_rx; |
| 816 | |
| 817 | err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0); |
| 818 | if (err) |
| 819 | goto rel_tx; |
| 820 | |
| 821 | /* TX-done queue handles skbs sent out by the NPEs */ |
| 822 | if (!ports_open) { |
| 823 | err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0); |
| 824 | if (err) |
| 825 | goto rel_txready; |
| 826 | } |
| 827 | return 0; |
| 828 | |
| 829 | rel_txready: |
| 830 | qmgr_release_queue(port->plat->txreadyq); |
| 831 | rel_tx: |
| 832 | qmgr_release_queue(TX_QUEUE(port->id)); |
| 833 | rel_rx: |
| 834 | qmgr_release_queue(port->plat->rxq); |
| 835 | rel_rxfree: |
| 836 | qmgr_release_queue(RXFREE_QUEUE(port->id)); |
| 837 | printk(KERN_DEBUG "%s: unable to request hardware queues\n", |
| 838 | port->netdev->name); |
| 839 | return err; |
| 840 | } |
| 841 | |
| 842 | static void release_queues(struct port *port) |
| 843 | { |
| 844 | qmgr_release_queue(RXFREE_QUEUE(port->id)); |
| 845 | qmgr_release_queue(port->plat->rxq); |
| 846 | qmgr_release_queue(TX_QUEUE(port->id)); |
| 847 | qmgr_release_queue(port->plat->txreadyq); |
| 848 | |
| 849 | if (!ports_open) |
| 850 | qmgr_release_queue(TXDONE_QUEUE); |
| 851 | } |
| 852 | |
| 853 | static int init_queues(struct port *port) |
| 854 | { |
| 855 | int i; |
| 856 | |
| 857 | if (!ports_open) |
| 858 | if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, |
| 859 | POOL_ALLOC_SIZE, 32, 0))) |
| 860 | return -ENOMEM; |
| 861 | |
| 862 | if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, |
| 863 | &port->desc_tab_phys))) |
| 864 | return -ENOMEM; |
| 865 | memset(port->desc_tab, 0, POOL_ALLOC_SIZE); |
| 866 | memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ |
| 867 | memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); |
| 868 | |
| 869 | /* Setup RX buffers */ |
| 870 | for (i = 0; i < RX_DESCS; i++) { |
| 871 | struct desc *desc = rx_desc_ptr(port, i); |
| 872 | buffer_t *buff; /* skb or kmalloc()ated memory */ |
| 873 | void *data; |
| 874 | #ifdef __ARMEB__ |
| 875 | if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) |
| 876 | return -ENOMEM; |
| 877 | data = buff->data; |
| 878 | #else |
| 879 | if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) |
| 880 | return -ENOMEM; |
| 881 | data = buff; |
| 882 | #endif |
| 883 | desc->buf_len = MAX_MRU; |
| 884 | desc->data = dma_map_single(&port->netdev->dev, data, |
| 885 | RX_BUFF_SIZE, DMA_FROM_DEVICE); |
Mikael Pettersson | 7144dec | 2008-08-13 21:08:14 +0200 | [diff] [blame] | 886 | if (dma_mapping_error(&port->netdev->dev, desc->data)) { |
Krzysztof Halasa | dac2f83 | 2008-04-20 19:06:39 +0200 | [diff] [blame] | 887 | free_buffer(buff); |
| 888 | return -EIO; |
| 889 | } |
| 890 | desc->data += NET_IP_ALIGN; |
| 891 | port->rx_buff_tab[i] = buff; |
| 892 | } |
| 893 | |
| 894 | return 0; |
| 895 | } |
| 896 | |
| 897 | static void destroy_queues(struct port *port) |
| 898 | { |
| 899 | int i; |
| 900 | |
| 901 | if (port->desc_tab) { |
| 902 | for (i = 0; i < RX_DESCS; i++) { |
| 903 | struct desc *desc = rx_desc_ptr(port, i); |
| 904 | buffer_t *buff = port->rx_buff_tab[i]; |
| 905 | if (buff) { |
| 906 | dma_unmap_single(&port->netdev->dev, |
| 907 | desc->data - NET_IP_ALIGN, |
| 908 | RX_BUFF_SIZE, DMA_FROM_DEVICE); |
| 909 | free_buffer(buff); |
| 910 | } |
| 911 | } |
| 912 | for (i = 0; i < TX_DESCS; i++) { |
| 913 | struct desc *desc = tx_desc_ptr(port, i); |
| 914 | buffer_t *buff = port->tx_buff_tab[i]; |
| 915 | if (buff) { |
| 916 | dma_unmap_tx(port, desc); |
| 917 | free_buffer(buff); |
| 918 | } |
| 919 | } |
| 920 | dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); |
| 921 | port->desc_tab = NULL; |
| 922 | } |
| 923 | |
| 924 | if (!ports_open && dma_pool) { |
| 925 | dma_pool_destroy(dma_pool); |
| 926 | dma_pool = NULL; |
| 927 | } |
| 928 | } |
| 929 | |
| 930 | static int eth_open(struct net_device *dev) |
| 931 | { |
| 932 | struct port *port = netdev_priv(dev); |
| 933 | struct npe *npe = port->npe; |
| 934 | struct msg msg; |
| 935 | int i, err; |
| 936 | |
| 937 | if (!npe_running(npe)) { |
| 938 | err = npe_load_firmware(npe, npe_name(npe), &dev->dev); |
| 939 | if (err) |
| 940 | return err; |
| 941 | |
| 942 | if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { |
| 943 | printk(KERN_ERR "%s: %s not responding\n", dev->name, |
| 944 | npe_name(npe)); |
| 945 | return -EIO; |
| 946 | } |
| 947 | } |
| 948 | |
| 949 | mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr); |
| 950 | |
| 951 | memset(&msg, 0, sizeof(msg)); |
| 952 | msg.cmd = NPE_VLAN_SETRXQOSENTRY; |
| 953 | msg.eth_id = port->id; |
| 954 | msg.byte5 = port->plat->rxq | 0x80; |
| 955 | msg.byte7 = port->plat->rxq << 4; |
| 956 | for (i = 0; i < 8; i++) { |
| 957 | msg.byte3 = i; |
| 958 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) |
| 959 | return -EIO; |
| 960 | } |
| 961 | |
| 962 | msg.cmd = NPE_EDB_SETPORTADDRESS; |
| 963 | msg.eth_id = PHYSICAL_ID(port->id); |
| 964 | msg.byte2 = dev->dev_addr[0]; |
| 965 | msg.byte3 = dev->dev_addr[1]; |
| 966 | msg.byte4 = dev->dev_addr[2]; |
| 967 | msg.byte5 = dev->dev_addr[3]; |
| 968 | msg.byte6 = dev->dev_addr[4]; |
| 969 | msg.byte7 = dev->dev_addr[5]; |
| 970 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) |
| 971 | return -EIO; |
| 972 | |
| 973 | memset(&msg, 0, sizeof(msg)); |
| 974 | msg.cmd = NPE_FW_SETFIREWALLMODE; |
| 975 | msg.eth_id = port->id; |
| 976 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) |
| 977 | return -EIO; |
| 978 | |
| 979 | if ((err = request_queues(port)) != 0) |
| 980 | return err; |
| 981 | |
| 982 | if ((err = init_queues(port)) != 0) { |
| 983 | destroy_queues(port); |
| 984 | release_queues(port); |
| 985 | return err; |
| 986 | } |
| 987 | |
| 988 | for (i = 0; i < ETH_ALEN; i++) |
| 989 | __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); |
| 990 | __raw_writel(0x08, &port->regs->random_seed); |
| 991 | __raw_writel(0x12, &port->regs->partial_empty_threshold); |
| 992 | __raw_writel(0x30, &port->regs->partial_full_threshold); |
| 993 | __raw_writel(0x08, &port->regs->tx_start_bytes); |
| 994 | __raw_writel(0x15, &port->regs->tx_deferral); |
| 995 | __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); |
| 996 | __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); |
| 997 | __raw_writel(0x80, &port->regs->slot_time); |
| 998 | __raw_writel(0x01, &port->regs->int_clock_threshold); |
| 999 | |
| 1000 | /* Populate queues with buffers, no failure after this point */ |
| 1001 | for (i = 0; i < TX_DESCS; i++) |
| 1002 | queue_put_desc(port->plat->txreadyq, |
| 1003 | tx_desc_phys(port, i), tx_desc_ptr(port, i)); |
| 1004 | |
| 1005 | for (i = 0; i < RX_DESCS; i++) |
| 1006 | queue_put_desc(RXFREE_QUEUE(port->id), |
| 1007 | rx_desc_phys(port, i), rx_desc_ptr(port, i)); |
| 1008 | |
| 1009 | __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); |
| 1010 | __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); |
| 1011 | __raw_writel(0, &port->regs->rx_control[1]); |
| 1012 | __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); |
| 1013 | |
| 1014 | napi_enable(&port->napi); |
| 1015 | phy_check_media(port, 1); |
| 1016 | eth_set_mcast_list(dev); |
| 1017 | netif_start_queue(dev); |
| 1018 | schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL); |
| 1019 | |
| 1020 | qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, |
| 1021 | eth_rx_irq, dev); |
| 1022 | if (!ports_open) { |
| 1023 | qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, |
| 1024 | eth_txdone_irq, NULL); |
| 1025 | qmgr_enable_irq(TXDONE_QUEUE); |
| 1026 | } |
| 1027 | ports_open++; |
| 1028 | /* we may already have RX data, enables IRQ */ |
| 1029 | netif_rx_schedule(dev, &port->napi); |
| 1030 | return 0; |
| 1031 | } |
| 1032 | |
| 1033 | static int eth_close(struct net_device *dev) |
| 1034 | { |
| 1035 | struct port *port = netdev_priv(dev); |
| 1036 | struct msg msg; |
| 1037 | int buffs = RX_DESCS; /* allocated RX buffers */ |
| 1038 | int i; |
| 1039 | |
| 1040 | ports_open--; |
| 1041 | qmgr_disable_irq(port->plat->rxq); |
| 1042 | napi_disable(&port->napi); |
| 1043 | netif_stop_queue(dev); |
| 1044 | |
| 1045 | while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) |
| 1046 | buffs--; |
| 1047 | |
| 1048 | memset(&msg, 0, sizeof(msg)); |
| 1049 | msg.cmd = NPE_SETLOOPBACK_MODE; |
| 1050 | msg.eth_id = port->id; |
| 1051 | msg.byte3 = 1; |
| 1052 | if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) |
| 1053 | printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name); |
| 1054 | |
| 1055 | i = 0; |
| 1056 | do { /* drain RX buffers */ |
| 1057 | while (queue_get_desc(port->plat->rxq, port, 0) >= 0) |
| 1058 | buffs--; |
| 1059 | if (!buffs) |
| 1060 | break; |
| 1061 | if (qmgr_stat_empty(TX_QUEUE(port->id))) { |
| 1062 | /* we have to inject some packet */ |
| 1063 | struct desc *desc; |
| 1064 | u32 phys; |
| 1065 | int n = queue_get_desc(port->plat->txreadyq, port, 1); |
| 1066 | BUG_ON(n < 0); |
| 1067 | desc = tx_desc_ptr(port, n); |
| 1068 | phys = tx_desc_phys(port, n); |
| 1069 | desc->buf_len = desc->pkt_len = 1; |
| 1070 | wmb(); |
| 1071 | queue_put_desc(TX_QUEUE(port->id), phys, desc); |
| 1072 | } |
| 1073 | udelay(1); |
| 1074 | } while (++i < MAX_CLOSE_WAIT); |
| 1075 | |
| 1076 | if (buffs) |
| 1077 | printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" |
| 1078 | " left in NPE\n", dev->name, buffs); |
| 1079 | #if DEBUG_CLOSE |
| 1080 | if (!buffs) |
| 1081 | printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i); |
| 1082 | #endif |
| 1083 | |
| 1084 | buffs = TX_DESCS; |
| 1085 | while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) |
| 1086 | buffs--; /* cancel TX */ |
| 1087 | |
| 1088 | i = 0; |
| 1089 | do { |
| 1090 | while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) |
| 1091 | buffs--; |
| 1092 | if (!buffs) |
| 1093 | break; |
| 1094 | } while (++i < MAX_CLOSE_WAIT); |
| 1095 | |
| 1096 | if (buffs) |
| 1097 | printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " |
| 1098 | "left in NPE\n", dev->name, buffs); |
| 1099 | #if DEBUG_CLOSE |
| 1100 | if (!buffs) |
| 1101 | printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); |
| 1102 | #endif |
| 1103 | |
| 1104 | msg.byte3 = 0; |
| 1105 | if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) |
| 1106 | printk(KERN_CRIT "%s: unable to disable loopback\n", |
| 1107 | dev->name); |
| 1108 | |
| 1109 | port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) & |
| 1110 | ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */ |
| 1111 | mdio_write(dev, port->plat->phy, MII_BMCR, |
| 1112 | port->mii_bmcr | BMCR_PDOWN); |
| 1113 | |
| 1114 | if (!ports_open) |
| 1115 | qmgr_disable_irq(TXDONE_QUEUE); |
| 1116 | cancel_rearming_delayed_work(&port->mdio_thread); |
| 1117 | destroy_queues(port); |
| 1118 | release_queues(port); |
| 1119 | return 0; |
| 1120 | } |
| 1121 | |
| 1122 | static int __devinit eth_init_one(struct platform_device *pdev) |
| 1123 | { |
| 1124 | struct port *port; |
| 1125 | struct net_device *dev; |
| 1126 | struct eth_plat_info *plat = pdev->dev.platform_data; |
| 1127 | u32 regs_phys; |
| 1128 | int err; |
| 1129 | |
| 1130 | if (!(dev = alloc_etherdev(sizeof(struct port)))) |
| 1131 | return -ENOMEM; |
| 1132 | |
| 1133 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 1134 | port = netdev_priv(dev); |
| 1135 | port->netdev = dev; |
| 1136 | port->id = pdev->id; |
| 1137 | |
| 1138 | switch (port->id) { |
| 1139 | case IXP4XX_ETH_NPEA: |
| 1140 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT; |
| 1141 | regs_phys = IXP4XX_EthA_BASE_PHYS; |
| 1142 | break; |
| 1143 | case IXP4XX_ETH_NPEB: |
| 1144 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; |
| 1145 | regs_phys = IXP4XX_EthB_BASE_PHYS; |
| 1146 | break; |
| 1147 | case IXP4XX_ETH_NPEC: |
| 1148 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; |
| 1149 | regs_phys = IXP4XX_EthC_BASE_PHYS; |
| 1150 | break; |
| 1151 | default: |
| 1152 | err = -ENOSYS; |
| 1153 | goto err_free; |
| 1154 | } |
| 1155 | |
| 1156 | dev->open = eth_open; |
| 1157 | dev->hard_start_xmit = eth_xmit; |
| 1158 | dev->stop = eth_close; |
| 1159 | dev->get_stats = eth_stats; |
| 1160 | dev->do_ioctl = eth_ioctl; |
| 1161 | dev->set_multicast_list = eth_set_mcast_list; |
| 1162 | dev->tx_queue_len = 100; |
| 1163 | |
| 1164 | netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT); |
| 1165 | |
| 1166 | if (!(port->npe = npe_request(NPE_ID(port->id)))) { |
| 1167 | err = -EIO; |
| 1168 | goto err_free; |
| 1169 | } |
| 1170 | |
| 1171 | if (register_netdev(dev)) { |
| 1172 | err = -EIO; |
| 1173 | goto err_npe_rel; |
| 1174 | } |
| 1175 | |
| 1176 | port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name); |
| 1177 | if (!port->mem_res) { |
| 1178 | err = -EBUSY; |
| 1179 | goto err_unreg; |
| 1180 | } |
| 1181 | |
| 1182 | port->plat = plat; |
| 1183 | npe_port_tab[NPE_ID(port->id)] = port; |
| 1184 | memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN); |
| 1185 | |
| 1186 | platform_set_drvdata(pdev, dev); |
| 1187 | |
| 1188 | __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, |
| 1189 | &port->regs->core_control); |
| 1190 | udelay(50); |
| 1191 | __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); |
| 1192 | udelay(50); |
| 1193 | |
| 1194 | port->mii.dev = dev; |
| 1195 | port->mii.mdio_read = mdio_read; |
| 1196 | port->mii.mdio_write = mdio_write; |
| 1197 | port->mii.phy_id = plat->phy; |
| 1198 | port->mii.phy_id_mask = 0x1F; |
| 1199 | port->mii.reg_num_mask = 0x1F; |
| 1200 | |
| 1201 | printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, |
| 1202 | npe_name(port->npe)); |
| 1203 | |
| 1204 | phy_reset(dev, plat->phy); |
| 1205 | port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) & |
| 1206 | ~(BMCR_RESET | BMCR_PDOWN); |
| 1207 | mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN); |
| 1208 | |
| 1209 | INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread); |
| 1210 | return 0; |
| 1211 | |
| 1212 | err_unreg: |
| 1213 | unregister_netdev(dev); |
| 1214 | err_npe_rel: |
| 1215 | npe_release(port->npe); |
| 1216 | err_free: |
| 1217 | free_netdev(dev); |
| 1218 | return err; |
| 1219 | } |
| 1220 | |
| 1221 | static int __devexit eth_remove_one(struct platform_device *pdev) |
| 1222 | { |
| 1223 | struct net_device *dev = platform_get_drvdata(pdev); |
| 1224 | struct port *port = netdev_priv(dev); |
| 1225 | |
| 1226 | unregister_netdev(dev); |
| 1227 | npe_port_tab[NPE_ID(port->id)] = NULL; |
| 1228 | platform_set_drvdata(pdev, NULL); |
| 1229 | npe_release(port->npe); |
| 1230 | release_resource(port->mem_res); |
| 1231 | free_netdev(dev); |
| 1232 | return 0; |
| 1233 | } |
| 1234 | |
| 1235 | static struct platform_driver drv = { |
| 1236 | .driver.name = DRV_NAME, |
| 1237 | .probe = eth_init_one, |
| 1238 | .remove = eth_remove_one, |
| 1239 | }; |
| 1240 | |
| 1241 | static int __init eth_init_module(void) |
| 1242 | { |
| 1243 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) |
| 1244 | return -ENOSYS; |
| 1245 | |
| 1246 | /* All MII PHY accesses use NPE-B Ethernet registers */ |
| 1247 | spin_lock_init(&mdio_lock); |
| 1248 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; |
| 1249 | __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); |
| 1250 | |
| 1251 | return platform_driver_register(&drv); |
| 1252 | } |
| 1253 | |
| 1254 | static void __exit eth_cleanup_module(void) |
| 1255 | { |
| 1256 | platform_driver_unregister(&drv); |
| 1257 | } |
| 1258 | |
| 1259 | MODULE_AUTHOR("Krzysztof Halasa"); |
| 1260 | MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); |
| 1261 | MODULE_LICENSE("GPL v2"); |
| 1262 | MODULE_ALIAS("platform:ixp4xx_eth"); |
| 1263 | module_init(eth_init_module); |
| 1264 | module_exit(eth_cleanup_module); |