Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 33 | #include "i915_drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 34 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 36 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
| 38 | { |
| 39 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 40 | u32 seqno; |
| 41 | |
| 42 | seqno = dev_priv->next_seqno; |
| 43 | |
| 44 | /* reserve 0 for non-seqno */ |
| 45 | if (++dev_priv->next_seqno == 0) |
| 46 | dev_priv->next_seqno = 1; |
| 47 | |
| 48 | return seqno; |
| 49 | } |
| 50 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 51 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 52 | render_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 53 | u32 invalidate_domains, |
| 54 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 55 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 56 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 57 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 58 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 59 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 60 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 61 | #if WATCH_EXEC |
| 62 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, |
| 63 | invalidate_domains, flush_domains); |
| 64 | #endif |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 65 | |
| 66 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 67 | invalidate_domains, flush_domains); |
| 68 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 69 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
| 70 | /* |
| 71 | * read/write caches: |
| 72 | * |
| 73 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 74 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 75 | * also flushed at 2d versus 3d pipeline switches. |
| 76 | * |
| 77 | * read-only caches: |
| 78 | * |
| 79 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 80 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 81 | * |
| 82 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 83 | * |
| 84 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 85 | * invalidated when MI_EXE_FLUSH is set. |
| 86 | * |
| 87 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 88 | * invalidated with every MI_FLUSH. |
| 89 | * |
| 90 | * TLBs: |
| 91 | * |
| 92 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 93 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 94 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 95 | * are flushed at any MI_FLUSH. |
| 96 | */ |
| 97 | |
| 98 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 99 | if ((invalidate_domains|flush_domains) & |
| 100 | I915_GEM_DOMAIN_RENDER) |
| 101 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 102 | if (INTEL_INFO(dev)->gen < 4) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 103 | /* |
| 104 | * On the 965, the sampler cache always gets flushed |
| 105 | * and this bit is reserved. |
| 106 | */ |
| 107 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 108 | cmd |= MI_READ_FLUSH; |
| 109 | } |
| 110 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 111 | cmd |= MI_EXE_FLUSH; |
| 112 | |
Chris Wilson | 70eac33 | 2010-11-30 14:07:47 +0000 | [diff] [blame] | 113 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 114 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 115 | cmd |= MI_INVALIDATE_ISP; |
| 116 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 117 | #if WATCH_EXEC |
| 118 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); |
| 119 | #endif |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 120 | ret = intel_ring_begin(ring, 2); |
| 121 | if (ret) |
| 122 | return ret; |
| 123 | |
| 124 | intel_ring_emit(ring, cmd); |
| 125 | intel_ring_emit(ring, MI_NOOP); |
| 126 | intel_ring_advance(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 127 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 128 | |
| 129 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 130 | } |
| 131 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 132 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 133 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 134 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 135 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 136 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 137 | } |
| 138 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 139 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 140 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 141 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 142 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 143 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 144 | |
| 145 | return I915_READ(acthd_reg); |
| 146 | } |
| 147 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 148 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 149 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 150 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 151 | struct drm_i915_gem_object *obj = ring->obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 152 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 153 | |
| 154 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 155 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 156 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 157 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 158 | |
| 159 | /* Initialize the ring. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 160 | I915_WRITE_START(ring, obj->gtt_offset); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 161 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 162 | |
| 163 | /* G45 ring initialization fails to reset head to zero */ |
| 164 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 165 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 166 | "ctl %08x head %08x tail %08x start %08x\n", |
| 167 | ring->name, |
| 168 | I915_READ_CTL(ring), |
| 169 | I915_READ_HEAD(ring), |
| 170 | I915_READ_TAIL(ring), |
| 171 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 172 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 173 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 174 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 175 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 176 | DRM_ERROR("failed to set %s head to zero " |
| 177 | "ctl %08x head %08x tail %08x start %08x\n", |
| 178 | ring->name, |
| 179 | I915_READ_CTL(ring), |
| 180 | I915_READ_HEAD(ring), |
| 181 | I915_READ_TAIL(ring), |
| 182 | I915_READ_START(ring)); |
| 183 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 184 | } |
| 185 | |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 186 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 187 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 6aa5606 | 2010-10-29 21:44:37 +0100 | [diff] [blame] | 188 | | RING_REPORT_64K | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 189 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 190 | /* If the head is still not zero, the ring is dead */ |
Chris Wilson | 176f28e | 2010-10-28 11:18:07 +0100 | [diff] [blame] | 191 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 192 | I915_READ_START(ring) != obj->gtt_offset || |
Chris Wilson | 176f28e | 2010-10-28 11:18:07 +0100 | [diff] [blame] | 193 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 194 | DRM_ERROR("%s initialization failed " |
| 195 | "ctl %08x head %08x tail %08x start %08x\n", |
| 196 | ring->name, |
| 197 | I915_READ_CTL(ring), |
| 198 | I915_READ_HEAD(ring), |
| 199 | I915_READ_TAIL(ring), |
| 200 | I915_READ_START(ring)); |
| 201 | return -EIO; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 202 | } |
| 203 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 204 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 205 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 206 | else { |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 207 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 208 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 209 | ring->space = ring->head - (ring->tail + 8); |
| 210 | if (ring->space < 0) |
| 211 | ring->space += ring->size; |
| 212 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 213 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 214 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 215 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 216 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 217 | /* |
| 218 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 219 | * over cache flushing. |
| 220 | */ |
| 221 | struct pipe_control { |
| 222 | struct drm_i915_gem_object *obj; |
| 223 | volatile u32 *cpu_page; |
| 224 | u32 gtt_offset; |
| 225 | }; |
| 226 | |
| 227 | static int |
| 228 | init_pipe_control(struct intel_ring_buffer *ring) |
| 229 | { |
| 230 | struct pipe_control *pc; |
| 231 | struct drm_i915_gem_object *obj; |
| 232 | int ret; |
| 233 | |
| 234 | if (ring->private) |
| 235 | return 0; |
| 236 | |
| 237 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
| 238 | if (!pc) |
| 239 | return -ENOMEM; |
| 240 | |
| 241 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 242 | if (obj == NULL) { |
| 243 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 244 | ret = -ENOMEM; |
| 245 | goto err; |
| 246 | } |
| 247 | obj->agp_type = AGP_USER_CACHED_MEMORY; |
| 248 | |
| 249 | ret = i915_gem_object_pin(obj, 4096, true); |
| 250 | if (ret) |
| 251 | goto err_unref; |
| 252 | |
| 253 | pc->gtt_offset = obj->gtt_offset; |
| 254 | pc->cpu_page = kmap(obj->pages[0]); |
| 255 | if (pc->cpu_page == NULL) |
| 256 | goto err_unpin; |
| 257 | |
| 258 | pc->obj = obj; |
| 259 | ring->private = pc; |
| 260 | return 0; |
| 261 | |
| 262 | err_unpin: |
| 263 | i915_gem_object_unpin(obj); |
| 264 | err_unref: |
| 265 | drm_gem_object_unreference(&obj->base); |
| 266 | err: |
| 267 | kfree(pc); |
| 268 | return ret; |
| 269 | } |
| 270 | |
| 271 | static void |
| 272 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
| 273 | { |
| 274 | struct pipe_control *pc = ring->private; |
| 275 | struct drm_i915_gem_object *obj; |
| 276 | |
| 277 | if (!ring->private) |
| 278 | return; |
| 279 | |
| 280 | obj = pc->obj; |
| 281 | kunmap(obj->pages[0]); |
| 282 | i915_gem_object_unpin(obj); |
| 283 | drm_gem_object_unreference(&obj->base); |
| 284 | |
| 285 | kfree(pc); |
| 286 | ring->private = NULL; |
| 287 | } |
| 288 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 289 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 290 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 291 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 292 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 293 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 294 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 295 | if (INTEL_INFO(dev)->gen > 3) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 296 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 297 | if (IS_GEN6(dev)) |
| 298 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; |
| 299 | I915_WRITE(MI_MODE, mode); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 300 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 301 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 302 | if (INTEL_INFO(dev)->gen >= 6) { |
| 303 | } else if (IS_GEN5(dev)) { |
| 304 | ret = init_pipe_control(ring); |
| 305 | if (ret) |
| 306 | return ret; |
| 307 | } |
| 308 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 309 | return ret; |
| 310 | } |
| 311 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 312 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 313 | { |
| 314 | if (!ring->private) |
| 315 | return; |
| 316 | |
| 317 | cleanup_pipe_control(ring); |
| 318 | } |
| 319 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 320 | static void |
| 321 | update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno) |
| 322 | { |
| 323 | struct drm_device *dev = ring->dev; |
| 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 325 | int id; |
| 326 | |
| 327 | /* |
| 328 | * cs -> 1 = vcs, 0 = bcs |
| 329 | * vcs -> 1 = bcs, 0 = cs, |
| 330 | * bcs -> 1 = cs, 0 = vcs. |
| 331 | */ |
| 332 | id = ring - dev_priv->ring; |
| 333 | id += 2 - i; |
| 334 | id %= 3; |
| 335 | |
| 336 | intel_ring_emit(ring, |
| 337 | MI_SEMAPHORE_MBOX | |
| 338 | MI_SEMAPHORE_REGISTER | |
| 339 | MI_SEMAPHORE_UPDATE); |
| 340 | intel_ring_emit(ring, seqno); |
| 341 | intel_ring_emit(ring, |
| 342 | RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i); |
| 343 | } |
| 344 | |
| 345 | static int |
| 346 | gen6_add_request(struct intel_ring_buffer *ring, |
| 347 | u32 *result) |
| 348 | { |
| 349 | u32 seqno; |
| 350 | int ret; |
| 351 | |
| 352 | ret = intel_ring_begin(ring, 10); |
| 353 | if (ret) |
| 354 | return ret; |
| 355 | |
| 356 | seqno = i915_gem_get_seqno(ring->dev); |
| 357 | update_semaphore(ring, 0, seqno); |
| 358 | update_semaphore(ring, 1, seqno); |
| 359 | |
| 360 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 361 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 362 | intel_ring_emit(ring, seqno); |
| 363 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 364 | intel_ring_advance(ring); |
| 365 | |
| 366 | *result = seqno; |
| 367 | return 0; |
| 368 | } |
| 369 | |
| 370 | int |
| 371 | intel_ring_sync(struct intel_ring_buffer *ring, |
| 372 | struct intel_ring_buffer *to, |
| 373 | u32 seqno) |
| 374 | { |
| 375 | int ret; |
| 376 | |
| 377 | ret = intel_ring_begin(ring, 4); |
| 378 | if (ret) |
| 379 | return ret; |
| 380 | |
| 381 | intel_ring_emit(ring, |
| 382 | MI_SEMAPHORE_MBOX | |
| 383 | MI_SEMAPHORE_REGISTER | |
| 384 | intel_ring_sync_index(ring, to) << 17 | |
| 385 | MI_SEMAPHORE_COMPARE); |
| 386 | intel_ring_emit(ring, seqno); |
| 387 | intel_ring_emit(ring, 0); |
| 388 | intel_ring_emit(ring, MI_NOOP); |
| 389 | intel_ring_advance(ring); |
| 390 | |
| 391 | return 0; |
| 392 | } |
| 393 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 394 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 395 | do { \ |
| 396 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
| 397 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
| 398 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 399 | intel_ring_emit(ring__, 0); \ |
| 400 | intel_ring_emit(ring__, 0); \ |
| 401 | } while (0) |
| 402 | |
| 403 | static int |
| 404 | pc_render_add_request(struct intel_ring_buffer *ring, |
| 405 | u32 *result) |
| 406 | { |
| 407 | struct drm_device *dev = ring->dev; |
| 408 | u32 seqno = i915_gem_get_seqno(dev); |
| 409 | struct pipe_control *pc = ring->private; |
| 410 | u32 scratch_addr = pc->gtt_offset + 128; |
| 411 | int ret; |
| 412 | |
| 413 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 414 | * incoherent with writes to memory, i.e. completely fubar, |
| 415 | * so we need to use PIPE_NOTIFY instead. |
| 416 | * |
| 417 | * However, we also need to workaround the qword write |
| 418 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 419 | * memory before requesting an interrupt. |
| 420 | */ |
| 421 | ret = intel_ring_begin(ring, 32); |
| 422 | if (ret) |
| 423 | return ret; |
| 424 | |
| 425 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
| 426 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); |
| 427 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 428 | intel_ring_emit(ring, seqno); |
| 429 | intel_ring_emit(ring, 0); |
| 430 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 431 | scratch_addr += 128; /* write to separate cachelines */ |
| 432 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 433 | scratch_addr += 128; |
| 434 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 435 | scratch_addr += 128; |
| 436 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 437 | scratch_addr += 128; |
| 438 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 439 | scratch_addr += 128; |
| 440 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 441 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
| 442 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | |
| 443 | PIPE_CONTROL_NOTIFY); |
| 444 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 445 | intel_ring_emit(ring, seqno); |
| 446 | intel_ring_emit(ring, 0); |
| 447 | intel_ring_advance(ring); |
| 448 | |
| 449 | *result = seqno; |
| 450 | return 0; |
| 451 | } |
| 452 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 453 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 454 | render_ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 455 | u32 *result) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 456 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 457 | struct drm_device *dev = ring->dev; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 458 | u32 seqno = i915_gem_get_seqno(dev); |
| 459 | int ret; |
Zhenyu Wang | ca76482 | 2010-05-27 10:26:42 +0800 | [diff] [blame] | 460 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 461 | ret = intel_ring_begin(ring, 4); |
| 462 | if (ret) |
| 463 | return ret; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 464 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 465 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 466 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 467 | intel_ring_emit(ring, seqno); |
| 468 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 469 | intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 470 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 471 | *result = seqno; |
| 472 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 473 | } |
| 474 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 475 | static u32 |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 476 | ring_get_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 477 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 478 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 479 | } |
| 480 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 481 | static u32 |
| 482 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
| 483 | { |
| 484 | struct pipe_control *pc = ring->private; |
| 485 | return pc->cpu_page[0]; |
| 486 | } |
| 487 | |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 488 | static void |
| 489 | ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 490 | { |
| 491 | dev_priv->gt_irq_mask &= ~mask; |
| 492 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 493 | POSTING_READ(GTIMR); |
| 494 | } |
| 495 | |
| 496 | static void |
| 497 | ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 498 | { |
| 499 | dev_priv->gt_irq_mask |= mask; |
| 500 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 501 | POSTING_READ(GTIMR); |
| 502 | } |
| 503 | |
| 504 | static void |
| 505 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 506 | { |
| 507 | dev_priv->irq_mask &= ~mask; |
| 508 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 509 | POSTING_READ(IMR); |
| 510 | } |
| 511 | |
| 512 | static void |
| 513 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 514 | { |
| 515 | dev_priv->irq_mask |= mask; |
| 516 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 517 | POSTING_READ(IMR); |
| 518 | } |
| 519 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 520 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 521 | render_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 522 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 523 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 524 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 525 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 526 | if (!dev->irq_enabled) |
| 527 | return false; |
| 528 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 529 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 530 | if (ring->irq_refcount++ == 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 531 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 532 | ironlake_enable_irq(dev_priv, |
| 533 | GT_PIPE_NOTIFY | GT_USER_INTERRUPT); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 534 | else |
| 535 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
| 536 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 537 | spin_unlock(&ring->irq_lock); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 538 | |
| 539 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 540 | } |
| 541 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 542 | static void |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 543 | render_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 544 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 545 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 546 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 547 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 548 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 549 | if (--ring->irq_refcount == 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 550 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 551 | ironlake_disable_irq(dev_priv, |
| 552 | GT_USER_INTERRUPT | |
| 553 | GT_PIPE_NOTIFY); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 554 | else |
| 555 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
| 556 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 557 | spin_unlock(&ring->irq_lock); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 558 | } |
| 559 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 560 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 561 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 562 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 563 | u32 mmio = IS_GEN6(ring->dev) ? |
| 564 | RING_HWS_PGA_GEN6(ring->mmio_base) : |
| 565 | RING_HWS_PGA(ring->mmio_base); |
| 566 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 567 | POSTING_READ(mmio); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 568 | } |
| 569 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 570 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 571 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 572 | u32 invalidate_domains, |
| 573 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 574 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 575 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 576 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 577 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
| 578 | return 0; |
| 579 | |
| 580 | ret = intel_ring_begin(ring, 2); |
| 581 | if (ret) |
| 582 | return ret; |
| 583 | |
| 584 | intel_ring_emit(ring, MI_FLUSH); |
| 585 | intel_ring_emit(ring, MI_NOOP); |
| 586 | intel_ring_advance(ring); |
| 587 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 588 | } |
| 589 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 590 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 591 | ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 592 | u32 *result) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 593 | { |
| 594 | u32 seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 595 | int ret; |
| 596 | |
| 597 | ret = intel_ring_begin(ring, 4); |
| 598 | if (ret) |
| 599 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 600 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 601 | seqno = i915_gem_get_seqno(ring->dev); |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 602 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 603 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 604 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 605 | intel_ring_emit(ring, seqno); |
| 606 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 607 | intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 608 | |
| 609 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 610 | *result = seqno; |
| 611 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 612 | } |
| 613 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 614 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 615 | ring_get_irq(struct intel_ring_buffer *ring, u32 flag) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 616 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 617 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 618 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 619 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 620 | if (!dev->irq_enabled) |
| 621 | return false; |
| 622 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 623 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 624 | if (ring->irq_refcount++ == 0) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 625 | ironlake_enable_irq(dev_priv, flag); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 626 | spin_unlock(&ring->irq_lock); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 627 | |
| 628 | return true; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 629 | } |
| 630 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 631 | static void |
| 632 | ring_put_irq(struct intel_ring_buffer *ring, u32 flag) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 633 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 634 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 635 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 636 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 637 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 638 | if (--ring->irq_refcount == 0) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 639 | ironlake_disable_irq(dev_priv, flag); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 640 | spin_unlock(&ring->irq_lock); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | static bool |
| 644 | gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
| 645 | { |
| 646 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 647 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 648 | |
| 649 | if (!dev->irq_enabled) |
| 650 | return false; |
| 651 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 652 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 653 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 654 | ring->irq_mask &= ~rflag; |
| 655 | I915_WRITE_IMR(ring, ring->irq_mask); |
| 656 | ironlake_enable_irq(dev_priv, gflag); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 657 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 658 | spin_unlock(&ring->irq_lock); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 659 | |
| 660 | return true; |
| 661 | } |
| 662 | |
| 663 | static void |
| 664 | gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
| 665 | { |
| 666 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 667 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 668 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 669 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 670 | if (--ring->irq_refcount == 0) { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 671 | ring->irq_mask |= rflag; |
| 672 | I915_WRITE_IMR(ring, ring->irq_mask); |
| 673 | ironlake_disable_irq(dev_priv, gflag); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 674 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 675 | spin_unlock(&ring->irq_lock); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 676 | } |
| 677 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 678 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 679 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
| 680 | { |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 681 | return ring_get_irq(ring, GT_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 682 | } |
| 683 | static void |
| 684 | bsd_ring_put_irq(struct intel_ring_buffer *ring) |
| 685 | { |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 686 | ring_put_irq(ring, GT_BSD_USER_INTERRUPT); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 687 | } |
| 688 | |
| 689 | static int |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 690 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 691 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 692 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 693 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 694 | ret = intel_ring_begin(ring, 2); |
| 695 | if (ret) |
| 696 | return ret; |
| 697 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 698 | intel_ring_emit(ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 699 | MI_BATCH_BUFFER_START | (2 << 6) | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 700 | MI_BATCH_NON_SECURE_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 701 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 702 | intel_ring_advance(ring); |
| 703 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 704 | return 0; |
| 705 | } |
| 706 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 707 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 708 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 709 | u32 offset, u32 len) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 710 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 711 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 712 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 713 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 714 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 715 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 716 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 717 | if (IS_I830(dev) || IS_845G(dev)) { |
| 718 | ret = intel_ring_begin(ring, 4); |
| 719 | if (ret) |
| 720 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 721 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 722 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 723 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
| 724 | intel_ring_emit(ring, offset + len - 8); |
| 725 | intel_ring_emit(ring, 0); |
| 726 | } else { |
| 727 | ret = intel_ring_begin(ring, 2); |
| 728 | if (ret) |
| 729 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 730 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 731 | if (INTEL_INFO(dev)->gen >= 4) { |
| 732 | intel_ring_emit(ring, |
| 733 | MI_BATCH_BUFFER_START | (2 << 6) | |
| 734 | MI_BATCH_NON_SECURE_I965); |
| 735 | intel_ring_emit(ring, offset); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 736 | } else { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 737 | intel_ring_emit(ring, |
| 738 | MI_BATCH_BUFFER_START | (2 << 6)); |
| 739 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 740 | } |
| 741 | } |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 742 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 743 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 744 | return 0; |
| 745 | } |
| 746 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 747 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 748 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 749 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 750 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 751 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 752 | obj = ring->status_page.obj; |
| 753 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 754 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 755 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 756 | kunmap(obj->pages[0]); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 757 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 758 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 759 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 760 | |
| 761 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 762 | } |
| 763 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 764 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 765 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 766 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 767 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 768 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 769 | int ret; |
| 770 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 771 | obj = i915_gem_alloc_object(dev, 4096); |
| 772 | if (obj == NULL) { |
| 773 | DRM_ERROR("Failed to allocate status page\n"); |
| 774 | ret = -ENOMEM; |
| 775 | goto err; |
| 776 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 777 | obj->agp_type = AGP_USER_CACHED_MEMORY; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 778 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 779 | ret = i915_gem_object_pin(obj, 4096, true); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 780 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 781 | goto err_unref; |
| 782 | } |
| 783 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 784 | ring->status_page.gfx_addr = obj->gtt_offset; |
| 785 | ring->status_page.page_addr = kmap(obj->pages[0]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 786 | if (ring->status_page.page_addr == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 787 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 788 | goto err_unpin; |
| 789 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 790 | ring->status_page.obj = obj; |
| 791 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 792 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 793 | intel_ring_setup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 794 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 795 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 796 | |
| 797 | return 0; |
| 798 | |
| 799 | err_unpin: |
| 800 | i915_gem_object_unpin(obj); |
| 801 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 802 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 803 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 804 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 805 | } |
| 806 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 807 | int intel_init_ring_buffer(struct drm_device *dev, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 808 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 809 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 810 | struct drm_i915_gem_object *obj; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 811 | int ret; |
| 812 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 813 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 814 | INIT_LIST_HEAD(&ring->active_list); |
| 815 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 816 | INIT_LIST_HEAD(&ring->gpu_write_list); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 817 | |
| 818 | spin_lock_init(&ring->irq_lock); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 819 | ring->irq_mask = ~0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 820 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 821 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 822 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 823 | if (ret) |
| 824 | return ret; |
| 825 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 826 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 827 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 828 | if (obj == NULL) { |
| 829 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 830 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 831 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 832 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 833 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 834 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 835 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 836 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 837 | if (ret) |
| 838 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 839 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 840 | ring->map.size = ring->size; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 841 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 842 | ring->map.type = 0; |
| 843 | ring->map.flags = 0; |
| 844 | ring->map.mtrr = 0; |
| 845 | |
| 846 | drm_core_ioremap_wc(&ring->map, dev); |
| 847 | if (ring->map.handle == NULL) { |
| 848 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 849 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 850 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 851 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 852 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 853 | ring->virtual_start = ring->map.handle; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 854 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 855 | if (ret) |
| 856 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 857 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 858 | /* Workaround an erratum on the i830 which causes a hang if |
| 859 | * the TAIL pointer points to within the last 2 cachelines |
| 860 | * of the buffer. |
| 861 | */ |
| 862 | ring->effective_size = ring->size; |
| 863 | if (IS_I830(ring->dev)) |
| 864 | ring->effective_size -= 128; |
| 865 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 866 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 867 | |
| 868 | err_unmap: |
| 869 | drm_core_ioremapfree(&ring->map, dev); |
| 870 | err_unpin: |
| 871 | i915_gem_object_unpin(obj); |
| 872 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 873 | drm_gem_object_unreference(&obj->base); |
| 874 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 875 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 876 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 877 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 878 | } |
| 879 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 880 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 881 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 882 | struct drm_i915_private *dev_priv; |
| 883 | int ret; |
| 884 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 885 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 886 | return; |
| 887 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 888 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 889 | dev_priv = ring->dev->dev_private; |
| 890 | ret = intel_wait_ring_buffer(ring, ring->size - 8); |
| 891 | I915_WRITE_CTL(ring, 0); |
| 892 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 893 | drm_core_ioremapfree(&ring->map, ring->dev); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 894 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 895 | i915_gem_object_unpin(ring->obj); |
| 896 | drm_gem_object_unreference(&ring->obj->base); |
| 897 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 898 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 899 | if (ring->cleanup) |
| 900 | ring->cleanup(ring); |
| 901 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 902 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 903 | } |
| 904 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 905 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 906 | { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 907 | unsigned int *virt; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 908 | int rem = ring->size - ring->tail; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 909 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 910 | if (ring->space < rem) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 911 | int ret = intel_wait_ring_buffer(ring, rem); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 912 | if (ret) |
| 913 | return ret; |
| 914 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 915 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 916 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 917 | rem /= 8; |
| 918 | while (rem--) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 919 | *virt++ = MI_NOOP; |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 920 | *virt++ = MI_NOOP; |
| 921 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 922 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 923 | ring->tail = 0; |
Chris Wilson | 43ed340 | 2010-07-01 17:53:00 +0100 | [diff] [blame] | 924 | ring->space = ring->head - 8; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 925 | |
| 926 | return 0; |
| 927 | } |
| 928 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 929 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 930 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 931 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 932 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 933 | unsigned long end; |
Chris Wilson | 6aa5606 | 2010-10-29 21:44:37 +0100 | [diff] [blame] | 934 | u32 head; |
| 935 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 936 | trace_i915_ring_wait_begin (dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 937 | end = jiffies + 3 * HZ; |
| 938 | do { |
Chris Wilson | 8c0a6bf | 2010-12-09 12:56:37 +0000 | [diff] [blame] | 939 | /* If the reported head position has wrapped or hasn't advanced, |
| 940 | * fallback to the slow and accurate path. |
| 941 | */ |
| 942 | head = intel_read_status_page(ring, 4); |
| 943 | if (head < ring->actual_head) |
| 944 | head = I915_READ_HEAD(ring); |
| 945 | ring->actual_head = head; |
| 946 | ring->head = head & HEAD_ADDR; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 947 | ring->space = ring->head - (ring->tail + 8); |
| 948 | if (ring->space < 0) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 949 | ring->space += ring->size; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 950 | if (ring->space >= n) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 951 | trace_i915_ring_wait_end(dev); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 952 | return 0; |
| 953 | } |
| 954 | |
| 955 | if (dev->primary->master) { |
| 956 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 957 | if (master_priv->sarea_priv) |
| 958 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 959 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 960 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 961 | msleep(1); |
Chris Wilson | f4e0b29 | 2010-10-29 21:06:16 +0100 | [diff] [blame] | 962 | if (atomic_read(&dev_priv->mm.wedged)) |
| 963 | return -EAGAIN; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 964 | } while (!time_after(jiffies, end)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 965 | trace_i915_ring_wait_end (dev); |
| 966 | return -EBUSY; |
| 967 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 968 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 969 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 970 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 971 | { |
Zou Nan hai | be26a10 | 2010-06-12 17:40:24 +0800 | [diff] [blame] | 972 | int n = 4*num_dwords; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 973 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 974 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 975 | if (unlikely(ring->tail + n > ring->effective_size)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 976 | ret = intel_wrap_ring_buffer(ring); |
| 977 | if (unlikely(ret)) |
| 978 | return ret; |
| 979 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 980 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 981 | if (unlikely(ring->space < n)) { |
| 982 | ret = intel_wait_ring_buffer(ring, n); |
| 983 | if (unlikely(ret)) |
| 984 | return ret; |
| 985 | } |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 986 | |
| 987 | ring->space -= n; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 988 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 989 | } |
| 990 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 991 | void intel_ring_advance(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 992 | { |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 993 | ring->tail &= ring->size - 1; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 994 | ring->write_tail(ring, ring->tail); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 995 | } |
| 996 | |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 997 | static const struct intel_ring_buffer render_ring = { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 998 | .name = "render ring", |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 999 | .id = RING_RENDER, |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 1000 | .mmio_base = RENDER_RING_BASE, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1001 | .size = 32 * PAGE_SIZE, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1002 | .init = init_render_ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1003 | .write_tail = ring_write_tail, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1004 | .flush = render_ring_flush, |
| 1005 | .add_request = render_ring_add_request, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1006 | .get_seqno = ring_get_seqno, |
| 1007 | .irq_get = render_ring_get_irq, |
| 1008 | .irq_put = render_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1009 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1010 | .cleanup = render_ring_cleanup, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1011 | }; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1012 | |
| 1013 | /* ring buffer for bit-stream decoder */ |
| 1014 | |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1015 | static const struct intel_ring_buffer bsd_ring = { |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1016 | .name = "bsd ring", |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 1017 | .id = RING_BSD, |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 1018 | .mmio_base = BSD_RING_BASE, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1019 | .size = 32 * PAGE_SIZE, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1020 | .init = init_ring_common, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1021 | .write_tail = ring_write_tail, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1022 | .flush = bsd_ring_flush, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1023 | .add_request = ring_add_request, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1024 | .get_seqno = ring_get_seqno, |
| 1025 | .irq_get = bsd_ring_get_irq, |
| 1026 | .irq_put = bsd_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1027 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1028 | }; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1029 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1030 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1031 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1032 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1033 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1034 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1035 | |
| 1036 | /* Every tail move must follow the sequence below */ |
| 1037 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1038 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 1039 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
| 1040 | I915_WRITE(GEN6_BSD_RNCID, 0x0); |
| 1041 | |
| 1042 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
| 1043 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
| 1044 | 50)) |
| 1045 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
| 1046 | |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 1047 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1048 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1049 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 1050 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
| 1051 | } |
| 1052 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1053 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
| 1054 | u32 invalidate_domains, |
| 1055 | u32 flush_domains) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1056 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1057 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1058 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1059 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
| 1060 | return 0; |
| 1061 | |
| 1062 | ret = intel_ring_begin(ring, 4); |
| 1063 | if (ret) |
| 1064 | return ret; |
| 1065 | |
| 1066 | intel_ring_emit(ring, MI_FLUSH_DW); |
| 1067 | intel_ring_emit(ring, 0); |
| 1068 | intel_ring_emit(ring, 0); |
| 1069 | intel_ring_emit(ring, 0); |
| 1070 | intel_ring_advance(ring); |
| 1071 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1072 | } |
| 1073 | |
| 1074 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1075 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1076 | u32 offset, u32 len) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1077 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1078 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1079 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1080 | ret = intel_ring_begin(ring, 2); |
| 1081 | if (ret) |
| 1082 | return ret; |
| 1083 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1084 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1085 | /* bit0-7 is the length on GEN6+ */ |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1086 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1087 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1088 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1089 | return 0; |
| 1090 | } |
| 1091 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1092 | static bool |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1093 | gen6_render_ring_get_irq(struct intel_ring_buffer *ring) |
| 1094 | { |
| 1095 | return gen6_ring_get_irq(ring, |
| 1096 | GT_USER_INTERRUPT, |
| 1097 | GEN6_RENDER_USER_INTERRUPT); |
| 1098 | } |
| 1099 | |
| 1100 | static void |
| 1101 | gen6_render_ring_put_irq(struct intel_ring_buffer *ring) |
| 1102 | { |
| 1103 | return gen6_ring_put_irq(ring, |
| 1104 | GT_USER_INTERRUPT, |
| 1105 | GEN6_RENDER_USER_INTERRUPT); |
| 1106 | } |
| 1107 | |
| 1108 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1109 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
| 1110 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1111 | return gen6_ring_get_irq(ring, |
| 1112 | GT_GEN6_BSD_USER_INTERRUPT, |
| 1113 | GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1114 | } |
| 1115 | |
| 1116 | static void |
| 1117 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) |
| 1118 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1119 | return gen6_ring_put_irq(ring, |
| 1120 | GT_GEN6_BSD_USER_INTERRUPT, |
| 1121 | GEN6_BSD_USER_INTERRUPT); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1122 | } |
| 1123 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1124 | /* ring buffer for Video Codec for Gen6+ */ |
Chris Wilson | e070868 | 2010-09-19 14:46:27 +0100 | [diff] [blame] | 1125 | static const struct intel_ring_buffer gen6_bsd_ring = { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1126 | .name = "gen6 bsd ring", |
| 1127 | .id = RING_BSD, |
| 1128 | .mmio_base = GEN6_BSD_RING_BASE, |
| 1129 | .size = 32 * PAGE_SIZE, |
| 1130 | .init = init_ring_common, |
| 1131 | .write_tail = gen6_bsd_ring_write_tail, |
| 1132 | .flush = gen6_ring_flush, |
| 1133 | .add_request = gen6_add_request, |
| 1134 | .get_seqno = ring_get_seqno, |
| 1135 | .irq_get = gen6_bsd_ring_get_irq, |
| 1136 | .irq_put = gen6_bsd_ring_put_irq, |
| 1137 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1138 | }; |
| 1139 | |
| 1140 | /* Blitter support (SandyBridge+) */ |
| 1141 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1142 | static bool |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1143 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1144 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1145 | return gen6_ring_get_irq(ring, |
| 1146 | GT_BLT_USER_INTERRUPT, |
| 1147 | GEN6_BLITTER_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1148 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1149 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1150 | static void |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1151 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1152 | { |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1153 | gen6_ring_put_irq(ring, |
| 1154 | GT_BLT_USER_INTERRUPT, |
| 1155 | GEN6_BLITTER_USER_INTERRUPT); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1156 | } |
| 1157 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1158 | |
| 1159 | /* Workaround for some stepping of SNB, |
| 1160 | * each time when BLT engine ring tail moved, |
| 1161 | * the first command in the ring to be parsed |
| 1162 | * should be MI_BATCH_BUFFER_START |
| 1163 | */ |
| 1164 | #define NEED_BLT_WORKAROUND(dev) \ |
| 1165 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) |
| 1166 | |
| 1167 | static inline struct drm_i915_gem_object * |
| 1168 | to_blt_workaround(struct intel_ring_buffer *ring) |
| 1169 | { |
| 1170 | return ring->private; |
| 1171 | } |
| 1172 | |
| 1173 | static int blt_ring_init(struct intel_ring_buffer *ring) |
| 1174 | { |
| 1175 | if (NEED_BLT_WORKAROUND(ring->dev)) { |
| 1176 | struct drm_i915_gem_object *obj; |
Chris Wilson | 27153f7 | 2010-11-02 11:17:23 +0000 | [diff] [blame] | 1177 | u32 *ptr; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1178 | int ret; |
| 1179 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1180 | obj = i915_gem_alloc_object(ring->dev, 4096); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1181 | if (obj == NULL) |
| 1182 | return -ENOMEM; |
| 1183 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1184 | ret = i915_gem_object_pin(obj, 4096, true); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1185 | if (ret) { |
| 1186 | drm_gem_object_unreference(&obj->base); |
| 1187 | return ret; |
| 1188 | } |
| 1189 | |
| 1190 | ptr = kmap(obj->pages[0]); |
Chris Wilson | 27153f7 | 2010-11-02 11:17:23 +0000 | [diff] [blame] | 1191 | *ptr++ = MI_BATCH_BUFFER_END; |
| 1192 | *ptr++ = MI_NOOP; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1193 | kunmap(obj->pages[0]); |
| 1194 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1195 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1196 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1197 | i915_gem_object_unpin(obj); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1198 | drm_gem_object_unreference(&obj->base); |
| 1199 | return ret; |
| 1200 | } |
| 1201 | |
| 1202 | ring->private = obj; |
| 1203 | } |
| 1204 | |
| 1205 | return init_ring_common(ring); |
| 1206 | } |
| 1207 | |
| 1208 | static int blt_ring_begin(struct intel_ring_buffer *ring, |
| 1209 | int num_dwords) |
| 1210 | { |
| 1211 | if (ring->private) { |
| 1212 | int ret = intel_ring_begin(ring, num_dwords+2); |
| 1213 | if (ret) |
| 1214 | return ret; |
| 1215 | |
| 1216 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); |
| 1217 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); |
| 1218 | |
| 1219 | return 0; |
| 1220 | } else |
| 1221 | return intel_ring_begin(ring, 4); |
| 1222 | } |
| 1223 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1224 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1225 | u32 invalidate_domains, |
| 1226 | u32 flush_domains) |
| 1227 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1228 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1229 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1230 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
| 1231 | return 0; |
| 1232 | |
| 1233 | ret = blt_ring_begin(ring, 4); |
| 1234 | if (ret) |
| 1235 | return ret; |
| 1236 | |
| 1237 | intel_ring_emit(ring, MI_FLUSH_DW); |
| 1238 | intel_ring_emit(ring, 0); |
| 1239 | intel_ring_emit(ring, 0); |
| 1240 | intel_ring_emit(ring, 0); |
| 1241 | intel_ring_advance(ring); |
| 1242 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1243 | } |
| 1244 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1245 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
| 1246 | { |
| 1247 | if (!ring->private) |
| 1248 | return; |
| 1249 | |
| 1250 | i915_gem_object_unpin(ring->private); |
| 1251 | drm_gem_object_unreference(ring->private); |
| 1252 | ring->private = NULL; |
| 1253 | } |
| 1254 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1255 | static const struct intel_ring_buffer gen6_blt_ring = { |
| 1256 | .name = "blt ring", |
| 1257 | .id = RING_BLT, |
| 1258 | .mmio_base = BLT_RING_BASE, |
| 1259 | .size = 32 * PAGE_SIZE, |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1260 | .init = blt_ring_init, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1261 | .write_tail = ring_write_tail, |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1262 | .flush = blt_ring_flush, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1263 | .add_request = gen6_add_request, |
| 1264 | .get_seqno = ring_get_seqno, |
| 1265 | .irq_get = blt_ring_get_irq, |
| 1266 | .irq_put = blt_ring_put_irq, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1267 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1268 | .cleanup = blt_ring_cleanup, |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1269 | }; |
| 1270 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1271 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1272 | { |
| 1273 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1274 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1275 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1276 | *ring = render_ring; |
| 1277 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1278 | ring->add_request = gen6_add_request; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1279 | ring->irq_get = gen6_render_ring_get_irq; |
| 1280 | ring->irq_put = gen6_render_ring_put_irq; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1281 | } else if (IS_GEN5(dev)) { |
| 1282 | ring->add_request = pc_render_add_request; |
| 1283 | ring->get_seqno = pc_render_get_seqno; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1284 | } |
| 1285 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1286 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1287 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1288 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1289 | } |
| 1290 | |
| 1291 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1292 | } |
| 1293 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame^] | 1294 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1295 | { |
| 1296 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1297 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
| 1298 | |
| 1299 | *ring = render_ring; |
| 1300 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1301 | ring->add_request = gen6_add_request; |
| 1302 | ring->irq_get = gen6_render_ring_get_irq; |
| 1303 | ring->irq_put = gen6_render_ring_put_irq; |
| 1304 | } else if (IS_GEN5(dev)) { |
| 1305 | ring->add_request = pc_render_add_request; |
| 1306 | ring->get_seqno = pc_render_get_seqno; |
| 1307 | } |
| 1308 | |
| 1309 | ring->dev = dev; |
| 1310 | INIT_LIST_HEAD(&ring->active_list); |
| 1311 | INIT_LIST_HEAD(&ring->request_list); |
| 1312 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 1313 | |
| 1314 | ring->size = size; |
| 1315 | ring->effective_size = ring->size; |
| 1316 | if (IS_I830(ring->dev)) |
| 1317 | ring->effective_size -= 128; |
| 1318 | |
| 1319 | ring->map.offset = start; |
| 1320 | ring->map.size = size; |
| 1321 | ring->map.type = 0; |
| 1322 | ring->map.flags = 0; |
| 1323 | ring->map.mtrr = 0; |
| 1324 | |
| 1325 | drm_core_ioremap_wc(&ring->map, dev); |
| 1326 | if (ring->map.handle == NULL) { |
| 1327 | DRM_ERROR("can not ioremap virtual address for" |
| 1328 | " ring buffer\n"); |
| 1329 | return -ENOMEM; |
| 1330 | } |
| 1331 | |
| 1332 | ring->virtual_start = (void __force __iomem *)ring->map.handle; |
| 1333 | return 0; |
| 1334 | } |
| 1335 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1336 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1337 | { |
| 1338 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1339 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1340 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1341 | if (IS_GEN6(dev)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1342 | *ring = gen6_bsd_ring; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1343 | else |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1344 | *ring = bsd_ring; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1345 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1346 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1347 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1348 | |
| 1349 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1350 | { |
| 1351 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1352 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1353 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1354 | *ring = gen6_blt_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1355 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1356 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1357 | } |