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Heiko Stuebnerd63dc052013-06-02 23:09:41 +02001/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
Heiko Stuebner5218c6b2015-03-06 19:04:00 +01005 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
Heiko Stuebnerd63dc052013-06-02 23:09:41 +02009 *
Heiko Stuebner5218c6b2015-03-06 19:04:00 +010010 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020042 */
43
44#include <dt-bindings/gpio/gpio.h>
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020045#include <dt-bindings/pinctrl/rockchip.h>
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +020046#include <dt-bindings/clock/rk3066a-cru.h>
Heiko Stuebnerf75efdd2013-09-29 13:25:08 +020047#include "rk3xxx.dtsi"
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020048
49/ {
50 compatible = "rockchip,rk3066a";
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020051
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
Heiko Stübner26ab69c2014-03-27 01:06:32 +010055 enable-method = "rockchip,rk3066-smp";
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020056
Heiko Stuebnerbe8a77c2014-09-13 00:34:29 +020057 cpu0: cpu@0 {
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020058 device_type = "cpu";
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
61 reg = <0x0>;
Heiko Stuebnerbe8a77c2014-09-13 00:34:29 +020062 operating-points = <
63 /* kHz uV */
Andy Yan3a429492016-01-15 21:25:21 +080064 1416000 1300000
65 1200000 1175000
66 1008000 1125000
67 816000 1125000
68 600000 1100000
69 504000 1100000
70 312000 1075000
Heiko Stuebnerbe8a77c2014-09-13 00:34:29 +020071 >;
72 clock-latency = <40000>;
73 clocks = <&cru ARMCLK>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +020074 };
75 cpu@1 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a9";
78 next-level-cache = <&L2>;
79 reg = <0x1>;
80 };
81 };
82
Heiko Stuebnerc3030d32014-07-26 18:44:35 +020083 sram: sram@10080000 {
84 compatible = "mmio-sram";
85 reg = <0x10080000 0x10000>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges = <0 0x10080000 0x10000>;
89
90 smp-sram@0 {
91 compatible = "rockchip,rk3066-smp-sram";
92 reg = <0x0 0x50>;
93 };
94 };
95
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +020096 i2s0: i2s@10118000 {
97 compatible = "rockchip,rk3066-i2s";
98 reg = <0x10118000 0x2000>;
99 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
100 #address-cells = <1>;
101 #size-cells = <0>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2s0_bus>;
104 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
105 dma-names = "tx", "rx";
106 clock-names = "i2s_hclk", "i2s_clk";
107 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
Sugar Zhange2416572015-11-10 15:32:09 +0800108 rockchip,playback-channels = <8>;
109 rockchip,capture-channels = <2>;
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +0200110 status = "disabled";
111 };
112
113 i2s1: i2s@1011a000 {
114 compatible = "rockchip,rk3066-i2s";
115 reg = <0x1011a000 0x2000>;
116 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
117 #address-cells = <1>;
118 #size-cells = <0>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&i2s1_bus>;
121 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
122 dma-names = "tx", "rx";
123 clock-names = "i2s_hclk", "i2s_clk";
124 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
Sugar Zhange2416572015-11-10 15:32:09 +0800125 rockchip,playback-channels = <2>;
126 rockchip,capture-channels = <2>;
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +0200127 status = "disabled";
128 };
129
130 i2s2: i2s@1011c000 {
131 compatible = "rockchip,rk3066-i2s";
132 reg = <0x1011c000 0x2000>;
133 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&i2s2_bus>;
138 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
139 dma-names = "tx", "rx";
140 clock-names = "i2s_hclk", "i2s_clk";
141 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
Sugar Zhange2416572015-11-10 15:32:09 +0800142 rockchip,playback-channels = <2>;
143 rockchip,capture-channels = <2>;
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +0200144 status = "disabled";
145 };
146
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200147 cru: clock-controller@20000000 {
148 compatible = "rockchip,rk3066a-cru";
149 reg = <0x20000000 0x1000>;
150 rockchip,grf = <&grf>;
151
152 #clock-cells = <1>;
153 #reset-cells = <1>;
154 };
155
Heiko Stuebnerff84b902014-07-26 23:28:03 +0200156 timer@2000e000 {
157 compatible = "snps,dw-apb-timer-osc";
158 reg = <0x2000e000 0x100>;
159 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
161 clock-names = "timer", "pclk";
162 };
163
Caesar Wangd3369b12015-11-11 15:34:30 +0800164 efuse: efuse@20010000 {
165 compatible = "rockchip,rockchip-efuse";
166 reg = <0x20010000 0x4000>;
167 #address-cells = <1>;
168 #size-cells = <1>;
169 clocks = <&cru PCLK_EFUSE>;
170 clock-names = "pclk_efuse";
171
Heiko Stuebner66914092016-03-31 22:15:43 +0200172 cpu_leakage: cpu_leakage@17 {
Caesar Wangd3369b12015-11-11 15:34:30 +0800173 reg = <0x17 0x1>;
174 };
175 };
176
Heiko Stuebnerff84b902014-07-26 23:28:03 +0200177 timer@20038000 {
178 compatible = "snps,dw-apb-timer-osc";
179 reg = <0x20038000 0x100>;
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
182 clock-names = "timer", "pclk";
183 };
184
185 timer@2003a000 {
186 compatible = "snps,dw-apb-timer-osc";
187 reg = <0x2003a000 0x100>;
188 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
190 clock-names = "timer", "pclk";
191 };
192
Paweł Jarosz00f85082016-01-19 13:09:21 +0100193 tsadc: tsadc@20060000 {
194 compatible = "rockchip,rk3066-tsadc";
195 reg = <0x20060000 0x100>;
196 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
197 clock-names = "saradc", "apb_pclk";
198 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
199 #io-channel-cells = <1>;
Caesar Wang3d4267a2016-07-27 22:24:07 +0800200 resets = <&cru SRST_SARADC>;
201 reset-names = "saradc-apb";
Paweł Jarosz00f85082016-01-19 13:09:21 +0100202 status = "disabled";
203 };
204
Heiko Stuebner760bb972015-08-01 20:28:36 +0200205 usbphy: phy {
206 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
207 rockchip,grf = <&grf>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 status = "disabled";
211
Heiko Stuebnera8f0fa22016-03-31 20:12:14 +0200212 usbphy0: usb-phy@17c {
Heiko Stuebner760bb972015-08-01 20:28:36 +0200213 #phy-cells = <0>;
214 reg = <0x17c>;
215 clocks = <&cru SCLK_OTGPHY0>;
216 clock-names = "phyclk";
Heiko Stuebner0ace8212015-11-19 22:22:27 +0100217 #clock-cells = <0>;
Heiko Stuebner760bb972015-08-01 20:28:36 +0200218 };
219
Heiko Stuebnera8f0fa22016-03-31 20:12:14 +0200220 usbphy1: usb-phy@188 {
Heiko Stuebner760bb972015-08-01 20:28:36 +0200221 #phy-cells = <0>;
222 reg = <0x188>;
223 clocks = <&cru SCLK_OTGPHY1>;
224 clock-names = "phyclk";
Heiko Stuebner0ace8212015-11-19 22:22:27 +0100225 #clock-cells = <0>;
Heiko Stuebner760bb972015-08-01 20:28:36 +0200226 };
227 };
228
Heiko Stuebner6e4b3b42014-07-22 22:56:16 +0200229 pinctrl: pinctrl {
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200230 compatible = "rockchip,rk3066a-pinctrl";
231 rockchip,grf = <&grf>;
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges;
235
236 gpio0: gpio0@20034000 {
237 compatible = "rockchip,gpio-bank";
238 reg = <0x20034000 0x100>;
239 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cru PCLK_GPIO0>;
241
242 gpio-controller;
243 #gpio-cells = <2>;
244
245 interrupt-controller;
246 #interrupt-cells = <2>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200247 };
248
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200249 gpio1: gpio1@2003c000 {
250 compatible = "rockchip,gpio-bank";
251 reg = <0x2003c000 0x100>;
252 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru PCLK_GPIO1>;
254
255 gpio-controller;
256 #gpio-cells = <2>;
257
258 interrupt-controller;
259 #interrupt-cells = <2>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200260 };
261
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200262 gpio2: gpio2@2003e000 {
263 compatible = "rockchip,gpio-bank";
264 reg = <0x2003e000 0x100>;
265 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&cru PCLK_GPIO2>;
267
268 gpio-controller;
269 #gpio-cells = <2>;
270
271 interrupt-controller;
272 #interrupt-cells = <2>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200273 };
274
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200275 gpio3: gpio3@20080000 {
276 compatible = "rockchip,gpio-bank";
277 reg = <0x20080000 0x100>;
278 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cru PCLK_GPIO3>;
Heiko Stuebnerde18e012013-06-17 22:08:31 +0200280
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200281 gpio-controller;
282 #gpio-cells = <2>;
283
284 interrupt-controller;
285 #interrupt-cells = <2>;
286 };
287
288 gpio4: gpio4@20084000 {
289 compatible = "rockchip,gpio-bank";
290 reg = <0x20084000 0x100>;
291 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru PCLK_GPIO4>;
293
294 gpio-controller;
295 #gpio-cells = <2>;
296
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 };
300
301 gpio6: gpio6@2000a000 {
302 compatible = "rockchip,gpio-bank";
303 reg = <0x2000a000 0x100>;
304 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru PCLK_GPIO6>;
306
307 gpio-controller;
308 #gpio-cells = <2>;
309
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
314 pcfg_pull_default: pcfg_pull_default {
315 bias-pull-pin-default;
316 };
317
318 pcfg_pull_none: pcfg_pull_none {
319 bias-disable;
320 };
321
Romain Perier89f66872014-11-02 10:20:00 +0000322 emac {
323 emac_xfer: emac-xfer {
324 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
325 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
326 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
327 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
328 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
329 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
330 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
331 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
332 };
333
334 emac_mdio: emac-mdio {
335 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
336 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
337 };
338 };
339
Heiko Stuebner4ff4ae12014-09-10 17:04:36 +0200340 emmc {
341 emmc_clk: emmc-clk {
342 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
343 };
344
345 emmc_cmd: emmc-cmd {
346 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
347 };
348
349 emmc_rst: emmc-rst {
350 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
351 };
352
353 /*
354 * The data pins are shared between nandc and emmc and
355 * not accessible through pinctrl. Also they should've
356 * been already set correctly by firmware, as
357 * flash/emmc is the boot-device.
358 */
359 };
360
Heiko Stuebner9cdffd82014-06-24 20:12:06 +0200361 i2c0 {
362 i2c0_xfer: i2c0-xfer {
363 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
364 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
365 };
366 };
367
368 i2c1 {
369 i2c1_xfer: i2c1-xfer {
370 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
371 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
372 };
373 };
374
375 i2c2 {
376 i2c2_xfer: i2c2-xfer {
377 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
378 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
379 };
380 };
381
382 i2c3 {
383 i2c3_xfer: i2c3-xfer {
384 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
385 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
386 };
387 };
388
389 i2c4 {
390 i2c4_xfer: i2c4-xfer {
391 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
392 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
393 };
394 };
395
Beniamino Galvani550c7f42014-06-26 20:03:41 +0200396 pwm0 {
397 pwm0_out: pwm0-out {
398 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
399 };
400 };
401
402 pwm1 {
403 pwm1_out: pwm1-out {
404 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
405 };
406 };
407
408 pwm2 {
409 pwm2_out: pwm2-out {
410 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
411 };
412 };
413
414 pwm3 {
415 pwm3_out: pwm3-out {
416 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
417 };
418 };
419
Heiko Stuebner39c2bd72014-09-10 16:28:02 +0200420 spi0 {
421 spi0_clk: spi0-clk {
422 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
423 };
424 spi0_cs0: spi0-cs0 {
425 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
426 };
427 spi0_tx: spi0-tx {
428 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
429 };
430 spi0_rx: spi0-rx {
431 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
432 };
433 spi0_cs1: spi0-cs1 {
434 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
435 };
436 };
437
438 spi1 {
439 spi1_clk: spi1-clk {
440 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
441 };
442 spi1_cs0: spi1-cs0 {
443 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
444 };
445 spi1_rx: spi1-rx {
446 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
447 };
448 spi1_tx: spi1-tx {
449 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
450 };
451 spi1_cs1: spi1-cs1 {
452 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
453 };
454 };
455
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200456 uart0 {
457 uart0_xfer: uart0-xfer {
458 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
459 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
460 };
461
462 uart0_cts: uart0-cts {
463 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
464 };
465
466 uart0_rts: uart0-rts {
467 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerde18e012013-06-17 22:08:31 +0200468 };
469 };
470
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200471 uart1 {
472 uart1_xfer: uart1-xfer {
473 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
474 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
475 };
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +0200476
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200477 uart1_cts: uart1-cts {
478 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
479 };
480
481 uart1_rts: uart1-rts {
482 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
483 };
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +0200484 };
485
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200486 uart2 {
487 uart2_xfer: uart2-xfer {
488 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
489 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
490 };
491 /* no rts / cts for uart2 */
492 };
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200493
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200494 uart3 {
495 uart3_xfer: uart3-xfer {
496 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
497 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200498 };
499
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200500 uart3_cts: uart3-cts {
501 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200502 };
503
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200504 uart3_rts: uart3-rts {
505 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
506 };
507 };
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200508
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200509 sd0 {
510 sd0_clk: sd0-clk {
511 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200512 };
513
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200514 sd0_cmd: sd0-cmd {
515 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200516 };
517
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200518 sd0_cd: sd0-cd {
519 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200520 };
521
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200522 sd0_wp: sd0-wp {
523 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200524 };
525
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200526 sd0_bus1: sd0-bus-width1 {
527 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200528 };
529
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200530 sd0_bus4: sd0-bus-width4 {
531 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
532 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
533 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
534 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
535 };
536 };
537
538 sd1 {
539 sd1_clk: sd1-clk {
540 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200541 };
542
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200543 sd1_cmd: sd1-cmd {
544 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200545 };
546
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200547 sd1_cd: sd1-cd {
548 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200549 };
550
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200551 sd1_wp: sd1-wp {
552 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200553 };
554
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200555 sd1_bus1: sd1-bus-width1 {
556 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200557 };
558
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200559 sd1_bus4: sd1-bus-width4 {
560 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
561 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
562 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
563 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200564 };
565 };
Julien CHAUVEAU5fe62b82014-10-14 10:16:37 +0200566
567 i2s0 {
568 i2s0_bus: i2s0-bus {
569 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
570 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
571 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
572 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
573 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
574 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
575 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
576 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
577 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
578 };
579 };
580
581 i2s1 {
582 i2s1_bus: i2s1-bus {
583 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
584 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
585 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
586 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
587 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
588 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
589 };
590 };
591
592 i2s2 {
593 i2s2_bus: i2s2-bus {
594 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
595 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
596 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
597 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
598 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
599 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
600 };
601 };
Heiko Stuebnerd63dc052013-06-02 23:09:41 +0200602 };
603};
Heiko Stuebnerfcbbf962014-07-26 23:08:06 +0200604
Heiko Stuebner9cdffd82014-06-24 20:12:06 +0200605&i2c0 {
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c0_xfer>;
608};
609
610&i2c1 {
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c1_xfer>;
613};
614
615&i2c2 {
616 pinctrl-names = "default";
617 pinctrl-0 = <&i2c2_xfer>;
618};
619
620&i2c3 {
621 pinctrl-names = "default";
622 pinctrl-0 = <&i2c3_xfer>;
623};
624
625&i2c4 {
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2c4_xfer>;
628};
629
Heiko Stuebnerfcbbf962014-07-26 23:08:06 +0200630&mmc0 {
631 pinctrl-names = "default";
632 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
633};
634
635&mmc1 {
636 pinctrl-names = "default";
637 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
638};
639
Beniamino Galvani550c7f42014-06-26 20:03:41 +0200640&pwm0 {
641 pinctrl-names = "default";
642 pinctrl-0 = <&pwm0_out>;
643};
644
645&pwm1 {
646 pinctrl-names = "default";
647 pinctrl-0 = <&pwm1_out>;
648};
649
650&pwm2 {
651 pinctrl-names = "default";
652 pinctrl-0 = <&pwm2_out>;
653};
654
655&pwm3 {
656 pinctrl-names = "default";
657 pinctrl-0 = <&pwm3_out>;
658};
659
Heiko Stuebner39c2bd72014-09-10 16:28:02 +0200660&spi0 {
661 pinctrl-names = "default";
662 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
663};
664
665&spi1 {
666 pinctrl-names = "default";
667 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
668};
669
Heiko Stuebnerfcbbf962014-07-26 23:08:06 +0200670&uart0 {
671 pinctrl-names = "default";
672 pinctrl-0 = <&uart0_xfer>;
673};
674
675&uart1 {
676 pinctrl-names = "default";
677 pinctrl-0 = <&uart1_xfer>;
678};
679
680&uart2 {
681 pinctrl-names = "default";
682 pinctrl-0 = <&uart2_xfer>;
683};
684
685&uart3 {
686 pinctrl-names = "default";
687 pinctrl-0 = <&uart3_xfer>;
688};
Heiko Stuebnereb2b9d42014-07-30 10:16:17 +0200689
690&wdt {
691 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
692};
Romain Perier89f66872014-11-02 10:20:00 +0000693
694&emac {
695 compatible = "rockchip,rk3066-emac";
696};