Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Probe for F81216A LPC to 4 UART |
| 3 | * |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 4 | * Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 5 | * |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License. |
| 10 | */ |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/pci.h> |
| 13 | #include <linux/pnp.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/serial_core.h> |
Ji-Ze Hong (Peter Hong) | 4da22f1 | 2016-05-27 10:02:51 +0800 | [diff] [blame] | 16 | #include <linux/irq.h> |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 17 | #include "8250.h" |
| 18 | |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 19 | #define ADDR_PORT 0 |
| 20 | #define DATA_PORT 1 |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 21 | #define EXIT_KEY 0xAA |
| 22 | #define CHIP_ID1 0x20 |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 23 | #define CHIP_ID2 0x21 |
Ricardo Ribalda Delgado | dae77f7 | 2015-06-16 10:59:38 +0200 | [diff] [blame] | 24 | #define CHIP_ID_0 0x1602 |
| 25 | #define CHIP_ID_1 0x0501 |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 26 | #define VENDOR_ID1 0x23 |
| 27 | #define VENDOR_ID1_VAL 0x19 |
| 28 | #define VENDOR_ID2 0x24 |
| 29 | #define VENDOR_ID2_VAL 0x34 |
Ricardo Ribalda Delgado | 29d5864 | 2015-06-16 10:59:40 +0200 | [diff] [blame] | 30 | #define IO_ADDR1 0x61 |
| 31 | #define IO_ADDR2 0x60 |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 32 | #define LDN 0x7 |
| 33 | |
Arnd Bergmann | 87a713c | 2016-08-10 23:54:13 +0200 | [diff] [blame] | 34 | #define FINTEK_IRQ_MODE 0x70 |
Ji-Ze Hong (Peter Hong) | 4da22f1 | 2016-05-27 10:02:51 +0800 | [diff] [blame] | 35 | #define IRQ_SHARE BIT(4) |
| 36 | #define IRQ_MODE_MASK (BIT(6) | BIT(5)) |
| 37 | #define IRQ_LEVEL_LOW 0 |
| 38 | #define IRQ_EDGE_HIGH BIT(5) |
| 39 | |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 40 | #define RS485 0xF0 |
| 41 | #define RTS_INVERT BIT(5) |
| 42 | #define RS485_URA BIT(4) |
| 43 | #define RXW4C_IRA BIT(3) |
| 44 | #define TXW4C_IRA BIT(2) |
| 45 | |
Ricardo Ribalda Delgado | 92a5f11 | 2015-06-16 10:59:36 +0200 | [diff] [blame] | 46 | struct fintek_8250 { |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 47 | u16 base_port; |
Ricardo Ribalda Delgado | 92a5f11 | 2015-06-16 10:59:36 +0200 | [diff] [blame] | 48 | u8 index; |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 49 | u8 key; |
Ricardo Ribalda Delgado | 92a5f11 | 2015-06-16 10:59:36 +0200 | [diff] [blame] | 50 | }; |
| 51 | |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 52 | static int fintek_8250_enter_key(u16 base_port, u8 key) |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 53 | { |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 54 | if (!request_muxed_region(base_port, 2, "8250_fintek")) |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 55 | return -EBUSY; |
| 56 | |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 57 | outb(key, base_port + ADDR_PORT); |
| 58 | outb(key, base_port + ADDR_PORT); |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 59 | return 0; |
| 60 | } |
| 61 | |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 62 | static void fintek_8250_exit_key(u16 base_port) |
| 63 | { |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 64 | |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 65 | outb(EXIT_KEY, base_port + ADDR_PORT); |
| 66 | release_region(base_port + ADDR_PORT, 2); |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 67 | } |
| 68 | |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 69 | static int fintek_8250_check_id(u16 base_port) |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 70 | { |
Ricardo Ribalda Delgado | dae77f7 | 2015-06-16 10:59:38 +0200 | [diff] [blame] | 71 | u16 chip; |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 72 | |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 73 | outb(VENDOR_ID1, base_port + ADDR_PORT); |
| 74 | if (inb(base_port + DATA_PORT) != VENDOR_ID1_VAL) |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 75 | return -ENODEV; |
| 76 | |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 77 | outb(VENDOR_ID2, base_port + ADDR_PORT); |
| 78 | if (inb(base_port + DATA_PORT) != VENDOR_ID2_VAL) |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 79 | return -ENODEV; |
| 80 | |
Ricardo Ribalda Delgado | dae77f7 | 2015-06-16 10:59:38 +0200 | [diff] [blame] | 81 | outb(CHIP_ID1, base_port + ADDR_PORT); |
| 82 | chip = inb(base_port + DATA_PORT); |
| 83 | outb(CHIP_ID2, base_port + ADDR_PORT); |
| 84 | chip |= inb(base_port + DATA_PORT) << 8; |
| 85 | |
| 86 | if (chip != CHIP_ID_0 && chip != CHIP_ID_1) |
| 87 | return -ENODEV; |
| 88 | |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 89 | return 0; |
| 90 | } |
| 91 | |
Ricardo Ribalda Delgado | 41e6909 | 2014-11-06 09:22:52 +0100 | [diff] [blame] | 92 | static int fintek_8250_rs485_config(struct uart_port *port, |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 93 | struct serial_rs485 *rs485) |
| 94 | { |
| 95 | uint8_t config = 0; |
Ricardo Ribalda Delgado | 92a5f11 | 2015-06-16 10:59:36 +0200 | [diff] [blame] | 96 | struct fintek_8250 *pdata = port->private_data; |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 97 | |
Ricardo Ribalda Delgado | 92a5f11 | 2015-06-16 10:59:36 +0200 | [diff] [blame] | 98 | if (!pdata) |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 99 | return -EINVAL; |
| 100 | |
| 101 | if (rs485->flags & SER_RS485_ENABLED) |
| 102 | memset(rs485->padding, 0, sizeof(rs485->padding)); |
| 103 | else |
| 104 | memset(rs485, 0, sizeof(*rs485)); |
| 105 | |
| 106 | rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | |
| 107 | SER_RS485_RTS_AFTER_SEND; |
| 108 | |
| 109 | if (rs485->delay_rts_before_send) { |
| 110 | rs485->delay_rts_before_send = 1; |
| 111 | config |= TXW4C_IRA; |
| 112 | } |
| 113 | |
| 114 | if (rs485->delay_rts_after_send) { |
| 115 | rs485->delay_rts_after_send = 1; |
| 116 | config |= RXW4C_IRA; |
| 117 | } |
| 118 | |
| 119 | if ((!!(rs485->flags & SER_RS485_RTS_ON_SEND)) == |
| 120 | (!!(rs485->flags & SER_RS485_RTS_AFTER_SEND))) |
| 121 | rs485->flags &= SER_RS485_ENABLED; |
| 122 | else |
| 123 | config |= RS485_URA; |
| 124 | |
| 125 | if (rs485->flags & SER_RS485_RTS_ON_SEND) |
| 126 | config |= RTS_INVERT; |
| 127 | |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 128 | if (fintek_8250_enter_key(pdata->base_port, pdata->key)) |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 129 | return -EBUSY; |
| 130 | |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 131 | outb(LDN, pdata->base_port + ADDR_PORT); |
| 132 | outb(pdata->index, pdata->base_port + DATA_PORT); |
| 133 | outb(RS485, pdata->base_port + ADDR_PORT); |
| 134 | outb(config, pdata->base_port + DATA_PORT); |
| 135 | fintek_8250_exit_key(pdata->base_port); |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 136 | |
Ricardo Ribalda Delgado | 41e6909 | 2014-11-06 09:22:52 +0100 | [diff] [blame] | 137 | port->rs485 = *rs485; |
| 138 | |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 139 | return 0; |
| 140 | } |
| 141 | |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 142 | static int find_base_port(struct fintek_8250 *pdata, u16 io_address) |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 143 | { |
| 144 | static const u16 addr[] = {0x4e, 0x2e}; |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 145 | static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67}; |
Ricardo Ribalda Delgado | 29d5864 | 2015-06-16 10:59:40 +0200 | [diff] [blame] | 146 | int i, j, k; |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 147 | |
| 148 | for (i = 0; i < ARRAY_SIZE(addr); i++) { |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 149 | for (j = 0; j < ARRAY_SIZE(keys); j++) { |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 150 | |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 151 | if (fintek_8250_enter_key(addr[i], keys[j])) |
| 152 | continue; |
Ricardo Ribalda Delgado | 29d5864 | 2015-06-16 10:59:40 +0200 | [diff] [blame] | 153 | if (fintek_8250_check_id(addr[i])) { |
| 154 | fintek_8250_exit_key(addr[i]); |
| 155 | continue; |
| 156 | } |
| 157 | |
| 158 | for (k = 0; k < 4; k++) { |
| 159 | u16 aux; |
| 160 | |
| 161 | outb(LDN, addr[i] + ADDR_PORT); |
| 162 | outb(k, addr[i] + DATA_PORT); |
| 163 | |
| 164 | outb(IO_ADDR1, addr[i] + ADDR_PORT); |
| 165 | aux = inb(addr[i] + DATA_PORT); |
| 166 | outb(IO_ADDR2, addr[i] + ADDR_PORT); |
| 167 | aux |= inb(addr[i] + DATA_PORT) << 8; |
| 168 | if (aux != io_address) |
| 169 | continue; |
| 170 | |
| 171 | fintek_8250_exit_key(addr[i]); |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 172 | pdata->key = keys[j]; |
| 173 | pdata->base_port = addr[i]; |
| 174 | pdata->index = k; |
| 175 | |
| 176 | return 0; |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 177 | } |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 178 | |
Ricardo Ribalda Delgado | 29d5864 | 2015-06-16 10:59:40 +0200 | [diff] [blame] | 179 | fintek_8250_exit_key(addr[i]); |
Ricardo Ribalda Delgado | ce8c267 | 2015-06-16 10:59:39 +0200 | [diff] [blame] | 180 | } |
Ricardo Ribalda Delgado | 017bec3 | 2015-06-16 10:59:37 +0200 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | return -ENODEV; |
| 184 | } |
| 185 | |
Ji-Ze Hong (Peter Hong) | 4da22f1 | 2016-05-27 10:02:51 +0800 | [diff] [blame] | 186 | static int fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool level_mode) |
| 187 | { |
| 188 | int status; |
| 189 | u8 tmp; |
| 190 | |
| 191 | status = fintek_8250_enter_key(pdata->base_port, pdata->key); |
| 192 | if (status) |
| 193 | return status; |
| 194 | |
| 195 | outb(LDN, pdata->base_port + ADDR_PORT); |
| 196 | outb(pdata->index, pdata->base_port + DATA_PORT); |
| 197 | |
Arnd Bergmann | 87a713c | 2016-08-10 23:54:13 +0200 | [diff] [blame] | 198 | outb(FINTEK_IRQ_MODE, pdata->base_port + ADDR_PORT); |
Ji-Ze Hong (Peter Hong) | 4da22f1 | 2016-05-27 10:02:51 +0800 | [diff] [blame] | 199 | tmp = inb(pdata->base_port + DATA_PORT); |
| 200 | |
| 201 | tmp &= ~IRQ_MODE_MASK; |
| 202 | tmp |= IRQ_SHARE; |
| 203 | if (!level_mode) |
| 204 | tmp |= IRQ_EDGE_HIGH; |
| 205 | |
| 206 | outb(tmp, pdata->base_port + DATA_PORT); |
| 207 | fintek_8250_exit_key(pdata->base_port); |
| 208 | return 0; |
| 209 | } |
| 210 | |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 211 | int fintek_8250_probe(struct uart_8250_port *uart) |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 212 | { |
Ricardo Ribalda Delgado | 92a5f11 | 2015-06-16 10:59:36 +0200 | [diff] [blame] | 213 | struct fintek_8250 *pdata; |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 214 | struct fintek_8250 probe_data; |
Ji-Ze Hong (Peter Hong) | 4da22f1 | 2016-05-27 10:02:51 +0800 | [diff] [blame] | 215 | struct irq_data *irq_data = irq_get_irq_data(uart->port.irq); |
| 216 | bool level_mode = irqd_is_level_type(irq_data); |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 217 | |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 218 | if (find_base_port(&probe_data, uart->port.iobase)) |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 219 | return -ENODEV; |
| 220 | |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 221 | pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL); |
Ricardo Ribalda Delgado | 92a5f11 | 2015-06-16 10:59:36 +0200 | [diff] [blame] | 222 | if (!pdata) |
| 223 | return -ENOMEM; |
Ricardo Ribalda Delgado | 92a5f11 | 2015-06-16 10:59:36 +0200 | [diff] [blame] | 224 | |
Ricardo Ribalda Delgado | fa01e2c | 2016-04-27 10:40:10 +0200 | [diff] [blame] | 225 | memcpy(pdata, &probe_data, sizeof(probe_data)); |
| 226 | uart->port.rs485_config = fintek_8250_rs485_config; |
| 227 | uart->port.private_data = pdata; |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 228 | |
Ji-Ze Hong (Peter Hong) | 4da22f1 | 2016-05-27 10:02:51 +0800 | [diff] [blame] | 229 | return fintek_8250_set_irq_mode(pdata, level_mode); |
Ricardo Ribalda Delgado | 28e3fb6 | 2014-07-31 21:22:26 +0200 | [diff] [blame] | 230 | } |