Satyajit Desai | 326497c | 2016-11-14 10:15:03 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2011-2012, 2016, The Linux Foundation. All rights reserved. |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 2 | * |
Paul Gortmaker | 941943c | 2016-02-17 17:52:03 -0700 | [diff] [blame] | 3 | * Description: CoreSight Program Flow Trace driver |
| 4 | * |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 and |
| 7 | * only version 2 as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/kernel.h> |
Paul Gortmaker | 941943c | 2016-02-17 17:52:03 -0700 | [diff] [blame] | 16 | #include <linux/moduleparam.h> |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 17 | #include <linux/init.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/device.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/fs.h> |
| 23 | #include <linux/slab.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/smp.h> |
| 26 | #include <linux/sysfs.h> |
| 27 | #include <linux/stat.h> |
Linus Walleij | ec36005 | 2015-05-19 10:55:09 -0600 | [diff] [blame] | 28 | #include <linux/pm_runtime.h> |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 29 | #include <linux/cpu.h> |
| 30 | #include <linux/of.h> |
| 31 | #include <linux/coresight.h> |
Mathieu Poirier | 17534ce | 2016-02-17 17:52:02 -0700 | [diff] [blame] | 32 | #include <linux/coresight-pmu.h> |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 33 | #include <linux/amba/bus.h> |
| 34 | #include <linux/seq_file.h> |
| 35 | #include <linux/uaccess.h> |
Linus Walleij | d1839e6 | 2015-05-19 10:55:14 -0600 | [diff] [blame] | 36 | #include <linux/clk.h> |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 37 | #include <linux/perf_event.h> |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 38 | #include <asm/sections.h> |
| 39 | |
| 40 | #include "coresight-etm.h" |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 41 | #include "coresight-etm-perf.h" |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 42 | |
Paul Gortmaker | 941943c | 2016-02-17 17:52:03 -0700 | [diff] [blame] | 43 | /* |
| 44 | * Not really modular but using module_param is the easiest way to |
| 45 | * remain consistent with existing use cases for now. |
| 46 | */ |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 47 | static int boot_enable; |
Satyajit Desai | 326497c | 2016-11-14 10:15:03 -0800 | [diff] [blame] | 48 | module_param_named(boot_enable, boot_enable, int, 0444); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 49 | |
| 50 | /* The number of ETM/PTM currently registered */ |
| 51 | static int etm_count; |
| 52 | static struct etm_drvdata *etmdrvdata[NR_CPUS]; |
| 53 | |
Richard Cochran | 2b5283d | 2016-07-13 17:16:54 +0000 | [diff] [blame] | 54 | static enum cpuhp_state hp_online; |
| 55 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 56 | /* |
| 57 | * Memory mapped writes to clear os lock are not supported on some processors |
| 58 | * and OS lock must be unlocked before any memory mapped access on such |
| 59 | * processors, otherwise memory mapped reads/writes will be invalid. |
| 60 | */ |
Mathieu Poirier | ae69a1d | 2016-02-17 17:51:50 -0700 | [diff] [blame] | 61 | static void etm_os_unlock(struct etm_drvdata *drvdata) |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 62 | { |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 63 | /* Writing any value to ETMOSLAR unlocks the trace registers */ |
| 64 | etm_writel(drvdata, 0x0, ETMOSLAR); |
Mathieu Poirier | ae69a1d | 2016-02-17 17:51:50 -0700 | [diff] [blame] | 65 | drvdata->os_unlock = true; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 66 | isb(); |
| 67 | } |
| 68 | |
| 69 | static void etm_set_pwrdwn(struct etm_drvdata *drvdata) |
| 70 | { |
| 71 | u32 etmcr; |
| 72 | |
| 73 | /* Ensure pending cp14 accesses complete before setting pwrdwn */ |
| 74 | mb(); |
| 75 | isb(); |
| 76 | etmcr = etm_readl(drvdata, ETMCR); |
| 77 | etmcr |= ETMCR_PWD_DWN; |
| 78 | etm_writel(drvdata, etmcr, ETMCR); |
| 79 | } |
| 80 | |
| 81 | static void etm_clr_pwrdwn(struct etm_drvdata *drvdata) |
| 82 | { |
| 83 | u32 etmcr; |
| 84 | |
| 85 | etmcr = etm_readl(drvdata, ETMCR); |
| 86 | etmcr &= ~ETMCR_PWD_DWN; |
| 87 | etm_writel(drvdata, etmcr, ETMCR); |
| 88 | /* Ensure pwrup completes before subsequent cp14 accesses */ |
| 89 | mb(); |
| 90 | isb(); |
| 91 | } |
| 92 | |
| 93 | static void etm_set_pwrup(struct etm_drvdata *drvdata) |
| 94 | { |
| 95 | u32 etmpdcr; |
| 96 | |
| 97 | etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); |
| 98 | etmpdcr |= ETMPDCR_PWD_UP; |
| 99 | writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); |
| 100 | /* Ensure pwrup completes before subsequent cp14 accesses */ |
| 101 | mb(); |
| 102 | isb(); |
| 103 | } |
| 104 | |
| 105 | static void etm_clr_pwrup(struct etm_drvdata *drvdata) |
| 106 | { |
| 107 | u32 etmpdcr; |
| 108 | |
| 109 | /* Ensure pending cp14 accesses complete before clearing pwrup */ |
| 110 | mb(); |
| 111 | isb(); |
| 112 | etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); |
| 113 | etmpdcr &= ~ETMPDCR_PWD_UP; |
| 114 | writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); |
| 115 | } |
| 116 | |
| 117 | /** |
| 118 | * coresight_timeout_etm - loop until a bit has changed to a specific state. |
| 119 | * @drvdata: etm's private data structure. |
| 120 | * @offset: address of a register, starting from @addr. |
| 121 | * @position: the position of the bit of interest. |
| 122 | * @value: the value the bit should have. |
| 123 | * |
| 124 | * Basically the same as @coresight_timeout except for the register access |
| 125 | * method where we have to account for CP14 configurations. |
| 126 | |
| 127 | * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if |
| 128 | * TIMEOUT_US has elapsed, which ever happens first. |
| 129 | */ |
| 130 | |
| 131 | static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset, |
| 132 | int position, int value) |
| 133 | { |
| 134 | int i; |
| 135 | u32 val; |
| 136 | |
| 137 | for (i = TIMEOUT_US; i > 0; i--) { |
| 138 | val = etm_readl(drvdata, offset); |
| 139 | /* Waiting on the bit to go from 0 to 1 */ |
| 140 | if (value) { |
| 141 | if (val & BIT(position)) |
| 142 | return 0; |
| 143 | /* Waiting on the bit to go from 1 to 0 */ |
| 144 | } else { |
| 145 | if (!(val & BIT(position))) |
| 146 | return 0; |
| 147 | } |
| 148 | |
| 149 | /* |
| 150 | * Delay is arbitrary - the specification doesn't say how long |
| 151 | * we are expected to wait. Extra check required to make sure |
| 152 | * we don't wait needlessly on the last iteration. |
| 153 | */ |
| 154 | if (i - 1) |
| 155 | udelay(1); |
| 156 | } |
| 157 | |
| 158 | return -EAGAIN; |
| 159 | } |
| 160 | |
| 161 | |
| 162 | static void etm_set_prog(struct etm_drvdata *drvdata) |
| 163 | { |
| 164 | u32 etmcr; |
| 165 | |
| 166 | etmcr = etm_readl(drvdata, ETMCR); |
| 167 | etmcr |= ETMCR_ETM_PRG; |
| 168 | etm_writel(drvdata, etmcr, ETMCR); |
| 169 | /* |
| 170 | * Recommended by spec for cp14 accesses to ensure etmcr write is |
| 171 | * complete before polling etmsr |
| 172 | */ |
| 173 | isb(); |
| 174 | if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) { |
| 175 | dev_err(drvdata->dev, |
Mathieu Poirier | af61621 | 2015-10-07 09:26:43 -0600 | [diff] [blame] | 176 | "%s: timeout observed when probing at offset %#x\n", |
| 177 | __func__, ETMSR); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 178 | } |
| 179 | } |
| 180 | |
| 181 | static void etm_clr_prog(struct etm_drvdata *drvdata) |
| 182 | { |
| 183 | u32 etmcr; |
| 184 | |
| 185 | etmcr = etm_readl(drvdata, ETMCR); |
| 186 | etmcr &= ~ETMCR_ETM_PRG; |
| 187 | etm_writel(drvdata, etmcr, ETMCR); |
| 188 | /* |
| 189 | * Recommended by spec for cp14 accesses to ensure etmcr write is |
| 190 | * complete before polling etmsr |
| 191 | */ |
| 192 | isb(); |
| 193 | if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) { |
| 194 | dev_err(drvdata->dev, |
Mathieu Poirier | af61621 | 2015-10-07 09:26:43 -0600 | [diff] [blame] | 195 | "%s: timeout observed when probing at offset %#x\n", |
| 196 | __func__, ETMSR); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 197 | } |
| 198 | } |
| 199 | |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 200 | void etm_set_default(struct etm_config *config) |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 201 | { |
| 202 | int i; |
| 203 | |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 204 | if (WARN_ON_ONCE(!config)) |
| 205 | return; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 206 | |
Mathieu Poirier | c528a25 | 2016-02-17 17:51:55 -0700 | [diff] [blame] | 207 | /* |
| 208 | * Taken verbatim from the TRM: |
| 209 | * |
| 210 | * To trace all memory: |
| 211 | * set bit [24] in register 0x009, the ETMTECR1, to 1 |
| 212 | * set all other bits in register 0x009, the ETMTECR1, to 0 |
| 213 | * set all bits in register 0x007, the ETMTECR2, to 0 |
| 214 | * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). |
| 215 | */ |
| 216 | config->enable_ctrl1 = BIT(24); |
| 217 | config->enable_ctrl2 = 0x0; |
| 218 | config->enable_event = ETM_HARD_WIRE_RES_A; |
| 219 | |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 220 | config->trigger_event = ETM_DEFAULT_EVENT_VAL; |
| 221 | config->enable_event = ETM_HARD_WIRE_RES_A; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 222 | |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 223 | config->seq_12_event = ETM_DEFAULT_EVENT_VAL; |
| 224 | config->seq_21_event = ETM_DEFAULT_EVENT_VAL; |
| 225 | config->seq_23_event = ETM_DEFAULT_EVENT_VAL; |
| 226 | config->seq_31_event = ETM_DEFAULT_EVENT_VAL; |
| 227 | config->seq_32_event = ETM_DEFAULT_EVENT_VAL; |
| 228 | config->seq_13_event = ETM_DEFAULT_EVENT_VAL; |
| 229 | config->timestamp_event = ETM_DEFAULT_EVENT_VAL; |
| 230 | |
| 231 | for (i = 0; i < ETM_MAX_CNTR; i++) { |
| 232 | config->cntr_rld_val[i] = 0x0; |
| 233 | config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL; |
| 234 | config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL; |
| 235 | config->cntr_val[i] = 0x0; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 236 | } |
| 237 | |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 238 | config->seq_curr_state = 0x0; |
| 239 | config->ctxid_idx = 0x0; |
| 240 | for (i = 0; i < ETM_MAX_CTXID_CMP; i++) { |
| 241 | config->ctxid_pid[i] = 0x0; |
| 242 | config->ctxid_vpid[i] = 0x0; |
Chunyan Zhang | a440617 | 2015-07-31 09:37:27 -0600 | [diff] [blame] | 243 | } |
| 244 | |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 245 | config->ctxid_mask = 0x0; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 246 | } |
| 247 | |
Mathieu Poirier | 2127154 | 2016-02-17 17:51:56 -0700 | [diff] [blame] | 248 | void etm_config_trace_mode(struct etm_config *config) |
| 249 | { |
| 250 | u32 flags, mode; |
| 251 | |
| 252 | mode = config->mode; |
| 253 | |
| 254 | mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); |
| 255 | |
| 256 | /* excluding kernel AND user space doesn't make sense */ |
| 257 | if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) |
| 258 | return; |
| 259 | |
| 260 | /* nothing to do if neither flags are set */ |
| 261 | if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) |
| 262 | return; |
| 263 | |
| 264 | flags = (1 << 0 | /* instruction execute */ |
| 265 | 3 << 3 | /* ARM instruction */ |
| 266 | 0 << 5 | /* No data value comparison */ |
| 267 | 0 << 7 | /* No exact mach */ |
| 268 | 0 << 8); /* Ignore context ID */ |
| 269 | |
| 270 | /* No need to worry about single address comparators. */ |
| 271 | config->enable_ctrl2 = 0x0; |
| 272 | |
| 273 | /* Bit 0 is address range comparator 1 */ |
| 274 | config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; |
| 275 | |
| 276 | /* |
| 277 | * On ETMv3.5: |
| 278 | * ETMACTRn[13,11] == Non-secure state comparison control |
| 279 | * ETMACTRn[12,10] == Secure state comparison control |
| 280 | * |
| 281 | * b00 == Match in all modes in this state |
| 282 | * b01 == Do not match in any more in this state |
| 283 | * b10 == Match in all modes excepts user mode in this state |
| 284 | * b11 == Match only in user mode in this state |
| 285 | */ |
| 286 | |
| 287 | /* Tracing in secure mode is not supported at this time */ |
| 288 | flags |= (0 << 12 | 1 << 10); |
| 289 | |
| 290 | if (mode & ETM_MODE_EXCL_USER) { |
| 291 | /* exclude user, match all modes except user mode */ |
| 292 | flags |= (1 << 13 | 0 << 11); |
| 293 | } else { |
| 294 | /* exclude kernel, match only in user mode */ |
| 295 | flags |= (1 << 13 | 1 << 11); |
| 296 | } |
| 297 | |
| 298 | /* |
| 299 | * The ETMEEVR register is already set to "hard wire A". As such |
| 300 | * all there is to do is setup an address comparator that spans |
| 301 | * the entire address range and configure the state and mode bits. |
| 302 | */ |
| 303 | config->addr_val[0] = (u32) 0x0; |
| 304 | config->addr_val[1] = (u32) ~0x0; |
| 305 | config->addr_acctype[0] = flags; |
| 306 | config->addr_acctype[1] = flags; |
| 307 | config->addr_type[0] = ETM_ADDR_TYPE_RANGE; |
| 308 | config->addr_type[1] = ETM_ADDR_TYPE_RANGE; |
| 309 | } |
| 310 | |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 311 | #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN) |
| 312 | |
| 313 | static int etm_parse_event_config(struct etm_drvdata *drvdata, |
Mathieu Poirier | 68905d7 | 2016-08-25 15:19:10 -0600 | [diff] [blame] | 314 | struct perf_event *event) |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 315 | { |
| 316 | struct etm_config *config = &drvdata->config; |
Mathieu Poirier | 68905d7 | 2016-08-25 15:19:10 -0600 | [diff] [blame] | 317 | struct perf_event_attr *attr = &event->attr; |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 318 | |
| 319 | if (!attr) |
| 320 | return -EINVAL; |
| 321 | |
| 322 | /* Clear configuration from previous run */ |
| 323 | memset(config, 0, sizeof(struct etm_config)); |
| 324 | |
| 325 | if (attr->exclude_kernel) |
| 326 | config->mode = ETM_MODE_EXCL_KERN; |
| 327 | |
| 328 | if (attr->exclude_user) |
| 329 | config->mode = ETM_MODE_EXCL_USER; |
| 330 | |
| 331 | /* Always start from the default config */ |
| 332 | etm_set_default(config); |
| 333 | |
| 334 | /* |
| 335 | * By default the tracers are configured to trace the whole address |
| 336 | * range. Narrow the field only if requested by user space. |
| 337 | */ |
| 338 | if (config->mode) |
| 339 | etm_config_trace_mode(config); |
| 340 | |
| 341 | /* |
| 342 | * At this time only cycle accurate and timestamp options are |
| 343 | * available. |
| 344 | */ |
| 345 | if (attr->config & ~ETM3X_SUPPORTED_OPTIONS) |
| 346 | return -EINVAL; |
| 347 | |
| 348 | config->ctrl = attr->config; |
| 349 | |
| 350 | return 0; |
| 351 | } |
| 352 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 353 | static void etm_enable_hw(void *info) |
| 354 | { |
| 355 | int i; |
| 356 | u32 etmcr; |
| 357 | struct etm_drvdata *drvdata = info; |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 358 | struct etm_config *config = &drvdata->config; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 359 | |
| 360 | CS_UNLOCK(drvdata->base); |
| 361 | |
| 362 | /* Turn engine on */ |
| 363 | etm_clr_pwrdwn(drvdata); |
| 364 | /* Apply power to trace registers */ |
| 365 | etm_set_pwrup(drvdata); |
| 366 | /* Make sure all registers are accessible */ |
| 367 | etm_os_unlock(drvdata); |
| 368 | |
| 369 | etm_set_prog(drvdata); |
| 370 | |
| 371 | etmcr = etm_readl(drvdata, ETMCR); |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 372 | /* Clear setting from a previous run if need be */ |
| 373 | etmcr &= ~ETM3X_SUPPORTED_OPTIONS; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 374 | etmcr |= drvdata->port_size; |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 375 | etmcr |= ETMCR_ETM_EN; |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 376 | etm_writel(drvdata, config->ctrl | etmcr, ETMCR); |
| 377 | etm_writel(drvdata, config->trigger_event, ETMTRIGGER); |
| 378 | etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR); |
| 379 | etm_writel(drvdata, config->enable_event, ETMTEEVR); |
| 380 | etm_writel(drvdata, config->enable_ctrl1, ETMTECR1); |
| 381 | etm_writel(drvdata, config->fifofull_level, ETMFFLR); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 382 | for (i = 0; i < drvdata->nr_addr_cmp; i++) { |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 383 | etm_writel(drvdata, config->addr_val[i], ETMACVRn(i)); |
| 384 | etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i)); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 385 | } |
| 386 | for (i = 0; i < drvdata->nr_cntr; i++) { |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 387 | etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i)); |
| 388 | etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i)); |
| 389 | etm_writel(drvdata, config->cntr_rld_event[i], |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 390 | ETMCNTRLDEVRn(i)); |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 391 | etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i)); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 392 | } |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 393 | etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR); |
| 394 | etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR); |
| 395 | etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR); |
| 396 | etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR); |
| 397 | etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR); |
| 398 | etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR); |
| 399 | etm_writel(drvdata, config->seq_curr_state, ETMSQR); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 400 | for (i = 0; i < drvdata->nr_ext_out; i++) |
| 401 | etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i)); |
| 402 | for (i = 0; i < drvdata->nr_ctxid_cmp; i++) |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 403 | etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i)); |
| 404 | etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR); |
| 405 | etm_writel(drvdata, config->sync_freq, ETMSYNCFR); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 406 | /* No external input selected */ |
| 407 | etm_writel(drvdata, 0x0, ETMEXTINSELR); |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 408 | etm_writel(drvdata, config->timestamp_event, ETMTSEVR); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 409 | /* No auxiliary control selected */ |
| 410 | etm_writel(drvdata, 0x0, ETMAUXCR); |
| 411 | etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR); |
| 412 | /* No VMID comparator value selected */ |
| 413 | etm_writel(drvdata, 0x0, ETMVMIDCVR); |
| 414 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 415 | etm_clr_prog(drvdata); |
| 416 | CS_LOCK(drvdata->base); |
| 417 | |
| 418 | dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); |
| 419 | } |
| 420 | |
Mathieu Poirier | 52210c8 | 2016-02-02 14:14:01 -0700 | [diff] [blame] | 421 | static int etm_cpu_id(struct coresight_device *csdev) |
| 422 | { |
| 423 | struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 424 | |
| 425 | return drvdata->cpu; |
| 426 | } |
| 427 | |
Mathieu Poirier | c04148e | 2016-02-17 17:51:49 -0700 | [diff] [blame] | 428 | int etm_get_trace_id(struct etm_drvdata *drvdata) |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 429 | { |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 430 | unsigned long flags; |
| 431 | int trace_id = -1; |
| 432 | |
Mathieu Poirier | c04148e | 2016-02-17 17:51:49 -0700 | [diff] [blame] | 433 | if (!drvdata) |
| 434 | goto out; |
| 435 | |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 436 | if (!local_read(&drvdata->mode)) |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 437 | return drvdata->traceid; |
Mathieu Poirier | c04148e | 2016-02-17 17:51:49 -0700 | [diff] [blame] | 438 | |
| 439 | pm_runtime_get_sync(drvdata->dev); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 440 | |
| 441 | spin_lock_irqsave(&drvdata->spinlock, flags); |
| 442 | |
| 443 | CS_UNLOCK(drvdata->base); |
| 444 | trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); |
| 445 | CS_LOCK(drvdata->base); |
| 446 | |
| 447 | spin_unlock_irqrestore(&drvdata->spinlock, flags); |
Mathieu Poirier | c04148e | 2016-02-17 17:51:49 -0700 | [diff] [blame] | 448 | pm_runtime_put(drvdata->dev); |
Linus Walleij | ec36005 | 2015-05-19 10:55:09 -0600 | [diff] [blame] | 449 | |
Mathieu Poirier | c04148e | 2016-02-17 17:51:49 -0700 | [diff] [blame] | 450 | out: |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 451 | return trace_id; |
Mathieu Poirier | c04148e | 2016-02-17 17:51:49 -0700 | [diff] [blame] | 452 | |
| 453 | } |
| 454 | |
| 455 | static int etm_trace_id(struct coresight_device *csdev) |
| 456 | { |
| 457 | struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 458 | |
| 459 | return etm_get_trace_id(drvdata); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 460 | } |
| 461 | |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 462 | static int etm_enable_perf(struct coresight_device *csdev, |
Mathieu Poirier | 68905d7 | 2016-08-25 15:19:10 -0600 | [diff] [blame] | 463 | struct perf_event *event) |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 464 | { |
| 465 | struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 466 | |
| 467 | if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) |
| 468 | return -EINVAL; |
| 469 | |
| 470 | /* Configure the tracer based on the session's specifics */ |
Mathieu Poirier | 68905d7 | 2016-08-25 15:19:10 -0600 | [diff] [blame] | 471 | etm_parse_event_config(drvdata, event); |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 472 | /* And enable it */ |
| 473 | etm_enable_hw(drvdata); |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 478 | static int etm_enable_sysfs(struct coresight_device *csdev) |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 479 | { |
| 480 | struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 481 | int ret; |
| 482 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 483 | spin_lock(&drvdata->spinlock); |
| 484 | |
| 485 | /* |
| 486 | * Configure the ETM only if the CPU is online. If it isn't online |
Richard Cochran | 2b5283d | 2016-07-13 17:16:54 +0000 | [diff] [blame] | 487 | * hw configuration will take place on the local CPU during bring up. |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 488 | */ |
| 489 | if (cpu_online(drvdata->cpu)) { |
| 490 | ret = smp_call_function_single(drvdata->cpu, |
| 491 | etm_enable_hw, drvdata, 1); |
| 492 | if (ret) |
| 493 | goto err; |
| 494 | } |
| 495 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 496 | drvdata->sticky_enable = true; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 497 | spin_unlock(&drvdata->spinlock); |
| 498 | |
| 499 | dev_info(drvdata->dev, "ETM tracing enabled\n"); |
| 500 | return 0; |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 501 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 502 | err: |
| 503 | spin_unlock(&drvdata->spinlock); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 504 | return ret; |
| 505 | } |
| 506 | |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 507 | static int etm_enable(struct coresight_device *csdev, |
Mathieu Poirier | 68905d7 | 2016-08-25 15:19:10 -0600 | [diff] [blame] | 508 | struct perf_event *event, u32 mode) |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 509 | { |
| 510 | int ret; |
| 511 | u32 val; |
| 512 | struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 513 | |
| 514 | val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); |
| 515 | |
| 516 | /* Someone is already using the tracer */ |
| 517 | if (val) |
| 518 | return -EBUSY; |
| 519 | |
| 520 | switch (mode) { |
| 521 | case CS_MODE_SYSFS: |
| 522 | ret = etm_enable_sysfs(csdev); |
| 523 | break; |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 524 | case CS_MODE_PERF: |
Mathieu Poirier | 68905d7 | 2016-08-25 15:19:10 -0600 | [diff] [blame] | 525 | ret = etm_enable_perf(csdev, event); |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 526 | break; |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 527 | default: |
| 528 | ret = -EINVAL; |
| 529 | } |
| 530 | |
| 531 | /* The tracer didn't start */ |
| 532 | if (ret) |
| 533 | local_set(&drvdata->mode, CS_MODE_DISABLED); |
| 534 | |
| 535 | return ret; |
| 536 | } |
| 537 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 538 | static void etm_disable_hw(void *info) |
| 539 | { |
| 540 | int i; |
| 541 | struct etm_drvdata *drvdata = info; |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 542 | struct etm_config *config = &drvdata->config; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 543 | |
| 544 | CS_UNLOCK(drvdata->base); |
| 545 | etm_set_prog(drvdata); |
| 546 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 547 | /* Read back sequencer and counters for post trace analysis */ |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 548 | config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 549 | |
| 550 | for (i = 0; i < drvdata->nr_cntr; i++) |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 551 | config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i)); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 552 | |
| 553 | etm_set_pwrdwn(drvdata); |
| 554 | CS_LOCK(drvdata->base); |
| 555 | |
| 556 | dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu); |
| 557 | } |
| 558 | |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 559 | static void etm_disable_perf(struct coresight_device *csdev) |
| 560 | { |
| 561 | struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 562 | |
| 563 | if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) |
| 564 | return; |
| 565 | |
| 566 | CS_UNLOCK(drvdata->base); |
| 567 | |
| 568 | /* Setting the prog bit disables tracing immediately */ |
| 569 | etm_set_prog(drvdata); |
| 570 | |
| 571 | /* |
| 572 | * There is no way to know when the tracer will be used again so |
| 573 | * power down the tracer. |
| 574 | */ |
| 575 | etm_set_pwrdwn(drvdata); |
| 576 | |
| 577 | CS_LOCK(drvdata->base); |
| 578 | } |
| 579 | |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 580 | static void etm_disable_sysfs(struct coresight_device *csdev) |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 581 | { |
| 582 | struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 583 | |
| 584 | /* |
| 585 | * Taking hotplug lock here protects from clocks getting disabled |
| 586 | * with tracing being left on (crash scenario) if user disable occurs |
| 587 | * after cpu online mask indicates the cpu is offline but before the |
| 588 | * DYING hotplug callback is serviced by the ETM driver. |
| 589 | */ |
| 590 | get_online_cpus(); |
| 591 | spin_lock(&drvdata->spinlock); |
| 592 | |
| 593 | /* |
| 594 | * Executing etm_disable_hw on the cpu whose ETM is being disabled |
| 595 | * ensures that register writes occur when cpu is powered. |
| 596 | */ |
| 597 | smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 598 | |
| 599 | spin_unlock(&drvdata->spinlock); |
| 600 | put_online_cpus(); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 601 | |
| 602 | dev_info(drvdata->dev, "ETM tracing disabled\n"); |
| 603 | } |
| 604 | |
Mathieu Poirier | 68905d7 | 2016-08-25 15:19:10 -0600 | [diff] [blame] | 605 | static void etm_disable(struct coresight_device *csdev, |
| 606 | struct perf_event *event) |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 607 | { |
| 608 | u32 mode; |
| 609 | struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 610 | |
| 611 | /* |
| 612 | * For as long as the tracer isn't disabled another entity can't |
| 613 | * change its status. As such we can read the status here without |
| 614 | * fearing it will change under us. |
| 615 | */ |
| 616 | mode = local_read(&drvdata->mode); |
| 617 | |
| 618 | switch (mode) { |
| 619 | case CS_MODE_DISABLED: |
| 620 | break; |
| 621 | case CS_MODE_SYSFS: |
| 622 | etm_disable_sysfs(csdev); |
| 623 | break; |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 624 | case CS_MODE_PERF: |
| 625 | etm_disable_perf(csdev); |
| 626 | break; |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 627 | default: |
| 628 | WARN_ON_ONCE(mode); |
| 629 | return; |
| 630 | } |
| 631 | |
| 632 | if (mode) |
| 633 | local_set(&drvdata->mode, CS_MODE_DISABLED); |
| 634 | } |
| 635 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 636 | static const struct coresight_ops_source etm_source_ops = { |
Mathieu Poirier | 52210c8 | 2016-02-02 14:14:01 -0700 | [diff] [blame] | 637 | .cpu_id = etm_cpu_id, |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 638 | .trace_id = etm_trace_id, |
| 639 | .enable = etm_enable, |
| 640 | .disable = etm_disable, |
| 641 | }; |
| 642 | |
| 643 | static const struct coresight_ops etm_cs_ops = { |
| 644 | .source_ops = &etm_source_ops, |
| 645 | }; |
| 646 | |
Richard Cochran | 2b5283d | 2016-07-13 17:16:54 +0000 | [diff] [blame] | 647 | static int etm_online_cpu(unsigned int cpu) |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 648 | { |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 649 | if (!etmdrvdata[cpu]) |
Richard Cochran | 2b5283d | 2016-07-13 17:16:54 +0000 | [diff] [blame] | 650 | return 0; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 651 | |
Richard Cochran | 2b5283d | 2016-07-13 17:16:54 +0000 | [diff] [blame] | 652 | if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) |
| 653 | coresight_enable(etmdrvdata[cpu]->csdev); |
| 654 | return 0; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 655 | } |
| 656 | |
Richard Cochran | 2b5283d | 2016-07-13 17:16:54 +0000 | [diff] [blame] | 657 | static int etm_starting_cpu(unsigned int cpu) |
| 658 | { |
| 659 | if (!etmdrvdata[cpu]) |
| 660 | return 0; |
| 661 | |
| 662 | spin_lock(&etmdrvdata[cpu]->spinlock); |
| 663 | if (!etmdrvdata[cpu]->os_unlock) { |
| 664 | etm_os_unlock(etmdrvdata[cpu]); |
| 665 | etmdrvdata[cpu]->os_unlock = true; |
| 666 | } |
| 667 | |
| 668 | if (local_read(&etmdrvdata[cpu]->mode)) |
| 669 | etm_enable_hw(etmdrvdata[cpu]); |
| 670 | spin_unlock(&etmdrvdata[cpu]->spinlock); |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | static int etm_dying_cpu(unsigned int cpu) |
| 675 | { |
| 676 | if (!etmdrvdata[cpu]) |
| 677 | return 0; |
| 678 | |
| 679 | spin_lock(&etmdrvdata[cpu]->spinlock); |
| 680 | if (local_read(&etmdrvdata[cpu]->mode)) |
| 681 | etm_disable_hw(etmdrvdata[cpu]); |
| 682 | spin_unlock(&etmdrvdata[cpu]->spinlock); |
| 683 | return 0; |
| 684 | } |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 685 | |
| 686 | static bool etm_arch_supported(u8 arch) |
| 687 | { |
| 688 | switch (arch) { |
| 689 | case ETM_ARCH_V3_3: |
| 690 | break; |
| 691 | case ETM_ARCH_V3_5: |
| 692 | break; |
| 693 | case PFT_ARCH_V1_0: |
| 694 | break; |
| 695 | case PFT_ARCH_V1_1: |
| 696 | break; |
| 697 | default: |
| 698 | return false; |
| 699 | } |
| 700 | return true; |
| 701 | } |
| 702 | |
| 703 | static void etm_init_arch_data(void *info) |
| 704 | { |
| 705 | u32 etmidr; |
| 706 | u32 etmccr; |
| 707 | struct etm_drvdata *drvdata = info; |
| 708 | |
Mathieu Poirier | ae69a1d | 2016-02-17 17:51:50 -0700 | [diff] [blame] | 709 | /* Make sure all registers are accessible */ |
| 710 | etm_os_unlock(drvdata); |
| 711 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 712 | CS_UNLOCK(drvdata->base); |
| 713 | |
| 714 | /* First dummy read */ |
| 715 | (void)etm_readl(drvdata, ETMPDSR); |
| 716 | /* Provide power to ETM: ETMPDCR[3] == 1 */ |
| 717 | etm_set_pwrup(drvdata); |
| 718 | /* |
| 719 | * Clear power down bit since when this bit is set writes to |
| 720 | * certain registers might be ignored. |
| 721 | */ |
| 722 | etm_clr_pwrdwn(drvdata); |
| 723 | /* |
| 724 | * Set prog bit. It will be set from reset but this is included to |
| 725 | * ensure it is set |
| 726 | */ |
| 727 | etm_set_prog(drvdata); |
| 728 | |
| 729 | /* Find all capabilities */ |
| 730 | etmidr = etm_readl(drvdata, ETMIDR); |
| 731 | drvdata->arch = BMVAL(etmidr, 4, 11); |
| 732 | drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK; |
| 733 | |
| 734 | drvdata->etmccer = etm_readl(drvdata, ETMCCER); |
| 735 | etmccr = etm_readl(drvdata, ETMCCR); |
| 736 | drvdata->etmccr = etmccr; |
| 737 | drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2; |
| 738 | drvdata->nr_cntr = BMVAL(etmccr, 13, 15); |
| 739 | drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19); |
| 740 | drvdata->nr_ext_out = BMVAL(etmccr, 20, 22); |
| 741 | drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25); |
| 742 | |
| 743 | etm_set_pwrdwn(drvdata); |
| 744 | etm_clr_pwrup(drvdata); |
| 745 | CS_LOCK(drvdata->base); |
| 746 | } |
| 747 | |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 748 | static void etm_init_trace_id(struct etm_drvdata *drvdata) |
| 749 | { |
Mathieu Poirier | 17534ce | 2016-02-17 17:52:02 -0700 | [diff] [blame] | 750 | drvdata->traceid = coresight_get_trace_id(drvdata->cpu); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 751 | } |
| 752 | |
| 753 | static int etm_probe(struct amba_device *adev, const struct amba_id *id) |
| 754 | { |
| 755 | int ret; |
| 756 | void __iomem *base; |
| 757 | struct device *dev = &adev->dev; |
| 758 | struct coresight_platform_data *pdata = NULL; |
| 759 | struct etm_drvdata *drvdata; |
| 760 | struct resource *res = &adev->res; |
Suzuki K Poulose | 9486295 | 2016-08-25 15:19:05 -0600 | [diff] [blame] | 761 | struct coresight_desc desc = { 0 }; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 762 | struct device_node *np = adev->dev.of_node; |
| 763 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 764 | drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); |
| 765 | if (!drvdata) |
| 766 | return -ENOMEM; |
| 767 | |
| 768 | if (np) { |
| 769 | pdata = of_get_coresight_platform_data(dev, np); |
| 770 | if (IS_ERR(pdata)) |
| 771 | return PTR_ERR(pdata); |
| 772 | |
| 773 | adev->dev.platform_data = pdata; |
| 774 | drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14"); |
| 775 | } |
| 776 | |
| 777 | drvdata->dev = &adev->dev; |
| 778 | dev_set_drvdata(dev, drvdata); |
| 779 | |
| 780 | /* Validity for the resource is already checked by the AMBA core */ |
| 781 | base = devm_ioremap_resource(dev, res); |
| 782 | if (IS_ERR(base)) |
| 783 | return PTR_ERR(base); |
| 784 | |
| 785 | drvdata->base = base; |
| 786 | |
| 787 | spin_lock_init(&drvdata->spinlock); |
| 788 | |
Linus Walleij | d1839e6 | 2015-05-19 10:55:14 -0600 | [diff] [blame] | 789 | drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ |
| 790 | if (!IS_ERR(drvdata->atclk)) { |
| 791 | ret = clk_prepare_enable(drvdata->atclk); |
| 792 | if (ret) |
| 793 | return ret; |
| 794 | } |
| 795 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 796 | drvdata->cpu = pdata ? pdata->cpu : 0; |
| 797 | |
| 798 | get_online_cpus(); |
| 799 | etmdrvdata[drvdata->cpu] = drvdata; |
| 800 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 801 | if (smp_call_function_single(drvdata->cpu, |
| 802 | etm_init_arch_data, drvdata, 1)) |
| 803 | dev_err(dev, "ETM arch init failed\n"); |
| 804 | |
Richard Cochran | 2b5283d | 2016-07-13 17:16:54 +0000 | [diff] [blame] | 805 | if (!etm_count++) { |
| 806 | cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING, |
| 807 | "AP_ARM_CORESIGHT_STARTING", |
| 808 | etm_starting_cpu, etm_dying_cpu); |
| 809 | ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, |
| 810 | "AP_ARM_CORESIGHT_ONLINE", |
| 811 | etm_online_cpu, NULL); |
| 812 | if (ret < 0) |
| 813 | goto err_arch_supported; |
| 814 | hp_online = ret; |
| 815 | } |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 816 | put_online_cpus(); |
| 817 | |
| 818 | if (etm_arch_supported(drvdata->arch) == false) { |
| 819 | ret = -EINVAL; |
| 820 | goto err_arch_supported; |
| 821 | } |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 822 | |
| 823 | etm_init_trace_id(drvdata); |
Mathieu Poirier | c528a25 | 2016-02-17 17:51:55 -0700 | [diff] [blame] | 824 | etm_set_default(&drvdata->config); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 825 | |
Suzuki K Poulose | 9486295 | 2016-08-25 15:19:05 -0600 | [diff] [blame] | 826 | desc.type = CORESIGHT_DEV_TYPE_SOURCE; |
| 827 | desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; |
| 828 | desc.ops = &etm_cs_ops; |
| 829 | desc.pdata = pdata; |
| 830 | desc.dev = dev; |
| 831 | desc.groups = coresight_etm_groups; |
| 832 | drvdata->csdev = coresight_register(&desc); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 833 | if (IS_ERR(drvdata->csdev)) { |
| 834 | ret = PTR_ERR(drvdata->csdev); |
| 835 | goto err_arch_supported; |
| 836 | } |
| 837 | |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 838 | ret = etm_perf_symlink(drvdata->csdev, true); |
| 839 | if (ret) { |
| 840 | coresight_unregister(drvdata->csdev); |
| 841 | goto err_arch_supported; |
| 842 | } |
| 843 | |
Linus Walleij | ec36005 | 2015-05-19 10:55:09 -0600 | [diff] [blame] | 844 | pm_runtime_put(&adev->dev); |
Linus Walleij | 1c65b38 | 2015-05-19 10:55:07 -0600 | [diff] [blame] | 845 | dev_info(dev, "%s initialized\n", (char *)id->data); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 846 | if (boot_enable) { |
| 847 | coresight_enable(drvdata->csdev); |
| 848 | drvdata->boot_enable = true; |
| 849 | } |
| 850 | |
| 851 | return 0; |
| 852 | |
| 853 | err_arch_supported: |
Richard Cochran | 2b5283d | 2016-07-13 17:16:54 +0000 | [diff] [blame] | 854 | if (--etm_count == 0) { |
| 855 | cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); |
| 856 | if (hp_online) |
| 857 | cpuhp_remove_state_nocalls(hp_online); |
| 858 | } |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 859 | return ret; |
| 860 | } |
| 861 | |
Linus Walleij | d1839e6 | 2015-05-19 10:55:14 -0600 | [diff] [blame] | 862 | #ifdef CONFIG_PM |
| 863 | static int etm_runtime_suspend(struct device *dev) |
| 864 | { |
| 865 | struct etm_drvdata *drvdata = dev_get_drvdata(dev); |
| 866 | |
| 867 | if (drvdata && !IS_ERR(drvdata->atclk)) |
| 868 | clk_disable_unprepare(drvdata->atclk); |
| 869 | |
| 870 | return 0; |
| 871 | } |
| 872 | |
| 873 | static int etm_runtime_resume(struct device *dev) |
| 874 | { |
| 875 | struct etm_drvdata *drvdata = dev_get_drvdata(dev); |
| 876 | |
| 877 | if (drvdata && !IS_ERR(drvdata->atclk)) |
| 878 | clk_prepare_enable(drvdata->atclk); |
| 879 | |
| 880 | return 0; |
| 881 | } |
| 882 | #endif |
| 883 | |
| 884 | static const struct dev_pm_ops etm_dev_pm_ops = { |
| 885 | SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL) |
| 886 | }; |
| 887 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 888 | static struct amba_id etm_ids[] = { |
| 889 | { /* ETM 3.3 */ |
| 890 | .id = 0x0003b921, |
| 891 | .mask = 0x0003ffff, |
Linus Walleij | 1c65b38 | 2015-05-19 10:55:07 -0600 | [diff] [blame] | 892 | .data = "ETM 3.3", |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 893 | }, |
Olivier Schonken | 2a18d72 | 2016-08-25 15:19:03 -0600 | [diff] [blame] | 894 | { /* ETM 3.5 - Cortex-A5 */ |
| 895 | .id = 0x0003b955, |
| 896 | .mask = 0x0003ffff, |
| 897 | .data = "ETM 3.5", |
| 898 | }, |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 899 | { /* ETM 3.5 */ |
| 900 | .id = 0x0003b956, |
| 901 | .mask = 0x0003ffff, |
Linus Walleij | 1c65b38 | 2015-05-19 10:55:07 -0600 | [diff] [blame] | 902 | .data = "ETM 3.5", |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 903 | }, |
| 904 | { /* PTM 1.0 */ |
| 905 | .id = 0x0003b950, |
| 906 | .mask = 0x0003ffff, |
Linus Walleij | 1c65b38 | 2015-05-19 10:55:07 -0600 | [diff] [blame] | 907 | .data = "PTM 1.0", |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 908 | }, |
| 909 | { /* PTM 1.1 */ |
| 910 | .id = 0x0003b95f, |
| 911 | .mask = 0x0003ffff, |
Linus Walleij | 1c65b38 | 2015-05-19 10:55:07 -0600 | [diff] [blame] | 912 | .data = "PTM 1.1", |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 913 | }, |
Ivan T. Ivanov | 27d3fd3 | 2015-07-31 09:37:22 -0600 | [diff] [blame] | 914 | { /* PTM 1.1 Qualcomm */ |
| 915 | .id = 0x0003006f, |
| 916 | .mask = 0x0003ffff, |
| 917 | .data = "PTM 1.1", |
| 918 | }, |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 919 | { 0, 0}, |
| 920 | }; |
| 921 | |
| 922 | static struct amba_driver etm_driver = { |
| 923 | .drv = { |
| 924 | .name = "coresight-etm3x", |
| 925 | .owner = THIS_MODULE, |
Linus Walleij | d1839e6 | 2015-05-19 10:55:14 -0600 | [diff] [blame] | 926 | .pm = &etm_dev_pm_ops, |
Mathieu Poirier | b15f0fb | 2016-02-02 14:14:00 -0700 | [diff] [blame] | 927 | .suppress_bind_attrs = true, |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 928 | }, |
| 929 | .probe = etm_probe, |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 930 | .id_table = etm_ids, |
| 931 | }; |
Paul Gortmaker | 941943c | 2016-02-17 17:52:03 -0700 | [diff] [blame] | 932 | builtin_amba_driver(etm_driver); |