Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 33 | #include "i915_reg.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 34 | #include "intel_bios.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 35 | #include "intel_ringbuffer.h" |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 36 | #include <linux/io-mapping.h> |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 37 | #include <linux/i2c.h> |
Chris Wilson | b0b544c | 2011-01-09 12:04:40 +0000 | [diff] [blame] | 38 | #include <linux/pm_qos_params.h> |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 39 | #include <drm/intel-gtt.h> |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 40 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | /* General customization: |
| 42 | */ |
| 43 | |
| 44 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| 45 | |
| 46 | #define DRIVER_NAME "i915" |
| 47 | #define DRIVER_DESC "Intel Graphics" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 48 | #define DRIVER_DATE "20080730" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 50 | enum pipe { |
| 51 | PIPE_A = 0, |
| 52 | PIPE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 53 | PIPE_C, |
| 54 | I915_MAX_PIPES |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 55 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 56 | #define pipe_name(p) ((p) + 'A') |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 57 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 58 | enum plane { |
| 59 | PLANE_A = 0, |
| 60 | PLANE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 61 | PLANE_C, |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 62 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 63 | #define plane_name(p) ((p) + 'A') |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 64 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 65 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 66 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 67 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
| 68 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | /* Interface history: |
| 70 | * |
| 71 | * 1.1: Original. |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 72 | * 1.2: Add Power Management |
| 73 | * 1.3: Add vblank support |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 74 | * 1.4: Fix cmdbuffer path, add heap destroy |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 75 | * 1.5: Add vblank pipe configuration |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 76 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| 77 | * - Support vertical blank on secondary display pipe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | */ |
| 79 | #define DRIVER_MAJOR 1 |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 80 | #define DRIVER_MINOR 6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | #define DRIVER_PATCHLEVEL 0 |
| 82 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 83 | #define WATCH_COHERENCY 0 |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 84 | #define WATCH_LISTS 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 85 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 86 | #define I915_GEM_PHYS_CURSOR_0 1 |
| 87 | #define I915_GEM_PHYS_CURSOR_1 2 |
| 88 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
| 89 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
| 90 | |
| 91 | struct drm_i915_gem_phys_object { |
| 92 | int id; |
| 93 | struct page **page_list; |
| 94 | drm_dma_handle_t *handle; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 95 | struct drm_i915_gem_object *cur_obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 96 | }; |
| 97 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | struct mem_block { |
| 99 | struct mem_block *next; |
| 100 | struct mem_block *prev; |
| 101 | int start; |
| 102 | int size; |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 103 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | }; |
| 105 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 106 | struct opregion_header; |
| 107 | struct opregion_acpi; |
| 108 | struct opregion_swsci; |
| 109 | struct opregion_asle; |
| 110 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 111 | struct intel_opregion { |
| 112 | struct opregion_header *header; |
| 113 | struct opregion_acpi *acpi; |
| 114 | struct opregion_swsci *swsci; |
| 115 | struct opregion_asle *asle; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 116 | void *vbt; |
Chris Wilson | 01fe9db | 2011-01-16 19:37:30 +0000 | [diff] [blame] | 117 | u32 __iomem *lid_state; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 118 | }; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 119 | #define OPREGION_SIZE (8*1024) |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 120 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 121 | struct intel_overlay; |
| 122 | struct intel_overlay_error_state; |
| 123 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 124 | struct drm_i915_master_private { |
| 125 | drm_local_map_t *sarea; |
| 126 | struct _drm_i915_sarea *sarea_priv; |
| 127 | }; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 128 | #define I915_FENCE_REG_NONE -1 |
| 129 | |
| 130 | struct drm_i915_fence_reg { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 131 | struct list_head lru_list; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 132 | struct drm_i915_gem_object *obj; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 133 | uint32_t setup_seqno; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 134 | }; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 135 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 136 | struct sdvo_device_mapping { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 137 | u8 initialized; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 138 | u8 dvo_port; |
| 139 | u8 slave_addr; |
| 140 | u8 dvo_wiring; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 141 | u8 i2c_pin; |
| 142 | u8 i2c_speed; |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 143 | u8 ddc_pin; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 144 | }; |
| 145 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 146 | struct intel_display_error_state; |
| 147 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 148 | struct drm_i915_error_state { |
| 149 | u32 eir; |
| 150 | u32 pgtbl_er; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 151 | u32 pipestat[I915_MAX_PIPES]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 152 | u32 ipeir; |
| 153 | u32 ipehr; |
| 154 | u32 instdone; |
| 155 | u32 acthd; |
Chris Wilson | 1d8f38f | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 156 | u32 error; /* gen6+ */ |
| 157 | u32 bcs_acthd; /* gen6+ blt engine */ |
| 158 | u32 bcs_ipehr; |
| 159 | u32 bcs_ipeir; |
| 160 | u32 bcs_instdone; |
| 161 | u32 bcs_seqno; |
Chris Wilson | add354d | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 162 | u32 vcs_acthd; /* gen6+ bsd engine */ |
| 163 | u32 vcs_ipehr; |
| 164 | u32 vcs_ipeir; |
| 165 | u32 vcs_instdone; |
| 166 | u32 vcs_seqno; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 167 | u32 instpm; |
| 168 | u32 instps; |
| 169 | u32 instdone1; |
| 170 | u32 seqno; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 171 | u64 bbaddr; |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 172 | u64 fence[16]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 173 | struct timeval time; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 174 | struct drm_i915_error_object { |
| 175 | int page_count; |
| 176 | u32 gtt_offset; |
| 177 | u32 *pages[0]; |
Chris Wilson | e2f973d | 2011-01-27 19:15:11 +0000 | [diff] [blame] | 178 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 179 | struct drm_i915_error_buffer { |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 180 | u32 size; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 181 | u32 name; |
| 182 | u32 seqno; |
| 183 | u32 gtt_offset; |
| 184 | u32 read_domains; |
| 185 | u32 write_domain; |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 186 | s32 fence_reg:5; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 187 | s32 pinned:2; |
| 188 | u32 tiling:2; |
| 189 | u32 dirty:1; |
| 190 | u32 purgeable:1; |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 191 | u32 ring:4; |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 192 | u32 agp_type:1; |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 193 | } *active_bo, *pinned_bo; |
| 194 | u32 active_bo_count, pinned_bo_count; |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 195 | struct intel_overlay_error_state *overlay; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 196 | struct intel_display_error_state *display; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 197 | }; |
| 198 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 199 | struct drm_i915_display_funcs { |
| 200 | void (*dpms)(struct drm_crtc *crtc, int mode); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 201 | bool (*fbc_enabled)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 202 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
| 203 | void (*disable_fbc)(struct drm_device *dev); |
| 204 | int (*get_display_clock_speed)(struct drm_device *dev); |
| 205 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
Chris Wilson | d210246 | 2011-01-24 17:43:27 +0000 | [diff] [blame] | 206 | void (*update_wm)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 207 | /* clock updates for mode set */ |
| 208 | /* cursor updates */ |
| 209 | /* render clock increase/decrease */ |
| 210 | /* display clock increase/decrease */ |
| 211 | /* pll clock increase/decrease */ |
| 212 | /* clock gating init */ |
| 213 | }; |
| 214 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 215 | struct intel_device_info { |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 216 | u8 gen; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 217 | u8 is_mobile : 1; |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 218 | u8 is_i85x : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 219 | u8 is_i915g : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 220 | u8 is_i945gm : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 221 | u8 is_g33 : 1; |
| 222 | u8 need_gfx_hws : 1; |
| 223 | u8 is_g4x : 1; |
| 224 | u8 is_pineview : 1; |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 225 | u8 is_broadwater : 1; |
| 226 | u8 is_crestline : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 227 | u8 has_fbc : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 228 | u8 has_pipe_cxsr : 1; |
| 229 | u8 has_hotplug : 1; |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 230 | u8 cursor_needs_physical : 1; |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 231 | u8 has_overlay : 1; |
| 232 | u8 overlay_needs_physical : 1; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 233 | u8 supports_tv : 1; |
Xiang, Haihao | 92f49d9 | 2010-09-16 10:43:10 +0800 | [diff] [blame] | 234 | u8 has_bsd_ring : 1; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 235 | u8 has_blt_ring : 1; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 236 | }; |
| 237 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 238 | enum no_fbc_reason { |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 239 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 240 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
| 241 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
| 242 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
| 243 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
| 244 | FBC_NOT_TILED, /* buffer not tiled */ |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 245 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 246 | }; |
| 247 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 248 | enum intel_pch { |
| 249 | PCH_IBX, /* Ibexpeak PCH */ |
| 250 | PCH_CPT, /* Cougarpoint PCH */ |
| 251 | }; |
| 252 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 253 | #define QUIRK_PIPEA_FORCE (1<<0) |
| 254 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 255 | struct intel_fbdev; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 256 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | typedef struct drm_i915_private { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 258 | struct drm_device *dev; |
| 259 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 260 | const struct intel_device_info *info; |
| 261 | |
Dave Airlie | ac5c4e7 | 2008-12-19 15:38:34 +1000 | [diff] [blame] | 262 | int has_gem; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 263 | int relative_constants_mode; |
Dave Airlie | ac5c4e7 | 2008-12-19 15:38:34 +1000 | [diff] [blame] | 264 | |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 265 | void __iomem *regs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 267 | struct intel_gmbus { |
| 268 | struct i2c_adapter adapter; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 269 | struct i2c_adapter *force_bit; |
| 270 | u32 reg0; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 271 | } *gmbus; |
| 272 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 273 | struct pci_dev *bridge_dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 274 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 275 | uint32_t next_seqno; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | |
Dave Airlie | 9c8da5e | 2005-07-10 15:38:56 +1000 | [diff] [blame] | 277 | drm_dma_handle_t *status_page_dmah; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | dma_addr_t dma_status_page; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 279 | uint32_t counter; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 280 | drm_local_map_t hws_map; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 281 | struct drm_i915_gem_object *pwrctx; |
| 282 | struct drm_i915_gem_object *renderctx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | |
Jesse Barnes | d765898 | 2009-06-05 14:41:29 +0000 | [diff] [blame] | 284 | struct resource mch_res; |
| 285 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 286 | unsigned int cpp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | int back_offset; |
| 288 | int front_offset; |
| 289 | int current_page; |
| 290 | int page_flipping; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | atomic_t irq_received; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 293 | |
| 294 | /* protects the irq masks */ |
| 295 | spinlock_t irq_lock; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 296 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 297 | u32 pipestat[2]; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 298 | u32 irq_mask; |
| 299 | u32 gt_irq_mask; |
| 300 | u32 pch_irq_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 302 | u32 hotplug_supported_mask; |
| 303 | struct work_struct hotplug_work; |
| 304 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | int tex_lru_log_granularity; |
| 306 | int allow_batchbuffer; |
| 307 | struct mem_block *agp_heap; |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 308 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 309 | int vblank_pipe; |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 310 | int num_pipe; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 311 | |
Chris Wilson | b0b544c | 2011-01-09 12:04:40 +0000 | [diff] [blame] | 312 | atomic_t vblank_enabled; |
| 313 | struct pm_qos_request_list vblank_pm_qos; |
| 314 | struct work_struct vblank_work; |
| 315 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 316 | /* For hangcheck timer */ |
Chris Wilson | 576ae4b | 2010-11-12 13:36:26 +0000 | [diff] [blame] | 317 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 318 | struct timer_list hangcheck_timer; |
| 319 | int hangcheck_count; |
| 320 | uint32_t last_acthd; |
Chris Wilson | cbb465e | 2010-06-06 12:16:24 +0100 | [diff] [blame] | 321 | uint32_t last_instdone; |
| 322 | uint32_t last_instdone1; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 323 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 324 | unsigned long cfb_size; |
| 325 | unsigned long cfb_pitch; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 326 | unsigned long cfb_offset; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 327 | int cfb_fence; |
| 328 | int cfb_plane; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 329 | int cfb_y; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 330 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 331 | struct intel_opregion opregion; |
| 332 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 333 | /* overlay */ |
| 334 | struct intel_overlay *overlay; |
| 335 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 336 | /* LVDS info */ |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 337 | int backlight_level; /* restore backlight to this value */ |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 338 | bool backlight_enabled; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 339 | struct drm_display_mode *panel_fixed_mode; |
Ma Ling | 8863170 | 2009-05-13 11:19:55 +0800 | [diff] [blame] | 340 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 341 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 342 | |
| 343 | /* Feature bits from the VBIOS */ |
Hannes Eder | 95281e3 | 2008-12-18 15:09:00 +0100 | [diff] [blame] | 344 | unsigned int int_tv_support:1; |
| 345 | unsigned int lvds_dither:1; |
| 346 | unsigned int lvds_vbt:1; |
| 347 | unsigned int int_crt_support:1; |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 348 | unsigned int lvds_use_ssc:1; |
| 349 | int lvds_ssc_freq; |
Chris Wilson | 5ceb0f9 | 2010-09-24 10:24:28 +0100 | [diff] [blame] | 350 | struct { |
Jesse Barnes | 9f0e7ff | 2010-10-07 16:01:14 -0700 | [diff] [blame] | 351 | int rate; |
| 352 | int lanes; |
| 353 | int preemphasis; |
| 354 | int vswing; |
Chris Wilson | 5ceb0f9 | 2010-09-24 10:24:28 +0100 | [diff] [blame] | 355 | |
Jesse Barnes | 9f0e7ff | 2010-10-07 16:01:14 -0700 | [diff] [blame] | 356 | bool initialized; |
| 357 | bool support; |
| 358 | int bpp; |
| 359 | struct edp_power_seq pps; |
Chris Wilson | 5ceb0f9 | 2010-09-24 10:24:28 +0100 | [diff] [blame] | 360 | } edp; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 361 | bool no_aux_handshake; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 362 | |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 363 | struct notifier_block lid_notifier; |
| 364 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 365 | int crt_ddc_pin; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 366 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
| 367 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| 368 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
| 369 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 370 | unsigned int fsb_freq, mem_freq, is_ddr3; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 371 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 372 | spinlock_t error_lock; |
| 373 | struct drm_i915_error_state *first_error; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 374 | struct work_struct error_work; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 375 | struct completion error_completion; |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 376 | struct workqueue_struct *wq; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 377 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 378 | /* Display functions */ |
| 379 | struct drm_i915_display_funcs display; |
| 380 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 381 | /* PCH chipset type */ |
| 382 | enum intel_pch pch_type; |
| 383 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 384 | unsigned long quirks; |
| 385 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 386 | /* Register state */ |
Linus Torvalds | c9354c8 | 2009-11-02 09:29:55 -0800 | [diff] [blame] | 387 | bool modeset_on_lid; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 388 | u8 saveLBB; |
| 389 | u32 saveDSPACNTR; |
| 390 | u32 saveDSPBCNTR; |
Keith Packard | e948e99 | 2008-05-07 12:27:53 +1000 | [diff] [blame] | 391 | u32 saveDSPARB; |
Peng Li | 461cba2 | 2008-11-18 12:39:02 +0800 | [diff] [blame] | 392 | u32 saveHWS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 393 | u32 savePIPEACONF; |
| 394 | u32 savePIPEBCONF; |
| 395 | u32 savePIPEASRC; |
| 396 | u32 savePIPEBSRC; |
| 397 | u32 saveFPA0; |
| 398 | u32 saveFPA1; |
| 399 | u32 saveDPLL_A; |
| 400 | u32 saveDPLL_A_MD; |
| 401 | u32 saveHTOTAL_A; |
| 402 | u32 saveHBLANK_A; |
| 403 | u32 saveHSYNC_A; |
| 404 | u32 saveVTOTAL_A; |
| 405 | u32 saveVBLANK_A; |
| 406 | u32 saveVSYNC_A; |
| 407 | u32 saveBCLRPAT_A; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 408 | u32 saveTRANSACONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 409 | u32 saveTRANS_HTOTAL_A; |
| 410 | u32 saveTRANS_HBLANK_A; |
| 411 | u32 saveTRANS_HSYNC_A; |
| 412 | u32 saveTRANS_VTOTAL_A; |
| 413 | u32 saveTRANS_VBLANK_A; |
| 414 | u32 saveTRANS_VSYNC_A; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 415 | u32 savePIPEASTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 416 | u32 saveDSPASTRIDE; |
| 417 | u32 saveDSPASIZE; |
| 418 | u32 saveDSPAPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 419 | u32 saveDSPAADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 420 | u32 saveDSPASURF; |
| 421 | u32 saveDSPATILEOFF; |
| 422 | u32 savePFIT_PGM_RATIOS; |
Jesse Barnes | 0eb96d6 | 2009-10-14 12:33:41 -0700 | [diff] [blame] | 423 | u32 saveBLC_HIST_CTL; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 424 | u32 saveBLC_PWM_CTL; |
| 425 | u32 saveBLC_PWM_CTL2; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 426 | u32 saveBLC_CPU_PWM_CTL; |
| 427 | u32 saveBLC_CPU_PWM_CTL2; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 428 | u32 saveFPB0; |
| 429 | u32 saveFPB1; |
| 430 | u32 saveDPLL_B; |
| 431 | u32 saveDPLL_B_MD; |
| 432 | u32 saveHTOTAL_B; |
| 433 | u32 saveHBLANK_B; |
| 434 | u32 saveHSYNC_B; |
| 435 | u32 saveVTOTAL_B; |
| 436 | u32 saveVBLANK_B; |
| 437 | u32 saveVSYNC_B; |
| 438 | u32 saveBCLRPAT_B; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 439 | u32 saveTRANSBCONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 440 | u32 saveTRANS_HTOTAL_B; |
| 441 | u32 saveTRANS_HBLANK_B; |
| 442 | u32 saveTRANS_HSYNC_B; |
| 443 | u32 saveTRANS_VTOTAL_B; |
| 444 | u32 saveTRANS_VBLANK_B; |
| 445 | u32 saveTRANS_VSYNC_B; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 446 | u32 savePIPEBSTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 447 | u32 saveDSPBSTRIDE; |
| 448 | u32 saveDSPBSIZE; |
| 449 | u32 saveDSPBPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 450 | u32 saveDSPBADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 451 | u32 saveDSPBSURF; |
| 452 | u32 saveDSPBTILEOFF; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 453 | u32 saveVGA0; |
| 454 | u32 saveVGA1; |
| 455 | u32 saveVGA_PD; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 456 | u32 saveVGACNTRL; |
| 457 | u32 saveADPA; |
| 458 | u32 saveLVDS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 459 | u32 savePP_ON_DELAYS; |
| 460 | u32 savePP_OFF_DELAYS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 461 | u32 saveDVOA; |
| 462 | u32 saveDVOB; |
| 463 | u32 saveDVOC; |
| 464 | u32 savePP_ON; |
| 465 | u32 savePP_OFF; |
| 466 | u32 savePP_CONTROL; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 467 | u32 savePP_DIVISOR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 468 | u32 savePFIT_CONTROL; |
| 469 | u32 save_palette_a[256]; |
| 470 | u32 save_palette_b[256]; |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 471 | u32 saveDPFC_CB_BASE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 472 | u32 saveFBC_CFB_BASE; |
| 473 | u32 saveFBC_LL_BASE; |
| 474 | u32 saveFBC_CONTROL; |
| 475 | u32 saveFBC_CONTROL2; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 476 | u32 saveIER; |
| 477 | u32 saveIIR; |
| 478 | u32 saveIMR; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 479 | u32 saveDEIER; |
| 480 | u32 saveDEIMR; |
| 481 | u32 saveGTIER; |
| 482 | u32 saveGTIMR; |
| 483 | u32 saveFDI_RXA_IMR; |
| 484 | u32 saveFDI_RXB_IMR; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 485 | u32 saveCACHE_MODE_0; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 486 | u32 saveMI_ARB_STATE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 487 | u32 saveSWF0[16]; |
| 488 | u32 saveSWF1[16]; |
| 489 | u32 saveSWF2[3]; |
| 490 | u8 saveMSR; |
| 491 | u8 saveSR[8]; |
Jesse Barnes | 123f794 | 2008-02-07 11:15:20 -0800 | [diff] [blame] | 492 | u8 saveGR[25]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 493 | u8 saveAR_INDEX; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 494 | u8 saveAR[21]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 495 | u8 saveDACMASK; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 496 | u8 saveCR[37]; |
Keith Packard | 79f11c1 | 2009-04-30 14:43:44 -0700 | [diff] [blame] | 497 | uint64_t saveFENCE[16]; |
Eric Anholt | 1fd1c62 | 2009-06-03 07:26:58 +0000 | [diff] [blame] | 498 | u32 saveCURACNTR; |
| 499 | u32 saveCURAPOS; |
| 500 | u32 saveCURABASE; |
| 501 | u32 saveCURBCNTR; |
| 502 | u32 saveCURBPOS; |
| 503 | u32 saveCURBBASE; |
| 504 | u32 saveCURSIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 505 | u32 saveDP_B; |
| 506 | u32 saveDP_C; |
| 507 | u32 saveDP_D; |
| 508 | u32 savePIPEA_GMCH_DATA_M; |
| 509 | u32 savePIPEB_GMCH_DATA_M; |
| 510 | u32 savePIPEA_GMCH_DATA_N; |
| 511 | u32 savePIPEB_GMCH_DATA_N; |
| 512 | u32 savePIPEA_DP_LINK_M; |
| 513 | u32 savePIPEB_DP_LINK_M; |
| 514 | u32 savePIPEA_DP_LINK_N; |
| 515 | u32 savePIPEB_DP_LINK_N; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 516 | u32 saveFDI_RXA_CTL; |
| 517 | u32 saveFDI_TXA_CTL; |
| 518 | u32 saveFDI_RXB_CTL; |
| 519 | u32 saveFDI_TXB_CTL; |
| 520 | u32 savePFA_CTL_1; |
| 521 | u32 savePFB_CTL_1; |
| 522 | u32 savePFA_WIN_SZ; |
| 523 | u32 savePFB_WIN_SZ; |
| 524 | u32 savePFA_WIN_POS; |
| 525 | u32 savePFB_WIN_POS; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 526 | u32 savePCH_DREF_CONTROL; |
| 527 | u32 saveDISP_ARB_CTL; |
| 528 | u32 savePIPEA_DATA_M1; |
| 529 | u32 savePIPEA_DATA_N1; |
| 530 | u32 savePIPEA_LINK_M1; |
| 531 | u32 savePIPEA_LINK_N1; |
| 532 | u32 savePIPEB_DATA_M1; |
| 533 | u32 savePIPEB_DATA_N1; |
| 534 | u32 savePIPEB_LINK_M1; |
| 535 | u32 savePIPEB_LINK_N1; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 536 | u32 saveMCHBAR_RENDER_STANDBY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 537 | |
| 538 | struct { |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 539 | /** Bridge to intel-gtt-ko */ |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 540 | const struct intel_gtt *gtt; |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 541 | /** Memory allocator for GTT stolen memory */ |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 542 | struct drm_mm stolen; |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 543 | /** Memory allocator for GTT */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 544 | struct drm_mm gtt_space; |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 545 | /** List of all objects in gtt_space. Used to restore gtt |
| 546 | * mappings on resume */ |
| 547 | struct list_head gtt_list; |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 548 | |
| 549 | /** Usable portion of the GTT for GEM */ |
| 550 | unsigned long gtt_start; |
Daniel Vetter | a6e0aa4 | 2010-09-16 15:45:15 +0200 | [diff] [blame] | 551 | unsigned long gtt_mappable_end; |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 552 | unsigned long gtt_end; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 553 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 554 | struct io_mapping *gtt_mapping; |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 555 | int gtt_mtrr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 556 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 557 | struct shrinker inactive_shrinker; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 558 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 559 | /** |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 560 | * List of objects currently involved in rendering. |
| 561 | * |
| 562 | * Includes buffers having the contents of their GPU caches |
| 563 | * flushed, not necessarily primitives. last_rendering_seqno |
| 564 | * represents when the rendering involved will be completed. |
| 565 | * |
| 566 | * A reference is held on the buffer while on this list. |
| 567 | */ |
| 568 | struct list_head active_list; |
| 569 | |
| 570 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 571 | * List of objects which are not in the ringbuffer but which |
| 572 | * still have a write_domain which needs to be flushed before |
| 573 | * unbinding. |
| 574 | * |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 575 | * last_rendering_seqno is 0 while an object is in this list. |
| 576 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 577 | * A reference is held on the buffer while on this list. |
| 578 | */ |
| 579 | struct list_head flushing_list; |
| 580 | |
| 581 | /** |
| 582 | * LRU list of objects which are not in the ringbuffer and |
| 583 | * are ready to unbind, but are still in the GTT. |
| 584 | * |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 585 | * last_rendering_seqno is 0 while an object is in this list. |
| 586 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 587 | * A reference is not held on the buffer while on this list, |
| 588 | * as merely being GTT-bound shouldn't prevent its being |
| 589 | * freed, and we'll pull it off the list in the free path. |
| 590 | */ |
| 591 | struct list_head inactive_list; |
| 592 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 593 | /** |
| 594 | * LRU list of objects which are not in the ringbuffer but |
| 595 | * are still pinned in the GTT. |
| 596 | */ |
| 597 | struct list_head pinned_list; |
| 598 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 599 | /** LRU list of objects with fence regs on them. */ |
| 600 | struct list_head fence_list; |
| 601 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 602 | /** |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 603 | * List of objects currently pending being freed. |
| 604 | * |
| 605 | * These objects are no longer in use, but due to a signal |
| 606 | * we were prevented from freeing them at the appointed time. |
| 607 | */ |
| 608 | struct list_head deferred_free_list; |
| 609 | |
| 610 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 611 | * We leave the user IRQ off as much as possible, |
| 612 | * but this means that requests will finish and never |
| 613 | * be retired once the system goes idle. Set a timer to |
| 614 | * fire periodically while the ring is running. When it |
| 615 | * fires, go retire requests. |
| 616 | */ |
| 617 | struct delayed_work retire_work; |
| 618 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 619 | /** |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame^] | 620 | * Are we in a non-interruptible section of code like |
| 621 | * modesetting? |
| 622 | */ |
| 623 | bool interruptible; |
| 624 | |
| 625 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 626 | * Flag if the X Server, and thus DRM, is not currently in |
| 627 | * control of the device. |
| 628 | * |
| 629 | * This is set between LeaveVT and EnterVT. It needs to be |
| 630 | * replaced with a semaphore. It also needs to be |
| 631 | * transitioned away from for kernel modesetting. |
| 632 | */ |
| 633 | int suspended; |
| 634 | |
| 635 | /** |
| 636 | * Flag if the hardware appears to be wedged. |
| 637 | * |
| 638 | * This is set when attempts to idle the device timeout. |
| 639 | * It prevents command submission from occuring and makes |
| 640 | * every pending request fail |
| 641 | */ |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 642 | atomic_t wedged; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 643 | |
| 644 | /** Bit 6 swizzling required for X tiling */ |
| 645 | uint32_t bit_6_swizzle_x; |
| 646 | /** Bit 6 swizzling required for Y tiling */ |
| 647 | uint32_t bit_6_swizzle_y; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 648 | |
| 649 | /* storage for physical objects */ |
| 650 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 651 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 652 | /* accounting, useful for userland debugging */ |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 653 | size_t gtt_total; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 654 | size_t mappable_gtt_total; |
| 655 | size_t object_memory; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 656 | u32 object_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 657 | } mm; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 658 | struct sdvo_device_mapping sdvo_mappings[2]; |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 659 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
| 660 | unsigned int lvds_border_bits; |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 661 | /* Panel fitter placement and size for Ironlake+ */ |
| 662 | u32 pch_pf_pos, pch_pf_size; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 663 | int panel_t3, panel_t12; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 664 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 665 | struct drm_crtc *plane_to_crtc_mapping[2]; |
| 666 | struct drm_crtc *pipe_to_crtc_mapping[2]; |
| 667 | wait_queue_head_t pending_flip_queue; |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 668 | bool flip_pending_is_done; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 669 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 670 | /* Reclocking support */ |
| 671 | bool render_reclock_avail; |
| 672 | bool lvds_downclock_avail; |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 673 | /* indicates the reduced downclock for LVDS*/ |
| 674 | int lvds_downclock; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 675 | struct work_struct idle_work; |
| 676 | struct timer_list idle_timer; |
| 677 | bool busy; |
| 678 | u16 orig_clock; |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 679 | int child_dev_num; |
| 680 | struct child_device_config *child_dev; |
Zhao Yakui | a256537 | 2009-12-11 09:26:11 +0800 | [diff] [blame] | 681 | struct drm_connector *int_lvds_connector; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 682 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 683 | bool mchbar_need_disable; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 684 | |
| 685 | u8 cur_delay; |
| 686 | u8 min_delay; |
| 687 | u8 max_delay; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 688 | u8 fmax; |
| 689 | u8 fstart; |
| 690 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 691 | u64 last_count1; |
| 692 | unsigned long last_time1; |
| 693 | u64 last_count2; |
| 694 | struct timespec last_time2; |
| 695 | unsigned long gfx_power; |
| 696 | int c_m; |
| 697 | int r_t; |
| 698 | u8 corr; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 699 | spinlock_t *mchdev_lock; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 700 | |
| 701 | enum no_fbc_reason no_fbc_reason; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 702 | |
Jesse Barnes | 20bf377 | 2010-04-21 11:39:22 -0700 | [diff] [blame] | 703 | struct drm_mm_node *compressed_fb; |
| 704 | struct drm_mm_node *compressed_llb; |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 705 | |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 706 | unsigned long last_gpu_reset; |
| 707 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 708 | /* list of fbdev register on this device */ |
| 709 | struct intel_fbdev *fbdev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 710 | } drm_i915_private_t; |
| 711 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 712 | struct drm_i915_gem_object { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 713 | struct drm_gem_object base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 714 | |
| 715 | /** Current space allocated to this object in the GTT, if any. */ |
| 716 | struct drm_mm_node *gtt_space; |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 717 | struct list_head gtt_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 718 | |
| 719 | /** This object's place on the active/flushing/inactive lists */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 720 | struct list_head ring_list; |
| 721 | struct list_head mm_list; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 722 | /** This object's place on GPU write list */ |
| 723 | struct list_head gpu_write_list; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 724 | /** This object's place in the batchbuffer or on the eviction list */ |
| 725 | struct list_head exec_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 726 | |
| 727 | /** |
| 728 | * This is set if the object is on the active or flushing lists |
| 729 | * (has pending rendering), and is not set if it's on inactive (ready |
| 730 | * to be unbound). |
| 731 | */ |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 732 | unsigned int active : 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 733 | |
| 734 | /** |
| 735 | * This is set if the object has been written to since last bound |
| 736 | * to the GTT |
| 737 | */ |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 738 | unsigned int dirty : 1; |
| 739 | |
| 740 | /** |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 741 | * This is set if the object has been written to since the last |
| 742 | * GPU flush. |
| 743 | */ |
| 744 | unsigned int pending_gpu_write : 1; |
| 745 | |
| 746 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 747 | * Fence register bits (if any) for this object. Will be set |
| 748 | * as needed when mapped into the GTT. |
| 749 | * Protected by dev->struct_mutex. |
| 750 | * |
| 751 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) |
| 752 | */ |
Chris Wilson | 11824e8 | 2010-06-06 15:40:18 +0100 | [diff] [blame] | 753 | signed int fence_reg : 5; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 754 | |
| 755 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 756 | * Advice: are the backing pages purgeable? |
| 757 | */ |
| 758 | unsigned int madv : 2; |
| 759 | |
| 760 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 761 | * Current tiling mode for the object. |
| 762 | */ |
| 763 | unsigned int tiling_mode : 2; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 764 | unsigned int tiling_changed : 1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 765 | |
| 766 | /** How many users have pinned this object in GTT space. The following |
| 767 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
| 768 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
| 769 | * times for the same batchbuffer), and the framebuffer code. When |
| 770 | * switching/pageflipping, the framebuffer code has at most two buffers |
| 771 | * pinned per crtc. |
| 772 | * |
| 773 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
| 774 | * bits with absolutely no headroom. So use 4 bits. */ |
Chris Wilson | 11824e8 | 2010-06-06 15:40:18 +0100 | [diff] [blame] | 775 | unsigned int pin_count : 4; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 776 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 777 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 778 | /** |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 779 | * Is the object at the current location in the gtt mappable and |
| 780 | * fenceable? Used to avoid costly recalculations. |
| 781 | */ |
| 782 | unsigned int map_and_fenceable : 1; |
| 783 | |
| 784 | /** |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 785 | * Whether the current gtt mapping needs to be mappable (and isn't just |
| 786 | * mappable by accident). Track pin and fault separate for a more |
| 787 | * accurate mappable working set. |
| 788 | */ |
| 789 | unsigned int fault_mappable : 1; |
| 790 | unsigned int pin_mappable : 1; |
| 791 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 792 | /* |
| 793 | * Is the GPU currently using a fence to access this buffer, |
| 794 | */ |
| 795 | unsigned int pending_fenced_gpu_access:1; |
| 796 | unsigned int fenced_gpu_access:1; |
| 797 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 798 | struct page **pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 799 | |
| 800 | /** |
Daniel Vetter | 185cbcb | 2010-11-06 12:12:35 +0100 | [diff] [blame] | 801 | * DMAR support |
| 802 | */ |
| 803 | struct scatterlist *sg_list; |
| 804 | int num_sg; |
| 805 | |
| 806 | /** |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 807 | * Used for performing relocations during execbuffer insertion. |
| 808 | */ |
| 809 | struct hlist_node exec_node; |
| 810 | unsigned long exec_handle; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 811 | struct drm_i915_gem_exec_object2 *exec_entry; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 812 | |
| 813 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 814 | * Current offset of the object in GTT space. |
| 815 | * |
| 816 | * This is the same as gtt_space->start |
| 817 | */ |
| 818 | uint32_t gtt_offset; |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 819 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 820 | /** Breadcrumb of last rendering to the buffer. */ |
| 821 | uint32_t last_rendering_seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 822 | struct intel_ring_buffer *ring; |
| 823 | |
| 824 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
| 825 | uint32_t last_fenced_seqno; |
| 826 | struct intel_ring_buffer *last_fenced_ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 827 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 828 | /** Current tiling stride for the object, if it's tiled. */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 829 | uint32_t stride; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 830 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 831 | /** Record of address bit 17 of each page at last unbind. */ |
Chris Wilson | d312ec2 | 2010-06-06 15:40:22 +0100 | [diff] [blame] | 832 | unsigned long *bit_17; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 833 | |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 834 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
| 835 | uint32_t agp_type; |
| 836 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 837 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 838 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
| 839 | * flags which individual pages are valid. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 840 | */ |
| 841 | uint8_t *page_cpu_valid; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 842 | |
| 843 | /** User space pin count and filp owning the pin */ |
| 844 | uint32_t user_pin_count; |
| 845 | struct drm_file *pin_filp; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 846 | |
| 847 | /** for phy allocated objects */ |
| 848 | struct drm_i915_gem_phys_object *phys_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 849 | |
| 850 | /** |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 851 | * Number of crtcs where this object is currently the fb, but |
| 852 | * will be page flipped away on the next vblank. When it |
| 853 | * reaches 0, dev_priv->pending_flip_queue will be woken up. |
| 854 | */ |
| 855 | atomic_t pending_flip; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 856 | }; |
| 857 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 858 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 859 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 860 | /** |
| 861 | * Request queue structure. |
| 862 | * |
| 863 | * The request queue allows us to note sequence numbers that have been emitted |
| 864 | * and may be associated with active buffers to be retired. |
| 865 | * |
| 866 | * By keeping this list, we can avoid having to do questionable |
| 867 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
| 868 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
| 869 | */ |
| 870 | struct drm_i915_gem_request { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 871 | /** On Which ring this request was generated */ |
| 872 | struct intel_ring_buffer *ring; |
| 873 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 874 | /** GEM sequence number associated with this request. */ |
| 875 | uint32_t seqno; |
| 876 | |
| 877 | /** Time at which this request was emitted, in jiffies. */ |
| 878 | unsigned long emitted_jiffies; |
| 879 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 880 | /** global list entry for this request */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 881 | struct list_head list; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 882 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 883 | struct drm_i915_file_private *file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 884 | /** file_priv list entry for this request */ |
| 885 | struct list_head client_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 886 | }; |
| 887 | |
| 888 | struct drm_i915_file_private { |
| 889 | struct { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 890 | struct spinlock lock; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 891 | struct list_head request_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 892 | } mm; |
| 893 | }; |
| 894 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 895 | enum intel_chip_family { |
| 896 | CHIP_I8XX = 0x01, |
| 897 | CHIP_I9XX = 0x02, |
| 898 | CHIP_I915 = 0x04, |
| 899 | CHIP_I965 = 0x08, |
| 900 | }; |
| 901 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 902 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
| 903 | |
| 904 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
| 905 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
| 906 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
| 907 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
| 908 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
| 909 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
| 910 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
| 911 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
| 912 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
| 913 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
| 914 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
| 915 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
| 916 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
| 917 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
| 918 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
| 919 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
| 920 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
| 921 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
| 922 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
| 923 | |
| 924 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
| 925 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
| 926 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
| 927 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
| 928 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
| 929 | |
| 930 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
| 931 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
| 932 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
| 933 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 934 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 935 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
| 936 | |
| 937 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 938 | * rows, which changed the alignment requirements and fence programming. |
| 939 | */ |
| 940 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
| 941 | IS_I915GM(dev))) |
| 942 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
| 943 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 944 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 945 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
| 946 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
| 947 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
| 948 | /* dsparb controlled by hw only */ |
| 949 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
| 950 | |
| 951 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
| 952 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
| 953 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 954 | |
| 955 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev)) |
| 956 | #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev)) |
| 957 | |
| 958 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
| 959 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
| 960 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
| 961 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 962 | #include "i915_trace.h" |
| 963 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 964 | extern struct drm_ioctl_desc i915_ioctls[]; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 965 | extern int i915_max_ioctl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 966 | extern unsigned int i915_fbpercrtc; |
Chris Wilson | fca8740 | 2011-02-17 13:44:48 +0000 | [diff] [blame] | 967 | extern int i915_panel_ignore_lid; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 968 | extern unsigned int i915_powersave; |
Jesse Barnes | 3381434 | 2010-01-14 20:48:02 +0000 | [diff] [blame] | 969 | extern unsigned int i915_lvds_downclock; |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 970 | extern unsigned int i915_panel_use_ssc; |
Chris Wilson | 5a1e5b6 | 2011-01-29 16:50:25 +0000 | [diff] [blame] | 971 | extern int i915_vbt_sdvo_panel_type; |
Chris Wilson | ac66808 | 2011-02-09 16:15:32 +0000 | [diff] [blame] | 972 | extern unsigned int i915_enable_rc6; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 973 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 974 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
| 975 | extern int i915_resume(struct drm_device *dev); |
Ben Gamari | 1341d65 | 2009-09-14 17:48:42 -0400 | [diff] [blame] | 976 | extern void i915_save_display(struct drm_device *dev); |
| 977 | extern void i915_restore_display(struct drm_device *dev); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 978 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
| 979 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
| 980 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 981 | /* i915_dma.c */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 982 | extern void i915_kernel_lost_context(struct drm_device * dev); |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 983 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 984 | extern int i915_driver_unload(struct drm_device *); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 985 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 986 | extern void i915_driver_lastclose(struct drm_device * dev); |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 987 | extern void i915_driver_preclose(struct drm_device *dev, |
| 988 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 989 | extern void i915_driver_postclose(struct drm_device *dev, |
| 990 | struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 991 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 992 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| 993 | unsigned long arg); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 994 | extern int i915_emit_box(struct drm_device *dev, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 995 | struct drm_clip_rect *box, |
| 996 | int DR1, int DR4); |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 997 | extern int i915_reset(struct drm_device *dev, u8 flags); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 998 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
| 999 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
| 1000 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 1001 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
| 1002 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1003 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1004 | /* i915_irq.c */ |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1005 | void i915_hangcheck_elapsed(unsigned long data); |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1006 | void i915_handle_error(struct drm_device *dev, bool wedged); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1007 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
| 1008 | struct drm_file *file_priv); |
| 1009 | extern int i915_irq_wait(struct drm_device *dev, void *data, |
| 1010 | struct drm_file *file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1011 | |
| 1012 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1013 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1014 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1015 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1016 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 1017 | struct drm_file *file_priv); |
| 1018 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 1019 | struct drm_file *file_priv); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1020 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
| 1021 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); |
| 1022 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 1023 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1024 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
| 1025 | struct drm_file *file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1026 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1027 | void |
| 1028 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
| 1029 | |
| 1030 | void |
| 1031 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
| 1032 | |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 1033 | void intel_enable_asle (struct drm_device *dev); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1034 | int i915_get_vblank_timestamp(struct drm_device *dev, int crtc, |
| 1035 | int *max_error, |
| 1036 | struct timeval *vblank_time, |
| 1037 | unsigned flags); |
| 1038 | |
| 1039 | int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
| 1040 | int *vpos, int *hpos); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 1041 | |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1042 | #ifdef CONFIG_DEBUG_FS |
| 1043 | extern void i915_destroy_error_state(struct drm_device *dev); |
| 1044 | #else |
| 1045 | #define i915_destroy_error_state(x) |
| 1046 | #endif |
| 1047 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1048 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1049 | /* i915_mem.c */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1050 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
| 1051 | struct drm_file *file_priv); |
| 1052 | extern int i915_mem_free(struct drm_device *dev, void *data, |
| 1053 | struct drm_file *file_priv); |
| 1054 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, |
| 1055 | struct drm_file *file_priv); |
| 1056 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, |
| 1057 | struct drm_file *file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1058 | extern void i915_mem_takedown(struct mem_block **heap); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1059 | extern void i915_mem_release(struct drm_device * dev, |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1060 | struct drm_file *file_priv, struct mem_block *heap); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1061 | /* i915_gem.c */ |
| 1062 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 1063 | struct drm_file *file_priv); |
| 1064 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1065 | struct drm_file *file_priv); |
| 1066 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1067 | struct drm_file *file_priv); |
| 1068 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1069 | struct drm_file *file_priv); |
| 1070 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1071 | struct drm_file *file_priv); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1072 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1073 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1074 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1075 | struct drm_file *file_priv); |
| 1076 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1077 | struct drm_file *file_priv); |
| 1078 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 1079 | struct drm_file *file_priv); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 1080 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 1081 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1082 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1083 | struct drm_file *file_priv); |
| 1084 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1085 | struct drm_file *file_priv); |
| 1086 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1087 | struct drm_file *file_priv); |
| 1088 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 1089 | struct drm_file *file_priv); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1090 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 1091 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1092 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 1093 | struct drm_file *file_priv); |
| 1094 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 1095 | struct drm_file *file_priv); |
| 1096 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 1097 | struct drm_file *file_priv); |
| 1098 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 1099 | struct drm_file *file_priv); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 1100 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 1101 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1102 | void i915_gem_load(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1103 | int i915_gem_init_object(struct drm_gem_object *obj); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1104 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 1105 | uint32_t invalidate_domains, |
| 1106 | uint32_t flush_domains); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1107 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 1108 | size_t size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1109 | void i915_gem_free_object(struct drm_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1110 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 1111 | uint32_t alignment, |
| 1112 | bool map_and_fenceable); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1113 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1114 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1115 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1116 | void i915_gem_lastclose(struct drm_device *dev); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1117 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1118 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame^] | 1119 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1120 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1121 | struct intel_ring_buffer *ring, |
| 1122 | u32 seqno); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1123 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1124 | /** |
| 1125 | * Returns true if seq1 is later than seq2. |
| 1126 | */ |
| 1127 | static inline bool |
| 1128 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 1129 | { |
| 1130 | return (int32_t)(seq1 - seq2) >= 0; |
| 1131 | } |
| 1132 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1133 | static inline u32 |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1134 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1135 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1136 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1137 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
| 1138 | } |
| 1139 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1140 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame^] | 1141 | struct intel_ring_buffer *pipelined); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1142 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1143 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1144 | void i915_gem_retire_requests(struct drm_device *dev); |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1145 | void i915_gem_reset(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1146 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1147 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
| 1148 | uint32_t read_domains, |
| 1149 | uint32_t write_domain); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame^] | 1150 | int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1151 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1152 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1153 | void i915_gem_do_init(struct drm_device *dev, |
| 1154 | unsigned long start, |
| 1155 | unsigned long mappable_end, |
| 1156 | unsigned long end); |
| 1157 | int __must_check i915_gpu_idle(struct drm_device *dev); |
| 1158 | int __must_check i915_gem_idle(struct drm_device *dev); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1159 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
| 1160 | struct drm_file *file, |
| 1161 | struct drm_i915_gem_request *request); |
| 1162 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame^] | 1163 | uint32_t seqno); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1164 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1165 | int __must_check |
| 1166 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
| 1167 | bool write); |
| 1168 | int __must_check |
| 1169 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
| 1170 | struct intel_ring_buffer *pipelined); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1171 | int i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1172 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 1173 | int id, |
| 1174 | int align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1175 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1176 | struct drm_i915_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1177 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1178 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1179 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1180 | /* i915_gem_gtt.c */ |
| 1181 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1182 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1183 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1184 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 1185 | /* i915_gem_evict.c */ |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 1186 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
| 1187 | unsigned alignment, bool mappable); |
| 1188 | int __must_check i915_gem_evict_everything(struct drm_device *dev, |
| 1189 | bool purgeable_only); |
| 1190 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, |
| 1191 | bool purgeable_only); |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 1192 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1193 | /* i915_gem_tiling.c */ |
| 1194 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1195 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 1196 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1197 | |
| 1198 | /* i915_gem_debug.c */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1199 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1200 | const char *where, uint32_t mark); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1201 | #if WATCH_LISTS |
| 1202 | int i915_verify_lists(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1203 | #else |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1204 | #define i915_verify_lists(dev) 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1205 | #endif |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1206 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
| 1207 | int handle); |
| 1208 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1209 | const char *where, uint32_t mark); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1210 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1211 | /* i915_debugfs.c */ |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 1212 | int i915_debugfs_init(struct drm_minor *minor); |
| 1213 | void i915_debugfs_cleanup(struct drm_minor *minor); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1214 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 1215 | /* i915_suspend.c */ |
| 1216 | extern int i915_save_state(struct drm_device *dev); |
| 1217 | extern int i915_restore_state(struct drm_device *dev); |
| 1218 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1219 | /* i915_suspend.c */ |
| 1220 | extern int i915_save_state(struct drm_device *dev); |
| 1221 | extern int i915_restore_state(struct drm_device *dev); |
| 1222 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1223 | /* intel_i2c.c */ |
| 1224 | extern int intel_setup_gmbus(struct drm_device *dev); |
| 1225 | extern void intel_teardown_gmbus(struct drm_device *dev); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1226 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
| 1227 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
Chris Wilson | b8232e9 | 2010-09-28 16:41:32 +0100 | [diff] [blame] | 1228 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
| 1229 | { |
| 1230 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
| 1231 | } |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1232 | extern void intel_i2c_reset(struct drm_device *dev); |
| 1233 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1234 | /* intel_opregion.c */ |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1235 | extern int intel_opregion_setup(struct drm_device *dev); |
| 1236 | #ifdef CONFIG_ACPI |
| 1237 | extern void intel_opregion_init(struct drm_device *dev); |
| 1238 | extern void intel_opregion_fini(struct drm_device *dev); |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1239 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
| 1240 | extern void intel_opregion_gse_intr(struct drm_device *dev); |
| 1241 | extern void intel_opregion_enable_asle(struct drm_device *dev); |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 1242 | #else |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1243 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
| 1244 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 1245 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
| 1246 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } |
| 1247 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 1248 | #endif |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1249 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 1250 | /* intel_acpi.c */ |
| 1251 | #ifdef CONFIG_ACPI |
| 1252 | extern void intel_register_dsm_handler(void); |
| 1253 | extern void intel_unregister_dsm_handler(void); |
| 1254 | #else |
| 1255 | static inline void intel_register_dsm_handler(void) { return; } |
| 1256 | static inline void intel_unregister_dsm_handler(void) { return; } |
| 1257 | #endif /* CONFIG_ACPI */ |
| 1258 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1259 | /* modesetting */ |
| 1260 | extern void intel_modeset_init(struct drm_device *dev); |
| 1261 | extern void intel_modeset_cleanup(struct drm_device *dev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1262 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1263 | extern void i8xx_disable_fbc(struct drm_device *dev); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1264 | extern void g4x_disable_fbc(struct drm_device *dev); |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1265 | extern void ironlake_disable_fbc(struct drm_device *dev); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1266 | extern void intel_disable_fbc(struct drm_device *dev); |
| 1267 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); |
| 1268 | extern bool intel_fbc_enabled(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1269 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 1270 | extern void ironlake_enable_rc6(struct drm_device *dev); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1271 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 1272 | extern void intel_detect_pch (struct drm_device *dev); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1273 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 1274 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1275 | /* overlay */ |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1276 | #ifdef CONFIG_DEBUG_FS |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1277 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
| 1278 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 1279 | |
| 1280 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
| 1281 | extern void intel_display_print_error_state(struct seq_file *m, |
| 1282 | struct drm_device *dev, |
| 1283 | struct intel_display_error_state *error); |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1284 | #endif |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1285 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1286 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
| 1287 | |
| 1288 | #define BEGIN_LP_RING(n) \ |
| 1289 | intel_ring_begin(LP_RING(dev_priv), (n)) |
| 1290 | |
| 1291 | #define OUT_RING(x) \ |
| 1292 | intel_ring_emit(LP_RING(dev_priv), x) |
| 1293 | |
| 1294 | #define ADVANCE_LP_RING() \ |
| 1295 | intel_ring_advance(LP_RING(dev_priv)) |
| 1296 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1297 | /** |
| 1298 | * Lock test for when it's just for synchronization of ring access. |
| 1299 | * |
| 1300 | * In that case, we don't need to do it when GEM is initialized as nobody else |
| 1301 | * has access to the ring. |
| 1302 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1303 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1304 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1305 | LOCK_TEST_WITH_RETURN(dev, file); \ |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 1306 | } while (0) |
| 1307 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1308 | |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 1309 | #define __i915_read(x, y) \ |
| 1310 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
| 1311 | u##x val = read##y(dev_priv->regs + reg); \ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1312 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 1313 | return val; \ |
| 1314 | } |
| 1315 | __i915_read(8, b) |
| 1316 | __i915_read(16, w) |
| 1317 | __i915_read(32, l) |
| 1318 | __i915_read(64, q) |
| 1319 | #undef __i915_read |
| 1320 | |
| 1321 | #define __i915_write(x, y) \ |
| 1322 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1323 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 1324 | write##y(val, dev_priv->regs + reg); \ |
| 1325 | } |
| 1326 | __i915_write(8, b) |
| 1327 | __i915_write(16, w) |
| 1328 | __i915_write(32, l) |
| 1329 | __i915_write(64, q) |
| 1330 | #undef __i915_write |
| 1331 | |
| 1332 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
| 1333 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
| 1334 | |
| 1335 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
| 1336 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
| 1337 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
| 1338 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
| 1339 | |
| 1340 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) |
| 1341 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1342 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
| 1343 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 1344 | |
| 1345 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
| 1346 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1347 | |
| 1348 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
| 1349 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
| 1350 | |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 1351 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1352 | /* On SNB platform, before reading ring registers forcewake bit |
| 1353 | * must be set to prevent GT core from power down and stale values being |
| 1354 | * returned. |
| 1355 | */ |
Chris Wilson | eb43f4a | 2010-12-08 17:32:24 +0000 | [diff] [blame] | 1356 | void __gen6_force_wake_get(struct drm_i915_private *dev_priv); |
| 1357 | void __gen6_force_wake_put (struct drm_i915_private *dev_priv); |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1358 | static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg) |
| 1359 | { |
Chris Wilson | eb43f4a | 2010-12-08 17:32:24 +0000 | [diff] [blame] | 1360 | u32 val; |
| 1361 | |
| 1362 | if (dev_priv->info->gen >= 6) { |
| 1363 | __gen6_force_wake_get(dev_priv); |
| 1364 | val = I915_READ(reg); |
| 1365 | __gen6_force_wake_put(dev_priv); |
| 1366 | } else |
| 1367 | val = I915_READ(reg); |
| 1368 | |
| 1369 | return val; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1370 | } |
| 1371 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1372 | #endif |