David Howells | 607ca46 | 2012-10-13 10:46:48 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/char/serial_core.h |
| 3 | * |
| 4 | * Copyright (C) 2000 Deep Blue Solutions Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | #ifndef _UAPILINUX_SERIAL_CORE_H |
| 21 | #define _UAPILINUX_SERIAL_CORE_H |
| 22 | |
| 23 | #include <linux/serial.h> |
| 24 | |
| 25 | /* |
| 26 | * The type definitions. These are from Ted Ts'o's serial.h |
| 27 | */ |
| 28 | #define PORT_UNKNOWN 0 |
| 29 | #define PORT_8250 1 |
| 30 | #define PORT_16450 2 |
| 31 | #define PORT_16550 3 |
| 32 | #define PORT_16550A 4 |
| 33 | #define PORT_CIRRUS 5 |
| 34 | #define PORT_16650 6 |
| 35 | #define PORT_16650V2 7 |
| 36 | #define PORT_16750 8 |
| 37 | #define PORT_STARTECH 9 |
| 38 | #define PORT_16C950 10 |
| 39 | #define PORT_16654 11 |
| 40 | #define PORT_16850 12 |
| 41 | #define PORT_RSA 13 |
| 42 | #define PORT_NS16550A 14 |
| 43 | #define PORT_XSCALE 15 |
| 44 | #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */ |
| 45 | #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */ |
| 46 | #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */ |
| 47 | #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */ |
| 48 | #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */ |
| 49 | #define PORT_XR17D15X 21 /* Exar XR17D15x UART */ |
| 50 | #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */ |
| 51 | #define PORT_8250_CIR 23 /* CIR infrared port, has its own driver */ |
Matt Schulte | dc96efb | 2012-11-19 09:12:04 -0600 | [diff] [blame] | 52 | #define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */ |
Michael Chan | 85f0244 | 2013-01-29 17:54:44 -0800 | [diff] [blame] | 53 | #define PORT_BRCM_TRUMANAGE 25 |
Ley Foon Tan | e06c93c | 2013-03-07 10:28:37 +0800 | [diff] [blame] | 54 | #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */ |
| 55 | #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ |
| 56 | #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ |
John Crispin | 9b8777e | 2014-10-16 21:48:21 +0200 | [diff] [blame] | 57 | #define PORT_RT2880 29 /* Ralink RT2880 internal UART */ |
Vijay Rai | fddceb8 | 2015-01-05 21:14:42 +0530 | [diff] [blame] | 58 | #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ |
| 59 | #define PORT_MAX_8250 30 /* max port ID */ |
David Howells | 607ca46 | 2012-10-13 10:46:48 +0100 | [diff] [blame] | 60 | |
| 61 | /* |
| 62 | * ARM specific type numbers. These are not currently guaranteed |
| 63 | * to be implemented, and will change in the future. These are |
| 64 | * separate so any additions to the old serial.c that occur before |
| 65 | * we are merged can be easily merged here. |
| 66 | */ |
| 67 | #define PORT_PXA 31 |
| 68 | #define PORT_AMBA 32 |
| 69 | #define PORT_CLPS711X 33 |
| 70 | #define PORT_SA1100 34 |
| 71 | #define PORT_UART00 35 |
| 72 | #define PORT_21285 37 |
| 73 | |
| 74 | /* Sparc type numbers. */ |
| 75 | #define PORT_SUNZILOG 38 |
| 76 | #define PORT_SUNSAB 39 |
| 77 | |
| 78 | /* DEC */ |
| 79 | #define PORT_DZ 46 |
| 80 | #define PORT_ZS 47 |
| 81 | |
| 82 | /* Parisc type numbers. */ |
| 83 | #define PORT_MUX 48 |
| 84 | |
| 85 | /* Atmel AT91 / AT32 SoC */ |
| 86 | #define PORT_ATMEL 49 |
| 87 | |
| 88 | /* Macintosh Zilog type numbers */ |
| 89 | #define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */ |
| 90 | #define PORT_PMAC_ZILOG 51 |
| 91 | |
| 92 | /* SH-SCI */ |
| 93 | #define PORT_SCI 52 |
| 94 | #define PORT_SCIF 53 |
| 95 | #define PORT_IRDA 54 |
| 96 | |
| 97 | /* Samsung S3C2410 SoC and derivatives thereof */ |
| 98 | #define PORT_S3C2410 55 |
| 99 | |
| 100 | /* SGI IP22 aka Indy / Challenge S / Indigo 2 */ |
| 101 | #define PORT_IP22ZILOG 56 |
| 102 | |
| 103 | /* Sharp LH7a40x -- an ARM9 SoC series */ |
| 104 | #define PORT_LH7A40X 57 |
| 105 | |
| 106 | /* PPC CPM type number */ |
| 107 | #define PORT_CPM 58 |
| 108 | |
| 109 | /* MPC52xx (and MPC512x) type numbers */ |
| 110 | #define PORT_MPC52xx 59 |
| 111 | |
| 112 | /* IBM icom */ |
| 113 | #define PORT_ICOM 60 |
| 114 | |
| 115 | /* Samsung S3C2440 SoC */ |
| 116 | #define PORT_S3C2440 61 |
| 117 | |
| 118 | /* Motorola i.MX SoC */ |
| 119 | #define PORT_IMX 62 |
| 120 | |
| 121 | /* Marvell MPSC */ |
| 122 | #define PORT_MPSC 63 |
| 123 | |
| 124 | /* TXX9 type number */ |
| 125 | #define PORT_TXX9 64 |
| 126 | |
| 127 | /* NEC VR4100 series SIU/DSIU */ |
| 128 | #define PORT_VR41XX_SIU 65 |
| 129 | #define PORT_VR41XX_DSIU 66 |
| 130 | |
| 131 | /* Samsung S3C2400 SoC */ |
| 132 | #define PORT_S3C2400 67 |
| 133 | |
| 134 | /* M32R SIO */ |
| 135 | #define PORT_M32R_SIO 68 |
| 136 | |
| 137 | /*Digi jsm */ |
| 138 | #define PORT_JSM 69 |
| 139 | |
| 140 | #define PORT_PNX8XXX 70 |
| 141 | |
| 142 | /* Hilscher netx */ |
| 143 | #define PORT_NETX 71 |
| 144 | |
| 145 | /* SUN4V Hypervisor Console */ |
| 146 | #define PORT_SUNHV 72 |
| 147 | |
| 148 | #define PORT_S3C2412 73 |
| 149 | |
| 150 | /* Xilinx uartlite */ |
| 151 | #define PORT_UARTLITE 74 |
| 152 | |
| 153 | /* Blackfin bf5xx */ |
| 154 | #define PORT_BFIN 75 |
| 155 | |
| 156 | /* Micrel KS8695 */ |
| 157 | #define PORT_KS8695 76 |
| 158 | |
| 159 | /* Broadcom SB1250, etc. SOC */ |
| 160 | #define PORT_SB1250_DUART 77 |
| 161 | |
| 162 | /* Freescale ColdFire */ |
| 163 | #define PORT_MCF 78 |
| 164 | |
| 165 | /* Blackfin SPORT */ |
| 166 | #define PORT_BFIN_SPORT 79 |
| 167 | |
| 168 | /* MN10300 on-chip UART numbers */ |
| 169 | #define PORT_MN10300 80 |
| 170 | #define PORT_MN10300_CTS 81 |
| 171 | |
| 172 | #define PORT_SC26XX 82 |
| 173 | |
| 174 | /* SH-SCI */ |
| 175 | #define PORT_SCIFA 83 |
| 176 | |
| 177 | #define PORT_S3C6400 84 |
| 178 | |
Arnd Bergmann | d1b5c87 | 2015-11-16 16:48:12 +0100 | [diff] [blame] | 179 | /* NWPSERIAL, now removed */ |
David Howells | 607ca46 | 2012-10-13 10:46:48 +0100 | [diff] [blame] | 180 | #define PORT_NWPSERIAL 85 |
| 181 | |
| 182 | /* MAX3100 */ |
| 183 | #define PORT_MAX3100 86 |
| 184 | |
| 185 | /* Timberdale UART */ |
| 186 | #define PORT_TIMBUART 87 |
| 187 | |
| 188 | /* Qualcomm MSM SoCs */ |
| 189 | #define PORT_MSM 88 |
| 190 | |
| 191 | /* BCM63xx family SoCs */ |
| 192 | #define PORT_BCM63XX 89 |
| 193 | |
| 194 | /* Aeroflex Gaisler GRLIB APBUART */ |
| 195 | #define PORT_APBUART 90 |
| 196 | |
| 197 | /* Altera UARTs */ |
| 198 | #define PORT_ALTERA_JTAGUART 91 |
| 199 | #define PORT_ALTERA_UART 92 |
| 200 | |
| 201 | /* SH-SCI */ |
| 202 | #define PORT_SCIFB 93 |
| 203 | |
| 204 | /* MAX310X */ |
| 205 | #define PORT_MAX310X 94 |
| 206 | |
| 207 | /* High Speed UART for Medfield */ |
| 208 | #define PORT_MFD 95 |
| 209 | |
| 210 | /* TI OMAP-UART */ |
| 211 | #define PORT_OMAP 96 |
| 212 | |
| 213 | /* VIA VT8500 SoC */ |
| 214 | #define PORT_VT8500 97 |
| 215 | |
Soren Brinkmann | d9bb3fb | 2014-04-04 17:23:43 -0700 | [diff] [blame] | 216 | /* Cadence (Xilinx Zynq) UART */ |
David Howells | 607ca46 | 2012-10-13 10:46:48 +0100 | [diff] [blame] | 217 | #define PORT_XUARTPS 98 |
| 218 | |
| 219 | /* Atheros AR933X SoC */ |
| 220 | #define PORT_AR933X 99 |
| 221 | |
| 222 | /* Energy Micro efm32 SoC */ |
| 223 | #define PORT_EFMUART 100 |
| 224 | |
Vineet Gupta | 2ac4ad2 | 2012-10-27 12:47:12 +0530 | [diff] [blame] | 225 | /* ARC (Synopsys) on-chip UART */ |
| 226 | #define PORT_ARC 101 |
David Howells | 607ca46 | 2012-10-13 10:46:48 +0100 | [diff] [blame] | 227 | |
Kevin Cernekee | 7d9f49a | 2013-01-16 20:28:40 -0800 | [diff] [blame] | 228 | /* Rocketport EXPRESS/INFINITY */ |
| 229 | #define PORT_RP2 102 |
| 230 | |
Jingchang Lu | c9e2e94 | 2013-06-07 09:20:40 +0800 | [diff] [blame] | 231 | /* Freescale lpuart */ |
| 232 | #define PORT_LPUART 103 |
| 233 | |
Ulrich Hecht | f303b36 | 2013-05-31 17:57:01 +0200 | [diff] [blame] | 234 | /* SH-SCI */ |
Linus Torvalds | 42daabf | 2013-07-02 14:42:51 -0700 | [diff] [blame] | 235 | #define PORT_HSCIF 104 |
Ulrich Hecht | f303b36 | 2013-05-31 17:57:01 +0200 | [diff] [blame] | 236 | |
Srinivas Kandagatla | c4b0585 | 2013-07-15 12:39:23 +0100 | [diff] [blame] | 237 | /* ST ASC type numbers */ |
| 238 | #define PORT_ASC 105 |
| 239 | |
Chris Metcalf | b5c6c1a | 2013-08-12 14:11:44 -0400 | [diff] [blame] | 240 | /* Tilera TILE-Gx UART */ |
Linus Torvalds | 4de9ad9 | 2013-09-06 11:14:33 -0700 | [diff] [blame] | 241 | #define PORT_TILEGX 106 |
Chris Metcalf | b5c6c1a | 2013-08-12 14:11:44 -0400 | [diff] [blame] | 242 | |
Johannes Thumshirn | e264ebf | 2014-04-17 15:47:58 +0200 | [diff] [blame] | 243 | /* MEN 16z135 UART */ |
| 244 | #define PORT_MEN_Z135 107 |
| 245 | |
Jon Ringle | dfeae61 | 2014-04-24 20:56:06 -0400 | [diff] [blame] | 246 | /* SC16IS74xx */ |
| 247 | #define PORT_SC16IS7XX 108 |
| 248 | |
Carlo Caione | ff7693d | 2014-08-17 12:49:49 +0200 | [diff] [blame] | 249 | /* MESON */ |
| 250 | #define PORT_MESON 109 |
| 251 | |
Baruch Siach | 5930cb3 | 2014-12-18 21:45:24 +0200 | [diff] [blame] | 252 | /* Conexant Digicolor */ |
| 253 | #define PORT_DIGICOLOR 110 |
| 254 | |
Chunyan Zhang | b7396a3 | 2015-01-28 19:08:44 +0800 | [diff] [blame] | 255 | /* SPRD SERIAL */ |
| 256 | #define PORT_SPRD 111 |
| 257 | |
Niklas Cassel | 692132b | 2015-02-02 23:19:20 +0100 | [diff] [blame] | 258 | /* Cris v10 / v32 SoC */ |
| 259 | #define PORT_CRIS 112 |
| 260 | |
Maxime Coquelin | 48a6092 | 2015-06-10 21:19:36 +0200 | [diff] [blame] | 261 | /* STM32 USART */ |
| 262 | #define PORT_STM32 113 |
| 263 | |
Wilson Ding | 3053079 | 2016-02-16 19:14:53 +0100 | [diff] [blame] | 264 | /* MVEBU UART */ |
| 265 | #define PORT_MVEBU 114 |
| 266 | |
Andrei Pistirica | 157b939 | 2016-01-13 18:15:43 -0700 | [diff] [blame] | 267 | /* Microchip PIC32 UART */ |
Linus Torvalds | 07b7526 | 2016-05-19 10:02:26 -0700 | [diff] [blame] | 268 | #define PORT_PIC32 115 |
Andrei Pistirica | 157b939 | 2016-01-13 18:15:43 -0700 | [diff] [blame] | 269 | |
Vladimir Murzin | 041f031 | 2016-04-25 09:47:47 +0100 | [diff] [blame] | 270 | /* MPS2 UART */ |
Linus Torvalds | e10abc6 | 2016-05-20 20:57:27 -0700 | [diff] [blame] | 271 | #define PORT_MPS2UART 116 |
Vladimir Murzin | 041f031 | 2016-04-25 09:47:47 +0100 | [diff] [blame] | 272 | |
David Howells | 607ca46 | 2012-10-13 10:46:48 +0100 | [diff] [blame] | 273 | #endif /* _UAPILINUX_SERIAL_CORE_H */ |