Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * TAS5086 ASoC codec driver |
| 3 | * |
| 4 | * Copyright (c) 2013 Daniel Mack <zonque@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * TODO: |
| 17 | * - implement DAPM and input muxing |
| 18 | * - implement modulation limit |
| 19 | * - implement non-default PWM start |
| 20 | * |
| 21 | * Note that this chip has a very unusual register layout, specifically |
| 22 | * because the registers are of unequal size, and multi-byte registers |
| 23 | * require bulk writes to take effect. Regmap does not support that kind |
| 24 | * of devices. |
| 25 | * |
| 26 | * Currently, the driver does not touch any of the registers >= 0x20, so |
| 27 | * it doesn't matter because the entire map can be accessed as 8-bit |
| 28 | * array. In case more features will be added in the future |
| 29 | * that require access to higher registers, the entire regmap H/W I/O |
| 30 | * routines have to be open-coded. |
| 31 | */ |
| 32 | |
| 33 | #include <linux/module.h> |
| 34 | #include <linux/slab.h> |
| 35 | #include <linux/delay.h> |
| 36 | #include <linux/gpio.h> |
| 37 | #include <linux/i2c.h> |
| 38 | #include <linux/regmap.h> |
| 39 | #include <linux/spi/spi.h> |
Sachin Kamat | 285d00c | 2013-10-11 17:23:59 +0530 | [diff] [blame] | 40 | #include <linux/of.h> |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 41 | #include <linux/of_device.h> |
| 42 | #include <linux/of_gpio.h> |
| 43 | #include <sound/pcm.h> |
| 44 | #include <sound/pcm_params.h> |
| 45 | #include <sound/soc.h> |
| 46 | #include <sound/tlv.h> |
| 47 | #include <sound/tas5086.h> |
| 48 | |
| 49 | #define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
| 50 | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 51 | SNDRV_PCM_FMTBIT_S24_3LE) |
| 52 | |
| 53 | #define TAS5086_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
| 54 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \ |
| 55 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \ |
| 56 | SNDRV_PCM_RATE_192000) |
| 57 | |
| 58 | /* |
| 59 | * TAS5086 registers |
| 60 | */ |
| 61 | #define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */ |
| 62 | #define TAS5086_CLOCK_RATE(val) (val << 5) |
| 63 | #define TAS5086_CLOCK_RATE_MASK (0x7 << 5) |
| 64 | #define TAS5086_CLOCK_RATIO(val) (val << 2) |
| 65 | #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2) |
| 66 | #define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1) |
| 67 | #define TAS5086_CLOCK_VALID (1 << 0) |
| 68 | |
| 69 | #define TAS5086_DEEMPH_MASK 0x03 |
| 70 | #define TAS5086_SOFT_MUTE_ALL 0x3f |
| 71 | |
| 72 | #define TAS5086_DEV_ID 0x01 /* Device ID register */ |
| 73 | #define TAS5086_ERROR_STATUS 0x02 /* Error status register */ |
| 74 | #define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */ |
| 75 | #define TAS5086_SERIAL_DATA_IF 0x04 /* Serial data interface register */ |
| 76 | #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */ |
| 77 | #define TAS5086_SOFT_MUTE 0x06 /* Soft mute register */ |
| 78 | #define TAS5086_MASTER_VOL 0x07 /* Master volume */ |
| 79 | #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */ |
| 80 | #define TAS5086_VOLUME_CONTROL 0x09 /* Volume control register */ |
| 81 | #define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */ |
| 82 | #define TAS5086_PWM_START 0x18 /* PWM start register */ |
| 83 | #define TAS5086_SURROUND 0x19 /* Surround register */ |
| 84 | #define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */ |
| 85 | #define TAS5086_OSC_TRIM 0x1b /* Oscillator trim register */ |
| 86 | #define TAS5086_BKNDERR 0x1c |
Daniel Mack | 8892d47 | 2013-06-24 16:25:30 +0200 | [diff] [blame] | 87 | #define TAS5086_INPUT_MUX 0x20 |
| 88 | #define TAS5086_PWM_OUTPUT_MUX 0x25 |
| 89 | |
| 90 | #define TAS5086_MAX_REGISTER TAS5086_PWM_OUTPUT_MUX |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 91 | |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 92 | #define TAS5086_PWM_START_MIDZ_FOR_START_1 (1 << 7) |
| 93 | #define TAS5086_PWM_START_MIDZ_FOR_START_2 (1 << 6) |
| 94 | #define TAS5086_PWM_START_CHANNEL_MASK (0x3f) |
| 95 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 96 | /* |
| 97 | * Default TAS5086 power-up configuration |
| 98 | */ |
| 99 | static const struct reg_default tas5086_reg_defaults[] = { |
| 100 | { 0x00, 0x6c }, |
| 101 | { 0x01, 0x03 }, |
| 102 | { 0x02, 0x00 }, |
| 103 | { 0x03, 0xa0 }, |
| 104 | { 0x04, 0x05 }, |
| 105 | { 0x05, 0x60 }, |
| 106 | { 0x06, 0x00 }, |
| 107 | { 0x07, 0xff }, |
| 108 | { 0x08, 0x30 }, |
| 109 | { 0x09, 0x30 }, |
| 110 | { 0x0a, 0x30 }, |
| 111 | { 0x0b, 0x30 }, |
| 112 | { 0x0c, 0x30 }, |
| 113 | { 0x0d, 0x30 }, |
| 114 | { 0x0e, 0xb1 }, |
| 115 | { 0x0f, 0x00 }, |
| 116 | { 0x10, 0x02 }, |
| 117 | { 0x11, 0x00 }, |
| 118 | { 0x12, 0x00 }, |
| 119 | { 0x13, 0x00 }, |
| 120 | { 0x14, 0x00 }, |
| 121 | { 0x15, 0x00 }, |
| 122 | { 0x16, 0x00 }, |
| 123 | { 0x17, 0x00 }, |
| 124 | { 0x18, 0x3f }, |
| 125 | { 0x19, 0x00 }, |
| 126 | { 0x1a, 0x18 }, |
| 127 | { 0x1b, 0x82 }, |
| 128 | { 0x1c, 0x05 }, |
| 129 | }; |
| 130 | |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 131 | static int tas5086_register_size(struct device *dev, unsigned int reg) |
| 132 | { |
| 133 | switch (reg) { |
Daniel Mack | 9f24dc8 | 2013-06-27 21:59:10 +0200 | [diff] [blame] | 134 | case TAS5086_CLOCK_CONTROL ... TAS5086_BKNDERR: |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 135 | return 1; |
Daniel Mack | 8892d47 | 2013-06-24 16:25:30 +0200 | [diff] [blame] | 136 | case TAS5086_INPUT_MUX: |
| 137 | case TAS5086_PWM_OUTPUT_MUX: |
| 138 | return 4; |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | dev_err(dev, "Unsupported register address: %d\n", reg); |
| 142 | return 0; |
| 143 | } |
| 144 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 145 | static bool tas5086_accessible_reg(struct device *dev, unsigned int reg) |
| 146 | { |
Daniel Mack | 8892d47 | 2013-06-24 16:25:30 +0200 | [diff] [blame] | 147 | switch (reg) { |
| 148 | case 0x0f: |
| 149 | case 0x11 ... 0x17: |
| 150 | case 0x1d ... 0x1f: |
| 151 | return false; |
| 152 | default: |
| 153 | return true; |
| 154 | } |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static bool tas5086_volatile_reg(struct device *dev, unsigned int reg) |
| 158 | { |
| 159 | switch (reg) { |
| 160 | case TAS5086_DEV_ID: |
| 161 | case TAS5086_ERROR_STATUS: |
| 162 | return true; |
| 163 | } |
| 164 | |
| 165 | return false; |
| 166 | } |
| 167 | |
| 168 | static bool tas5086_writeable_reg(struct device *dev, unsigned int reg) |
| 169 | { |
| 170 | return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID); |
| 171 | } |
| 172 | |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 173 | static int tas5086_reg_write(void *context, unsigned int reg, |
| 174 | unsigned int value) |
| 175 | { |
| 176 | struct i2c_client *client = context; |
| 177 | unsigned int i, size; |
| 178 | uint8_t buf[5]; |
| 179 | int ret; |
| 180 | |
| 181 | size = tas5086_register_size(&client->dev, reg); |
| 182 | if (size == 0) |
| 183 | return -EINVAL; |
| 184 | |
| 185 | buf[0] = reg; |
| 186 | |
| 187 | for (i = size; i >= 1; --i) { |
| 188 | buf[i] = value; |
| 189 | value >>= 8; |
| 190 | } |
| 191 | |
| 192 | ret = i2c_master_send(client, buf, size + 1); |
| 193 | if (ret == size + 1) |
| 194 | return 0; |
| 195 | else if (ret < 0) |
| 196 | return ret; |
| 197 | else |
| 198 | return -EIO; |
| 199 | } |
| 200 | |
| 201 | static int tas5086_reg_read(void *context, unsigned int reg, |
| 202 | unsigned int *value) |
| 203 | { |
| 204 | struct i2c_client *client = context; |
| 205 | uint8_t send_buf, recv_buf[4]; |
| 206 | struct i2c_msg msgs[2]; |
| 207 | unsigned int size; |
| 208 | unsigned int i; |
| 209 | int ret; |
| 210 | |
| 211 | size = tas5086_register_size(&client->dev, reg); |
| 212 | if (size == 0) |
| 213 | return -EINVAL; |
| 214 | |
| 215 | send_buf = reg; |
| 216 | |
| 217 | msgs[0].addr = client->addr; |
| 218 | msgs[0].len = sizeof(send_buf); |
| 219 | msgs[0].buf = &send_buf; |
| 220 | msgs[0].flags = 0; |
| 221 | |
| 222 | msgs[1].addr = client->addr; |
| 223 | msgs[1].len = size; |
| 224 | msgs[1].buf = recv_buf; |
| 225 | msgs[1].flags = I2C_M_RD; |
| 226 | |
| 227 | ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); |
| 228 | if (ret < 0) |
| 229 | return ret; |
| 230 | else if (ret != ARRAY_SIZE(msgs)) |
| 231 | return -EIO; |
| 232 | |
| 233 | *value = 0; |
| 234 | |
| 235 | for (i = 0; i < size; i++) { |
| 236 | *value <<= 8; |
| 237 | *value |= recv_buf[i]; |
| 238 | } |
| 239 | |
| 240 | return 0; |
| 241 | } |
| 242 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 243 | struct tas5086_private { |
| 244 | struct regmap *regmap; |
| 245 | unsigned int mclk, sclk; |
| 246 | unsigned int format; |
| 247 | bool deemph; |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame] | 248 | unsigned int charge_period; |
| 249 | unsigned int pwm_start_mid_z; |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 250 | /* Current sample rate for de-emphasis control */ |
| 251 | int rate; |
| 252 | /* GPIO driving Reset pin, if any */ |
| 253 | int gpio_nreset; |
| 254 | }; |
| 255 | |
| 256 | static int tas5086_deemph[] = { 0, 32000, 44100, 48000 }; |
| 257 | |
| 258 | static int tas5086_set_deemph(struct snd_soc_codec *codec) |
| 259 | { |
| 260 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 261 | int i, val = 0; |
| 262 | |
| 263 | if (priv->deemph) |
| 264 | for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++) |
| 265 | if (tas5086_deemph[i] == priv->rate) |
| 266 | val = i; |
| 267 | |
| 268 | return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1, |
| 269 | TAS5086_DEEMPH_MASK, val); |
| 270 | } |
| 271 | |
| 272 | static int tas5086_get_deemph(struct snd_kcontrol *kcontrol, |
| 273 | struct snd_ctl_elem_value *ucontrol) |
| 274 | { |
Lars-Peter Clausen | ea53bf7 | 2014-03-18 09:02:04 +0100 | [diff] [blame^] | 275 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 276 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 277 | |
| 278 | ucontrol->value.enumerated.item[0] = priv->deemph; |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | static int tas5086_put_deemph(struct snd_kcontrol *kcontrol, |
| 284 | struct snd_ctl_elem_value *ucontrol) |
| 285 | { |
Lars-Peter Clausen | ea53bf7 | 2014-03-18 09:02:04 +0100 | [diff] [blame^] | 286 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 287 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 288 | |
| 289 | priv->deemph = ucontrol->value.enumerated.item[0]; |
| 290 | |
| 291 | return tas5086_set_deemph(codec); |
| 292 | } |
| 293 | |
| 294 | |
| 295 | static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
| 296 | int clk_id, unsigned int freq, int dir) |
| 297 | { |
| 298 | struct snd_soc_codec *codec = codec_dai->codec; |
| 299 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 300 | |
| 301 | switch (clk_id) { |
| 302 | case TAS5086_CLK_IDX_MCLK: |
| 303 | priv->mclk = freq; |
| 304 | break; |
| 305 | case TAS5086_CLK_IDX_SCLK: |
| 306 | priv->sclk = freq; |
| 307 | break; |
| 308 | } |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
| 313 | static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai, |
| 314 | unsigned int format) |
| 315 | { |
| 316 | struct snd_soc_codec *codec = codec_dai->codec; |
| 317 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 318 | |
| 319 | /* The TAS5086 can only be slave to all clocks */ |
| 320 | if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) { |
| 321 | dev_err(codec->dev, "Invalid clocking mode\n"); |
| 322 | return -EINVAL; |
| 323 | } |
| 324 | |
| 325 | /* we need to refer to the data format from hw_params() */ |
| 326 | priv->format = format; |
| 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
| 331 | static const int tas5086_sample_rates[] = { |
| 332 | 32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000 |
| 333 | }; |
| 334 | |
| 335 | static const int tas5086_ratios[] = { |
| 336 | 64, 128, 192, 256, 384, 512 |
| 337 | }; |
| 338 | |
| 339 | static int index_in_array(const int *array, int len, int needle) |
| 340 | { |
| 341 | int i; |
| 342 | |
| 343 | for (i = 0; i < len; i++) |
| 344 | if (array[i] == needle) |
| 345 | return i; |
| 346 | |
| 347 | return -ENOENT; |
| 348 | } |
| 349 | |
| 350 | static int tas5086_hw_params(struct snd_pcm_substream *substream, |
| 351 | struct snd_pcm_hw_params *params, |
| 352 | struct snd_soc_dai *dai) |
| 353 | { |
| 354 | struct snd_soc_codec *codec = dai->codec; |
| 355 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
Dan Carpenter | 28dbd16 | 2013-03-13 08:32:53 +0300 | [diff] [blame] | 356 | int val; |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 357 | int ret; |
| 358 | |
| 359 | priv->rate = params_rate(params); |
| 360 | |
| 361 | /* Look up the sample rate and refer to the offset in the list */ |
| 362 | val = index_in_array(tas5086_sample_rates, |
| 363 | ARRAY_SIZE(tas5086_sample_rates), priv->rate); |
| 364 | |
| 365 | if (val < 0) { |
| 366 | dev_err(codec->dev, "Invalid sample rate\n"); |
| 367 | return -EINVAL; |
| 368 | } |
| 369 | |
| 370 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, |
| 371 | TAS5086_CLOCK_RATE_MASK, |
| 372 | TAS5086_CLOCK_RATE(val)); |
| 373 | if (ret < 0) |
| 374 | return ret; |
| 375 | |
| 376 | /* MCLK / Fs ratio */ |
| 377 | val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios), |
| 378 | priv->mclk / priv->rate); |
| 379 | if (val < 0) { |
| 380 | dev_err(codec->dev, "Inavlid MCLK / Fs ratio\n"); |
| 381 | return -EINVAL; |
| 382 | } |
| 383 | |
| 384 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, |
| 385 | TAS5086_CLOCK_RATIO_MASK, |
| 386 | TAS5086_CLOCK_RATIO(val)); |
| 387 | if (ret < 0) |
| 388 | return ret; |
| 389 | |
| 390 | |
| 391 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, |
| 392 | TAS5086_CLOCK_SCLK_RATIO_48, |
| 393 | (priv->sclk == 48 * priv->rate) ? |
| 394 | TAS5086_CLOCK_SCLK_RATIO_48 : 0); |
| 395 | if (ret < 0) |
| 396 | return ret; |
| 397 | |
| 398 | /* |
| 399 | * The chip has a very unituitive register mapping and muxes information |
| 400 | * about data format and sample depth into the same register, but not on |
| 401 | * a logical bit-boundary. Hence, we have to refer to the format passed |
| 402 | * in the set_dai_fmt() callback and set up everything from here. |
| 403 | * |
| 404 | * First, determine the 'base' value, using the format ... |
| 405 | */ |
| 406 | switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 407 | case SND_SOC_DAIFMT_RIGHT_J: |
| 408 | val = 0x00; |
| 409 | break; |
| 410 | case SND_SOC_DAIFMT_I2S: |
| 411 | val = 0x03; |
| 412 | break; |
| 413 | case SND_SOC_DAIFMT_LEFT_J: |
| 414 | val = 0x06; |
| 415 | break; |
| 416 | default: |
| 417 | dev_err(codec->dev, "Invalid DAI format\n"); |
| 418 | return -EINVAL; |
| 419 | } |
| 420 | |
| 421 | /* ... then add the offset for the sample bit depth. */ |
| 422 | switch (params_format(params)) { |
| 423 | case SNDRV_PCM_FORMAT_S16_LE: |
| 424 | val += 0; |
| 425 | break; |
| 426 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 427 | val += 1; |
| 428 | break; |
| 429 | case SNDRV_PCM_FORMAT_S24_3LE: |
| 430 | val += 2; |
| 431 | break; |
| 432 | default: |
| 433 | dev_err(codec->dev, "Invalid bit width\n"); |
| 434 | return -EINVAL; |
Joe Perches | 1d198f2 | 2013-10-08 15:55:45 -0700 | [diff] [blame] | 435 | } |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 436 | |
| 437 | ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val); |
| 438 | if (ret < 0) |
| 439 | return ret; |
| 440 | |
| 441 | /* clock is considered valid now */ |
| 442 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, |
| 443 | TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID); |
| 444 | if (ret < 0) |
| 445 | return ret; |
| 446 | |
| 447 | return tas5086_set_deemph(codec); |
| 448 | } |
| 449 | |
| 450 | static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream) |
| 451 | { |
| 452 | struct snd_soc_codec *codec = dai->codec; |
| 453 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 454 | unsigned int val = 0; |
| 455 | |
| 456 | if (mute) |
| 457 | val = TAS5086_SOFT_MUTE_ALL; |
| 458 | |
| 459 | return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val); |
| 460 | } |
| 461 | |
Daniel Mack | d5fd3cc | 2013-10-01 14:48:25 +0200 | [diff] [blame] | 462 | static void tas5086_reset(struct tas5086_private *priv) |
| 463 | { |
| 464 | if (gpio_is_valid(priv->gpio_nreset)) { |
| 465 | /* Reset codec - minimum assertion time is 400ns */ |
| 466 | gpio_direction_output(priv->gpio_nreset, 0); |
| 467 | udelay(1); |
| 468 | gpio_set_value(priv->gpio_nreset, 1); |
| 469 | |
| 470 | /* Codec needs ~15ms to wake up */ |
| 471 | msleep(15); |
| 472 | } |
| 473 | } |
| 474 | |
| 475 | /* charge period values in microseconds */ |
| 476 | static const int tas5086_charge_period[] = { |
| 477 | 13000, 16900, 23400, 31200, 41600, 54600, 72800, 96200, |
| 478 | 130000, 156000, 234000, 312000, 416000, 546000, 728000, 962000, |
| 479 | 1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000, |
| 480 | }; |
| 481 | |
| 482 | static int tas5086_init(struct device *dev, struct tas5086_private *priv) |
| 483 | { |
| 484 | int ret, i; |
| 485 | |
| 486 | /* |
| 487 | * If any of the channels is configured to start in Mid-Z mode, |
| 488 | * configure 'part 1' of the PWM starts to use Mid-Z, and tell |
| 489 | * all configured mid-z channels to start start under 'part 1'. |
| 490 | */ |
| 491 | if (priv->pwm_start_mid_z) |
| 492 | regmap_write(priv->regmap, TAS5086_PWM_START, |
| 493 | TAS5086_PWM_START_MIDZ_FOR_START_1 | |
| 494 | priv->pwm_start_mid_z); |
| 495 | |
| 496 | /* lookup and set split-capacitor charge period */ |
| 497 | if (priv->charge_period == 0) { |
| 498 | regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0); |
| 499 | } else { |
| 500 | i = index_in_array(tas5086_charge_period, |
| 501 | ARRAY_SIZE(tas5086_charge_period), |
| 502 | priv->charge_period); |
| 503 | if (i >= 0) |
| 504 | regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, |
| 505 | i + 0x08); |
| 506 | else |
| 507 | dev_warn(dev, |
| 508 | "Invalid split-cap charge period of %d ns.\n", |
| 509 | priv->charge_period); |
| 510 | } |
| 511 | |
| 512 | /* enable factory trim */ |
| 513 | ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00); |
| 514 | if (ret < 0) |
| 515 | return ret; |
| 516 | |
| 517 | /* start all channels */ |
| 518 | ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20); |
| 519 | if (ret < 0) |
| 520 | return ret; |
| 521 | |
| 522 | /* mute all channels for now */ |
| 523 | ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE, |
| 524 | TAS5086_SOFT_MUTE_ALL); |
| 525 | if (ret < 0) |
| 526 | return ret; |
| 527 | |
| 528 | return 0; |
| 529 | } |
| 530 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 531 | /* TAS5086 controls */ |
| 532 | static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1); |
| 533 | |
| 534 | static const struct snd_kcontrol_new tas5086_controls[] = { |
| 535 | SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL, |
| 536 | 0, 0xff, 1, tas5086_dac_tlv), |
| 537 | SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume", |
| 538 | TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1), |
| 539 | 0, 0xff, 1, tas5086_dac_tlv), |
| 540 | SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume", |
| 541 | TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3), |
| 542 | 0, 0xff, 1, tas5086_dac_tlv), |
| 543 | SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume", |
| 544 | TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5), |
| 545 | 0, 0xff, 1, tas5086_dac_tlv), |
| 546 | SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, |
| 547 | tas5086_get_deemph, tas5086_put_deemph), |
| 548 | }; |
| 549 | |
Daniel Mack | 18710ac | 2013-06-24 16:25:31 +0200 | [diff] [blame] | 550 | /* Input mux controls */ |
| 551 | static const char *tas5086_dapm_sdin_texts[] = |
| 552 | { |
| 553 | "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R", |
| 554 | "SDIN3-L", "SDIN3-R", "Ground (0)", "nc" |
| 555 | }; |
| 556 | |
| 557 | static const struct soc_enum tas5086_dapm_input_mux_enum[] = { |
| 558 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts), |
| 559 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts), |
| 560 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts), |
| 561 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts), |
| 562 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts), |
| 563 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts), |
| 564 | }; |
| 565 | |
| 566 | static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = { |
| 567 | SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]), |
| 568 | SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]), |
| 569 | SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]), |
| 570 | SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]), |
| 571 | SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]), |
| 572 | SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]), |
| 573 | }; |
| 574 | |
| 575 | /* Output mux controls */ |
| 576 | static const char *tas5086_dapm_channel_texts[] = |
| 577 | { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux", |
| 578 | "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" }; |
| 579 | |
| 580 | static const struct soc_enum tas5086_dapm_output_mux_enum[] = { |
| 581 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts), |
| 582 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts), |
| 583 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts), |
| 584 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts), |
| 585 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts), |
| 586 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0, 6, tas5086_dapm_channel_texts), |
| 587 | }; |
| 588 | |
| 589 | static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = { |
| 590 | SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]), |
| 591 | SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]), |
| 592 | SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]), |
| 593 | SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]), |
| 594 | SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]), |
| 595 | SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]), |
| 596 | }; |
| 597 | |
| 598 | static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = { |
| 599 | SND_SOC_DAPM_INPUT("SDIN1-L"), |
| 600 | SND_SOC_DAPM_INPUT("SDIN1-R"), |
| 601 | SND_SOC_DAPM_INPUT("SDIN2-L"), |
| 602 | SND_SOC_DAPM_INPUT("SDIN2-R"), |
| 603 | SND_SOC_DAPM_INPUT("SDIN3-L"), |
| 604 | SND_SOC_DAPM_INPUT("SDIN3-R"), |
| 605 | SND_SOC_DAPM_INPUT("SDIN4-L"), |
| 606 | SND_SOC_DAPM_INPUT("SDIN4-R"), |
| 607 | |
| 608 | SND_SOC_DAPM_OUTPUT("PWM1"), |
| 609 | SND_SOC_DAPM_OUTPUT("PWM2"), |
| 610 | SND_SOC_DAPM_OUTPUT("PWM3"), |
| 611 | SND_SOC_DAPM_OUTPUT("PWM4"), |
| 612 | SND_SOC_DAPM_OUTPUT("PWM5"), |
| 613 | SND_SOC_DAPM_OUTPUT("PWM6"), |
| 614 | |
| 615 | SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0, |
| 616 | &tas5086_dapm_input_mux_controls[0]), |
| 617 | SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0, |
| 618 | &tas5086_dapm_input_mux_controls[1]), |
| 619 | SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0, |
| 620 | &tas5086_dapm_input_mux_controls[2]), |
| 621 | SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0, |
| 622 | &tas5086_dapm_input_mux_controls[3]), |
| 623 | SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0, |
| 624 | &tas5086_dapm_input_mux_controls[4]), |
| 625 | SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0, |
| 626 | &tas5086_dapm_input_mux_controls[5]), |
| 627 | |
| 628 | SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0, |
| 629 | &tas5086_dapm_output_mux_controls[0]), |
| 630 | SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0, |
| 631 | &tas5086_dapm_output_mux_controls[1]), |
| 632 | SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0, |
| 633 | &tas5086_dapm_output_mux_controls[2]), |
| 634 | SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0, |
| 635 | &tas5086_dapm_output_mux_controls[3]), |
| 636 | SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0, |
| 637 | &tas5086_dapm_output_mux_controls[4]), |
| 638 | SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0, |
| 639 | &tas5086_dapm_output_mux_controls[5]), |
| 640 | }; |
| 641 | |
| 642 | static const struct snd_soc_dapm_route tas5086_dapm_routes[] = { |
| 643 | /* SDIN inputs -> channel muxes */ |
| 644 | { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" }, |
| 645 | { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" }, |
| 646 | { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" }, |
| 647 | { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" }, |
| 648 | { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" }, |
| 649 | { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" }, |
| 650 | |
| 651 | { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" }, |
| 652 | { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" }, |
| 653 | { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" }, |
| 654 | { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" }, |
| 655 | { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" }, |
| 656 | { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" }, |
| 657 | |
| 658 | { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" }, |
| 659 | { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" }, |
| 660 | { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" }, |
| 661 | { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" }, |
| 662 | { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" }, |
| 663 | { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" }, |
| 664 | |
| 665 | { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" }, |
| 666 | { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" }, |
| 667 | { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" }, |
| 668 | { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" }, |
| 669 | { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" }, |
| 670 | { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" }, |
| 671 | |
| 672 | { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" }, |
| 673 | { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" }, |
| 674 | { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" }, |
| 675 | { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" }, |
| 676 | { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" }, |
| 677 | { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" }, |
| 678 | |
| 679 | { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" }, |
| 680 | { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" }, |
| 681 | { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" }, |
| 682 | { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" }, |
| 683 | { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" }, |
| 684 | { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" }, |
| 685 | |
| 686 | { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" }, |
| 687 | { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" }, |
| 688 | { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" }, |
| 689 | { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" }, |
| 690 | { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" }, |
| 691 | { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" }, |
| 692 | |
| 693 | /* Channel muxes -> PWM muxes */ |
| 694 | { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 695 | { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 696 | { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 697 | { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 698 | { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 699 | { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" }, |
| 700 | |
| 701 | { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 702 | { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 703 | { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 704 | { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 705 | { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 706 | { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" }, |
| 707 | |
| 708 | { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 709 | { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 710 | { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 711 | { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 712 | { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 713 | { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" }, |
| 714 | |
| 715 | { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 716 | { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 717 | { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 718 | { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 719 | { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 720 | { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" }, |
| 721 | |
| 722 | { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 723 | { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 724 | { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 725 | { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 726 | { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 727 | { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" }, |
| 728 | |
| 729 | { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 730 | { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 731 | { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 732 | { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 733 | { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 734 | { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" }, |
| 735 | |
| 736 | /* The PWM muxes are directly connected to the PWM outputs */ |
| 737 | { "PWM1", NULL, "PWM1 Mux" }, |
| 738 | { "PWM2", NULL, "PWM2 Mux" }, |
| 739 | { "PWM3", NULL, "PWM3 Mux" }, |
| 740 | { "PWM4", NULL, "PWM4 Mux" }, |
| 741 | { "PWM5", NULL, "PWM5 Mux" }, |
| 742 | { "PWM6", NULL, "PWM6 Mux" }, |
| 743 | |
| 744 | }; |
| 745 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 746 | static const struct snd_soc_dai_ops tas5086_dai_ops = { |
| 747 | .hw_params = tas5086_hw_params, |
| 748 | .set_sysclk = tas5086_set_dai_sysclk, |
| 749 | .set_fmt = tas5086_set_dai_fmt, |
| 750 | .mute_stream = tas5086_mute_stream, |
| 751 | }; |
| 752 | |
| 753 | static struct snd_soc_dai_driver tas5086_dai = { |
| 754 | .name = "tas5086-hifi", |
| 755 | .playback = { |
| 756 | .stream_name = "Playback", |
| 757 | .channels_min = 2, |
| 758 | .channels_max = 6, |
| 759 | .rates = TAS5086_PCM_RATES, |
| 760 | .formats = TAS5086_PCM_FORMATS, |
| 761 | }, |
| 762 | .ops = &tas5086_dai_ops, |
| 763 | }; |
| 764 | |
| 765 | #ifdef CONFIG_PM |
Daniel Mack | 25c84cc | 2013-10-01 14:48:26 +0200 | [diff] [blame] | 766 | static int tas5086_soc_suspend(struct snd_soc_codec *codec) |
| 767 | { |
| 768 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 769 | int ret; |
| 770 | |
| 771 | /* Shut down all channels */ |
| 772 | ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x60); |
| 773 | if (ret < 0) |
| 774 | return ret; |
| 775 | |
| 776 | return 0; |
| 777 | } |
| 778 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 779 | static int tas5086_soc_resume(struct snd_soc_codec *codec) |
| 780 | { |
| 781 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
Daniel Mack | 25c84cc | 2013-10-01 14:48:26 +0200 | [diff] [blame] | 782 | int ret; |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 783 | |
Daniel Mack | 25c84cc | 2013-10-01 14:48:26 +0200 | [diff] [blame] | 784 | tas5086_reset(priv); |
| 785 | regcache_mark_dirty(priv->regmap); |
| 786 | |
| 787 | ret = tas5086_init(codec->dev, priv); |
| 788 | if (ret < 0) |
| 789 | return ret; |
| 790 | |
| 791 | ret = regcache_sync(priv->regmap); |
| 792 | if (ret < 0) |
| 793 | return ret; |
| 794 | |
| 795 | return 0; |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 796 | } |
| 797 | #else |
Daniel Mack | 25c84cc | 2013-10-01 14:48:26 +0200 | [diff] [blame] | 798 | #define tas5086_soc_suspend NULL |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 799 | #define tas5086_soc_resume NULL |
| 800 | #endif /* CONFIG_PM */ |
| 801 | |
| 802 | #ifdef CONFIG_OF |
| 803 | static const struct of_device_id tas5086_dt_ids[] = { |
| 804 | { .compatible = "ti,tas5086", }, |
| 805 | { } |
| 806 | }; |
| 807 | MODULE_DEVICE_TABLE(of, tas5086_dt_ids); |
| 808 | #endif |
| 809 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 810 | static int tas5086_probe(struct snd_soc_codec *codec) |
| 811 | { |
| 812 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 813 | int i, ret; |
| 814 | |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame] | 815 | priv->pwm_start_mid_z = 0; |
| 816 | priv->charge_period = 1300000; /* hardware default is 1300 ms */ |
| 817 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 818 | if (of_match_device(of_match_ptr(tas5086_dt_ids), codec->dev)) { |
| 819 | struct device_node *of_node = codec->dev->of_node; |
Daniel Mack | d5fd3cc | 2013-10-01 14:48:25 +0200 | [diff] [blame] | 820 | |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame] | 821 | of_property_read_u32(of_node, "ti,charge-period", |
| 822 | &priv->charge_period); |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 823 | |
| 824 | for (i = 0; i < 6; i++) { |
| 825 | char name[25]; |
| 826 | |
| 827 | snprintf(name, sizeof(name), |
| 828 | "ti,mid-z-channel-%d", i + 1); |
| 829 | |
| 830 | if (of_get_property(of_node, name, NULL) != NULL) |
Daniel Mack | 648c538 | 2013-10-01 14:48:24 +0200 | [diff] [blame] | 831 | priv->pwm_start_mid_z |= 1 << i; |
Daniel Mack | 79b23b5 | 2013-06-24 16:25:32 +0200 | [diff] [blame] | 832 | } |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 833 | } |
| 834 | |
Daniel Mack | d5fd3cc | 2013-10-01 14:48:25 +0200 | [diff] [blame] | 835 | ret = tas5086_init(codec->dev, priv); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 836 | if (ret < 0) |
| 837 | return ret; |
| 838 | |
| 839 | /* set master volume to 0 dB */ |
| 840 | ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30); |
| 841 | if (ret < 0) |
| 842 | return ret; |
| 843 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 844 | return 0; |
| 845 | } |
| 846 | |
| 847 | static int tas5086_remove(struct snd_soc_codec *codec) |
| 848 | { |
| 849 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); |
| 850 | |
| 851 | if (gpio_is_valid(priv->gpio_nreset)) |
| 852 | /* Set codec to the reset state */ |
| 853 | gpio_set_value(priv->gpio_nreset, 0); |
| 854 | |
| 855 | return 0; |
| 856 | }; |
| 857 | |
| 858 | static struct snd_soc_codec_driver soc_codec_dev_tas5086 = { |
| 859 | .probe = tas5086_probe, |
| 860 | .remove = tas5086_remove, |
Daniel Mack | 25c84cc | 2013-10-01 14:48:26 +0200 | [diff] [blame] | 861 | .suspend = tas5086_soc_suspend, |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 862 | .resume = tas5086_soc_resume, |
| 863 | .controls = tas5086_controls, |
| 864 | .num_controls = ARRAY_SIZE(tas5086_controls), |
Daniel Mack | 18710ac | 2013-06-24 16:25:31 +0200 | [diff] [blame] | 865 | .dapm_widgets = tas5086_dapm_widgets, |
| 866 | .num_dapm_widgets = ARRAY_SIZE(tas5086_dapm_widgets), |
| 867 | .dapm_routes = tas5086_dapm_routes, |
| 868 | .num_dapm_routes = ARRAY_SIZE(tas5086_dapm_routes), |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 869 | }; |
| 870 | |
| 871 | static const struct i2c_device_id tas5086_i2c_id[] = { |
| 872 | { "tas5086", 0 }, |
| 873 | { } |
| 874 | }; |
| 875 | MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id); |
| 876 | |
| 877 | static const struct regmap_config tas5086_regmap = { |
| 878 | .reg_bits = 8, |
Daniel Mack | 8892d47 | 2013-06-24 16:25:30 +0200 | [diff] [blame] | 879 | .val_bits = 32, |
| 880 | .max_register = TAS5086_MAX_REGISTER, |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 881 | .reg_defaults = tas5086_reg_defaults, |
| 882 | .num_reg_defaults = ARRAY_SIZE(tas5086_reg_defaults), |
| 883 | .cache_type = REGCACHE_RBTREE, |
| 884 | .volatile_reg = tas5086_volatile_reg, |
| 885 | .writeable_reg = tas5086_writeable_reg, |
| 886 | .readable_reg = tas5086_accessible_reg, |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 887 | .reg_read = tas5086_reg_read, |
| 888 | .reg_write = tas5086_reg_write, |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 889 | }; |
| 890 | |
| 891 | static int tas5086_i2c_probe(struct i2c_client *i2c, |
| 892 | const struct i2c_device_id *id) |
| 893 | { |
| 894 | struct tas5086_private *priv; |
| 895 | struct device *dev = &i2c->dev; |
| 896 | int gpio_nreset = -EINVAL; |
| 897 | int i, ret; |
| 898 | |
| 899 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
| 900 | if (!priv) |
| 901 | return -ENOMEM; |
| 902 | |
Daniel Mack | 6b36d37 | 2013-06-24 16:25:29 +0200 | [diff] [blame] | 903 | priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 904 | if (IS_ERR(priv->regmap)) { |
| 905 | ret = PTR_ERR(priv->regmap); |
| 906 | dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret); |
| 907 | return ret; |
| 908 | } |
| 909 | |
| 910 | i2c_set_clientdata(i2c, priv); |
| 911 | |
| 912 | if (of_match_device(of_match_ptr(tas5086_dt_ids), dev)) { |
| 913 | struct device_node *of_node = dev->of_node; |
| 914 | gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0); |
| 915 | } |
| 916 | |
| 917 | if (gpio_is_valid(gpio_nreset)) |
| 918 | if (devm_gpio_request(dev, gpio_nreset, "TAS5086 Reset")) |
| 919 | gpio_nreset = -EINVAL; |
| 920 | |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 921 | priv->gpio_nreset = gpio_nreset; |
Daniel Mack | d5fd3cc | 2013-10-01 14:48:25 +0200 | [diff] [blame] | 922 | tas5086_reset(priv); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 923 | |
| 924 | /* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */ |
| 925 | ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i); |
| 926 | if (ret < 0) |
| 927 | return ret; |
| 928 | |
| 929 | if (i != 0x3) { |
| 930 | dev_err(dev, |
| 931 | "Failed to identify TAS5086 codec (got %02x)\n", i); |
| 932 | return -ENODEV; |
| 933 | } |
| 934 | |
| 935 | return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tas5086, |
| 936 | &tas5086_dai, 1); |
| 937 | } |
| 938 | |
| 939 | static int tas5086_i2c_remove(struct i2c_client *i2c) |
| 940 | { |
| 941 | snd_soc_unregister_codec(&i2c->dev); |
| 942 | return 0; |
| 943 | } |
| 944 | |
| 945 | static struct i2c_driver tas5086_i2c_driver = { |
| 946 | .driver = { |
| 947 | .name = "tas5086", |
| 948 | .owner = THIS_MODULE, |
| 949 | .of_match_table = of_match_ptr(tas5086_dt_ids), |
| 950 | }, |
| 951 | .id_table = tas5086_i2c_id, |
| 952 | .probe = tas5086_i2c_probe, |
| 953 | .remove = tas5086_i2c_remove, |
| 954 | }; |
| 955 | |
Wei Yongjun | c300d6d | 2013-03-12 21:36:24 +0800 | [diff] [blame] | 956 | module_i2c_driver(tas5086_i2c_driver); |
Daniel Mack | 4fa8934 | 2013-03-08 13:52:09 +0100 | [diff] [blame] | 957 | |
| 958 | MODULE_AUTHOR("Daniel Mack <zonque@gmail.com>"); |
| 959 | MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver"); |
| 960 | MODULE_LICENSE("GPL"); |