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Kristian Høgsbergc781c062007-05-07 20:33:32 -04001/*
2 * Driver for OHCI 1394 controllers
Kristian Høgsberged568912006-12-19 19:58:35 -05003 *
Kristian Høgsberged568912006-12-19 19:58:35 -05004 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
Stefan Richtere524f6162007-08-20 21:58:30 +020021#include <linux/compiler.h>
Kristian Høgsberged568912006-12-19 19:58:35 -050022#include <linux/delay.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080023#include <linux/dma-mapping.h>
Stefan Richterc26f0232007-08-20 21:40:30 +020024#include <linux/gfp.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020025#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
Al Virofaa2fb42007-05-15 20:36:10 +010028#include <linux/mm.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020029#include <linux/module.h>
30#include <linux/pci.h>
Stefan Richterc26f0232007-08-20 21:40:30 +020031#include <linux/spinlock.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080032
Stefan Richterc26f0232007-08-20 21:40:30 +020033#include <asm/page.h>
Stefan Richteree71c2f2007-08-25 14:08:19 +020034#include <asm/system.h>
Kristian Høgsberged568912006-12-19 19:58:35 -050035
Kristian Høgsberged568912006-12-19 19:58:35 -050036#include "fw-ohci.h"
Stefan Richtera7fb60d2007-08-20 21:41:22 +020037#include "fw-transaction.h"
Kristian Høgsberged568912006-12-19 19:58:35 -050038
Kristian Høgsberga77754a2007-05-07 20:33:35 -040039#define DESCRIPTOR_OUTPUT_MORE 0
40#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
41#define DESCRIPTOR_INPUT_MORE (2 << 12)
42#define DESCRIPTOR_INPUT_LAST (3 << 12)
43#define DESCRIPTOR_STATUS (1 << 11)
44#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
45#define DESCRIPTOR_PING (1 << 7)
46#define DESCRIPTOR_YY (1 << 6)
47#define DESCRIPTOR_NO_IRQ (0 << 4)
48#define DESCRIPTOR_IRQ_ERROR (1 << 4)
49#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
50#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
51#define DESCRIPTOR_WAIT (3 << 0)
Kristian Høgsberged568912006-12-19 19:58:35 -050052
53struct descriptor {
54 __le16 req_count;
55 __le16 control;
56 __le32 data_address;
57 __le32 branch_address;
58 __le16 res_count;
59 __le16 transfer_status;
60} __attribute__((aligned(16)));
61
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -050062struct db_descriptor {
63 __le16 first_size;
64 __le16 control;
65 __le16 second_req_count;
66 __le16 first_req_count;
67 __le32 branch_address;
68 __le16 second_res_count;
69 __le16 first_res_count;
70 __le32 reserved0;
71 __le32 first_buffer;
72 __le32 second_buffer;
73 __le32 reserved1;
74} __attribute__((aligned(16)));
75
Kristian Høgsberga77754a2007-05-07 20:33:35 -040076#define CONTROL_SET(regs) (regs)
77#define CONTROL_CLEAR(regs) ((regs) + 4)
78#define COMMAND_PTR(regs) ((regs) + 12)
79#define CONTEXT_MATCH(regs) ((regs) + 16)
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050080
Kristian Høgsberg32b46092007-02-06 14:49:30 -050081struct ar_buffer {
82 struct descriptor descriptor;
83 struct ar_buffer *next;
84 __le32 data[0];
85};
86
Kristian Høgsberged568912006-12-19 19:58:35 -050087struct ar_context {
88 struct fw_ohci *ohci;
Kristian Høgsberg32b46092007-02-06 14:49:30 -050089 struct ar_buffer *current_buffer;
90 struct ar_buffer *last_buffer;
91 void *pointer;
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050092 u32 regs;
Kristian Høgsberged568912006-12-19 19:58:35 -050093 struct tasklet_struct tasklet;
94};
95
Kristian Høgsberg30200732007-02-16 17:34:39 -050096struct context;
97
98typedef int (*descriptor_callback_t)(struct context *ctx,
99 struct descriptor *d,
100 struct descriptor *last);
David Moorefe5ca632008-01-06 17:21:41 -0500101
102/*
103 * A buffer that contains a block of DMA-able coherent memory used for
104 * storing a portion of a DMA descriptor program.
105 */
106struct descriptor_buffer {
107 struct list_head list;
108 dma_addr_t buffer_bus;
109 size_t buffer_size;
110 size_t used;
111 struct descriptor buffer[0];
112};
113
Kristian Høgsberg30200732007-02-16 17:34:39 -0500114struct context {
Stefan Richter373b2ed2007-03-04 14:45:18 +0100115 struct fw_ohci *ohci;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500116 u32 regs;
David Moorefe5ca632008-01-06 17:21:41 -0500117 int total_allocation;
Stefan Richter373b2ed2007-03-04 14:45:18 +0100118
David Moorefe5ca632008-01-06 17:21:41 -0500119 /*
120 * List of page-sized buffers for storing DMA descriptors.
121 * Head of list contains buffers in use and tail of list contains
122 * free buffers.
123 */
124 struct list_head buffer_list;
125
126 /*
127 * Pointer to a buffer inside buffer_list that contains the tail
128 * end of the current DMA program.
129 */
130 struct descriptor_buffer *buffer_tail;
131
132 /*
133 * The descriptor containing the branch address of the first
134 * descriptor that has not yet been filled by the device.
135 */
136 struct descriptor *last;
137
138 /*
139 * The last descriptor in the DMA program. It contains the branch
140 * address that must be updated upon appending a new descriptor.
141 */
142 struct descriptor *prev;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500143
144 descriptor_callback_t callback;
145
Stefan Richter373b2ed2007-03-04 14:45:18 +0100146 struct tasklet_struct tasklet;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500147};
Kristian Høgsberg30200732007-02-16 17:34:39 -0500148
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400149#define IT_HEADER_SY(v) ((v) << 0)
150#define IT_HEADER_TCODE(v) ((v) << 4)
151#define IT_HEADER_CHANNEL(v) ((v) << 8)
152#define IT_HEADER_TAG(v) ((v) << 14)
153#define IT_HEADER_SPEED(v) ((v) << 16)
154#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
Kristian Høgsberged568912006-12-19 19:58:35 -0500155
156struct iso_context {
157 struct fw_iso_context base;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500158 struct context context;
David Moore0642b652007-12-19 03:09:18 -0500159 int excess_bytes;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -0500160 void *header;
161 size_t header_length;
Kristian Høgsberged568912006-12-19 19:58:35 -0500162};
163
164#define CONFIG_ROM_SIZE 1024
165
166struct fw_ohci {
167 struct fw_card card;
168
Kristian Høgsberge364cf42007-02-16 17:34:49 -0500169 u32 version;
Kristian Høgsberged568912006-12-19 19:58:35 -0500170 __iomem char *registers;
171 dma_addr_t self_id_bus;
172 __le32 *self_id_cpu;
173 struct tasklet_struct bus_reset_tasklet;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500174 int node_id;
Kristian Høgsberged568912006-12-19 19:58:35 -0500175 int generation;
176 int request_generation;
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -0500177 u32 bus_seconds;
Kristian Høgsberged568912006-12-19 19:58:35 -0500178
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400179 /*
180 * Spinlock for accessing fw_ohci data. Never call out of
181 * this driver with this lock held.
182 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500183 spinlock_t lock;
184 u32 self_id_buffer[512];
185
186 /* Config rom buffers */
187 __be32 *config_rom;
188 dma_addr_t config_rom_bus;
189 __be32 *next_config_rom;
190 dma_addr_t next_config_rom_bus;
191 u32 next_header;
192
193 struct ar_context ar_request_ctx;
194 struct ar_context ar_response_ctx;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500195 struct context at_request_ctx;
196 struct context at_response_ctx;
Kristian Høgsberged568912006-12-19 19:58:35 -0500197
198 u32 it_context_mask;
199 struct iso_context *it_context_list;
200 u32 ir_context_mask;
201 struct iso_context *ir_context_list;
202};
203
Adrian Bunk95688e92007-01-22 19:17:37 +0100204static inline struct fw_ohci *fw_ohci(struct fw_card *card)
Kristian Høgsberged568912006-12-19 19:58:35 -0500205{
206 return container_of(card, struct fw_ohci, card);
207}
208
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500209#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
210#define IR_CONTEXT_BUFFER_FILL 0x80000000
211#define IR_CONTEXT_ISOCH_HEADER 0x40000000
212#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
213#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
214#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
Kristian Høgsberged568912006-12-19 19:58:35 -0500215
216#define CONTEXT_RUN 0x8000
217#define CONTEXT_WAKE 0x1000
218#define CONTEXT_DEAD 0x0800
219#define CONTEXT_ACTIVE 0x0400
220
221#define OHCI1394_MAX_AT_REQ_RETRIES 0x2
222#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
223#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
224
225#define FW_OHCI_MAJOR 240
226#define OHCI1394_REGISTER_SIZE 0x800
227#define OHCI_LOOP_COUNT 500
228#define OHCI1394_PCI_HCI_Control 0x40
229#define SELF_ID_BUF_SIZE 0x800
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500230#define OHCI_TCODE_PHY_PACKET 0x0e
Kristian Høgsberge364cf42007-02-16 17:34:49 -0500231#define OHCI_VERSION_1_1 0x010010
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500232
Kristian Høgsberged568912006-12-19 19:58:35 -0500233static char ohci_driver_name[] = KBUILD_MODNAME;
234
Adrian Bunk95688e92007-01-22 19:17:37 +0100235static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
Kristian Høgsberged568912006-12-19 19:58:35 -0500236{
237 writel(data, ohci->registers + offset);
238}
239
Adrian Bunk95688e92007-01-22 19:17:37 +0100240static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
Kristian Høgsberged568912006-12-19 19:58:35 -0500241{
242 return readl(ohci->registers + offset);
243}
244
Adrian Bunk95688e92007-01-22 19:17:37 +0100245static inline void flush_writes(const struct fw_ohci *ohci)
Kristian Høgsberged568912006-12-19 19:58:35 -0500246{
247 /* Do a dummy read to flush writes. */
248 reg_read(ohci, OHCI1394_Version);
249}
250
251static int
252ohci_update_phy_reg(struct fw_card *card, int addr,
253 int clear_bits, int set_bits)
254{
255 struct fw_ohci *ohci = fw_ohci(card);
256 u32 val, old;
257
258 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
Stefan Richter362e9012007-07-12 22:24:19 +0200259 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -0500260 msleep(2);
261 val = reg_read(ohci, OHCI1394_PhyControl);
262 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
263 fw_error("failed to set phy reg bits.\n");
264 return -EBUSY;
265 }
266
267 old = OHCI1394_PhyControl_ReadData(val);
268 old = (old & ~clear_bits) | set_bits;
269 reg_write(ohci, OHCI1394_PhyControl,
270 OHCI1394_PhyControl_Write(addr, old));
271
272 return 0;
273}
274
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500275static int ar_context_add_page(struct ar_context *ctx)
Kristian Høgsberged568912006-12-19 19:58:35 -0500276{
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500277 struct device *dev = ctx->ohci->card.device;
278 struct ar_buffer *ab;
279 dma_addr_t ab_bus;
280 size_t offset;
281
282 ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
283 if (ab == NULL)
284 return -ENOMEM;
285
286 ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
287 if (dma_mapping_error(ab_bus)) {
288 free_page((unsigned long) ab);
289 return -ENOMEM;
290 }
291
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400292 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400293 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
294 DESCRIPTOR_STATUS |
295 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500296 offset = offsetof(struct ar_buffer, data);
297 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
298 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
299 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
300 ab->descriptor.branch_address = 0;
301
302 dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
303
Kristian Høgsbergec839e42007-05-22 18:55:48 -0400304 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500305 ctx->last_buffer->next = ab;
306 ctx->last_buffer = ab;
307
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400308 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Kristian Høgsberged568912006-12-19 19:58:35 -0500309 flush_writes(ctx->ohci);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500310
311 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -0500312}
313
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500314static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
Kristian Høgsberged568912006-12-19 19:58:35 -0500315{
Kristian Høgsberged568912006-12-19 19:58:35 -0500316 struct fw_ohci *ohci = ctx->ohci;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500317 struct fw_packet p;
318 u32 status, length, tcode;
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500319
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500320 p.header[0] = le32_to_cpu(buffer[0]);
321 p.header[1] = le32_to_cpu(buffer[1]);
322 p.header[2] = le32_to_cpu(buffer[2]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500323
324 tcode = (p.header[0] >> 4) & 0x0f;
325 switch (tcode) {
326 case TCODE_WRITE_QUADLET_REQUEST:
327 case TCODE_READ_QUADLET_RESPONSE:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500328 p.header[3] = (__force __u32) buffer[3];
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500329 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500330 p.payload_length = 0;
331 break;
332
333 case TCODE_READ_BLOCK_REQUEST :
334 p.header[3] = le32_to_cpu(buffer[3]);
335 p.header_length = 16;
336 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500337 break;
338
339 case TCODE_WRITE_BLOCK_REQUEST:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500340 case TCODE_READ_BLOCK_RESPONSE:
341 case TCODE_LOCK_REQUEST:
342 case TCODE_LOCK_RESPONSE:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500343 p.header[3] = le32_to_cpu(buffer[3]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500344 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500345 p.payload_length = p.header[3] >> 16;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500346 break;
347
348 case TCODE_WRITE_RESPONSE:
349 case TCODE_READ_QUADLET_REQUEST:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500350 case OHCI_TCODE_PHY_PACKET:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500351 p.header_length = 12;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500352 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500353 break;
354 }
355
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500356 p.payload = (void *) buffer + p.header_length;
357
358 /* FIXME: What to do about evt_* errors? */
359 length = (p.header_length + p.payload_length + 3) / 4;
360 status = le32_to_cpu(buffer[length]);
361
362 p.ack = ((status >> 16) & 0x1f) - 16;
363 p.speed = (status >> 21) & 0x7;
364 p.timestamp = status & 0xffff;
365 p.generation = ohci->request_generation;
Kristian Høgsberged568912006-12-19 19:58:35 -0500366
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400367 /*
368 * The OHCI bus reset handler synthesizes a phy packet with
Kristian Høgsberged568912006-12-19 19:58:35 -0500369 * the new generation number when a bus reset happens (see
370 * section 8.4.2.3). This helps us determine when a request
371 * was received and make sure we send the response in the same
372 * generation. We only need this for requests; for responses
373 * we use the unique tlabel for finding the matching
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400374 * request.
375 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500376
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500377 if (p.ack + 16 == 0x09)
Stefan Richter25df2872008-02-23 12:24:17 +0100378 ohci->request_generation = (p.header[2] >> 16) & 0xff;
Kristian Høgsberged568912006-12-19 19:58:35 -0500379 else if (ctx == &ohci->ar_request_ctx)
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500380 fw_core_handle_request(&ohci->card, &p);
Kristian Høgsberged568912006-12-19 19:58:35 -0500381 else
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500382 fw_core_handle_response(&ohci->card, &p);
Kristian Høgsberged568912006-12-19 19:58:35 -0500383
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500384 return buffer + length + 1;
385}
Kristian Høgsberged568912006-12-19 19:58:35 -0500386
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500387static void ar_context_tasklet(unsigned long data)
388{
389 struct ar_context *ctx = (struct ar_context *)data;
390 struct fw_ohci *ohci = ctx->ohci;
391 struct ar_buffer *ab;
392 struct descriptor *d;
393 void *buffer, *end;
Kristian Høgsberged568912006-12-19 19:58:35 -0500394
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500395 ab = ctx->current_buffer;
396 d = &ab->descriptor;
Kristian Høgsberged568912006-12-19 19:58:35 -0500397
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500398 if (d->res_count == 0) {
399 size_t size, rest, offset;
400
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400401 /*
402 * This descriptor is finished and we may have a
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500403 * packet split across this and the next buffer. We
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400404 * reuse the page for reassembling the split packet.
405 */
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500406
407 offset = offsetof(struct ar_buffer, data);
408 dma_unmap_single(ohci->card.device,
Stefan Richter0a9972b2007-06-23 20:28:17 +0200409 le32_to_cpu(ab->descriptor.data_address) - offset,
410 PAGE_SIZE, DMA_BIDIRECTIONAL);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500411
412 buffer = ab;
413 ab = ab->next;
414 d = &ab->descriptor;
415 size = buffer + PAGE_SIZE - ctx->pointer;
416 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
417 memmove(buffer, ctx->pointer, size);
418 memcpy(buffer + size, ab->data, rest);
419 ctx->current_buffer = ab;
420 ctx->pointer = (void *) ab->data + rest;
421 end = buffer + size + rest;
422
423 while (buffer < end)
424 buffer = handle_ar_packet(ctx, buffer);
425
426 free_page((unsigned long)buffer);
427 ar_context_add_page(ctx);
428 } else {
429 buffer = ctx->pointer;
430 ctx->pointer = end =
431 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
432
433 while (buffer < end)
434 buffer = handle_ar_packet(ctx, buffer);
435 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500436}
437
438static int
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500439ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
Kristian Høgsberged568912006-12-19 19:58:35 -0500440{
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500441 struct ar_buffer ab;
Kristian Høgsberged568912006-12-19 19:58:35 -0500442
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500443 ctx->regs = regs;
444 ctx->ohci = ohci;
445 ctx->last_buffer = &ab;
Kristian Høgsberged568912006-12-19 19:58:35 -0500446 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
447
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500448 ar_context_add_page(ctx);
449 ar_context_add_page(ctx);
450 ctx->current_buffer = ab.next;
451 ctx->pointer = ctx->current_buffer->data;
452
Kristian Høgsberg2aef4692007-05-30 19:06:35 -0400453 return 0;
454}
455
456static void ar_context_run(struct ar_context *ctx)
457{
458 struct ar_buffer *ab = ctx->current_buffer;
459 dma_addr_t ab_bus;
460 size_t offset;
461
462 offset = offsetof(struct ar_buffer, data);
Stefan Richter0a9972b2007-06-23 20:28:17 +0200463 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -0400464
465 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400466 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500467 flush_writes(ctx->ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -0500468}
Stefan Richter373b2ed2007-03-04 14:45:18 +0100469
Jarod Wilsona186b4a2007-12-03 13:43:12 -0500470static struct descriptor *
471find_branch_descriptor(struct descriptor *d, int z)
472{
473 int b, key;
474
475 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
476 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
477
478 /* figure out which descriptor the branch address goes in */
479 if (z == 2 && (b == 3 || key == 2))
480 return d;
481 else
482 return d + z - 1;
483}
484
Kristian Høgsberg30200732007-02-16 17:34:39 -0500485static void context_tasklet(unsigned long data)
486{
487 struct context *ctx = (struct context *) data;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500488 struct descriptor *d, *last;
489 u32 address;
490 int z;
David Moorefe5ca632008-01-06 17:21:41 -0500491 struct descriptor_buffer *desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500492
David Moorefe5ca632008-01-06 17:21:41 -0500493 desc = list_entry(ctx->buffer_list.next,
494 struct descriptor_buffer, list);
495 last = ctx->last;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500496 while (last->branch_address != 0) {
David Moorefe5ca632008-01-06 17:21:41 -0500497 struct descriptor_buffer *old_desc = desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500498 address = le32_to_cpu(last->branch_address);
499 z = address & 0xf;
David Moorefe5ca632008-01-06 17:21:41 -0500500 address &= ~0xf;
501
502 /* If the branch address points to a buffer outside of the
503 * current buffer, advance to the next buffer. */
504 if (address < desc->buffer_bus ||
505 address >= desc->buffer_bus + desc->used)
506 desc = list_entry(desc->list.next,
507 struct descriptor_buffer, list);
508 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
Jarod Wilsona186b4a2007-12-03 13:43:12 -0500509 last = find_branch_descriptor(d, z);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500510
511 if (!ctx->callback(ctx, d, last))
512 break;
513
David Moorefe5ca632008-01-06 17:21:41 -0500514 if (old_desc != desc) {
515 /* If we've advanced to the next buffer, move the
516 * previous buffer to the free list. */
517 unsigned long flags;
518 old_desc->used = 0;
519 spin_lock_irqsave(&ctx->ohci->lock, flags);
520 list_move_tail(&old_desc->list, &ctx->buffer_list);
521 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
522 }
523 ctx->last = last;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500524 }
525}
526
David Moorefe5ca632008-01-06 17:21:41 -0500527/*
528 * Allocate a new buffer and add it to the list of free buffers for this
529 * context. Must be called with ohci->lock held.
530 */
531static int
532context_add_buffer(struct context *ctx)
533{
534 struct descriptor_buffer *desc;
535 dma_addr_t bus_addr;
536 int offset;
537
538 /*
539 * 16MB of descriptors should be far more than enough for any DMA
540 * program. This will catch run-away userspace or DoS attacks.
541 */
542 if (ctx->total_allocation >= 16*1024*1024)
543 return -ENOMEM;
544
545 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
546 &bus_addr, GFP_ATOMIC);
547 if (!desc)
548 return -ENOMEM;
549
550 offset = (void *)&desc->buffer - (void *)desc;
551 desc->buffer_size = PAGE_SIZE - offset;
552 desc->buffer_bus = bus_addr + offset;
553 desc->used = 0;
554
555 list_add_tail(&desc->list, &ctx->buffer_list);
556 ctx->total_allocation += PAGE_SIZE;
557
558 return 0;
559}
560
Kristian Høgsberg30200732007-02-16 17:34:39 -0500561static int
562context_init(struct context *ctx, struct fw_ohci *ohci,
David Moorefe5ca632008-01-06 17:21:41 -0500563 u32 regs, descriptor_callback_t callback)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500564{
565 ctx->ohci = ohci;
566 ctx->regs = regs;
David Moorefe5ca632008-01-06 17:21:41 -0500567 ctx->total_allocation = 0;
568
569 INIT_LIST_HEAD(&ctx->buffer_list);
570 if (context_add_buffer(ctx) < 0)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500571 return -ENOMEM;
572
David Moorefe5ca632008-01-06 17:21:41 -0500573 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
574 struct descriptor_buffer, list);
575
Kristian Høgsberg30200732007-02-16 17:34:39 -0500576 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
577 ctx->callback = callback;
578
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400579 /*
580 * We put a dummy descriptor in the buffer that has a NULL
Kristian Høgsberg30200732007-02-16 17:34:39 -0500581 * branch address and looks like it's been sent. That way we
David Moorefe5ca632008-01-06 17:21:41 -0500582 * have a descriptor to append DMA programs to.
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400583 */
David Moorefe5ca632008-01-06 17:21:41 -0500584 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
585 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
586 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
587 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
588 ctx->last = ctx->buffer_tail->buffer;
589 ctx->prev = ctx->buffer_tail->buffer;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500590
591 return 0;
592}
593
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -0500594static void
Kristian Høgsberg30200732007-02-16 17:34:39 -0500595context_release(struct context *ctx)
596{
597 struct fw_card *card = &ctx->ohci->card;
David Moorefe5ca632008-01-06 17:21:41 -0500598 struct descriptor_buffer *desc, *tmp;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500599
David Moorefe5ca632008-01-06 17:21:41 -0500600 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
601 dma_free_coherent(card->device, PAGE_SIZE, desc,
602 desc->buffer_bus -
603 ((void *)&desc->buffer - (void *)desc));
Kristian Høgsberg30200732007-02-16 17:34:39 -0500604}
605
David Moorefe5ca632008-01-06 17:21:41 -0500606/* Must be called with ohci->lock held */
Kristian Høgsberg30200732007-02-16 17:34:39 -0500607static struct descriptor *
608context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
609{
David Moorefe5ca632008-01-06 17:21:41 -0500610 struct descriptor *d = NULL;
611 struct descriptor_buffer *desc = ctx->buffer_tail;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500612
David Moorefe5ca632008-01-06 17:21:41 -0500613 if (z * sizeof(*d) > desc->buffer_size)
614 return NULL;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500615
David Moorefe5ca632008-01-06 17:21:41 -0500616 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
617 /* No room for the descriptor in this buffer, so advance to the
618 * next one. */
619
620 if (desc->list.next == &ctx->buffer_list) {
621 /* If there is no free buffer next in the list,
622 * allocate one. */
623 if (context_add_buffer(ctx) < 0)
624 return NULL;
625 }
626 desc = list_entry(desc->list.next,
627 struct descriptor_buffer, list);
628 ctx->buffer_tail = desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500629 }
630
David Moorefe5ca632008-01-06 17:21:41 -0500631 d = desc->buffer + desc->used / sizeof(*d);
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400632 memset(d, 0, z * sizeof(*d));
David Moorefe5ca632008-01-06 17:21:41 -0500633 *d_bus = desc->buffer_bus + desc->used;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500634
635 return d;
636}
637
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500638static void context_run(struct context *ctx, u32 extra)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500639{
640 struct fw_ohci *ohci = ctx->ohci;
641
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400642 reg_write(ohci, COMMAND_PTR(ctx->regs),
David Moorefe5ca632008-01-06 17:21:41 -0500643 le32_to_cpu(ctx->last->branch_address));
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400644 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
645 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500646 flush_writes(ohci);
647}
648
649static void context_append(struct context *ctx,
650 struct descriptor *d, int z, int extra)
651{
652 dma_addr_t d_bus;
David Moorefe5ca632008-01-06 17:21:41 -0500653 struct descriptor_buffer *desc = ctx->buffer_tail;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500654
David Moorefe5ca632008-01-06 17:21:41 -0500655 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500656
David Moorefe5ca632008-01-06 17:21:41 -0500657 desc->used += (z + extra) * sizeof(*d);
658 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
659 ctx->prev = find_branch_descriptor(d, z);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500660
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400661 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500662 flush_writes(ctx->ohci);
663}
664
665static void context_stop(struct context *ctx)
666{
667 u32 reg;
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500668 int i;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500669
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400670 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500671 flush_writes(ctx->ohci);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500672
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500673 for (i = 0; i < 10; i++) {
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400674 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500675 if ((reg & CONTEXT_ACTIVE) == 0)
676 break;
677
678 fw_notify("context_stop: still active (0x%08x)\n", reg);
Stefan Richterb980f5a2007-07-12 22:25:14 +0200679 mdelay(1);
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500680 }
Kristian Høgsberg30200732007-02-16 17:34:39 -0500681}
Kristian Høgsberged568912006-12-19 19:58:35 -0500682
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500683struct driver_data {
Kristian Høgsberged568912006-12-19 19:58:35 -0500684 struct fw_packet *packet;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500685};
686
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400687/*
688 * This function apppends a packet to the DMA queue for transmission.
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500689 * Must always be called with the ochi->lock held to ensure proper
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400690 * generation handling and locking around packet queue manipulation.
691 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500692static int
693at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
694{
Kristian Høgsberged568912006-12-19 19:58:35 -0500695 struct fw_ohci *ohci = ctx->ohci;
Stefan Richter4b6d51e2007-10-21 11:20:07 +0200696 dma_addr_t d_bus, uninitialized_var(payload_bus);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500697 struct driver_data *driver_data;
698 struct descriptor *d, *last;
699 __le32 *header;
Kristian Høgsberged568912006-12-19 19:58:35 -0500700 int z, tcode;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500701 u32 reg;
Kristian Høgsberged568912006-12-19 19:58:35 -0500702
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500703 d = context_get_descriptors(ctx, 4, &d_bus);
704 if (d == NULL) {
705 packet->ack = RCODE_SEND_ERROR;
706 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -0500707 }
708
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400709 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500710 d[0].res_count = cpu_to_le16(packet->timestamp);
711
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400712 /*
713 * The DMA format for asyncronous link packets is different
Kristian Høgsberged568912006-12-19 19:58:35 -0500714 * from the IEEE1394 layout, so shift the fields around
715 * accordingly. If header_length is 8, it's a PHY packet, to
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400716 * which we need to prepend an extra quadlet.
717 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500718
719 header = (__le32 *) &d[1];
Kristian Høgsberged568912006-12-19 19:58:35 -0500720 if (packet->header_length > 8) {
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500721 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
722 (packet->speed << 16));
723 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
724 (packet->header[0] & 0xffff0000));
725 header[2] = cpu_to_le32(packet->header[2]);
Kristian Høgsberged568912006-12-19 19:58:35 -0500726
727 tcode = (packet->header[0] >> 4) & 0x0f;
728 if (TCODE_IS_BLOCK_PACKET(tcode))
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500729 header[3] = cpu_to_le32(packet->header[3]);
Kristian Høgsberged568912006-12-19 19:58:35 -0500730 else
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500731 header[3] = (__force __le32) packet->header[3];
732
733 d[0].req_count = cpu_to_le16(packet->header_length);
Kristian Høgsberged568912006-12-19 19:58:35 -0500734 } else {
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500735 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
736 (packet->speed << 16));
737 header[1] = cpu_to_le32(packet->header[0]);
738 header[2] = cpu_to_le32(packet->header[1]);
739 d[0].req_count = cpu_to_le16(12);
Kristian Høgsberged568912006-12-19 19:58:35 -0500740 }
741
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500742 driver_data = (struct driver_data *) &d[3];
743 driver_data->packet = packet;
Kristian Høgsberg20d11672007-03-26 19:18:19 -0400744 packet->driver_data = driver_data;
Jarod Wilsona186b4a2007-12-03 13:43:12 -0500745
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500746 if (packet->payload_length > 0) {
747 payload_bus =
748 dma_map_single(ohci->card.device, packet->payload,
749 packet->payload_length, DMA_TO_DEVICE);
750 if (dma_mapping_error(payload_bus)) {
751 packet->ack = RCODE_SEND_ERROR;
752 return -1;
753 }
754
755 d[2].req_count = cpu_to_le16(packet->payload_length);
756 d[2].data_address = cpu_to_le32(payload_bus);
757 last = &d[2];
758 z = 3;
759 } else {
760 last = &d[0];
761 z = 2;
762 }
763
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400764 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
765 DESCRIPTOR_IRQ_ALWAYS |
766 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500767
Kristian Høgsberged568912006-12-19 19:58:35 -0500768 /* FIXME: Document how the locking works. */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500769 if (ohci->generation != packet->generation) {
Stefan Richterab88ca42007-08-29 19:40:28 +0200770 if (packet->payload_length > 0)
771 dma_unmap_single(ohci->card.device, payload_bus,
772 packet->payload_length, DMA_TO_DEVICE);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500773 packet->ack = RCODE_GENERATION;
774 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -0500775 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500776
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500777 context_append(ctx, d, z, 4 - z);
Kristian Høgsberged568912006-12-19 19:58:35 -0500778
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500779 /* If the context isn't already running, start it up. */
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400780 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
Kristian Høgsberg053b3082007-04-10 18:11:17 -0400781 if ((reg & CONTEXT_RUN) == 0)
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500782 context_run(ctx, 0);
Kristian Høgsberged568912006-12-19 19:58:35 -0500783
784 return 0;
785}
786
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500787static int handle_at_packet(struct context *context,
788 struct descriptor *d,
789 struct descriptor *last)
790{
791 struct driver_data *driver_data;
792 struct fw_packet *packet;
793 struct fw_ohci *ohci = context->ohci;
794 dma_addr_t payload_bus;
795 int evt;
796
797 if (last->transfer_status == 0)
798 /* This descriptor isn't done yet, stop iteration. */
799 return 0;
800
801 driver_data = (struct driver_data *) &d[3];
802 packet = driver_data->packet;
803 if (packet == NULL)
804 /* This packet was cancelled, just continue. */
805 return 1;
806
807 payload_bus = le32_to_cpu(last->data_address);
808 if (payload_bus != 0)
809 dma_unmap_single(ohci->card.device, payload_bus,
810 packet->payload_length, DMA_TO_DEVICE);
811
812 evt = le16_to_cpu(last->transfer_status) & 0x1f;
813 packet->timestamp = le16_to_cpu(last->res_count);
814
815 switch (evt) {
816 case OHCI1394_evt_timeout:
817 /* Async response transmit timed out. */
818 packet->ack = RCODE_CANCELLED;
819 break;
820
821 case OHCI1394_evt_flushed:
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400822 /*
823 * The packet was flushed should give same error as
824 * when we try to use a stale generation count.
825 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500826 packet->ack = RCODE_GENERATION;
827 break;
828
829 case OHCI1394_evt_missing_ack:
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400830 /*
831 * Using a valid (current) generation count, but the
832 * node is not on the bus or not sending acks.
833 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500834 packet->ack = RCODE_NO_ACK;
835 break;
836
837 case ACK_COMPLETE + 0x10:
838 case ACK_PENDING + 0x10:
839 case ACK_BUSY_X + 0x10:
840 case ACK_BUSY_A + 0x10:
841 case ACK_BUSY_B + 0x10:
842 case ACK_DATA_ERROR + 0x10:
843 case ACK_TYPE_ERROR + 0x10:
844 packet->ack = evt - 0x10;
845 break;
846
847 default:
848 packet->ack = RCODE_SEND_ERROR;
849 break;
850 }
851
852 packet->callback(packet, &ohci->card, packet->ack);
853
854 return 1;
855}
856
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400857#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
858#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
859#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
860#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
861#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500862
863static void
864handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
865{
866 struct fw_packet response;
867 int tcode, length, i;
868
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400869 tcode = HEADER_GET_TCODE(packet->header[0]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500870 if (TCODE_IS_BLOCK_PACKET(tcode))
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400871 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500872 else
873 length = 4;
874
875 i = csr - CSR_CONFIG_ROM;
876 if (i + length > CONFIG_ROM_SIZE) {
877 fw_fill_response(&response, packet->header,
878 RCODE_ADDRESS_ERROR, NULL, 0);
879 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
880 fw_fill_response(&response, packet->header,
881 RCODE_TYPE_ERROR, NULL, 0);
882 } else {
883 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
884 (void *) ohci->config_rom + i, length);
885 }
886
887 fw_core_handle_response(&ohci->card, &response);
888}
889
890static void
891handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
892{
893 struct fw_packet response;
894 int tcode, length, ext_tcode, sel;
895 __be32 *payload, lock_old;
896 u32 lock_arg, lock_data;
897
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400898 tcode = HEADER_GET_TCODE(packet->header[0]);
899 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500900 payload = packet->payload;
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400901 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500902
903 if (tcode == TCODE_LOCK_REQUEST &&
904 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
905 lock_arg = be32_to_cpu(payload[0]);
906 lock_data = be32_to_cpu(payload[1]);
907 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
908 lock_arg = 0;
909 lock_data = 0;
910 } else {
911 fw_fill_response(&response, packet->header,
912 RCODE_TYPE_ERROR, NULL, 0);
913 goto out;
914 }
915
916 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
917 reg_write(ohci, OHCI1394_CSRData, lock_data);
918 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
919 reg_write(ohci, OHCI1394_CSRControl, sel);
920
921 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
922 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
923 else
924 fw_notify("swap not done yet\n");
925
926 fw_fill_response(&response, packet->header,
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -0400927 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500928 out:
929 fw_core_handle_response(&ohci->card, &response);
930}
931
932static void
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500933handle_local_request(struct context *ctx, struct fw_packet *packet)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500934{
935 u64 offset;
936 u32 csr;
937
Kristian Høgsberg473d28c2007-03-07 12:12:55 -0500938 if (ctx == &ctx->ohci->at_request_ctx) {
939 packet->ack = ACK_PENDING;
940 packet->callback(packet, &ctx->ohci->card, packet->ack);
941 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500942
943 offset =
944 ((unsigned long long)
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400945 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500946 packet->header[2];
947 csr = offset - CSR_REGISTER_BASE;
948
949 /* Handle config rom reads. */
950 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
951 handle_local_rom(ctx->ohci, packet, csr);
952 else switch (csr) {
953 case CSR_BUS_MANAGER_ID:
954 case CSR_BANDWIDTH_AVAILABLE:
955 case CSR_CHANNELS_AVAILABLE_HI:
956 case CSR_CHANNELS_AVAILABLE_LO:
957 handle_local_lock(ctx->ohci, packet, csr);
958 break;
959 default:
960 if (ctx == &ctx->ohci->at_request_ctx)
961 fw_core_handle_request(&ctx->ohci->card, packet);
962 else
963 fw_core_handle_response(&ctx->ohci->card, packet);
964 break;
965 }
Kristian Høgsberg473d28c2007-03-07 12:12:55 -0500966
967 if (ctx == &ctx->ohci->at_response_ctx) {
968 packet->ack = ACK_COMPLETE;
969 packet->callback(packet, &ctx->ohci->card, packet->ack);
970 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500971}
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500972
Kristian Høgsberged568912006-12-19 19:58:35 -0500973static void
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500974at_context_transmit(struct context *ctx, struct fw_packet *packet)
Kristian Høgsberged568912006-12-19 19:58:35 -0500975{
Kristian Høgsberged568912006-12-19 19:58:35 -0500976 unsigned long flags;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500977 int retval;
Kristian Høgsberged568912006-12-19 19:58:35 -0500978
979 spin_lock_irqsave(&ctx->ohci->lock, flags);
980
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400981 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500982 ctx->ohci->generation == packet->generation) {
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500983 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
984 handle_local_request(ctx, packet);
985 return;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500986 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500987
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500988 retval = at_context_queue_packet(ctx, packet);
Kristian Høgsberged568912006-12-19 19:58:35 -0500989 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
990
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500991 if (retval < 0)
992 packet->callback(packet, &ctx->ohci->card, packet->ack);
Jarod Wilsona186b4a2007-12-03 13:43:12 -0500993
Kristian Høgsberged568912006-12-19 19:58:35 -0500994}
995
996static void bus_reset_tasklet(unsigned long data)
997{
998 struct fw_ohci *ohci = (struct fw_ohci *)data;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500999 int self_id_count, i, j, reg;
Kristian Høgsberged568912006-12-19 19:58:35 -05001000 int generation, new_generation;
1001 unsigned long flags;
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001002 void *free_rom = NULL;
1003 dma_addr_t free_rom_bus = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001004
1005 reg = reg_read(ohci, OHCI1394_NodeID);
1006 if (!(reg & OHCI1394_NodeID_idValid)) {
Stefan Richter02ff8f82007-08-30 00:11:40 +02001007 fw_notify("node ID not valid, new bus reset in progress\n");
Kristian Høgsberged568912006-12-19 19:58:35 -05001008 return;
1009 }
Stefan Richter02ff8f82007-08-30 00:11:40 +02001010 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1011 fw_notify("malconfigured bus\n");
1012 return;
1013 }
1014 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1015 OHCI1394_NodeID_nodeNumber);
Kristian Høgsberged568912006-12-19 19:58:35 -05001016
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001017 /*
1018 * The count in the SelfIDCount register is the number of
Kristian Høgsberged568912006-12-19 19:58:35 -05001019 * bytes in the self ID receive buffer. Since we also receive
1020 * the inverted quadlets and a header quadlet, we shift one
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001021 * bit extra to get the actual number of self IDs.
1022 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001023
1024 self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
1025 generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
Stefan Richteree71c2f2007-08-25 14:08:19 +02001026 rmb();
Kristian Høgsberged568912006-12-19 19:58:35 -05001027
1028 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1029 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
1030 fw_error("inconsistent self IDs\n");
1031 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
1032 }
Stefan Richteree71c2f2007-08-25 14:08:19 +02001033 rmb();
Kristian Høgsberged568912006-12-19 19:58:35 -05001034
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001035 /*
1036 * Check the consistency of the self IDs we just read. The
Kristian Høgsberged568912006-12-19 19:58:35 -05001037 * problem we face is that a new bus reset can start while we
1038 * read out the self IDs from the DMA buffer. If this happens,
1039 * the DMA buffer will be overwritten with new self IDs and we
1040 * will read out inconsistent data. The OHCI specification
1041 * (section 11.2) recommends a technique similar to
1042 * linux/seqlock.h, where we remember the generation of the
1043 * self IDs in the buffer before reading them out and compare
1044 * it to the current generation after reading them out. If
1045 * the two generations match we know we have a consistent set
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001046 * of self IDs.
1047 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001048
1049 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1050 if (new_generation != generation) {
1051 fw_notify("recursive bus reset detected, "
1052 "discarding self ids\n");
1053 return;
1054 }
1055
1056 /* FIXME: Document how the locking works. */
1057 spin_lock_irqsave(&ohci->lock, flags);
1058
1059 ohci->generation = generation;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001060 context_stop(&ohci->at_request_ctx);
1061 context_stop(&ohci->at_response_ctx);
Kristian Høgsberged568912006-12-19 19:58:35 -05001062 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1063
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001064 /*
1065 * This next bit is unrelated to the AT context stuff but we
Kristian Høgsberged568912006-12-19 19:58:35 -05001066 * have to do it under the spinlock also. If a new config rom
1067 * was set up before this reset, the old one is now no longer
1068 * in use and we can free it. Update the config rom pointers
1069 * to point to the current config rom and clear the
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001070 * next_config_rom pointer so a new udpate can take place.
1071 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001072
1073 if (ohci->next_config_rom != NULL) {
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001074 if (ohci->next_config_rom != ohci->config_rom) {
1075 free_rom = ohci->config_rom;
1076 free_rom_bus = ohci->config_rom_bus;
1077 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001078 ohci->config_rom = ohci->next_config_rom;
1079 ohci->config_rom_bus = ohci->next_config_rom_bus;
1080 ohci->next_config_rom = NULL;
1081
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001082 /*
1083 * Restore config_rom image and manually update
Kristian Høgsberged568912006-12-19 19:58:35 -05001084 * config_rom registers. Writing the header quadlet
1085 * will indicate that the config rom is ready, so we
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001086 * do that last.
1087 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001088 reg_write(ohci, OHCI1394_BusOptions,
1089 be32_to_cpu(ohci->config_rom[2]));
1090 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1091 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1092 }
1093
1094 spin_unlock_irqrestore(&ohci->lock, flags);
1095
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001096 if (free_rom)
1097 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1098 free_rom, free_rom_bus);
1099
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001100 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
Kristian Høgsberged568912006-12-19 19:58:35 -05001101 self_id_count, ohci->self_id_buffer);
1102}
1103
1104static irqreturn_t irq_handler(int irq, void *data)
1105{
1106 struct fw_ohci *ohci = data;
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05001107 u32 event, iso_event, cycle_time;
Kristian Høgsberged568912006-12-19 19:58:35 -05001108 int i;
1109
1110 event = reg_read(ohci, OHCI1394_IntEventClear);
1111
Stefan Richtera5159582007-06-09 19:31:14 +02001112 if (!event || !~event)
Kristian Høgsberged568912006-12-19 19:58:35 -05001113 return IRQ_NONE;
1114
1115 reg_write(ohci, OHCI1394_IntEventClear, event);
1116
1117 if (event & OHCI1394_selfIDComplete)
1118 tasklet_schedule(&ohci->bus_reset_tasklet);
1119
1120 if (event & OHCI1394_RQPkt)
1121 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1122
1123 if (event & OHCI1394_RSPkt)
1124 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1125
1126 if (event & OHCI1394_reqTxComplete)
1127 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1128
1129 if (event & OHCI1394_respTxComplete)
1130 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1131
Kristian Høgsbergc8894752007-02-16 17:34:36 -05001132 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
Kristian Høgsberged568912006-12-19 19:58:35 -05001133 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1134
1135 while (iso_event) {
1136 i = ffs(iso_event) - 1;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001137 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001138 iso_event &= ~(1 << i);
1139 }
1140
Kristian Høgsbergc8894752007-02-16 17:34:36 -05001141 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
Kristian Høgsberged568912006-12-19 19:58:35 -05001142 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1143
1144 while (iso_event) {
1145 i = ffs(iso_event) - 1;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001146 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001147 iso_event &= ~(1 << i);
1148 }
1149
Stefan Richtere524f6162007-08-20 21:58:30 +02001150 if (unlikely(event & OHCI1394_postedWriteErr))
1151 fw_error("PCI posted write error\n");
1152
Stefan Richterbb9f2202007-12-22 22:14:52 +01001153 if (unlikely(event & OHCI1394_cycleTooLong)) {
1154 if (printk_ratelimit())
1155 fw_notify("isochronous cycle too long\n");
1156 reg_write(ohci, OHCI1394_LinkControlSet,
1157 OHCI1394_LinkControl_cycleMaster);
1158 }
1159
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05001160 if (event & OHCI1394_cycle64Seconds) {
1161 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1162 if ((cycle_time & 0x80000000) == 0)
1163 ohci->bus_seconds++;
1164 }
1165
Kristian Høgsberged568912006-12-19 19:58:35 -05001166 return IRQ_HANDLED;
1167}
1168
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001169static int software_reset(struct fw_ohci *ohci)
1170{
1171 int i;
1172
1173 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1174
1175 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1176 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1177 OHCI1394_HCControl_softReset) == 0)
1178 return 0;
1179 msleep(1);
1180 }
1181
1182 return -EBUSY;
1183}
1184
Kristian Høgsberged568912006-12-19 19:58:35 -05001185static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1186{
1187 struct fw_ohci *ohci = fw_ohci(card);
1188 struct pci_dev *dev = to_pci_dev(card->device);
1189
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001190 if (software_reset(ohci)) {
1191 fw_error("Failed to reset ohci card.\n");
1192 return -EBUSY;
1193 }
1194
1195 /*
1196 * Now enable LPS, which we need in order to start accessing
1197 * most of the registers. In fact, on some cards (ALI M5251),
1198 * accessing registers in the SClk domain without LPS enabled
1199 * will lock up the machine. Wait 50msec to make sure we have
1200 * full link enabled.
1201 */
1202 reg_write(ohci, OHCI1394_HCControlSet,
1203 OHCI1394_HCControl_LPS |
1204 OHCI1394_HCControl_postedWriteEnable);
1205 flush_writes(ohci);
1206 msleep(50);
1207
1208 reg_write(ohci, OHCI1394_HCControlClear,
1209 OHCI1394_HCControl_noByteSwapData);
1210
1211 reg_write(ohci, OHCI1394_LinkControlSet,
1212 OHCI1394_LinkControl_rcvSelfID |
1213 OHCI1394_LinkControl_cycleTimerEnable |
1214 OHCI1394_LinkControl_cycleMaster);
1215
1216 reg_write(ohci, OHCI1394_ATRetries,
1217 OHCI1394_MAX_AT_REQ_RETRIES |
1218 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1219 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1220
1221 ar_context_run(&ohci->ar_request_ctx);
1222 ar_context_run(&ohci->ar_response_ctx);
1223
1224 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1225 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1226 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1227 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1228 reg_write(ohci, OHCI1394_IntMaskSet,
1229 OHCI1394_selfIDComplete |
1230 OHCI1394_RQPkt | OHCI1394_RSPkt |
1231 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1232 OHCI1394_isochRx | OHCI1394_isochTx |
Stefan Richterbb9f2202007-12-22 22:14:52 +01001233 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1234 OHCI1394_cycle64Seconds | OHCI1394_masterIntEnable);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001235
1236 /* Activate link_on bit and contender bit in our self ID packets.*/
1237 if (ohci_update_phy_reg(card, 4, 0,
1238 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1239 return -EIO;
1240
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001241 /*
1242 * When the link is not yet enabled, the atomic config rom
Kristian Høgsberged568912006-12-19 19:58:35 -05001243 * update mechanism described below in ohci_set_config_rom()
1244 * is not active. We have to update ConfigRomHeader and
1245 * BusOptions manually, and the write to ConfigROMmap takes
1246 * effect immediately. We tie this to the enabling of the
1247 * link, so we have a valid config rom before enabling - the
1248 * OHCI requires that ConfigROMhdr and BusOptions have valid
1249 * values before enabling.
1250 *
1251 * However, when the ConfigROMmap is written, some controllers
1252 * always read back quadlets 0 and 2 from the config rom to
1253 * the ConfigRomHeader and BusOptions registers on bus reset.
1254 * They shouldn't do that in this initial case where the link
1255 * isn't enabled. This means we have to use the same
1256 * workaround here, setting the bus header to 0 and then write
1257 * the right values in the bus reset tasklet.
1258 */
1259
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001260 if (config_rom) {
1261 ohci->next_config_rom =
1262 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1263 &ohci->next_config_rom_bus,
1264 GFP_KERNEL);
1265 if (ohci->next_config_rom == NULL)
1266 return -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05001267
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001268 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1269 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1270 } else {
1271 /*
1272 * In the suspend case, config_rom is NULL, which
1273 * means that we just reuse the old config rom.
1274 */
1275 ohci->next_config_rom = ohci->config_rom;
1276 ohci->next_config_rom_bus = ohci->config_rom_bus;
1277 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001278
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001279 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
Kristian Høgsberged568912006-12-19 19:58:35 -05001280 ohci->next_config_rom[0] = 0;
1281 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001282 reg_write(ohci, OHCI1394_BusOptions,
1283 be32_to_cpu(ohci->next_config_rom[2]));
Kristian Høgsberged568912006-12-19 19:58:35 -05001284 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1285
1286 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1287
1288 if (request_irq(dev->irq, irq_handler,
Thomas Gleixner65efffa2007-03-05 18:19:51 -08001289 IRQF_SHARED, ohci_driver_name, ohci)) {
Kristian Høgsberged568912006-12-19 19:58:35 -05001290 fw_error("Failed to allocate shared interrupt %d.\n",
1291 dev->irq);
1292 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1293 ohci->config_rom, ohci->config_rom_bus);
1294 return -EIO;
1295 }
1296
1297 reg_write(ohci, OHCI1394_HCControlSet,
1298 OHCI1394_HCControl_linkEnable |
1299 OHCI1394_HCControl_BIBimageValid);
1300 flush_writes(ohci);
1301
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001302 /*
1303 * We are ready to go, initiate bus reset to finish the
1304 * initialization.
1305 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001306
1307 fw_core_initiate_bus_reset(&ohci->card, 1);
1308
1309 return 0;
1310}
1311
1312static int
1313ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1314{
1315 struct fw_ohci *ohci;
1316 unsigned long flags;
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001317 int retval = -EBUSY;
Kristian Høgsberged568912006-12-19 19:58:35 -05001318 __be32 *next_config_rom;
1319 dma_addr_t next_config_rom_bus;
1320
1321 ohci = fw_ohci(card);
1322
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001323 /*
1324 * When the OHCI controller is enabled, the config rom update
Kristian Høgsberged568912006-12-19 19:58:35 -05001325 * mechanism is a bit tricky, but easy enough to use. See
1326 * section 5.5.6 in the OHCI specification.
1327 *
1328 * The OHCI controller caches the new config rom address in a
1329 * shadow register (ConfigROMmapNext) and needs a bus reset
1330 * for the changes to take place. When the bus reset is
1331 * detected, the controller loads the new values for the
1332 * ConfigRomHeader and BusOptions registers from the specified
1333 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1334 * shadow register. All automatically and atomically.
1335 *
1336 * Now, there's a twist to this story. The automatic load of
1337 * ConfigRomHeader and BusOptions doesn't honor the
1338 * noByteSwapData bit, so with a be32 config rom, the
1339 * controller will load be32 values in to these registers
1340 * during the atomic update, even on litte endian
1341 * architectures. The workaround we use is to put a 0 in the
1342 * header quadlet; 0 is endian agnostic and means that the
1343 * config rom isn't ready yet. In the bus reset tasklet we
1344 * then set up the real values for the two registers.
1345 *
1346 * We use ohci->lock to avoid racing with the code that sets
1347 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1348 */
1349
1350 next_config_rom =
1351 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1352 &next_config_rom_bus, GFP_KERNEL);
1353 if (next_config_rom == NULL)
1354 return -ENOMEM;
1355
1356 spin_lock_irqsave(&ohci->lock, flags);
1357
1358 if (ohci->next_config_rom == NULL) {
1359 ohci->next_config_rom = next_config_rom;
1360 ohci->next_config_rom_bus = next_config_rom_bus;
1361
1362 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1363 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1364 length * 4);
1365
1366 ohci->next_header = config_rom[0];
1367 ohci->next_config_rom[0] = 0;
1368
1369 reg_write(ohci, OHCI1394_ConfigROMmap,
1370 ohci->next_config_rom_bus);
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001371 retval = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001372 }
1373
1374 spin_unlock_irqrestore(&ohci->lock, flags);
1375
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001376 /*
1377 * Now initiate a bus reset to have the changes take
Kristian Høgsberged568912006-12-19 19:58:35 -05001378 * effect. We clean up the old config rom memory and DMA
1379 * mappings in the bus reset tasklet, since the OHCI
1380 * controller could need to access it before the bus reset
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001381 * takes effect.
1382 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001383 if (retval == 0)
1384 fw_core_initiate_bus_reset(&ohci->card, 1);
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001385 else
1386 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1387 next_config_rom, next_config_rom_bus);
Kristian Høgsberged568912006-12-19 19:58:35 -05001388
1389 return retval;
1390}
1391
1392static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1393{
1394 struct fw_ohci *ohci = fw_ohci(card);
1395
1396 at_context_transmit(&ohci->at_request_ctx, packet);
1397}
1398
1399static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1400{
1401 struct fw_ohci *ohci = fw_ohci(card);
1402
1403 at_context_transmit(&ohci->at_response_ctx, packet);
1404}
1405
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001406static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1407{
1408 struct fw_ohci *ohci = fw_ohci(card);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001409 struct context *ctx = &ohci->at_request_ctx;
1410 struct driver_data *driver_data = packet->driver_data;
1411 int retval = -ENOENT;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001412
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001413 tasklet_disable(&ctx->tasklet);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001414
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001415 if (packet->ack != 0)
1416 goto out;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001417
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001418 driver_data->packet = NULL;
1419 packet->ack = RCODE_CANCELLED;
1420 packet->callback(packet, &ohci->card, packet->ack);
1421 retval = 0;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001422
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001423 out:
1424 tasklet_enable(&ctx->tasklet);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001425
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001426 return retval;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001427}
1428
Kristian Høgsberged568912006-12-19 19:58:35 -05001429static int
1430ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1431{
1432 struct fw_ohci *ohci = fw_ohci(card);
1433 unsigned long flags;
Stefan Richter907293d2007-01-23 21:11:43 +01001434 int n, retval = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001435
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001436 /*
1437 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1438 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1439 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001440
1441 spin_lock_irqsave(&ohci->lock, flags);
1442
1443 if (ohci->generation != generation) {
1444 retval = -ESTALE;
1445 goto out;
1446 }
1447
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001448 /*
1449 * Note, if the node ID contains a non-local bus ID, physical DMA is
1450 * enabled for _all_ nodes on remote buses.
1451 */
Stefan Richter907293d2007-01-23 21:11:43 +01001452
1453 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1454 if (n < 32)
1455 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1456 else
1457 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1458
Kristian Høgsberged568912006-12-19 19:58:35 -05001459 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05001460 out:
Stefan Richter6cad95f2007-01-21 20:46:45 +01001461 spin_unlock_irqrestore(&ohci->lock, flags);
Kristian Høgsberged568912006-12-19 19:58:35 -05001462 return retval;
1463}
Stefan Richter373b2ed2007-03-04 14:45:18 +01001464
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05001465static u64
1466ohci_get_bus_time(struct fw_card *card)
1467{
1468 struct fw_ohci *ohci = fw_ohci(card);
1469 u32 cycle_time;
1470 u64 bus_time;
1471
1472 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1473 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1474
1475 return bus_time;
1476}
1477
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001478static int handle_ir_dualbuffer_packet(struct context *context,
1479 struct descriptor *d,
1480 struct descriptor *last)
Kristian Høgsberged568912006-12-19 19:58:35 -05001481{
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001482 struct iso_context *ctx =
1483 container_of(context, struct iso_context, context);
1484 struct db_descriptor *db = (struct db_descriptor *) d;
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001485 __le32 *ir_header;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001486 size_t header_length;
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001487 void *p, *end;
1488 int i;
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001489
Stefan Richterefbf3902008-02-23 12:24:57 +01001490 if (db->first_res_count != 0 && db->second_res_count != 0) {
David Moore0642b652007-12-19 03:09:18 -05001491 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1492 /* This descriptor isn't done yet, stop iteration. */
1493 return 0;
1494 }
1495 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1496 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001497
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001498 header_length = le16_to_cpu(db->first_req_count) -
1499 le16_to_cpu(db->first_res_count);
1500
1501 i = ctx->header_length;
1502 p = db + 1;
1503 end = p + header_length;
1504 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001505 /*
1506 * The iso header is byteswapped to little endian by
Kristian Høgsberg15536222007-04-10 18:11:16 -04001507 * the controller, but the remaining header quadlets
1508 * are big endian. We want to present all the headers
1509 * as big endian, so we have to swap the first
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001510 * quadlet.
1511 */
Kristian Høgsberg15536222007-04-10 18:11:16 -04001512 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1513 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001514 i += ctx->base.header_size;
David Moore0642b652007-12-19 03:09:18 -05001515 ctx->excess_bytes +=
Stefan Richterefbf3902008-02-23 12:24:57 +01001516 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001517 p += ctx->base.header_size + 4;
1518 }
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001519 ctx->header_length = i;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001520
David Moore0642b652007-12-19 03:09:18 -05001521 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1522 le16_to_cpu(db->second_res_count);
1523
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001524 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001525 ir_header = (__le32 *) (db + 1);
1526 ctx->base.callback(&ctx->base,
1527 le32_to_cpu(ir_header[0]) & 0xffff,
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001528 ctx->header_length, ctx->header,
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001529 ctx->base.callback_data);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001530 ctx->header_length = 0;
1531 }
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001532
1533 return 1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001534}
1535
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001536static int handle_ir_packet_per_buffer(struct context *context,
1537 struct descriptor *d,
1538 struct descriptor *last)
1539{
1540 struct iso_context *ctx =
1541 container_of(context, struct iso_context, context);
David Moorebcee8932007-12-19 15:26:38 -05001542 struct descriptor *pd;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001543 __le32 *ir_header;
David Moorebcee8932007-12-19 15:26:38 -05001544 void *p;
1545 int i;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001546
David Moorebcee8932007-12-19 15:26:38 -05001547 for (pd = d; pd <= last; pd++) {
1548 if (pd->transfer_status)
1549 break;
1550 }
1551 if (pd > last)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001552 /* Descriptor(s) not done yet, stop iteration */
1553 return 0;
1554
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001555 i = ctx->header_length;
David Moorebcee8932007-12-19 15:26:38 -05001556 p = last + 1;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001557
David Moorebcee8932007-12-19 15:26:38 -05001558 if (ctx->base.header_size > 0 &&
1559 i + ctx->base.header_size <= PAGE_SIZE) {
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001560 /*
1561 * The iso header is byteswapped to little endian by
1562 * the controller, but the remaining header quadlets
1563 * are big endian. We want to present all the headers
1564 * as big endian, so we have to swap the first quadlet.
1565 */
1566 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1567 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
David Moorebcee8932007-12-19 15:26:38 -05001568 ctx->header_length += ctx->base.header_size;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001569 }
1570
David Moorebcee8932007-12-19 15:26:38 -05001571 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1572 ir_header = (__le32 *) p;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001573 ctx->base.callback(&ctx->base,
1574 le32_to_cpu(ir_header[0]) & 0xffff,
1575 ctx->header_length, ctx->header,
1576 ctx->base.callback_data);
1577 ctx->header_length = 0;
1578 }
1579
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001580 return 1;
1581}
1582
Kristian Høgsberg30200732007-02-16 17:34:39 -05001583static int handle_it_packet(struct context *context,
1584 struct descriptor *d,
1585 struct descriptor *last)
Kristian Høgsberged568912006-12-19 19:58:35 -05001586{
Kristian Høgsberg30200732007-02-16 17:34:39 -05001587 struct iso_context *ctx =
1588 container_of(context, struct iso_context, context);
Stefan Richter373b2ed2007-03-04 14:45:18 +01001589
Kristian Høgsberg30200732007-02-16 17:34:39 -05001590 if (last->transfer_status == 0)
1591 /* This descriptor isn't done yet, stop iteration. */
1592 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001593
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001594 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001595 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1596 0, NULL, ctx->base.callback_data);
Kristian Høgsberged568912006-12-19 19:58:35 -05001597
Kristian Høgsberg30200732007-02-16 17:34:39 -05001598 return 1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001599}
1600
Kristian Høgsberg30200732007-02-16 17:34:39 -05001601static struct fw_iso_context *
Kristian Høgsbergeb0306e2007-03-14 17:34:54 -04001602ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
Kristian Høgsberged568912006-12-19 19:58:35 -05001603{
1604 struct fw_ohci *ohci = fw_ohci(card);
1605 struct iso_context *ctx, *list;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001606 descriptor_callback_t callback;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001607 u32 *mask, regs;
Kristian Høgsberged568912006-12-19 19:58:35 -05001608 unsigned long flags;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001609 int index, retval = -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05001610
1611 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1612 mask = &ohci->it_context_mask;
1613 list = ohci->it_context_list;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001614 callback = handle_it_packet;
Kristian Høgsberged568912006-12-19 19:58:35 -05001615 } else {
Stefan Richter373b2ed2007-03-04 14:45:18 +01001616 mask = &ohci->ir_context_mask;
1617 list = ohci->ir_context_list;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001618 if (ohci->version >= OHCI_VERSION_1_1)
1619 callback = handle_ir_dualbuffer_packet;
1620 else
1621 callback = handle_ir_packet_per_buffer;
Kristian Høgsberged568912006-12-19 19:58:35 -05001622 }
1623
1624 spin_lock_irqsave(&ohci->lock, flags);
1625 index = ffs(*mask) - 1;
1626 if (index >= 0)
1627 *mask &= ~(1 << index);
1628 spin_unlock_irqrestore(&ohci->lock, flags);
1629
1630 if (index < 0)
1631 return ERR_PTR(-EBUSY);
1632
Stefan Richter373b2ed2007-03-04 14:45:18 +01001633 if (type == FW_ISO_CONTEXT_TRANSMIT)
1634 regs = OHCI1394_IsoXmitContextBase(index);
1635 else
1636 regs = OHCI1394_IsoRcvContextBase(index);
1637
Kristian Høgsberged568912006-12-19 19:58:35 -05001638 ctx = &list[index];
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001639 memset(ctx, 0, sizeof(*ctx));
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001640 ctx->header_length = 0;
1641 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1642 if (ctx->header == NULL)
1643 goto out;
1644
David Moorefe5ca632008-01-06 17:21:41 -05001645 retval = context_init(&ctx->context, ohci, regs, callback);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001646 if (retval < 0)
1647 goto out_with_header;
Kristian Høgsberged568912006-12-19 19:58:35 -05001648
1649 return &ctx->base;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001650
1651 out_with_header:
1652 free_page((unsigned long)ctx->header);
1653 out:
1654 spin_lock_irqsave(&ohci->lock, flags);
1655 *mask |= 1 << index;
1656 spin_unlock_irqrestore(&ohci->lock, flags);
1657
1658 return ERR_PTR(retval);
Kristian Høgsberged568912006-12-19 19:58:35 -05001659}
1660
Kristian Høgsbergeb0306e2007-03-14 17:34:54 -04001661static int ohci_start_iso(struct fw_iso_context *base,
1662 s32 cycle, u32 sync, u32 tags)
Kristian Høgsberged568912006-12-19 19:58:35 -05001663{
Stefan Richter373b2ed2007-03-04 14:45:18 +01001664 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001665 struct fw_ohci *ohci = ctx->context.ohci;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001666 u32 control, match;
Kristian Høgsberged568912006-12-19 19:58:35 -05001667 int index;
1668
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001669 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1670 index = ctx - ohci->it_context_list;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001671 match = 0;
1672 if (cycle >= 0)
1673 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001674 (cycle & 0x7fff) << 16;
Kristian Høgsberg21efb3c2007-02-16 17:34:50 -05001675
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001676 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1677 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001678 context_run(&ctx->context, match);
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001679 } else {
1680 index = ctx - ohci->ir_context_list;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001681 control = IR_CONTEXT_ISOCH_HEADER;
1682 if (ohci->version >= OHCI_VERSION_1_1)
1683 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001684 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1685 if (cycle >= 0) {
1686 match |= (cycle & 0x07fff) << 12;
1687 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1688 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001689
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001690 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1691 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001692 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04001693 context_run(&ctx->context, control);
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001694 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001695
1696 return 0;
1697}
1698
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001699static int ohci_stop_iso(struct fw_iso_context *base)
1700{
1701 struct fw_ohci *ohci = fw_ohci(base->card);
Stefan Richter373b2ed2007-03-04 14:45:18 +01001702 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001703 int index;
1704
1705 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1706 index = ctx - ohci->it_context_list;
1707 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1708 } else {
1709 index = ctx - ohci->ir_context_list;
1710 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1711 }
1712 flush_writes(ohci);
1713 context_stop(&ctx->context);
1714
1715 return 0;
1716}
1717
Kristian Høgsberged568912006-12-19 19:58:35 -05001718static void ohci_free_iso_context(struct fw_iso_context *base)
1719{
1720 struct fw_ohci *ohci = fw_ohci(base->card);
Stefan Richter373b2ed2007-03-04 14:45:18 +01001721 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberged568912006-12-19 19:58:35 -05001722 unsigned long flags;
1723 int index;
1724
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001725 ohci_stop_iso(base);
1726 context_release(&ctx->context);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001727 free_page((unsigned long)ctx->header);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001728
Kristian Høgsberged568912006-12-19 19:58:35 -05001729 spin_lock_irqsave(&ohci->lock, flags);
1730
1731 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1732 index = ctx - ohci->it_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05001733 ohci->it_context_mask |= 1 << index;
1734 } else {
1735 index = ctx - ohci->ir_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05001736 ohci->ir_context_mask |= 1 << index;
1737 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001738
1739 spin_unlock_irqrestore(&ohci->lock, flags);
1740}
1741
1742static int
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001743ohci_queue_iso_transmit(struct fw_iso_context *base,
1744 struct fw_iso_packet *packet,
1745 struct fw_iso_buffer *buffer,
1746 unsigned long payload)
Kristian Høgsberged568912006-12-19 19:58:35 -05001747{
Stefan Richter373b2ed2007-03-04 14:45:18 +01001748 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001749 struct descriptor *d, *last, *pd;
Kristian Høgsberged568912006-12-19 19:58:35 -05001750 struct fw_iso_packet *p;
1751 __le32 *header;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001752 dma_addr_t d_bus, page_bus;
Kristian Høgsberged568912006-12-19 19:58:35 -05001753 u32 z, header_z, payload_z, irq;
1754 u32 payload_index, payload_end_index, next_page_index;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001755 int page, end_page, i, length, offset;
Kristian Høgsberged568912006-12-19 19:58:35 -05001756
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001757 /*
1758 * FIXME: Cycle lost behavior should be configurable: lose
1759 * packet, retransmit or terminate..
1760 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001761
1762 p = packet;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001763 payload_index = payload;
Kristian Høgsberged568912006-12-19 19:58:35 -05001764
1765 if (p->skip)
1766 z = 1;
1767 else
1768 z = 2;
1769 if (p->header_length > 0)
1770 z++;
1771
1772 /* Determine the first page the payload isn't contained in. */
1773 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1774 if (p->payload_length > 0)
1775 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1776 else
1777 payload_z = 0;
1778
1779 z += payload_z;
1780
1781 /* Get header size in number of descriptors. */
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001782 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
Kristian Høgsberged568912006-12-19 19:58:35 -05001783
Kristian Høgsberg30200732007-02-16 17:34:39 -05001784 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1785 if (d == NULL)
1786 return -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05001787
1788 if (!p->skip) {
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001789 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
Kristian Høgsberged568912006-12-19 19:58:35 -05001790 d[0].req_count = cpu_to_le16(8);
1791
1792 header = (__le32 *) &d[1];
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001793 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1794 IT_HEADER_TAG(p->tag) |
1795 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1796 IT_HEADER_CHANNEL(ctx->base.channel) |
1797 IT_HEADER_SPEED(ctx->base.speed));
Kristian Høgsberged568912006-12-19 19:58:35 -05001798 header[1] =
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001799 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
Kristian Høgsberged568912006-12-19 19:58:35 -05001800 p->payload_length));
1801 }
1802
1803 if (p->header_length > 0) {
1804 d[2].req_count = cpu_to_le16(p->header_length);
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001805 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
Kristian Høgsberged568912006-12-19 19:58:35 -05001806 memcpy(&d[z], p->header, p->header_length);
1807 }
1808
1809 pd = d + z - payload_z;
1810 payload_end_index = payload_index + p->payload_length;
1811 for (i = 0; i < payload_z; i++) {
1812 page = payload_index >> PAGE_SHIFT;
1813 offset = payload_index & ~PAGE_MASK;
1814 next_page_index = (page + 1) << PAGE_SHIFT;
1815 length =
1816 min(next_page_index, payload_end_index) - payload_index;
1817 pd[i].req_count = cpu_to_le16(length);
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001818
1819 page_bus = page_private(buffer->pages[page]);
1820 pd[i].data_address = cpu_to_le32(page_bus + offset);
Kristian Høgsberged568912006-12-19 19:58:35 -05001821
1822 payload_index += length;
1823 }
1824
Kristian Høgsberged568912006-12-19 19:58:35 -05001825 if (p->interrupt)
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001826 irq = DESCRIPTOR_IRQ_ALWAYS;
Kristian Høgsberged568912006-12-19 19:58:35 -05001827 else
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001828 irq = DESCRIPTOR_NO_IRQ;
Kristian Høgsberged568912006-12-19 19:58:35 -05001829
Kristian Høgsberg30200732007-02-16 17:34:39 -05001830 last = z == 2 ? d : d + z - 1;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001831 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1832 DESCRIPTOR_STATUS |
1833 DESCRIPTOR_BRANCH_ALWAYS |
Kristian Høgsbergcbb59da2007-02-16 17:34:35 -05001834 irq);
Kristian Høgsberged568912006-12-19 19:58:35 -05001835
Kristian Høgsberg30200732007-02-16 17:34:39 -05001836 context_append(&ctx->context, d, z, header_z);
Kristian Høgsberged568912006-12-19 19:58:35 -05001837
1838 return 0;
1839}
Stefan Richter373b2ed2007-03-04 14:45:18 +01001840
Kristian Høgsberg98b6cbe2007-02-16 17:34:51 -05001841static int
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001842ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1843 struct fw_iso_packet *packet,
1844 struct fw_iso_buffer *buffer,
1845 unsigned long payload)
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001846{
1847 struct iso_context *ctx = container_of(base, struct iso_context, base);
1848 struct db_descriptor *db = NULL;
1849 struct descriptor *d;
1850 struct fw_iso_packet *p;
1851 dma_addr_t d_bus, page_bus;
1852 u32 z, header_z, length, rest;
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001853 int page, offset, packet_count, header_size;
Stefan Richter373b2ed2007-03-04 14:45:18 +01001854
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001855 /*
1856 * FIXME: Cycle lost behavior should be configurable: lose
1857 * packet, retransmit or terminate..
1858 */
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001859
1860 p = packet;
1861 z = 2;
1862
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001863 /*
1864 * The OHCI controller puts the status word in the header
1865 * buffer too, so we need 4 extra bytes per packet.
1866 */
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001867 packet_count = p->header_length / ctx->base.header_size;
1868 header_size = packet_count * (ctx->base.header_size + 4);
1869
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001870 /* Get header size in number of descriptors. */
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001871 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001872 page = payload >> PAGE_SHIFT;
1873 offset = payload & ~PAGE_MASK;
1874 rest = p->payload_length;
1875
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001876 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1877 while (rest > 0) {
1878 d = context_get_descriptors(&ctx->context,
1879 z + header_z, &d_bus);
1880 if (d == NULL)
1881 return -ENOMEM;
1882
1883 db = (struct db_descriptor *) d;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001884 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1885 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsbergc70dc782007-03-14 17:34:53 -04001886 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
David Moore0642b652007-12-19 03:09:18 -05001887 if (p->skip && rest == p->payload_length) {
1888 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
1889 db->first_req_count = db->first_size;
1890 } else {
1891 db->first_req_count = cpu_to_le16(header_size);
1892 }
Kristian Høgsberg1e1d1962007-02-16 17:34:45 -05001893 db->first_res_count = db->first_req_count;
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001894 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
Stefan Richter373b2ed2007-03-04 14:45:18 +01001895
David Moore0642b652007-12-19 03:09:18 -05001896 if (p->skip && rest == p->payload_length)
1897 length = 4;
1898 else if (offset + rest < PAGE_SIZE)
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001899 length = rest;
1900 else
1901 length = PAGE_SIZE - offset;
1902
Kristian Høgsberg1e1d1962007-02-16 17:34:45 -05001903 db->second_req_count = cpu_to_le16(length);
1904 db->second_res_count = db->second_req_count;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001905 page_bus = page_private(buffer->pages[page]);
1906 db->second_buffer = cpu_to_le32(page_bus + offset);
1907
Kristian Høgsbergcb2d2cd2007-02-16 17:34:47 -05001908 if (p->interrupt && length == rest)
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001909 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
Kristian Høgsbergcb2d2cd2007-02-16 17:34:47 -05001910
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001911 context_append(&ctx->context, d, z, header_z);
1912 offset = (offset + length) & ~PAGE_MASK;
1913 rest -= length;
David Moore0642b652007-12-19 03:09:18 -05001914 if (offset == 0)
1915 page++;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001916 }
1917
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001918 return 0;
1919}
Kristian Høgsberg21efb3c2007-02-16 17:34:50 -05001920
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05001921static int
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001922ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
1923 struct fw_iso_packet *packet,
1924 struct fw_iso_buffer *buffer,
1925 unsigned long payload)
1926{
1927 struct iso_context *ctx = container_of(base, struct iso_context, base);
1928 struct descriptor *d = NULL, *pd = NULL;
David Moorebcee8932007-12-19 15:26:38 -05001929 struct fw_iso_packet *p = packet;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001930 dma_addr_t d_bus, page_bus;
1931 u32 z, header_z, rest;
David Moorebcee8932007-12-19 15:26:38 -05001932 int i, j, length;
1933 int page, offset, packet_count, header_size, payload_per_buffer;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001934
1935 /*
1936 * The OHCI controller puts the status word in the
1937 * buffer too, so we need 4 extra bytes per packet.
1938 */
1939 packet_count = p->header_length / ctx->base.header_size;
David Moorebcee8932007-12-19 15:26:38 -05001940 header_size = ctx->base.header_size + 4;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001941
1942 /* Get header size in number of descriptors. */
1943 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1944 page = payload >> PAGE_SHIFT;
1945 offset = payload & ~PAGE_MASK;
David Moorebcee8932007-12-19 15:26:38 -05001946 payload_per_buffer = p->payload_length / packet_count;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001947
1948 for (i = 0; i < packet_count; i++) {
1949 /* d points to the header descriptor */
David Moorebcee8932007-12-19 15:26:38 -05001950 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001951 d = context_get_descriptors(&ctx->context,
David Moorebcee8932007-12-19 15:26:38 -05001952 z + header_z, &d_bus);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001953 if (d == NULL)
1954 return -ENOMEM;
1955
David Moorebcee8932007-12-19 15:26:38 -05001956 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
1957 DESCRIPTOR_INPUT_MORE);
1958 if (p->skip && i == 0)
1959 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001960 d->req_count = cpu_to_le16(header_size);
1961 d->res_count = d->req_count;
David Moorebcee8932007-12-19 15:26:38 -05001962 d->transfer_status = 0;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001963 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
1964
David Moorebcee8932007-12-19 15:26:38 -05001965 rest = payload_per_buffer;
1966 for (j = 1; j < z; j++) {
1967 pd = d + j;
1968 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
1969 DESCRIPTOR_INPUT_MORE);
1970
1971 if (offset + rest < PAGE_SIZE)
1972 length = rest;
1973 else
1974 length = PAGE_SIZE - offset;
1975 pd->req_count = cpu_to_le16(length);
1976 pd->res_count = pd->req_count;
1977 pd->transfer_status = 0;
1978
1979 page_bus = page_private(buffer->pages[page]);
1980 pd->data_address = cpu_to_le32(page_bus + offset);
1981
1982 offset = (offset + length) & ~PAGE_MASK;
1983 rest -= length;
1984 if (offset == 0)
1985 page++;
1986 }
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001987 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
1988 DESCRIPTOR_INPUT_LAST |
1989 DESCRIPTOR_BRANCH_ALWAYS);
David Moorebcee8932007-12-19 15:26:38 -05001990 if (p->interrupt && i == packet_count - 1)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001991 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1992
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001993 context_append(&ctx->context, d, z, header_z);
1994 }
1995
1996 return 0;
1997}
1998
1999static int
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002000ohci_queue_iso(struct fw_iso_context *base,
2001 struct fw_iso_packet *packet,
2002 struct fw_iso_buffer *buffer,
2003 unsigned long payload)
2004{
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002005 struct iso_context *ctx = container_of(base, struct iso_context, base);
David Moorefe5ca632008-01-06 17:21:41 -05002006 unsigned long flags;
2007 int retval;
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002008
David Moorefe5ca632008-01-06 17:21:41 -05002009 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002010 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
David Moorefe5ca632008-01-06 17:21:41 -05002011 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002012 else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
David Moorefe5ca632008-01-06 17:21:41 -05002013 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
Kristian Høgsbergd2746dc2007-02-16 17:34:46 -05002014 buffer, payload);
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002015 else
David Moorefe5ca632008-01-06 17:21:41 -05002016 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002017 buffer,
2018 payload);
David Moorefe5ca632008-01-06 17:21:41 -05002019 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2020
2021 return retval;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002022}
2023
Stefan Richter21ebcd12007-01-14 15:29:07 +01002024static const struct fw_card_driver ohci_driver = {
Kristian Høgsberged568912006-12-19 19:58:35 -05002025 .name = ohci_driver_name,
2026 .enable = ohci_enable,
2027 .update_phy_reg = ohci_update_phy_reg,
2028 .set_config_rom = ohci_set_config_rom,
2029 .send_request = ohci_send_request,
2030 .send_response = ohci_send_response,
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002031 .cancel_packet = ohci_cancel_packet,
Kristian Høgsberged568912006-12-19 19:58:35 -05002032 .enable_phys_dma = ohci_enable_phys_dma,
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002033 .get_bus_time = ohci_get_bus_time,
Kristian Høgsberged568912006-12-19 19:58:35 -05002034
2035 .allocate_iso_context = ohci_allocate_iso_context,
2036 .free_iso_context = ohci_free_iso_context,
2037 .queue_iso = ohci_queue_iso,
Kristian Høgsberg69cdb722007-02-16 17:34:41 -05002038 .start_iso = ohci_start_iso,
Kristian Høgsbergb8295662007-02-16 17:34:42 -05002039 .stop_iso = ohci_stop_iso,
Kristian Høgsberged568912006-12-19 19:58:35 -05002040};
2041
Kristian Høgsberged568912006-12-19 19:58:35 -05002042static int __devinit
2043pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2044{
2045 struct fw_ohci *ohci;
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002046 u32 bus_options, max_receive, link_speed;
Kristian Høgsberged568912006-12-19 19:58:35 -05002047 u64 guid;
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002048 int err;
Kristian Høgsberged568912006-12-19 19:58:35 -05002049 size_t size;
2050
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04002051 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
Kristian Høgsberged568912006-12-19 19:58:35 -05002052 if (ohci == NULL) {
2053 fw_error("Could not malloc fw_ohci data.\n");
2054 return -ENOMEM;
2055 }
2056
2057 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2058
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002059 err = pci_enable_device(dev);
2060 if (err) {
Kristian Høgsberged568912006-12-19 19:58:35 -05002061 fw_error("Failed to enable OHCI hardware.\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002062 goto fail_put_card;
Kristian Høgsberged568912006-12-19 19:58:35 -05002063 }
2064
2065 pci_set_master(dev);
2066 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2067 pci_set_drvdata(dev, ohci);
2068
2069 spin_lock_init(&ohci->lock);
2070
2071 tasklet_init(&ohci->bus_reset_tasklet,
2072 bus_reset_tasklet, (unsigned long)ohci);
2073
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002074 err = pci_request_region(dev, 0, ohci_driver_name);
2075 if (err) {
Kristian Høgsberged568912006-12-19 19:58:35 -05002076 fw_error("MMIO resource unavailable\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002077 goto fail_disable;
Kristian Høgsberged568912006-12-19 19:58:35 -05002078 }
2079
2080 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2081 if (ohci->registers == NULL) {
2082 fw_error("Failed to remap registers\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002083 err = -ENXIO;
2084 goto fail_iomem;
Kristian Høgsberged568912006-12-19 19:58:35 -05002085 }
2086
Kristian Høgsberged568912006-12-19 19:58:35 -05002087 ar_context_init(&ohci->ar_request_ctx, ohci,
2088 OHCI1394_AsReqRcvContextControlSet);
2089
2090 ar_context_init(&ohci->ar_response_ctx, ohci,
2091 OHCI1394_AsRspRcvContextControlSet);
2092
David Moorefe5ca632008-01-06 17:21:41 -05002093 context_init(&ohci->at_request_ctx, ohci,
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002094 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
Kristian Høgsberged568912006-12-19 19:58:35 -05002095
David Moorefe5ca632008-01-06 17:21:41 -05002096 context_init(&ohci->at_response_ctx, ohci,
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002097 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
Kristian Høgsberged568912006-12-19 19:58:35 -05002098
Kristian Høgsberged568912006-12-19 19:58:35 -05002099 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2100 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2101 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2102 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2103 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2104
2105 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2106 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2107 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2108 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2109 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2110
2111 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2112 fw_error("Out of memory for it/ir contexts.\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002113 err = -ENOMEM;
2114 goto fail_registers;
Kristian Høgsberged568912006-12-19 19:58:35 -05002115 }
2116
2117 /* self-id dma buffer allocation */
2118 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2119 SELF_ID_BUF_SIZE,
2120 &ohci->self_id_bus,
2121 GFP_KERNEL);
2122 if (ohci->self_id_cpu == NULL) {
2123 fw_error("Out of memory for self ID buffer.\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002124 err = -ENOMEM;
2125 goto fail_registers;
Kristian Høgsberged568912006-12-19 19:58:35 -05002126 }
2127
Kristian Høgsberged568912006-12-19 19:58:35 -05002128 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2129 max_receive = (bus_options >> 12) & 0xf;
2130 link_speed = bus_options & 0x7;
2131 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2132 reg_read(ohci, OHCI1394_GUIDLo);
2133
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002134 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2135 if (err < 0)
2136 goto fail_self_id;
Kristian Høgsberged568912006-12-19 19:58:35 -05002137
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002138 ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
Kristian Høgsberg500be722007-02-16 17:34:43 -05002139 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
Kristian Høgsberge364cf42007-02-16 17:34:49 -05002140 dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
Kristian Høgsberged568912006-12-19 19:58:35 -05002141 return 0;
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002142
2143 fail_self_id:
2144 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2145 ohci->self_id_cpu, ohci->self_id_bus);
2146 fail_registers:
2147 kfree(ohci->it_context_list);
2148 kfree(ohci->ir_context_list);
2149 pci_iounmap(dev, ohci->registers);
2150 fail_iomem:
2151 pci_release_region(dev, 0);
2152 fail_disable:
2153 pci_disable_device(dev);
2154 fail_put_card:
2155 fw_card_put(&ohci->card);
2156
2157 return err;
Kristian Høgsberged568912006-12-19 19:58:35 -05002158}
2159
2160static void pci_remove(struct pci_dev *dev)
2161{
2162 struct fw_ohci *ohci;
2163
2164 ohci = pci_get_drvdata(dev);
Kristian Høgsberge254a4b2007-03-07 12:12:38 -05002165 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2166 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05002167 fw_core_remove_card(&ohci->card);
2168
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002169 /*
2170 * FIXME: Fail all pending packets here, now that the upper
2171 * layers can't queue any more.
2172 */
Kristian Høgsberged568912006-12-19 19:58:35 -05002173
2174 software_reset(ohci);
2175 free_irq(dev->irq, ohci);
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04002176 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2177 ohci->self_id_cpu, ohci->self_id_bus);
2178 kfree(ohci->it_context_list);
2179 kfree(ohci->ir_context_list);
2180 pci_iounmap(dev, ohci->registers);
2181 pci_release_region(dev, 0);
2182 pci_disable_device(dev);
2183 fw_card_put(&ohci->card);
Kristian Høgsberged568912006-12-19 19:58:35 -05002184
2185 fw_notify("Removed fw-ohci device.\n");
2186}
2187
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002188#ifdef CONFIG_PM
2189static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
2190{
2191 struct fw_ohci *ohci = pci_get_drvdata(pdev);
2192 int err;
2193
2194 software_reset(ohci);
2195 free_irq(pdev->irq, ohci);
2196 err = pci_save_state(pdev);
2197 if (err) {
Stefan Richter8a8cea22007-06-09 19:26:22 +02002198 fw_error("pci_save_state failed\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002199 return err;
2200 }
2201 err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
Stefan Richter55111422007-09-06 09:50:30 +02002202 if (err)
2203 fw_error("pci_set_power_state failed with %d\n", err);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002204
2205 return 0;
2206}
2207
2208static int pci_resume(struct pci_dev *pdev)
2209{
2210 struct fw_ohci *ohci = pci_get_drvdata(pdev);
2211 int err;
2212
2213 pci_set_power_state(pdev, PCI_D0);
2214 pci_restore_state(pdev);
2215 err = pci_enable_device(pdev);
2216 if (err) {
Stefan Richter8a8cea22007-06-09 19:26:22 +02002217 fw_error("pci_enable_device failed\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002218 return err;
2219 }
2220
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04002221 return ohci_enable(&ohci->card, NULL, 0);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002222}
2223#endif
2224
Kristian Høgsberged568912006-12-19 19:58:35 -05002225static struct pci_device_id pci_table[] = {
2226 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2227 { }
2228};
2229
2230MODULE_DEVICE_TABLE(pci, pci_table);
2231
2232static struct pci_driver fw_ohci_pci_driver = {
2233 .name = ohci_driver_name,
2234 .id_table = pci_table,
2235 .probe = pci_probe,
2236 .remove = pci_remove,
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002237#ifdef CONFIG_PM
2238 .resume = pci_resume,
2239 .suspend = pci_suspend,
2240#endif
Kristian Høgsberged568912006-12-19 19:58:35 -05002241};
2242
2243MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2244MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2245MODULE_LICENSE("GPL");
2246
Olaf Hering1e4c7b02007-05-05 23:17:13 +02002247/* Provide a module alias so root-on-sbp2 initrds don't break. */
2248#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2249MODULE_ALIAS("ohci1394");
2250#endif
2251
Kristian Høgsberged568912006-12-19 19:58:35 -05002252static int __init fw_ohci_init(void)
2253{
2254 return pci_register_driver(&fw_ohci_pci_driver);
2255}
2256
2257static void __exit fw_ohci_cleanup(void)
2258{
2259 pci_unregister_driver(&fw_ohci_pci_driver);
2260}
2261
2262module_init(fw_ohci_init);
2263module_exit(fw_ohci_cleanup);