LABBE Corentin | 6298e94 | 2015-07-17 16:39:41 +0200 | [diff] [blame] | 1 | /* |
| 2 | * sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC |
| 3 | * |
| 4 | * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com> |
| 5 | * |
| 6 | * This file add support for MD5 and SHA1. |
| 7 | * |
| 8 | * You could find the datasheet in Documentation/arm/sunxi/README |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | #include "sun4i-ss.h" |
| 16 | #include <linux/scatterlist.h> |
| 17 | |
| 18 | /* This is a totally arbitrary value */ |
| 19 | #define SS_TIMEOUT 100 |
| 20 | |
| 21 | int sun4i_hash_crainit(struct crypto_tfm *tfm) |
| 22 | { |
| 23 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), |
| 24 | sizeof(struct sun4i_req_ctx)); |
| 25 | return 0; |
| 26 | } |
| 27 | |
| 28 | /* sun4i_hash_init: initialize request context */ |
| 29 | int sun4i_hash_init(struct ahash_request *areq) |
| 30 | { |
| 31 | struct sun4i_req_ctx *op = ahash_request_ctx(areq); |
| 32 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); |
| 33 | struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); |
| 34 | struct sun4i_ss_alg_template *algt; |
| 35 | struct sun4i_ss_ctx *ss; |
| 36 | |
| 37 | memset(op, 0, sizeof(struct sun4i_req_ctx)); |
| 38 | |
| 39 | algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash); |
| 40 | ss = algt->ss; |
| 41 | op->ss = algt->ss; |
| 42 | op->mode = algt->mode; |
| 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | int sun4i_hash_export_md5(struct ahash_request *areq, void *out) |
| 48 | { |
| 49 | struct sun4i_req_ctx *op = ahash_request_ctx(areq); |
| 50 | struct md5_state *octx = out; |
| 51 | int i; |
| 52 | |
| 53 | octx->byte_count = op->byte_count + op->len; |
| 54 | |
| 55 | memcpy(octx->block, op->buf, op->len); |
| 56 | |
| 57 | if (op->byte_count > 0) { |
| 58 | for (i = 0; i < 4; i++) |
| 59 | octx->hash[i] = op->hash[i]; |
| 60 | } else { |
| 61 | octx->hash[0] = SHA1_H0; |
| 62 | octx->hash[1] = SHA1_H1; |
| 63 | octx->hash[2] = SHA1_H2; |
| 64 | octx->hash[3] = SHA1_H3; |
| 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | int sun4i_hash_import_md5(struct ahash_request *areq, const void *in) |
| 71 | { |
| 72 | struct sun4i_req_ctx *op = ahash_request_ctx(areq); |
| 73 | const struct md5_state *ictx = in; |
| 74 | int i; |
| 75 | |
| 76 | sun4i_hash_init(areq); |
| 77 | |
| 78 | op->byte_count = ictx->byte_count & ~0x3F; |
| 79 | op->len = ictx->byte_count & 0x3F; |
| 80 | |
| 81 | memcpy(op->buf, ictx->block, op->len); |
| 82 | |
| 83 | for (i = 0; i < 4; i++) |
| 84 | op->hash[i] = ictx->hash[i]; |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | int sun4i_hash_export_sha1(struct ahash_request *areq, void *out) |
| 90 | { |
| 91 | struct sun4i_req_ctx *op = ahash_request_ctx(areq); |
| 92 | struct sha1_state *octx = out; |
| 93 | int i; |
| 94 | |
| 95 | octx->count = op->byte_count + op->len; |
| 96 | |
| 97 | memcpy(octx->buffer, op->buf, op->len); |
| 98 | |
| 99 | if (op->byte_count > 0) { |
| 100 | for (i = 0; i < 5; i++) |
| 101 | octx->state[i] = op->hash[i]; |
| 102 | } else { |
| 103 | octx->state[0] = SHA1_H0; |
| 104 | octx->state[1] = SHA1_H1; |
| 105 | octx->state[2] = SHA1_H2; |
| 106 | octx->state[3] = SHA1_H3; |
| 107 | octx->state[4] = SHA1_H4; |
| 108 | } |
| 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in) |
| 114 | { |
| 115 | struct sun4i_req_ctx *op = ahash_request_ctx(areq); |
| 116 | const struct sha1_state *ictx = in; |
| 117 | int i; |
| 118 | |
| 119 | sun4i_hash_init(areq); |
| 120 | |
| 121 | op->byte_count = ictx->count & ~0x3F; |
| 122 | op->len = ictx->count & 0x3F; |
| 123 | |
| 124 | memcpy(op->buf, ictx->buffer, op->len); |
| 125 | |
| 126 | for (i = 0; i < 5; i++) |
| 127 | op->hash[i] = ictx->state[i]; |
| 128 | |
| 129 | return 0; |
| 130 | } |
| 131 | |
| 132 | /* |
| 133 | * sun4i_hash_update: update hash engine |
| 134 | * |
| 135 | * Could be used for both SHA1 and MD5 |
| 136 | * Write data by step of 32bits and put then in the SS. |
| 137 | * |
| 138 | * Since we cannot leave partial data and hash state in the engine, |
| 139 | * we need to get the hash state at the end of this function. |
| 140 | * We can get the hash state every 64 bytes |
| 141 | * |
| 142 | * So the first work is to get the number of bytes to write to SS modulo 64 |
| 143 | * The extra bytes will go to a temporary buffer op->buf storing op->len bytes |
| 144 | * |
| 145 | * So at the begin of update() |
| 146 | * if op->len + areq->nbytes < 64 |
| 147 | * => all data will be written to wait buffer (op->buf) and end=0 |
| 148 | * if not, write all data from op->buf to the device and position end to |
| 149 | * complete to 64bytes |
| 150 | * |
| 151 | * example 1: |
| 152 | * update1 60o => op->len=60 |
| 153 | * update2 60o => need one more word to have 64 bytes |
| 154 | * end=4 |
| 155 | * so write all data from op->buf and one word of SGs |
| 156 | * write remaining data in op->buf |
| 157 | * final state op->len=56 |
| 158 | */ |
| 159 | int sun4i_hash_update(struct ahash_request *areq) |
| 160 | { |
| 161 | u32 v, ivmode = 0; |
| 162 | unsigned int i = 0; |
| 163 | /* |
| 164 | * i is the total bytes read from SGs, to be compared to areq->nbytes |
| 165 | * i is important because we cannot rely on SG length since the sum of |
| 166 | * SG->length could be greater than areq->nbytes |
| 167 | */ |
| 168 | |
| 169 | struct sun4i_req_ctx *op = ahash_request_ctx(areq); |
| 170 | struct sun4i_ss_ctx *ss = op->ss; |
| 171 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); |
| 172 | unsigned int in_i = 0; /* advancement in the current SG */ |
| 173 | unsigned int end; |
| 174 | /* |
| 175 | * end is the position when we need to stop writing to the device, |
| 176 | * to be compared to i |
| 177 | */ |
| 178 | int in_r, err = 0; |
| 179 | unsigned int todo; |
| 180 | u32 spaces, rx_cnt = SS_RX_DEFAULT; |
| 181 | size_t copied = 0; |
| 182 | struct sg_mapping_iter mi; |
| 183 | |
| 184 | dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x wl=%u h0=%0x", |
| 185 | __func__, crypto_tfm_alg_name(areq->base.tfm), |
| 186 | op->byte_count, areq->nbytes, op->mode, |
| 187 | op->len, op->hash[0]); |
| 188 | |
| 189 | if (areq->nbytes == 0) |
| 190 | return 0; |
| 191 | |
| 192 | /* protect against overflow */ |
| 193 | if (areq->nbytes > UINT_MAX - op->len) { |
| 194 | dev_err(ss->dev, "Cannot process too large request\n"); |
| 195 | return -EINVAL; |
| 196 | } |
| 197 | |
| 198 | if (op->len + areq->nbytes < 64) { |
| 199 | /* linearize data to op->buf */ |
| 200 | copied = sg_pcopy_to_buffer(areq->src, sg_nents(areq->src), |
| 201 | op->buf + op->len, areq->nbytes, 0); |
| 202 | op->len += copied; |
| 203 | return 0; |
| 204 | } |
| 205 | |
| 206 | end = ((areq->nbytes + op->len) / 64) * 64 - op->len; |
| 207 | |
| 208 | if (end > areq->nbytes || areq->nbytes - end > 63) { |
| 209 | dev_err(ss->dev, "ERROR: Bound error %u %u\n", |
| 210 | end, areq->nbytes); |
| 211 | return -EINVAL; |
| 212 | } |
| 213 | |
| 214 | spin_lock_bh(&ss->slock); |
| 215 | |
| 216 | /* |
| 217 | * if some data have been processed before, |
| 218 | * we need to restore the partial hash state |
| 219 | */ |
| 220 | if (op->byte_count > 0) { |
| 221 | ivmode = SS_IV_ARBITRARY; |
| 222 | for (i = 0; i < 5; i++) |
| 223 | writel(op->hash[i], ss->base + SS_IV0 + i * 4); |
| 224 | } |
| 225 | /* Enable the device */ |
| 226 | writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL); |
| 227 | |
| 228 | i = 0; |
| 229 | sg_miter_start(&mi, areq->src, sg_nents(areq->src), |
| 230 | SG_MITER_FROM_SG | SG_MITER_ATOMIC); |
| 231 | sg_miter_next(&mi); |
| 232 | in_i = 0; |
| 233 | |
| 234 | do { |
| 235 | /* |
| 236 | * we need to linearize in two case: |
| 237 | * - the buffer is already used |
| 238 | * - the SG does not have enough byte remaining ( < 4) |
| 239 | */ |
| 240 | if (op->len > 0 || (mi.length - in_i) < 4) { |
| 241 | /* |
| 242 | * if we have entered here we have two reason to stop |
| 243 | * - the buffer is full |
| 244 | * - reach the end |
| 245 | */ |
| 246 | while (op->len < 64 && i < end) { |
| 247 | /* how many bytes we can read from current SG */ |
| 248 | in_r = min3(mi.length - in_i, end - i, |
| 249 | 64 - op->len); |
| 250 | memcpy(op->buf + op->len, mi.addr + in_i, in_r); |
| 251 | op->len += in_r; |
| 252 | i += in_r; |
| 253 | in_i += in_r; |
| 254 | if (in_i == mi.length) { |
| 255 | sg_miter_next(&mi); |
| 256 | in_i = 0; |
| 257 | } |
| 258 | } |
| 259 | if (op->len > 3 && (op->len % 4) == 0) { |
| 260 | /* write buf to the device */ |
| 261 | writesl(ss->base + SS_RXFIFO, op->buf, |
| 262 | op->len / 4); |
| 263 | op->byte_count += op->len; |
| 264 | op->len = 0; |
| 265 | } |
| 266 | } |
| 267 | if (mi.length - in_i > 3 && i < end) { |
| 268 | /* how many bytes we can read from current SG */ |
| 269 | in_r = min3(mi.length - in_i, areq->nbytes - i, |
| 270 | ((mi.length - in_i) / 4) * 4); |
| 271 | /* how many bytes we can write in the device*/ |
| 272 | todo = min3((u32)(end - i) / 4, rx_cnt, (u32)in_r / 4); |
| 273 | writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo); |
| 274 | op->byte_count += todo * 4; |
| 275 | i += todo * 4; |
| 276 | in_i += todo * 4; |
| 277 | rx_cnt -= todo; |
| 278 | if (rx_cnt == 0) { |
| 279 | spaces = readl(ss->base + SS_FCSR); |
| 280 | rx_cnt = SS_RXFIFO_SPACES(spaces); |
| 281 | } |
| 282 | if (in_i == mi.length) { |
| 283 | sg_miter_next(&mi); |
| 284 | in_i = 0; |
| 285 | } |
| 286 | } |
| 287 | } while (i < end); |
| 288 | /* final linear */ |
| 289 | if ((areq->nbytes - i) < 64) { |
| 290 | while (i < areq->nbytes && in_i < mi.length && op->len < 64) { |
| 291 | /* how many bytes we can read from current SG */ |
| 292 | in_r = min3(mi.length - in_i, areq->nbytes - i, |
| 293 | 64 - op->len); |
| 294 | memcpy(op->buf + op->len, mi.addr + in_i, in_r); |
| 295 | op->len += in_r; |
| 296 | i += in_r; |
| 297 | in_i += in_r; |
| 298 | if (in_i == mi.length) { |
| 299 | sg_miter_next(&mi); |
| 300 | in_i = 0; |
| 301 | } |
| 302 | } |
| 303 | } |
| 304 | |
| 305 | sg_miter_stop(&mi); |
| 306 | |
| 307 | writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL); |
| 308 | i = 0; |
| 309 | do { |
| 310 | v = readl(ss->base + SS_CTL); |
| 311 | i++; |
| 312 | } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0); |
| 313 | if (i >= SS_TIMEOUT) { |
| 314 | dev_err_ratelimited(ss->dev, |
| 315 | "ERROR: hash end timeout %d>%d ctl=%x len=%u\n", |
| 316 | i, SS_TIMEOUT, v, areq->nbytes); |
| 317 | err = -EIO; |
| 318 | goto release_ss; |
| 319 | } |
| 320 | |
| 321 | /* get the partial hash only if something was written */ |
| 322 | for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) |
| 323 | op->hash[i] = readl(ss->base + SS_MD0 + i * 4); |
| 324 | |
| 325 | release_ss: |
| 326 | writel(0, ss->base + SS_CTL); |
| 327 | spin_unlock_bh(&ss->slock); |
| 328 | return err; |
| 329 | } |
| 330 | |
| 331 | /* |
| 332 | * sun4i_hash_final: finalize hashing operation |
| 333 | * |
| 334 | * If we have some remaining bytes, we write them. |
| 335 | * Then ask the SS for finalizing the hashing operation |
| 336 | * |
| 337 | * I do not check RX FIFO size in this function since the size is 32 |
| 338 | * after each enabling and this function neither write more than 32 words. |
| 339 | */ |
| 340 | int sun4i_hash_final(struct ahash_request *areq) |
| 341 | { |
| 342 | u32 v, ivmode = 0; |
| 343 | unsigned int i; |
| 344 | unsigned int j = 0; |
| 345 | int zeros, err = 0; |
| 346 | unsigned int index, padlen; |
| 347 | __be64 bits; |
| 348 | struct sun4i_req_ctx *op = ahash_request_ctx(areq); |
| 349 | struct sun4i_ss_ctx *ss = op->ss; |
| 350 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); |
| 351 | u32 bf[32]; |
| 352 | u32 wb = 0; |
| 353 | unsigned int nwait, nbw = 0; |
| 354 | |
| 355 | dev_dbg(ss->dev, "%s: byte=%llu len=%u mode=%x wl=%u h=%x", |
| 356 | __func__, op->byte_count, areq->nbytes, op->mode, |
| 357 | op->len, op->hash[0]); |
| 358 | |
| 359 | spin_lock_bh(&ss->slock); |
| 360 | |
| 361 | /* |
| 362 | * if we have already written something, |
| 363 | * restore the partial hash state |
| 364 | */ |
| 365 | if (op->byte_count > 0) { |
| 366 | ivmode = SS_IV_ARBITRARY; |
| 367 | for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) |
| 368 | writel(op->hash[i], ss->base + SS_IV0 + i * 4); |
| 369 | } |
| 370 | writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL); |
| 371 | |
| 372 | /* write the remaining words of the wait buffer */ |
| 373 | if (op->len > 0) { |
| 374 | nwait = op->len / 4; |
| 375 | if (nwait > 0) { |
| 376 | writesl(ss->base + SS_RXFIFO, op->buf, nwait); |
| 377 | op->byte_count += 4 * nwait; |
| 378 | } |
| 379 | nbw = op->len - 4 * nwait; |
| 380 | wb = *(u32 *)(op->buf + nwait * 4); |
| 381 | wb &= (0xFFFFFFFF >> (4 - nbw) * 8); |
| 382 | } |
| 383 | |
| 384 | /* write the remaining bytes of the nbw buffer */ |
| 385 | if (nbw > 0) { |
| 386 | wb |= ((1 << 7) << (nbw * 8)); |
| 387 | bf[j++] = wb; |
| 388 | } else { |
| 389 | bf[j++] = 1 << 7; |
| 390 | } |
| 391 | |
| 392 | /* |
| 393 | * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1) |
| 394 | * I take the operations from other MD5/SHA1 implementations |
| 395 | */ |
| 396 | |
| 397 | /* we have already send 4 more byte of which nbw data */ |
| 398 | if (op->mode == SS_OP_MD5) { |
| 399 | index = (op->byte_count + 4) & 0x3f; |
| 400 | op->byte_count += nbw; |
| 401 | if (index > 56) |
| 402 | zeros = (120 - index) / 4; |
| 403 | else |
| 404 | zeros = (56 - index) / 4; |
| 405 | } else { |
| 406 | op->byte_count += nbw; |
| 407 | index = op->byte_count & 0x3f; |
| 408 | padlen = (index < 56) ? (56 - index) : ((64 + 56) - index); |
| 409 | zeros = (padlen - 1) / 4; |
| 410 | } |
| 411 | |
| 412 | memset(bf + j, 0, 4 * zeros); |
| 413 | j += zeros; |
| 414 | |
| 415 | /* write the length of data */ |
| 416 | if (op->mode == SS_OP_SHA1) { |
| 417 | bits = cpu_to_be64(op->byte_count << 3); |
| 418 | bf[j++] = bits & 0xffffffff; |
| 419 | bf[j++] = (bits >> 32) & 0xffffffff; |
| 420 | } else { |
| 421 | bf[j++] = (op->byte_count << 3) & 0xffffffff; |
| 422 | bf[j++] = (op->byte_count >> 29) & 0xffffffff; |
| 423 | } |
| 424 | writesl(ss->base + SS_RXFIFO, bf, j); |
| 425 | |
| 426 | /* Tell the SS to stop the hashing */ |
| 427 | writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL); |
| 428 | |
| 429 | /* |
| 430 | * Wait for SS to finish the hash. |
| 431 | * The timeout could happen only in case of bad overcloking |
| 432 | * or driver bug. |
| 433 | */ |
| 434 | i = 0; |
| 435 | do { |
| 436 | v = readl(ss->base + SS_CTL); |
| 437 | i++; |
| 438 | } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0); |
| 439 | if (i >= SS_TIMEOUT) { |
| 440 | dev_err_ratelimited(ss->dev, |
| 441 | "ERROR: hash end timeout %d>%d ctl=%x len=%u\n", |
| 442 | i, SS_TIMEOUT, v, areq->nbytes); |
| 443 | err = -EIO; |
| 444 | goto release_ss; |
| 445 | } |
| 446 | |
| 447 | /* Get the hash from the device */ |
| 448 | if (op->mode == SS_OP_SHA1) { |
| 449 | for (i = 0; i < 5; i++) { |
| 450 | v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4)); |
| 451 | memcpy(areq->result + i * 4, &v, 4); |
| 452 | } |
| 453 | } else { |
| 454 | for (i = 0; i < 4; i++) { |
| 455 | v = readl(ss->base + SS_MD0 + i * 4); |
| 456 | memcpy(areq->result + i * 4, &v, 4); |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | release_ss: |
| 461 | writel(0, ss->base + SS_CTL); |
| 462 | spin_unlock_bh(&ss->slock); |
| 463 | return err; |
| 464 | } |
| 465 | |
| 466 | /* sun4i_hash_finup: finalize hashing operation after an update */ |
| 467 | int sun4i_hash_finup(struct ahash_request *areq) |
| 468 | { |
| 469 | int err; |
| 470 | |
| 471 | err = sun4i_hash_update(areq); |
| 472 | if (err != 0) |
| 473 | return err; |
| 474 | |
| 475 | return sun4i_hash_final(areq); |
| 476 | } |
| 477 | |
| 478 | /* combo of init/update/final functions */ |
| 479 | int sun4i_hash_digest(struct ahash_request *areq) |
| 480 | { |
| 481 | int err; |
| 482 | |
| 483 | err = sun4i_hash_init(areq); |
| 484 | if (err != 0) |
| 485 | return err; |
| 486 | |
| 487 | err = sun4i_hash_update(areq); |
| 488 | if (err != 0) |
| 489 | return err; |
| 490 | |
| 491 | return sun4i_hash_final(areq); |
| 492 | } |