Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 1 | /* |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 2 | * Xilinx SPI controller driver (master mode only) |
| 3 | * |
| 4 | * Author: MontaVista Software, Inc. |
| 5 | * source@mvista.com |
| 6 | * |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 7 | * Copyright (c) 2010 Secret Lab Technologies, Ltd. |
| 8 | * Copyright (c) 2009 Intel Corporation |
| 9 | * 2002-2007 (c) MontaVista Software, Inc. |
| 10 | |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <linux/module.h> |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 17 | #include <linux/interrupt.h> |
Grant Likely | eae6cb3 | 2010-10-14 09:32:53 -0600 | [diff] [blame] | 18 | #include <linux/of.h> |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 19 | #include <linux/platform_device.h> |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 20 | #include <linux/spi/spi.h> |
| 21 | #include <linux/spi/spi_bitbang.h> |
Richard Röjfors | d5af91a | 2009-11-13 12:28:39 +0100 | [diff] [blame] | 22 | #include <linux/spi/xilinx_spi.h> |
Grant Likely | eae6cb3 | 2010-10-14 09:32:53 -0600 | [diff] [blame] | 23 | #include <linux/io.h> |
Richard Röjfors | d5af91a | 2009-11-13 12:28:39 +0100 | [diff] [blame] | 24 | |
David Brownell | fc3ba95 | 2007-08-30 23:56:24 -0700 | [diff] [blame] | 25 | #define XILINX_SPI_NAME "xilinx_spi" |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 26 | |
| 27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) |
| 28 | * Product Specification", DS464 |
| 29 | */ |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 30 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 31 | |
Michal Simek | 082339b | 2013-06-04 16:02:36 +0200 | [diff] [blame] | 32 | #define XSPI_CR_LOOP 0x01 |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 33 | #define XSPI_CR_ENABLE 0x02 |
| 34 | #define XSPI_CR_MASTER_MODE 0x04 |
| 35 | #define XSPI_CR_CPOL 0x08 |
| 36 | #define XSPI_CR_CPHA 0x10 |
Ricardo Ribalda Delgado | bca690d | 2015-01-23 17:08:33 +0100 | [diff] [blame] | 37 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ |
Ricardo Ribalda Delgado | 0240f94 | 2015-01-23 17:08:34 +0100 | [diff] [blame] | 38 | XSPI_CR_LSB_FIRST | XSPI_CR_LOOP) |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 39 | #define XSPI_CR_TXFIFO_RESET 0x20 |
| 40 | #define XSPI_CR_RXFIFO_RESET 0x40 |
| 41 | #define XSPI_CR_MANUAL_SSELECT 0x80 |
| 42 | #define XSPI_CR_TRANS_INHIBIT 0x100 |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 43 | #define XSPI_CR_LSB_FIRST 0x200 |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 44 | |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 45 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 46 | |
| 47 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ |
| 48 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ |
| 49 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ |
| 50 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ |
| 51 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ |
| 52 | |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 53 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
| 54 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 55 | |
| 56 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ |
| 57 | |
| 58 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 |
| 59 | * IPIF registers are 32 bit |
| 60 | */ |
| 61 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ |
| 62 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 |
| 63 | |
| 64 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ |
| 65 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ |
| 66 | |
| 67 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ |
| 68 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while |
| 69 | * disabled */ |
| 70 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ |
| 71 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ |
| 72 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ |
| 73 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 74 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 75 | |
| 76 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ |
| 77 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ |
| 78 | |
| 79 | struct xilinx_spi { |
| 80 | /* bitbang has to be first */ |
| 81 | struct spi_bitbang bitbang; |
| 82 | struct completion done; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 83 | void __iomem *regs; /* virt. address of the control registers */ |
| 84 | |
Dan Carpenter | 9ca1273 | 2013-07-17 18:34:48 +0300 | [diff] [blame] | 85 | int irq; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 86 | |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 87 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
| 88 | const u8 *tx_ptr; /* pointer in the Rx buffer */ |
Ricardo Ribalda Delgado | 17aaaa8 | 2015-01-28 13:23:50 +0100 | [diff] [blame] | 89 | u8 bytes_per_word; |
Ricardo Ribalda Delgado | 4c9a761 | 2015-01-28 13:23:40 +0100 | [diff] [blame] | 90 | int buffer_size; /* buffer size in words */ |
Ricardo Ribalda Delgado | f9c6ef6 | 2015-01-28 13:23:46 +0100 | [diff] [blame] | 91 | u32 cs_inactive; /* Level of the CS pins when inactive*/ |
Jingoo Han | 6ff8672 | 2014-02-26 10:24:47 +0900 | [diff] [blame] | 92 | unsigned int (*read_fn)(void __iomem *); |
| 93 | void (*write_fn)(u32, void __iomem *); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 94 | }; |
| 95 | |
Ricardo Ribalda Delgado | 24ba5e5 | 2015-01-28 13:23:47 +0100 | [diff] [blame] | 96 | static void xilinx_spi_tx(struct xilinx_spi *xspi) |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 97 | { |
Ricardo Ribalda Delgado | c309294 | 2015-01-28 13:23:48 +0100 | [diff] [blame] | 98 | if (!xspi->tx_ptr) { |
| 99 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); |
| 100 | return; |
| 101 | } |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 102 | xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); |
Ricardo Ribalda Delgado | 17aaaa8 | 2015-01-28 13:23:50 +0100 | [diff] [blame] | 103 | xspi->tx_ptr += xspi->bytes_per_word; |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 104 | } |
| 105 | |
Ricardo Ribalda Delgado | 24ba5e5 | 2015-01-28 13:23:47 +0100 | [diff] [blame] | 106 | static void xilinx_spi_rx(struct xilinx_spi *xspi) |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 107 | { |
| 108 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 109 | |
Ricardo Ribalda Delgado | 24ba5e5 | 2015-01-28 13:23:47 +0100 | [diff] [blame] | 110 | if (!xspi->rx_ptr) |
| 111 | return; |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 112 | |
Ricardo Ribalda Delgado | 17aaaa8 | 2015-01-28 13:23:50 +0100 | [diff] [blame] | 113 | switch (xspi->bytes_per_word) { |
| 114 | case 1: |
Ricardo Ribalda Delgado | 24ba5e5 | 2015-01-28 13:23:47 +0100 | [diff] [blame] | 115 | *(u8 *)(xspi->rx_ptr) = data; |
| 116 | break; |
Ricardo Ribalda Delgado | 17aaaa8 | 2015-01-28 13:23:50 +0100 | [diff] [blame] | 117 | case 2: |
Ricardo Ribalda Delgado | 24ba5e5 | 2015-01-28 13:23:47 +0100 | [diff] [blame] | 118 | *(u16 *)(xspi->rx_ptr) = data; |
| 119 | break; |
Ricardo Ribalda Delgado | 17aaaa8 | 2015-01-28 13:23:50 +0100 | [diff] [blame] | 120 | case 4: |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 121 | *(u32 *)(xspi->rx_ptr) = data; |
Ricardo Ribalda Delgado | 24ba5e5 | 2015-01-28 13:23:47 +0100 | [diff] [blame] | 122 | break; |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 123 | } |
Ricardo Ribalda Delgado | 24ba5e5 | 2015-01-28 13:23:47 +0100 | [diff] [blame] | 124 | |
Ricardo Ribalda Delgado | 17aaaa8 | 2015-01-28 13:23:50 +0100 | [diff] [blame] | 125 | xspi->rx_ptr += xspi->bytes_per_word; |
Richard Röjfors | c9da2e1 | 2009-11-13 12:28:55 +0100 | [diff] [blame] | 126 | } |
| 127 | |
Richard Röjfors | 86fc593 | 2009-11-13 12:28:49 +0100 | [diff] [blame] | 128 | static void xspi_init_hw(struct xilinx_spi *xspi) |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 129 | { |
Richard Röjfors | 86fc593 | 2009-11-13 12:28:49 +0100 | [diff] [blame] | 130 | void __iomem *regs_base = xspi->regs; |
| 131 | |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 132 | /* Reset the SPI device */ |
Richard Röjfors | 86fc593 | 2009-11-13 12:28:49 +0100 | [diff] [blame] | 133 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
| 134 | regs_base + XIPIF_V123B_RESETR_OFFSET); |
Ricardo Ribalda Delgado | 899929b | 2015-01-28 13:23:41 +0100 | [diff] [blame] | 135 | /* Enable the transmit empty interrupt, which we use to determine |
| 136 | * progress on the transmission. |
| 137 | */ |
| 138 | xspi->write_fn(XSPI_INTR_TX_EMPTY, |
| 139 | regs_base + XIPIF_V123B_IIER_OFFSET); |
Ricardo Ribalda Delgado | 2241735 | 2015-01-28 13:23:54 +0100 | [diff] [blame^] | 140 | /* Disable the global IPIF interrupt */ |
| 141 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 142 | /* Deselect the slave on the SPI bus */ |
Richard Röjfors | 86fc593 | 2009-11-13 12:28:49 +0100 | [diff] [blame] | 143 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 144 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
| 145 | * put SPI controller into master mode, and enable it */ |
Ricardo Ribalda Delgado | 2241735 | 2015-01-28 13:23:54 +0100 | [diff] [blame^] | 146 | xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE | |
| 147 | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET, |
| 148 | regs_base + XSPI_CR_OFFSET); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) |
| 152 | { |
| 153 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
Ricardo Ribalda Delgado | f9c6ef6 | 2015-01-28 13:23:46 +0100 | [diff] [blame] | 154 | u16 cr; |
| 155 | u32 cs; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 156 | |
| 157 | if (is_on == BITBANG_CS_INACTIVE) { |
| 158 | /* Deselect the slave on the SPI bus */ |
Ricardo Ribalda Delgado | f9c6ef6 | 2015-01-28 13:23:46 +0100 | [diff] [blame] | 159 | xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); |
| 160 | return; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 161 | } |
Ricardo Ribalda Delgado | f9c6ef6 | 2015-01-28 13:23:46 +0100 | [diff] [blame] | 162 | |
| 163 | /* Set the SPI clock phase and polarity */ |
| 164 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; |
| 165 | if (spi->mode & SPI_CPHA) |
| 166 | cr |= XSPI_CR_CPHA; |
| 167 | if (spi->mode & SPI_CPOL) |
| 168 | cr |= XSPI_CR_CPOL; |
| 169 | if (spi->mode & SPI_LSB_FIRST) |
| 170 | cr |= XSPI_CR_LSB_FIRST; |
| 171 | if (spi->mode & SPI_LOOP) |
| 172 | cr |= XSPI_CR_LOOP; |
| 173 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
| 174 | |
| 175 | /* We do not check spi->max_speed_hz here as the SPI clock |
| 176 | * frequency is not software programmable (the IP block design |
| 177 | * parameter) |
| 178 | */ |
| 179 | |
| 180 | cs = xspi->cs_inactive; |
| 181 | cs ^= BIT(spi->chip_select); |
| 182 | |
| 183 | /* Activate the chip select */ |
| 184 | xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a |
Axel Lin | 9bf46f6 | 2014-02-14 21:06:43 +0800 | [diff] [blame] | 188 | * custom txrx_bufs(). |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 189 | */ |
| 190 | static int xilinx_spi_setup_transfer(struct spi_device *spi, |
| 191 | struct spi_transfer *t) |
| 192 | { |
Ricardo Ribalda Delgado | f9c6ef6 | 2015-01-28 13:23:46 +0100 | [diff] [blame] | 193 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
| 194 | |
| 195 | if (spi->mode & SPI_CS_HIGH) |
| 196 | xspi->cs_inactive &= ~BIT(spi->chip_select); |
| 197 | else |
| 198 | xspi->cs_inactive |= BIT(spi->chip_select); |
| 199 | |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 200 | return 0; |
| 201 | } |
| 202 | |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 203 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
| 204 | { |
| 205 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
Ricardo Ribalda Delgado | b563bfb | 2015-01-28 13:23:52 +0100 | [diff] [blame] | 206 | int remaining_words; /* the number of words left to transfer */ |
Ricardo Ribalda Delgado | 2241735 | 2015-01-28 13:23:54 +0100 | [diff] [blame^] | 207 | bool use_irq = false; |
| 208 | u16 cr = 0; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 209 | |
| 210 | /* We get here with transmitter inhibited */ |
| 211 | |
| 212 | xspi->tx_ptr = t->tx_buf; |
| 213 | xspi->rx_ptr = t->rx_buf; |
Ricardo Ribalda Delgado | b563bfb | 2015-01-28 13:23:52 +0100 | [diff] [blame] | 214 | remaining_words = t->len / xspi->bytes_per_word; |
Wolfram Sang | 16735d0 | 2013-11-14 14:32:02 -0800 | [diff] [blame] | 215 | reinit_completion(&xspi->done); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 216 | |
Ricardo Ribalda Delgado | 2241735 | 2015-01-28 13:23:54 +0100 | [diff] [blame^] | 217 | if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) { |
| 218 | use_irq = true; |
| 219 | xspi->write_fn(XSPI_INTR_TX_EMPTY, |
| 220 | xspi->regs + XIPIF_V123B_IISR_OFFSET); |
| 221 | /* Enable the global IPIF interrupt */ |
| 222 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, |
| 223 | xspi->regs + XIPIF_V123B_DGIER_OFFSET); |
| 224 | /* Inhibit irq to avoid spurious irqs on tx_empty*/ |
| 225 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); |
| 226 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, |
| 227 | xspi->regs + XSPI_CR_OFFSET); |
| 228 | } |
| 229 | |
Ricardo Ribalda Delgado | b563bfb | 2015-01-28 13:23:52 +0100 | [diff] [blame] | 230 | while (remaining_words) { |
Ricardo Ribalda Delgado | b563bfb | 2015-01-28 13:23:52 +0100 | [diff] [blame] | 231 | int n_words, tx_words, rx_words; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 232 | |
Ricardo Ribalda Delgado | b563bfb | 2015-01-28 13:23:52 +0100 | [diff] [blame] | 233 | n_words = min(remaining_words, xspi->buffer_size); |
Ricardo Ribalda Delgado | 4c9a761 | 2015-01-28 13:23:40 +0100 | [diff] [blame] | 234 | |
Ricardo Ribalda Delgado | b563bfb | 2015-01-28 13:23:52 +0100 | [diff] [blame] | 235 | tx_words = n_words; |
| 236 | while (tx_words--) |
| 237 | xilinx_spi_tx(xspi); |
Peter Crosthwaite | 68c315b | 2013-06-04 16:02:34 +0200 | [diff] [blame] | 238 | |
| 239 | /* Start the transfer by not inhibiting the transmitter any |
| 240 | * longer |
| 241 | */ |
Peter Crosthwaite | 68c315b | 2013-06-04 16:02:34 +0200 | [diff] [blame] | 242 | |
Ricardo Ribalda Delgado | 2241735 | 2015-01-28 13:23:54 +0100 | [diff] [blame^] | 243 | if (use_irq) { |
Ricardo Ribalda Delgado | d9f5881 | 2015-01-28 13:23:45 +0100 | [diff] [blame] | 244 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
Ricardo Ribalda Delgado | 5fe11cc | 2015-01-28 13:23:44 +0100 | [diff] [blame] | 245 | wait_for_completion(&xspi->done); |
Ricardo Ribalda Delgado | d9f5881 | 2015-01-28 13:23:45 +0100 | [diff] [blame] | 246 | } else |
Ricardo Ribalda Delgado | 5fe11cc | 2015-01-28 13:23:44 +0100 | [diff] [blame] | 247 | while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) & |
| 248 | XSPI_SR_TX_EMPTY_MASK)) |
| 249 | ; |
Peter Crosthwaite | 68c315b | 2013-06-04 16:02:34 +0200 | [diff] [blame] | 250 | |
| 251 | /* A transmit has just completed. Process received data and |
| 252 | * check for more data to transmit. Always inhibit the |
| 253 | * transmitter while the Isr refills the transmit register/FIFO, |
| 254 | * or make sure it is stopped if we're done. |
| 255 | */ |
Ricardo Ribalda Delgado | 2241735 | 2015-01-28 13:23:54 +0100 | [diff] [blame^] | 256 | if (use_irq) |
Ricardo Ribalda Delgado | d9f5881 | 2015-01-28 13:23:45 +0100 | [diff] [blame] | 257 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, |
Peter Crosthwaite | 68c315b | 2013-06-04 16:02:34 +0200 | [diff] [blame] | 258 | xspi->regs + XSPI_CR_OFFSET); |
| 259 | |
| 260 | /* Read out all the data from the Rx FIFO */ |
Ricardo Ribalda Delgado | b563bfb | 2015-01-28 13:23:52 +0100 | [diff] [blame] | 261 | rx_words = n_words; |
| 262 | while (rx_words--) |
Ricardo Ribalda Delgado | 24ba5e5 | 2015-01-28 13:23:47 +0100 | [diff] [blame] | 263 | xilinx_spi_rx(xspi); |
Ricardo Ribalda Delgado | b563bfb | 2015-01-28 13:23:52 +0100 | [diff] [blame] | 264 | |
| 265 | remaining_words -= n_words; |
Peter Crosthwaite | 68c315b | 2013-06-04 16:02:34 +0200 | [diff] [blame] | 266 | } |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 267 | |
Ricardo Ribalda Delgado | 2241735 | 2015-01-28 13:23:54 +0100 | [diff] [blame^] | 268 | if (use_irq) |
| 269 | xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET); |
| 270 | |
Ricardo Ribalda Delgado | d79b2d0 | 2015-01-28 13:23:49 +0100 | [diff] [blame] | 271 | return t->len; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | |
| 275 | /* This driver supports single master mode only. Hence Tx FIFO Empty |
| 276 | * is the only interrupt we care about. |
| 277 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode |
| 278 | * Fault are not to happen. |
| 279 | */ |
| 280 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) |
| 281 | { |
| 282 | struct xilinx_spi *xspi = dev_id; |
| 283 | u32 ipif_isr; |
| 284 | |
| 285 | /* Get the IPIF interrupts, and clear them immediately */ |
Richard Röjfors | 86fc593 | 2009-11-13 12:28:49 +0100 | [diff] [blame] | 286 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
| 287 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 288 | |
| 289 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ |
Peter Crosthwaite | 68c315b | 2013-06-04 16:02:34 +0200 | [diff] [blame] | 290 | complete(&xspi->done); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | return IRQ_HANDLED; |
| 294 | } |
| 295 | |
Ricardo Ribalda Delgado | 4c9a761 | 2015-01-28 13:23:40 +0100 | [diff] [blame] | 296 | static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) |
| 297 | { |
| 298 | u8 sr; |
| 299 | int n_words = 0; |
| 300 | |
| 301 | /* |
| 302 | * Before the buffer_size detection we reset the core |
| 303 | * to make sure we start with a clean state. |
| 304 | */ |
| 305 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
| 306 | xspi->regs + XIPIF_V123B_RESETR_OFFSET); |
| 307 | |
| 308 | /* Fill the Tx FIFO with as many words as possible */ |
| 309 | do { |
| 310 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); |
| 311 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); |
| 312 | n_words++; |
| 313 | } while (!(sr & XSPI_SR_TX_FULL_MASK)); |
| 314 | |
| 315 | return n_words; |
| 316 | } |
| 317 | |
Grant Likely | eae6cb3 | 2010-10-14 09:32:53 -0600 | [diff] [blame] | 318 | static const struct of_device_id xilinx_spi_of_match[] = { |
| 319 | { .compatible = "xlnx,xps-spi-2.00.a", }, |
| 320 | { .compatible = "xlnx,xps-spi-2.00.b", }, |
| 321 | {} |
| 322 | }; |
| 323 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); |
Grant Likely | eae6cb3 | 2010-10-14 09:32:53 -0600 | [diff] [blame] | 324 | |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 325 | static int xilinx_spi_probe(struct platform_device *pdev) |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 326 | { |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 327 | struct xilinx_spi *xspi; |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 328 | struct xspi_platform_data *pdata; |
Michal Simek | ad3fdbc | 2013-07-08 15:29:15 +0200 | [diff] [blame] | 329 | struct resource *res; |
Michal Simek | 7b3b743 | 2013-07-09 18:05:16 +0200 | [diff] [blame] | 330 | int ret, num_cs = 0, bits_per_word = 8; |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 331 | struct spi_master *master; |
Michal Simek | 082339b | 2013-06-04 16:02:36 +0200 | [diff] [blame] | 332 | u32 tmp; |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 333 | u8 i; |
John Linn | ff82c58 | 2009-01-09 16:01:53 -0700 | [diff] [blame] | 334 | |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 335 | pdata = dev_get_platdata(&pdev->dev); |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 336 | if (pdata) { |
| 337 | num_cs = pdata->num_chipselect; |
| 338 | bits_per_word = pdata->bits_per_word; |
Michal Simek | be3acdf | 2013-07-08 15:29:17 +0200 | [diff] [blame] | 339 | } else { |
| 340 | of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits", |
| 341 | &num_cs); |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 342 | } |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 343 | |
| 344 | if (!num_cs) { |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 345 | dev_err(&pdev->dev, |
| 346 | "Missing slave select configuration data\n"); |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 347 | return -EINVAL; |
| 348 | } |
| 349 | |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 350 | master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); |
Richard Röjfors | d5af91a | 2009-11-13 12:28:39 +0100 | [diff] [blame] | 351 | if (!master) |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 352 | return -ENODEV; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 353 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 354 | /* the spi->mode bits understood by this driver: */ |
Ricardo Ribalda Delgado | f9c6ef6 | 2015-01-28 13:23:46 +0100 | [diff] [blame] | 355 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | |
| 356 | SPI_CS_HIGH; |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 357 | |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 358 | xspi = spi_master_get_devdata(master); |
Ricardo Ribalda Delgado | f9c6ef6 | 2015-01-28 13:23:46 +0100 | [diff] [blame] | 359 | xspi->cs_inactive = 0xffffffff; |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 360 | xspi->bitbang.master = master; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 361 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
| 362 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; |
| 363 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 364 | init_completion(&xspi->done); |
| 365 | |
Michal Simek | ad3fdbc | 2013-07-08 15:29:15 +0200 | [diff] [blame] | 366 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 367 | xspi->regs = devm_ioremap_resource(&pdev->dev, res); |
Mark Brown | c40537d | 2013-07-01 20:33:01 +0100 | [diff] [blame] | 368 | if (IS_ERR(xspi->regs)) { |
| 369 | ret = PTR_ERR(xspi->regs); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 370 | goto put_master; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 371 | } |
| 372 | |
Lars-Peter Clausen | 4b153a2 | 2014-07-10 10:30:20 +0200 | [diff] [blame] | 373 | master->bus_num = pdev->id; |
Grant Likely | 91565c4 | 2010-10-14 08:54:55 -0600 | [diff] [blame] | 374 | master->num_chipselect = num_cs; |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 375 | master->dev.of_node = pdev->dev.of_node; |
Michal Simek | 082339b | 2013-06-04 16:02:36 +0200 | [diff] [blame] | 376 | |
| 377 | /* |
| 378 | * Detect endianess on the IP via loop bit in CR. Detection |
| 379 | * must be done before reset is sent because incorrect reset |
| 380 | * value generates error interrupt. |
| 381 | * Setup little endian helper functions first and try to use them |
| 382 | * and check if bit was correctly setup or not. |
| 383 | */ |
Ricardo Ribalda Delgado | 99082ea | 2015-01-28 13:23:51 +0100 | [diff] [blame] | 384 | xspi->read_fn = ioread32; |
| 385 | xspi->write_fn = iowrite32; |
Michal Simek | 082339b | 2013-06-04 16:02:36 +0200 | [diff] [blame] | 386 | |
| 387 | xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); |
| 388 | tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); |
| 389 | tmp &= XSPI_CR_LOOP; |
| 390 | if (tmp != XSPI_CR_LOOP) { |
Ricardo Ribalda Delgado | 99082ea | 2015-01-28 13:23:51 +0100 | [diff] [blame] | 391 | xspi->read_fn = ioread32be; |
| 392 | xspi->write_fn = iowrite32be; |
Richard Röjfors | 86fc593 | 2009-11-13 12:28:49 +0100 | [diff] [blame] | 393 | } |
Michal Simek | 082339b | 2013-06-04 16:02:36 +0200 | [diff] [blame] | 394 | |
Axel Lin | 9bf46f6 | 2014-02-14 21:06:43 +0800 | [diff] [blame] | 395 | master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); |
Ricardo Ribalda Delgado | 17aaaa8 | 2015-01-28 13:23:50 +0100 | [diff] [blame] | 396 | xspi->bytes_per_word = bits_per_word / 8; |
Ricardo Ribalda Delgado | 4c9a761 | 2015-01-28 13:23:40 +0100 | [diff] [blame] | 397 | xspi->buffer_size = xilinx_spi_find_buffer_size(xspi); |
| 398 | |
Michal Simek | 7b3b743 | 2013-07-09 18:05:16 +0200 | [diff] [blame] | 399 | xspi->irq = platform_get_irq(pdev, 0); |
Ricardo Ribalda Delgado | 5fe11cc | 2015-01-28 13:23:44 +0100 | [diff] [blame] | 400 | if (xspi->irq >= 0) { |
| 401 | /* Register for SPI Interrupt */ |
| 402 | ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, |
| 403 | dev_name(&pdev->dev), xspi); |
| 404 | if (ret) |
| 405 | goto put_master; |
Michal Simek | 7b3b743 | 2013-07-09 18:05:16 +0200 | [diff] [blame] | 406 | } |
| 407 | |
Ricardo Ribalda Delgado | 5fe11cc | 2015-01-28 13:23:44 +0100 | [diff] [blame] | 408 | /* SPI controller initializations */ |
| 409 | xspi_init_hw(xspi); |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 410 | |
Richard Röjfors | d5af91a | 2009-11-13 12:28:39 +0100 | [diff] [blame] | 411 | ret = spi_bitbang_start(&xspi->bitbang); |
| 412 | if (ret) { |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 413 | dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); |
Michal Simek | 7b3b743 | 2013-07-09 18:05:16 +0200 | [diff] [blame] | 414 | goto put_master; |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 415 | } |
| 416 | |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 417 | dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", |
Michal Simek | ad3fdbc | 2013-07-08 15:29:15 +0200 | [diff] [blame] | 418 | (unsigned long long)res->start, xspi->regs, xspi->irq); |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 419 | |
Grant Likely | eae6cb3 | 2010-10-14 09:32:53 -0600 | [diff] [blame] | 420 | if (pdata) { |
| 421 | for (i = 0; i < pdata->num_devices; i++) |
| 422 | spi_new_device(master, pdata->devices + i); |
| 423 | } |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 424 | |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 425 | platform_set_drvdata(pdev, master); |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 426 | return 0; |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 427 | |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 428 | put_master: |
| 429 | spi_master_put(master); |
| 430 | |
| 431 | return ret; |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 432 | } |
| 433 | |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 434 | static int xilinx_spi_remove(struct platform_device *pdev) |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 435 | { |
Mark Brown | 7cb2abd | 2013-07-05 11:24:26 +0100 | [diff] [blame] | 436 | struct spi_master *master = platform_get_drvdata(pdev); |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 437 | struct xilinx_spi *xspi = spi_master_get_devdata(master); |
Michal Simek | 7b3b743 | 2013-07-09 18:05:16 +0200 | [diff] [blame] | 438 | void __iomem *regs_base = xspi->regs; |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 439 | |
| 440 | spi_bitbang_stop(&xspi->bitbang); |
Michal Simek | 7b3b743 | 2013-07-09 18:05:16 +0200 | [diff] [blame] | 441 | |
| 442 | /* Disable all the interrupts just in case */ |
| 443 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); |
| 444 | /* Disable the global IPIF interrupt */ |
| 445 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); |
Mark Brown | d81c0bb | 2013-07-03 12:05:42 +0100 | [diff] [blame] | 446 | |
| 447 | spi_master_put(xspi->bitbang.master); |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | /* work with hotplug and coldplug */ |
| 453 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); |
| 454 | |
| 455 | static struct platform_driver xilinx_spi_driver = { |
| 456 | .probe = xilinx_spi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 457 | .remove = xilinx_spi_remove, |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 458 | .driver = { |
| 459 | .name = XILINX_SPI_NAME, |
Grant Likely | eae6cb3 | 2010-10-14 09:32:53 -0600 | [diff] [blame] | 460 | .of_match_table = xilinx_spi_of_match, |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 461 | }, |
| 462 | }; |
Grant Likely | 940ab88 | 2011-10-05 11:29:49 -0600 | [diff] [blame] | 463 | module_platform_driver(xilinx_spi_driver); |
Grant Likely | 8fd8821 | 2010-10-14 09:04:29 -0600 | [diff] [blame] | 464 | |
Andrei Konovalov | ae918c0 | 2007-07-17 04:04:11 -0700 | [diff] [blame] | 465 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
| 466 | MODULE_DESCRIPTION("Xilinx SPI driver"); |
| 467 | MODULE_LICENSE("GPL"); |