blob: 255b09124e1120c6c3be9306eaadac0ef1740f48 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
10 *
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +100011 * Right now, I am very wasteful with the buffers. I allocate memory
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets.
17 *
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
20 *
Greg Ungerer562d2f82005-11-07 14:09:50 +100021 * Support for FEC controller of ColdFire processors.
22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +100023 *
24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
Philippe De Muyter677177c2006-06-27 13:05:33 +100025 * Copyright (c) 2004-2006 Macq Electronique SA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070026 */
27
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/string.h>
31#include <linux/ptrace.h>
32#include <linux/errno.h>
33#include <linux/ioport.h>
34#include <linux/slab.h>
35#include <linux/interrupt.h>
36#include <linux/pci.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/spinlock.h>
43#include <linux/workqueue.h>
44#include <linux/bitops.h>
45
46#include <asm/irq.h>
47#include <asm/uaccess.h>
48#include <asm/io.h>
49#include <asm/pgtable.h>
50
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +100051#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
Greg Ungerer562d2f82005-11-07 14:09:50 +100052 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
Matt Waddel6b265292006-06-27 13:10:56 +100053 defined(CONFIG_M520x) || defined(CONFIG_M532x)
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#include <asm/coldfire.h>
55#include <asm/mcfsim.h>
56#include "fec.h"
57#else
58#include <asm/8xx_immap.h>
59#include <asm/mpc8xx.h>
60#include "commproc.h"
61#endif
62
63#if defined(CONFIG_FEC2)
64#define FEC_MAX_PORTS 2
65#else
66#define FEC_MAX_PORTS 1
67#endif
68
69/*
70 * Define the fixed address of the FEC hardware.
71 */
72static unsigned int fec_hw[] = {
73#if defined(CONFIG_M5272)
74 (MCF_MBAR + 0x840),
75#elif defined(CONFIG_M527x)
76 (MCF_MBAR + 0x1000),
77 (MCF_MBAR + 0x1800),
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +100078#elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
Linus Torvalds1da177e2005-04-16 15:20:36 -070079 (MCF_MBAR + 0x1000),
Greg Ungerer562d2f82005-11-07 14:09:50 +100080#elif defined(CONFIG_M520x)
81 (MCF_MBAR+0x30000),
Matt Waddel6b265292006-06-27 13:10:56 +100082#elif defined(CONFIG_M532x)
83 (MCF_MBAR+0xfc030000),
Linus Torvalds1da177e2005-04-16 15:20:36 -070084#else
85 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
86#endif
87};
88
89static unsigned char fec_mac_default[] = {
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
91};
92
93/*
94 * Some hardware gets it MAC address out of local flash memory.
95 * if this is non-zero then assume it is the address to get MAC from.
96 */
97#if defined(CONFIG_NETtel)
98#define FEC_FLASHMAC 0xf0006006
99#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
100#define FEC_FLASHMAC 0xf0006000
101#elif defined (CONFIG_MTD_KeyTechnology)
102#define FEC_FLASHMAC 0xffe04000
103#elif defined(CONFIG_CANCam)
104#define FEC_FLASHMAC 0xf0020000
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000105#elif defined (CONFIG_M5272C3)
106#define FEC_FLASHMAC (0xffe04000 + 4)
107#elif defined(CONFIG_MOD5272)
108#define FEC_FLASHMAC 0xffc0406b
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109#else
110#define FEC_FLASHMAC 0
111#endif
112
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113/* Forward declarations of some structures to support different PHYs
114*/
115
116typedef struct {
117 uint mii_data;
118 void (*funct)(uint mii_reg, struct net_device *dev);
119} phy_cmd_t;
120
121typedef struct {
122 uint id;
123 char *name;
124
125 const phy_cmd_t *config;
126 const phy_cmd_t *startup;
127 const phy_cmd_t *ack_int;
128 const phy_cmd_t *shutdown;
129} phy_info_t;
130
131/* The number of Tx and Rx buffers. These are allocated from the page
132 * pool. The code may assume these are power of two, so it it best
133 * to keep them that size.
134 * We don't need to allocate pages for the transmitter. We just use
135 * the skbuffer directly.
136 */
137#define FEC_ENET_RX_PAGES 8
138#define FEC_ENET_RX_FRSIZE 2048
139#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
140#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
141#define FEC_ENET_TX_FRSIZE 2048
142#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
143#define TX_RING_SIZE 16 /* Must be power of two */
144#define TX_RING_MOD_MASK 15 /* for this to work */
145
Greg Ungerer562d2f82005-11-07 14:09:50 +1000146#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
Matt Waddel6b265292006-06-27 13:10:56 +1000147#error "FEC: descriptor ring size constants too large"
Greg Ungerer562d2f82005-11-07 14:09:50 +1000148#endif
149
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150/* Interrupt events/masks.
151*/
152#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
153#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
154#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
155#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
156#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
157#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
158#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
159#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
160#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
161#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
162
163/* The FEC stores dest/src/type, data, and checksum for receive packets.
164 */
165#define PKT_MAXBUF_SIZE 1518
166#define PKT_MINBUF_SIZE 64
167#define PKT_MAXBLR_SIZE 1520
168
169
170/*
Matt Waddel6b265292006-06-27 13:10:56 +1000171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 * size bits. Other FEC hardware does not, so we need to take that into
173 * account when setting it.
174 */
Greg Ungerer562d2f82005-11-07 14:09:50 +1000175#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
Matt Waddel6b265292006-06-27 13:10:56 +1000176 defined(CONFIG_M520x) || defined(CONFIG_M532x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
178#else
179#define OPT_FRAME_SIZE 0
180#endif
181
182/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
183 * tx_bd_base always point to the base of the buffer descriptors. The
184 * cur_rx and cur_tx point to the currently available buffer.
185 * The dirty_tx tracks the current buffer that is being sent by the
186 * controller. The cur_tx and dirty_tx are equal under both completely
187 * empty and completely full conditions. The empty/ready indicator in
188 * the buffer descriptor determines the actual condition.
189 */
190struct fec_enet_private {
191 /* Hardware registers of the FEC device */
192 volatile fec_t *hwp;
193
194 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
195 unsigned char *tx_bounce[TX_RING_SIZE];
196 struct sk_buff* tx_skbuff[TX_RING_SIZE];
197 ushort skb_cur;
198 ushort skb_dirty;
199
200 /* CPM dual port RAM relative addresses.
201 */
202 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
203 cbd_t *tx_bd_base;
204 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
205 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
206 struct net_device_stats stats;
207 uint tx_full;
208 spinlock_t lock;
209
210 uint phy_id;
211 uint phy_id_done;
212 uint phy_status;
213 uint phy_speed;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000214 phy_info_t const *phy;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 struct work_struct phy_task;
216
217 uint sequence_done;
218 uint mii_phy_task_queued;
219
220 uint phy_addr;
221
222 int index;
223 int opened;
224 int link;
225 int old_link;
226 int full_duplex;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227};
228
229static int fec_enet_open(struct net_device *dev);
230static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
231static void fec_enet_mii(struct net_device *dev);
David Howells7d12e782006-10-05 14:55:46 +0100232static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233static void fec_enet_tx(struct net_device *dev);
234static void fec_enet_rx(struct net_device *dev);
235static int fec_enet_close(struct net_device *dev);
236static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
237static void set_multicast_list(struct net_device *dev);
238static void fec_restart(struct net_device *dev, int duplex);
239static void fec_stop(struct net_device *dev);
240static void fec_set_mac_address(struct net_device *dev);
241
242
243/* MII processing. We keep this as simple as possible. Requests are
244 * placed on the list (if there is room). When the request is finished
245 * by the MII, an optional function may be called.
246 */
247typedef struct mii_list {
248 uint mii_regval;
249 void (*mii_func)(uint val, struct net_device *dev);
250 struct mii_list *mii_next;
251} mii_list_t;
252
253#define NMII 20
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000254static mii_list_t mii_cmds[NMII];
255static mii_list_t *mii_free;
256static mii_list_t *mii_head;
257static mii_list_t *mii_tail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400259static int mii_queue(struct net_device *dev, int request,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 void (*func)(uint, struct net_device *));
261
262/* Make MII read/write commands for the FEC.
263*/
264#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
265#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
266 (VAL & 0xffff))
267#define mk_mii_end 0
268
269/* Transmitter timeout.
270*/
271#define TX_TIMEOUT (2*HZ)
272
273/* Register definitions for the PHY.
274*/
275
276#define MII_REG_CR 0 /* Control Register */
277#define MII_REG_SR 1 /* Status Register */
278#define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
279#define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400280#define MII_REG_ANAR 4 /* A-N Advertisement Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281#define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
282#define MII_REG_ANER 6 /* A-N Expansion Register */
283#define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
284#define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
285
286/* values for phy_status */
287
288#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
289#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
290#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
291#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400292#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400294#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295
296#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
297#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
298#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
299#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
300#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400301#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400303#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
305
306static int
307fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
308{
309 struct fec_enet_private *fep;
310 volatile fec_t *fecp;
311 volatile cbd_t *bdp;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000312 unsigned short status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313
314 fep = netdev_priv(dev);
315 fecp = (volatile fec_t*)dev->base_addr;
316
317 if (!fep->link) {
318 /* Link is down or autonegotiation is in progress. */
319 return 1;
320 }
321
322 /* Fill in a Tx ring entry */
323 bdp = fep->cur_tx;
324
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000325 status = bdp->cbd_sc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326#ifndef final_version
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000327 if (status & BD_ENET_TX_READY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328 /* Ooops. All transmit buffers are full. Bail out.
329 * This should not happen, since dev->tbusy should be set.
330 */
331 printk("%s: tx queue full!.\n", dev->name);
332 return 1;
333 }
334#endif
335
336 /* Clear all of the status flags.
337 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000338 status &= ~BD_ENET_TX_STATS;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339
340 /* Set buffer length and buffer pointer.
341 */
342 bdp->cbd_bufaddr = __pa(skb->data);
343 bdp->cbd_datlen = skb->len;
344
345 /*
346 * On some FEC implementations data must be aligned on
347 * 4-byte boundaries. Use bounce buffers to copy data
348 * and get it aligned. Ugh.
349 */
350 if (bdp->cbd_bufaddr & 0x3) {
351 unsigned int index;
352 index = bdp - fep->tx_bd_base;
353 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
354 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
355 }
356
357 /* Save skb pointer.
358 */
359 fep->tx_skbuff[fep->skb_cur] = skb;
360
361 fep->stats.tx_bytes += skb->len;
362 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400363
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 /* Push the data cache so the CPM does not get stale memory
365 * data.
366 */
367 flush_dcache_range((unsigned long)skb->data,
368 (unsigned long)skb->data + skb->len);
369
370 spin_lock_irq(&fep->lock);
371
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000372 /* Send it on its way. Tell FEC it's ready, interrupt when done,
373 * it's the last BD of the frame, and to put the CRC on the end.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 */
375
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000376 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000378 bdp->cbd_sc = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379
380 dev->trans_start = jiffies;
381
382 /* Trigger transmission start */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000383 fecp->fec_x_des_active = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384
385 /* If this was the last BD in the ring, start at the beginning again.
386 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000387 if (status & BD_ENET_TX_WRAP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 bdp = fep->tx_bd_base;
389 } else {
390 bdp++;
391 }
392
393 if (bdp == fep->dirty_tx) {
394 fep->tx_full = 1;
395 netif_stop_queue(dev);
396 }
397
398 fep->cur_tx = (cbd_t *)bdp;
399
400 spin_unlock_irq(&fep->lock);
401
402 return 0;
403}
404
405static void
406fec_timeout(struct net_device *dev)
407{
408 struct fec_enet_private *fep = netdev_priv(dev);
409
410 printk("%s: transmit timed out.\n", dev->name);
411 fep->stats.tx_errors++;
412#ifndef final_version
413 {
414 int i;
415 cbd_t *bdp;
416
417 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
418 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
419 (unsigned long)fep->dirty_tx,
420 (unsigned long)fep->cur_rx);
421
422 bdp = fep->tx_bd_base;
423 printk(" tx: %u buffers\n", TX_RING_SIZE);
424 for (i = 0 ; i < TX_RING_SIZE; i++) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400425 printk(" %08x: %04x %04x %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 (uint) bdp,
427 bdp->cbd_sc,
428 bdp->cbd_datlen,
429 (int) bdp->cbd_bufaddr);
430 bdp++;
431 }
432
433 bdp = fep->rx_bd_base;
434 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
435 for (i = 0 ; i < RX_RING_SIZE; i++) {
436 printk(" %08x: %04x %04x %08x\n",
437 (uint) bdp,
438 bdp->cbd_sc,
439 bdp->cbd_datlen,
440 (int) bdp->cbd_bufaddr);
441 bdp++;
442 }
443 }
444#endif
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000445 fec_restart(dev, fep->full_duplex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 netif_wake_queue(dev);
447}
448
449/* The interrupt handler.
450 * This is called from the MPC core interrupt.
451 */
452static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +0100453fec_enet_interrupt(int irq, void * dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454{
455 struct net_device *dev = dev_id;
456 volatile fec_t *fecp;
457 uint int_events;
458 int handled = 0;
459
460 fecp = (volatile fec_t*)dev->base_addr;
461
462 /* Get the interrupt events that caused us to be here.
463 */
464 while ((int_events = fecp->fec_ievent) != 0) {
465 fecp->fec_ievent = int_events;
466
467 /* Handle receive event in its own function.
468 */
469 if (int_events & FEC_ENET_RXF) {
470 handled = 1;
471 fec_enet_rx(dev);
472 }
473
474 /* Transmit OK, or non-fatal error. Update the buffer
475 descriptors. FEC handles all errors, we just discover
476 them as part of the transmit process.
477 */
478 if (int_events & FEC_ENET_TXF) {
479 handled = 1;
480 fec_enet_tx(dev);
481 }
482
483 if (int_events & FEC_ENET_MII) {
484 handled = 1;
485 fec_enet_mii(dev);
486 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400487
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 }
489 return IRQ_RETVAL(handled);
490}
491
492
493static void
494fec_enet_tx(struct net_device *dev)
495{
496 struct fec_enet_private *fep;
497 volatile cbd_t *bdp;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000498 unsigned short status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 struct sk_buff *skb;
500
501 fep = netdev_priv(dev);
502 spin_lock(&fep->lock);
503 bdp = fep->dirty_tx;
504
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000505 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
507
508 skb = fep->tx_skbuff[fep->skb_dirty];
509 /* Check for errors. */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000510 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 BD_ENET_TX_RL | BD_ENET_TX_UN |
512 BD_ENET_TX_CSL)) {
513 fep->stats.tx_errors++;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000514 if (status & BD_ENET_TX_HB) /* No heartbeat */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 fep->stats.tx_heartbeat_errors++;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000516 if (status & BD_ENET_TX_LC) /* Late collision */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 fep->stats.tx_window_errors++;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000518 if (status & BD_ENET_TX_RL) /* Retrans limit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 fep->stats.tx_aborted_errors++;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000520 if (status & BD_ENET_TX_UN) /* Underrun */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521 fep->stats.tx_fifo_errors++;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000522 if (status & BD_ENET_TX_CSL) /* Carrier lost */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 fep->stats.tx_carrier_errors++;
524 } else {
525 fep->stats.tx_packets++;
526 }
527
528#ifndef final_version
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000529 if (status & BD_ENET_TX_READY)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530 printk("HEY! Enet xmit interrupt and TX_READY.\n");
531#endif
532 /* Deferred means some collisions occurred during transmit,
533 * but we eventually sent the packet OK.
534 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000535 if (status & BD_ENET_TX_DEF)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 fep->stats.collisions++;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400537
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 /* Free the sk buffer associated with this last transmit.
539 */
540 dev_kfree_skb_any(skb);
541 fep->tx_skbuff[fep->skb_dirty] = NULL;
542 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400543
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 /* Update pointer to next buffer descriptor to be transmitted.
545 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000546 if (status & BD_ENET_TX_WRAP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 bdp = fep->tx_bd_base;
548 else
549 bdp++;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400550
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551 /* Since we have freed up a buffer, the ring is no longer
552 * full.
553 */
554 if (fep->tx_full) {
555 fep->tx_full = 0;
556 if (netif_queue_stopped(dev))
557 netif_wake_queue(dev);
558 }
559 }
560 fep->dirty_tx = (cbd_t *)bdp;
561 spin_unlock(&fep->lock);
562}
563
564
565/* During a receive, the cur_rx points to the current incoming buffer.
566 * When we update through the ring, if the next incoming buffer has
567 * not been given to the system, we just set the empty indicator,
568 * effectively tossing the packet.
569 */
570static void
571fec_enet_rx(struct net_device *dev)
572{
573 struct fec_enet_private *fep;
574 volatile fec_t *fecp;
575 volatile cbd_t *bdp;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000576 unsigned short status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 struct sk_buff *skb;
578 ushort pkt_len;
579 __u8 *data;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400580
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000581#ifdef CONFIG_M532x
582 flush_cache_all();
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400583#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584
585 fep = netdev_priv(dev);
586 fecp = (volatile fec_t*)dev->base_addr;
587
588 /* First, grab all of the stats for the incoming packet.
589 * These get messed up if we get called due to a busy condition.
590 */
591 bdp = fep->cur_rx;
592
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000593while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594
595#ifndef final_version
596 /* Since we have allocated space to hold a complete frame,
597 * the last indicator should be set.
598 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000599 if ((status & BD_ENET_RX_LAST) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600 printk("FEC ENET: rcv is not +last\n");
601#endif
602
603 if (!fep->opened)
604 goto rx_processing_done;
605
606 /* Check for errors. */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000607 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400609 fep->stats.rx_errors++;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000610 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611 /* Frame too long or too short. */
612 fep->stats.rx_length_errors++;
613 }
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000614 if (status & BD_ENET_RX_NO) /* Frame alignment */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 fep->stats.rx_frame_errors++;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000616 if (status & BD_ENET_RX_CR) /* CRC Error */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617 fep->stats.rx_crc_errors++;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000618 if (status & BD_ENET_RX_OV) /* FIFO overrun */
619 fep->stats.rx_fifo_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 }
621
622 /* Report late collisions as a frame error.
623 * On this error, the BD is closed, but we don't know what we
624 * have in the buffer. So, just drop this frame on the floor.
625 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000626 if (status & BD_ENET_RX_CL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 fep->stats.rx_errors++;
628 fep->stats.rx_frame_errors++;
629 goto rx_processing_done;
630 }
631
632 /* Process the incoming frame.
633 */
634 fep->stats.rx_packets++;
635 pkt_len = bdp->cbd_datlen;
636 fep->stats.rx_bytes += pkt_len;
637 data = (__u8*)__va(bdp->cbd_bufaddr);
638
639 /* This does 16 byte alignment, exactly what we need.
640 * The packet length includes FCS, but we don't want to
641 * include that when passing upstream as it messes up
642 * bridging applications.
643 */
644 skb = dev_alloc_skb(pkt_len-4);
645
646 if (skb == NULL) {
647 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
648 fep->stats.rx_dropped++;
649 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650 skb_put(skb,pkt_len-4); /* Make room */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000651 eth_copy_and_sum(skb, data, pkt_len-4, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 skb->protocol=eth_type_trans(skb,dev);
653 netif_rx(skb);
654 }
655 rx_processing_done:
656
657 /* Clear the status flags for this buffer.
658 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000659 status &= ~BD_ENET_RX_STATS;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660
661 /* Mark the buffer empty.
662 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000663 status |= BD_ENET_RX_EMPTY;
664 bdp->cbd_sc = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665
666 /* Update BD pointer to next entry.
667 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000668 if (status & BD_ENET_RX_WRAP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 bdp = fep->rx_bd_base;
670 else
671 bdp++;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400672
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673#if 1
674 /* Doing this here will keep the FEC running while we process
675 * incoming frames. On a heavily loaded network, we should be
676 * able to keep up at the expense of system resources.
677 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000678 fecp->fec_r_des_active = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679#endif
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000680 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681 fep->cur_rx = (cbd_t *)bdp;
682
683#if 0
684 /* Doing this here will allow us to process all frames in the
685 * ring before the FEC is allowed to put more there. On a heavily
686 * loaded network, some frames may be lost. Unfortunately, this
687 * increases the interrupt overhead since we can potentially work
688 * our way back to the interrupt return only to come right back
689 * here.
690 */
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000691 fecp->fec_r_des_active = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692#endif
693}
694
695
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000696/* called from interrupt context */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697static void
698fec_enet_mii(struct net_device *dev)
699{
700 struct fec_enet_private *fep;
701 volatile fec_t *ep;
702 mii_list_t *mip;
703 uint mii_reg;
704
705 fep = netdev_priv(dev);
706 ep = fep->hwp;
707 mii_reg = ep->fec_mii_data;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000708
709 spin_lock(&fep->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400710
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711 if ((mip = mii_head) == NULL) {
712 printk("MII and no head!\n");
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000713 goto unlock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714 }
715
716 if (mip->mii_func != NULL)
717 (*(mip->mii_func))(mii_reg, dev);
718
719 mii_head = mip->mii_next;
720 mip->mii_next = mii_free;
721 mii_free = mip;
722
723 if ((mip = mii_head) != NULL)
724 ep->fec_mii_data = mip->mii_regval;
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000725
726unlock:
727 spin_unlock(&fep->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728}
729
730static int
731mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
732{
733 struct fec_enet_private *fep;
734 unsigned long flags;
735 mii_list_t *mip;
736 int retval;
737
738 /* Add PHY address to register command.
739 */
740 fep = netdev_priv(dev);
741 regval |= fep->phy_addr << 23;
742
743 retval = 0;
744
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000745 spin_lock_irqsave(&fep->lock,flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746
747 if ((mip = mii_free) != NULL) {
748 mii_free = mip->mii_next;
749 mip->mii_regval = regval;
750 mip->mii_func = func;
751 mip->mii_next = NULL;
752 if (mii_head) {
753 mii_tail->mii_next = mip;
754 mii_tail = mip;
755 }
756 else {
757 mii_head = mii_tail = mip;
758 fep->hwp->fec_mii_data = regval;
759 }
760 }
761 else {
762 retval = 1;
763 }
764
Greg Ungerer0e702ab2006-06-27 13:19:33 +1000765 spin_unlock_irqrestore(&fep->lock,flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766
767 return(retval);
768}
769
770static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
771{
772 int k;
773
774 if(!c)
775 return;
776
777 for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
778 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
779 }
780}
781
782static void mii_parse_sr(uint mii_reg, struct net_device *dev)
783{
784 struct fec_enet_private *fep = netdev_priv(dev);
785 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000786 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000788 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789
790 if (mii_reg & 0x0004)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000791 status |= PHY_STAT_LINK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 if (mii_reg & 0x0010)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000793 status |= PHY_STAT_FAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 if (mii_reg & 0x0020)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000795 status |= PHY_STAT_ANC;
796
797 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798}
799
800static void mii_parse_cr(uint mii_reg, struct net_device *dev)
801{
802 struct fec_enet_private *fep = netdev_priv(dev);
803 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000804 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000806 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
808 if (mii_reg & 0x1000)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000809 status |= PHY_CONF_ANE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 if (mii_reg & 0x4000)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000811 status |= PHY_CONF_LOOP;
812 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813}
814
815static void mii_parse_anar(uint mii_reg, struct net_device *dev)
816{
817 struct fec_enet_private *fep = netdev_priv(dev);
818 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000819 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000821 status = *s & ~(PHY_CONF_SPMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
823 if (mii_reg & 0x0020)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000824 status |= PHY_CONF_10HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 if (mii_reg & 0x0040)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000826 status |= PHY_CONF_10FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 if (mii_reg & 0x0080)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000828 status |= PHY_CONF_100HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 if (mii_reg & 0x00100)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000830 status |= PHY_CONF_100FDX;
831 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832}
833
834/* ------------------------------------------------------------------------- */
835/* The Level one LXT970 is used by many boards */
836
837#define MII_LXT970_MIRROR 16 /* Mirror register */
838#define MII_LXT970_IER 17 /* Interrupt Enable Register */
839#define MII_LXT970_ISR 18 /* Interrupt Status Register */
840#define MII_LXT970_CONFIG 19 /* Configuration Register */
841#define MII_LXT970_CSR 20 /* Chip Status Register */
842
843static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
844{
845 struct fec_enet_private *fep = netdev_priv(dev);
846 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000847 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000849 status = *s & ~(PHY_STAT_SPMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 if (mii_reg & 0x0800) {
851 if (mii_reg & 0x1000)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000852 status |= PHY_STAT_100FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000854 status |= PHY_STAT_100HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700855 } else {
856 if (mii_reg & 0x1000)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000857 status |= PHY_STAT_10FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000859 status |= PHY_STAT_10HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000861 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862}
863
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000864static phy_cmd_t const phy_cmd_lxt970_config[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 { mk_mii_read(MII_REG_CR), mii_parse_cr },
866 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
867 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000868 };
869static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
871 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
872 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000873 };
874static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 /* read SR and ISR to acknowledge */
876 { mk_mii_read(MII_REG_SR), mii_parse_sr },
877 { mk_mii_read(MII_LXT970_ISR), NULL },
878
879 /* find out the current status */
880 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
881 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000882 };
883static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
885 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000886 };
887static phy_info_t const phy_info_lxt970 = {
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400888 .id = 0x07810000,
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000889 .name = "LXT970",
890 .config = phy_cmd_lxt970_config,
891 .startup = phy_cmd_lxt970_startup,
892 .ack_int = phy_cmd_lxt970_ack_int,
893 .shutdown = phy_cmd_lxt970_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894};
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400895
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896/* ------------------------------------------------------------------------- */
897/* The Level one LXT971 is used on some of my custom boards */
898
899/* register definitions for the 971 */
900
901#define MII_LXT971_PCR 16 /* Port Control Register */
902#define MII_LXT971_SR2 17 /* Status Register 2 */
903#define MII_LXT971_IER 18 /* Interrupt Enable Register */
904#define MII_LXT971_ISR 19 /* Interrupt Status Register */
905#define MII_LXT971_LCR 20 /* LED Control Register */
906#define MII_LXT971_TCR 30 /* Transmit Control Register */
907
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400908/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909 * I had some nice ideas of running the MDIO faster...
910 * The 971 should support 8MHz and I tried it, but things acted really
911 * weird, so 2.5 MHz ought to be enough for anyone...
912 */
913
914static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
915{
916 struct fec_enet_private *fep = netdev_priv(dev);
917 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000918 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000920 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921
922 if (mii_reg & 0x0400) {
923 fep->link = 1;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000924 status |= PHY_STAT_LINK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 } else {
926 fep->link = 0;
927 }
928 if (mii_reg & 0x0080)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000929 status |= PHY_STAT_ANC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930 if (mii_reg & 0x4000) {
931 if (mii_reg & 0x0200)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000932 status |= PHY_STAT_100FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000934 status |= PHY_STAT_100HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935 } else {
936 if (mii_reg & 0x0200)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000937 status |= PHY_STAT_10FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000939 status |= PHY_STAT_10HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940 }
941 if (mii_reg & 0x0008)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000942 status |= PHY_STAT_FAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000944 *s = status;
945}
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400946
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000947static phy_cmd_t const phy_cmd_lxt971_config[] = {
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400948 /* limit to 10MBit because my prototype board
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949 * doesn't work with 100. */
950 { mk_mii_read(MII_REG_CR), mii_parse_cr },
951 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
952 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
953 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000954 };
955static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
957 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
958 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
959 /* Somehow does the 971 tell me that the link is down
960 * the first read after power-up.
961 * read here to get a valid value in ack_int */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400962 { mk_mii_read(MII_REG_SR), mii_parse_sr },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700963 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000964 };
965static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
966 /* acknowledge the int before reading status ! */
967 { mk_mii_read(MII_LXT971_ISR), NULL },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968 /* find out the current status */
969 { mk_mii_read(MII_REG_SR), mii_parse_sr },
970 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000972 };
973static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
975 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000976 };
977static phy_info_t const phy_info_lxt971 = {
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400978 .id = 0x0001378e,
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000979 .name = "LXT971",
980 .config = phy_cmd_lxt971_config,
981 .startup = phy_cmd_lxt971_startup,
982 .ack_int = phy_cmd_lxt971_ack_int,
983 .shutdown = phy_cmd_lxt971_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984};
985
986/* ------------------------------------------------------------------------- */
987/* The Quality Semiconductor QS6612 is used on the RPX CLLF */
988
989/* register definitions */
990
991#define MII_QS6612_MCR 17 /* Mode Control Register */
992#define MII_QS6612_FTR 27 /* Factory Test Register */
993#define MII_QS6612_MCO 28 /* Misc. Control Register */
994#define MII_QS6612_ISR 29 /* Interrupt Source Register */
995#define MII_QS6612_IMR 30 /* Interrupt Mask Register */
996#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
997
998static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
999{
1000 struct fec_enet_private *fep = netdev_priv(dev);
1001 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001002 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001004 status = *s & ~(PHY_STAT_SPMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005
1006 switch((mii_reg >> 2) & 7) {
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001007 case 1: status |= PHY_STAT_10HDX; break;
1008 case 2: status |= PHY_STAT_100HDX; break;
1009 case 5: status |= PHY_STAT_10FDX; break;
1010 case 6: status |= PHY_STAT_100FDX; break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011}
1012
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001013 *s = status;
1014}
1015
1016static phy_cmd_t const phy_cmd_qs6612_config[] = {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001017 /* The PHY powers up isolated on the RPX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018 * so send a command to allow operation.
1019 */
1020 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1021
1022 /* parse cr and anar to get some info */
1023 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1024 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1025 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001026 };
1027static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1029 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1030 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001031 };
1032static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033 /* we need to read ISR, SR and ANER to acknowledge */
1034 { mk_mii_read(MII_QS6612_ISR), NULL },
1035 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1036 { mk_mii_read(MII_REG_ANER), NULL },
1037
1038 /* read pcr to get info */
1039 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1040 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001041 };
1042static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001043 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1044 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001045 };
1046static phy_info_t const phy_info_qs6612 = {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001047 .id = 0x00181440,
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001048 .name = "QS6612",
1049 .config = phy_cmd_qs6612_config,
1050 .startup = phy_cmd_qs6612_startup,
1051 .ack_int = phy_cmd_qs6612_ack_int,
1052 .shutdown = phy_cmd_qs6612_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053};
1054
1055/* ------------------------------------------------------------------------- */
1056/* AMD AM79C874 phy */
1057
1058/* register definitions for the 874 */
1059
1060#define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1061#define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1062#define MII_AM79C874_DR 18 /* Diagnostic Register */
1063#define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1064#define MII_AM79C874_MCR 21 /* ModeControl Register */
1065#define MII_AM79C874_DC 23 /* Disconnect Counter */
1066#define MII_AM79C874_REC 24 /* Recieve Error Counter */
1067
1068static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1069{
1070 struct fec_enet_private *fep = netdev_priv(dev);
1071 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001072 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001074 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075
1076 if (mii_reg & 0x0080)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001077 status |= PHY_STAT_ANC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 if (mii_reg & 0x0400)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001079 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001081 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1082
1083 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084}
1085
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001086static phy_cmd_t const phy_cmd_am79c874_config[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1088 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1089 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1090 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001091 };
1092static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1094 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001095 { mk_mii_read(MII_REG_SR), mii_parse_sr },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001097 };
1098static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 /* find out the current status */
1100 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1101 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1102 /* we only need to read ISR to acknowledge */
1103 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1104 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001105 };
1106static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1108 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001109 };
1110static phy_info_t const phy_info_am79c874 = {
1111 .id = 0x00022561,
1112 .name = "AM79C874",
1113 .config = phy_cmd_am79c874_config,
1114 .startup = phy_cmd_am79c874_startup,
1115 .ack_int = phy_cmd_am79c874_ack_int,
1116 .shutdown = phy_cmd_am79c874_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117};
1118
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001119
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120/* ------------------------------------------------------------------------- */
1121/* Kendin KS8721BL phy */
1122
1123/* register definitions for the 8721 */
1124
1125#define MII_KS8721BL_RXERCR 21
1126#define MII_KS8721BL_ICSR 22
1127#define MII_KS8721BL_PHYCR 31
1128
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001129static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1131 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1132 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001133 };
1134static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1136 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001137 { mk_mii_read(MII_REG_SR), mii_parse_sr },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001138 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001139 };
1140static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 /* find out the current status */
1142 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1143 /* we only need to read ISR to acknowledge */
1144 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1145 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001146 };
1147static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1149 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001150 };
1151static phy_info_t const phy_info_ks8721bl = {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001152 .id = 0x00022161,
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001153 .name = "KS8721BL",
1154 .config = phy_cmd_ks8721bl_config,
1155 .startup = phy_cmd_ks8721bl_startup,
1156 .ack_int = phy_cmd_ks8721bl_ack_int,
1157 .shutdown = phy_cmd_ks8721bl_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158};
1159
1160/* ------------------------------------------------------------------------- */
Greg Ungerer562d2f82005-11-07 14:09:50 +10001161/* register definitions for the DP83848 */
1162
1163#define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1164
1165static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1166{
1167 struct fec_enet_private *fep = dev->priv;
1168 volatile uint *s = &(fep->phy_status);
1169
1170 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1171
1172 /* Link up */
1173 if (mii_reg & 0x0001) {
1174 fep->link = 1;
1175 *s |= PHY_STAT_LINK;
1176 } else
1177 fep->link = 0;
1178 /* Status of link */
1179 if (mii_reg & 0x0010) /* Autonegotioation complete */
1180 *s |= PHY_STAT_ANC;
1181 if (mii_reg & 0x0002) { /* 10MBps? */
1182 if (mii_reg & 0x0004) /* Full Duplex? */
1183 *s |= PHY_STAT_10FDX;
1184 else
1185 *s |= PHY_STAT_10HDX;
1186 } else { /* 100 Mbps? */
1187 if (mii_reg & 0x0004) /* Full Duplex? */
1188 *s |= PHY_STAT_100FDX;
1189 else
1190 *s |= PHY_STAT_100HDX;
1191 }
1192 if (mii_reg & 0x0008)
1193 *s |= PHY_STAT_FAULT;
1194}
1195
1196static phy_info_t phy_info_dp83848= {
1197 0x020005c9,
1198 "DP83848",
1199
1200 (const phy_cmd_t []) { /* config */
1201 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1202 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1203 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1204 { mk_mii_end, }
1205 },
1206 (const phy_cmd_t []) { /* startup - enable interrupts */
1207 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1208 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1209 { mk_mii_end, }
1210 },
1211 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1212 { mk_mii_end, }
1213 },
1214 (const phy_cmd_t []) { /* shutdown */
1215 { mk_mii_end, }
1216 },
1217};
1218
1219/* ------------------------------------------------------------------------- */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001221static phy_info_t const * const phy_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222 &phy_info_lxt970,
1223 &phy_info_lxt971,
1224 &phy_info_qs6612,
1225 &phy_info_am79c874,
1226 &phy_info_ks8721bl,
Greg Ungerer562d2f82005-11-07 14:09:50 +10001227 &phy_info_dp83848,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228 NULL
1229};
1230
1231/* ------------------------------------------------------------------------- */
Matt Waddel6b265292006-06-27 13:10:56 +10001232#if !defined(CONFIG_M532x)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233#ifdef CONFIG_RPXCLASSIC
1234static void
1235mii_link_interrupt(void *dev_id);
1236#else
1237static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01001238mii_link_interrupt(int irq, void * dev_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239#endif
Matt Waddel6b265292006-06-27 13:10:56 +10001240#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241
1242#if defined(CONFIG_M5272)
1243
1244/*
1245 * Code specific to Coldfire 5272 setup.
1246 */
1247static void __inline__ fec_request_intrs(struct net_device *dev)
1248{
1249 volatile unsigned long *icrp;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001250 static const struct idesc {
1251 char *name;
1252 unsigned short irq;
David Howells7d12e782006-10-05 14:55:46 +01001253 irq_handler_t handler;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001254 } *idp, id[] = {
1255 { "fec(RX)", 86, fec_enet_interrupt },
1256 { "fec(TX)", 87, fec_enet_interrupt },
1257 { "fec(OTHER)", 88, fec_enet_interrupt },
1258 { "fec(MII)", 66, mii_link_interrupt },
1259 { NULL },
1260 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261
1262 /* Setup interrupt handlers. */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001263 for (idp = id; idp->name; idp++) {
1264 if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
1265 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1266 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267
1268 /* Unmask interrupt at ColdFire 5272 SIM */
1269 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1270 *icrp = 0x00000ddd;
1271 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1272 *icrp = (*icrp & 0x70777777) | 0x0d000000;
1273}
1274
1275static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1276{
1277 volatile fec_t *fecp;
1278
1279 fecp = fep->hwp;
1280 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1281 fecp->fec_x_cntrl = 0x00;
1282
1283 /*
1284 * Set MII speed to 2.5 MHz
1285 * See 5272 manual section 11.5.8: MSCR
1286 */
1287 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1288 fecp->fec_mii_speed = fep->phy_speed;
1289
1290 fec_restart(dev, 0);
1291}
1292
1293static void __inline__ fec_get_mac(struct net_device *dev)
1294{
1295 struct fec_enet_private *fep = netdev_priv(dev);
1296 volatile fec_t *fecp;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001297 unsigned char *iap, tmpaddr[ETH_ALEN];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298
1299 fecp = fep->hwp;
1300
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001301 if (FEC_FLASHMAC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302 /*
1303 * Get MAC address from FLASH.
1304 * If it is all 1's or 0's, use the default.
1305 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001306 iap = (unsigned char *)FEC_FLASHMAC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001307 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1308 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1309 iap = fec_mac_default;
1310 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1311 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1312 iap = fec_mac_default;
1313 } else {
1314 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1315 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1316 iap = &tmpaddr[0];
1317 }
1318
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001319 memcpy(dev->dev_addr, iap, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320
1321 /* Adjust MAC if using default MAC address */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001322 if (iap == fec_mac_default)
1323 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324}
1325
1326static void __inline__ fec_enable_phy_intr(void)
1327{
1328}
1329
1330static void __inline__ fec_disable_phy_intr(void)
1331{
1332 volatile unsigned long *icrp;
1333 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1334 *icrp = (*icrp & 0x70777777) | 0x08000000;
1335}
1336
1337static void __inline__ fec_phy_ack_intr(void)
1338{
1339 volatile unsigned long *icrp;
1340 /* Acknowledge the interrupt */
1341 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1342 *icrp = (*icrp & 0x77777777) | 0x08000000;
1343}
1344
1345static void __inline__ fec_localhw_setup(void)
1346{
1347}
1348
1349/*
1350 * Do not need to make region uncached on 5272.
1351 */
1352static void __inline__ fec_uncache(unsigned long addr)
1353{
1354}
1355
1356/* ------------------------------------------------------------------------- */
1357
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001358#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359
1360/*
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001361 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1362 * the 5270/5271/5274/5275 and 5280/5282 setups.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363 */
1364static void __inline__ fec_request_intrs(struct net_device *dev)
1365{
1366 struct fec_enet_private *fep;
1367 int b;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001368 static const struct idesc {
1369 char *name;
1370 unsigned short irq;
1371 } *idp, id[] = {
1372 { "fec(TXF)", 23 },
1373 { "fec(TXB)", 24 },
1374 { "fec(TXFIFO)", 25 },
1375 { "fec(TXCR)", 26 },
1376 { "fec(RXF)", 27 },
1377 { "fec(RXB)", 28 },
1378 { "fec(MII)", 29 },
1379 { "fec(LC)", 30 },
1380 { "fec(HBERR)", 31 },
1381 { "fec(GRA)", 32 },
1382 { "fec(EBERR)", 33 },
1383 { "fec(BABT)", 34 },
1384 { "fec(BABR)", 35 },
1385 { NULL },
1386 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001387
1388 fep = netdev_priv(dev);
1389 b = (fep->index) ? 128 : 64;
1390
1391 /* Setup interrupt handlers. */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001392 for (idp = id; idp->name; idp++) {
1393 if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
1394 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1395 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001396
1397 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1398 {
1399 volatile unsigned char *icrp;
1400 volatile unsigned long *imrp;
Willson Callan83901fc2006-06-27 13:13:44 +10001401 int i, ilip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402
1403 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1404 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1405 MCFINTC_ICR0);
Willson Callan83901fc2006-06-27 13:13:44 +10001406 for (i = 23, ilip = 0x28; (i < 36); i++)
1407 icrp[i] = ilip--;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408
1409 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1410 MCFINTC_IMRH);
1411 *imrp &= ~0x0000000f;
1412 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1413 MCFINTC_IMRL);
1414 *imrp &= ~0xff800001;
1415 }
1416
1417#if defined(CONFIG_M528x)
1418 /* Set up gpio outputs for MII lines */
1419 {
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001420 volatile u16 *gpio_paspar;
1421 volatile u8 *gpio_pehlpar;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001422
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001423 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1424 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1425 *gpio_paspar |= 0x0f00;
1426 *gpio_pehlpar = 0xc0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427 }
1428#endif
1429}
1430
1431static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1432{
1433 volatile fec_t *fecp;
1434
1435 fecp = fep->hwp;
1436 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1437 fecp->fec_x_cntrl = 0x00;
1438
1439 /*
1440 * Set MII speed to 2.5 MHz
1441 * See 5282 manual section 17.5.4.7: MSCR
1442 */
1443 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1444 fecp->fec_mii_speed = fep->phy_speed;
1445
1446 fec_restart(dev, 0);
1447}
1448
1449static void __inline__ fec_get_mac(struct net_device *dev)
1450{
1451 struct fec_enet_private *fep = netdev_priv(dev);
1452 volatile fec_t *fecp;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001453 unsigned char *iap, tmpaddr[ETH_ALEN];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454
1455 fecp = fep->hwp;
1456
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001457 if (FEC_FLASHMAC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458 /*
1459 * Get MAC address from FLASH.
1460 * If it is all 1's or 0's, use the default.
1461 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001462 iap = FEC_FLASHMAC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1464 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1465 iap = fec_mac_default;
1466 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1467 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1468 iap = fec_mac_default;
1469 } else {
1470 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1471 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1472 iap = &tmpaddr[0];
1473 }
1474
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001475 memcpy(dev->dev_addr, iap, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476
1477 /* Adjust MAC if using default MAC address */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001478 if (iap == fec_mac_default)
1479 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480}
1481
1482static void __inline__ fec_enable_phy_intr(void)
1483{
1484}
1485
1486static void __inline__ fec_disable_phy_intr(void)
1487{
1488}
1489
1490static void __inline__ fec_phy_ack_intr(void)
1491{
1492}
1493
1494static void __inline__ fec_localhw_setup(void)
1495{
1496}
1497
1498/*
1499 * Do not need to make region uncached on 5272.
1500 */
1501static void __inline__ fec_uncache(unsigned long addr)
1502{
1503}
1504
1505/* ------------------------------------------------------------------------- */
1506
Greg Ungerer562d2f82005-11-07 14:09:50 +10001507#elif defined(CONFIG_M520x)
1508
1509/*
1510 * Code specific to Coldfire 520x
1511 */
1512static void __inline__ fec_request_intrs(struct net_device *dev)
1513{
1514 struct fec_enet_private *fep;
1515 int b;
1516 static const struct idesc {
1517 char *name;
1518 unsigned short irq;
1519 } *idp, id[] = {
1520 { "fec(TXF)", 23 },
1521 { "fec(TXB)", 24 },
1522 { "fec(TXFIFO)", 25 },
1523 { "fec(TXCR)", 26 },
1524 { "fec(RXF)", 27 },
1525 { "fec(RXB)", 28 },
1526 { "fec(MII)", 29 },
1527 { "fec(LC)", 30 },
1528 { "fec(HBERR)", 31 },
1529 { "fec(GRA)", 32 },
1530 { "fec(EBERR)", 33 },
1531 { "fec(BABT)", 34 },
1532 { "fec(BABR)", 35 },
1533 { NULL },
1534 };
1535
1536 fep = netdev_priv(dev);
1537 b = 64 + 13;
1538
1539 /* Setup interrupt handlers. */
1540 for (idp = id; idp->name; idp++) {
1541 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1542 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1543 }
1544
1545 /* Unmask interrupts at ColdFire interrupt controller */
1546 {
1547 volatile unsigned char *icrp;
1548 volatile unsigned long *imrp;
1549
1550 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1551 MCFINTC_ICR0);
1552 for (b = 36; (b < 49); b++)
1553 icrp[b] = 0x04;
1554 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1555 MCFINTC_IMRH);
1556 *imrp &= ~0x0001FFF0;
1557 }
1558 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1559 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1560}
1561
1562static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1563{
1564 volatile fec_t *fecp;
1565
1566 fecp = fep->hwp;
1567 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1568 fecp->fec_x_cntrl = 0x00;
1569
1570 /*
1571 * Set MII speed to 2.5 MHz
1572 * See 5282 manual section 17.5.4.7: MSCR
1573 */
1574 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1575 fecp->fec_mii_speed = fep->phy_speed;
1576
1577 fec_restart(dev, 0);
1578}
1579
1580static void __inline__ fec_get_mac(struct net_device *dev)
1581{
1582 struct fec_enet_private *fep = netdev_priv(dev);
1583 volatile fec_t *fecp;
1584 unsigned char *iap, tmpaddr[ETH_ALEN];
1585
1586 fecp = fep->hwp;
1587
1588 if (FEC_FLASHMAC) {
1589 /*
1590 * Get MAC address from FLASH.
1591 * If it is all 1's or 0's, use the default.
1592 */
1593 iap = FEC_FLASHMAC;
1594 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1595 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1596 iap = fec_mac_default;
1597 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1598 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1599 iap = fec_mac_default;
1600 } else {
1601 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1602 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1603 iap = &tmpaddr[0];
1604 }
1605
1606 memcpy(dev->dev_addr, iap, ETH_ALEN);
1607
1608 /* Adjust MAC if using default MAC address */
1609 if (iap == fec_mac_default)
1610 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1611}
1612
1613static void __inline__ fec_enable_phy_intr(void)
1614{
1615}
1616
1617static void __inline__ fec_disable_phy_intr(void)
1618{
1619}
1620
1621static void __inline__ fec_phy_ack_intr(void)
1622{
1623}
1624
1625static void __inline__ fec_localhw_setup(void)
1626{
1627}
1628
1629static void __inline__ fec_uncache(unsigned long addr)
1630{
1631}
1632
1633/* ------------------------------------------------------------------------- */
1634
Matt Waddel6b265292006-06-27 13:10:56 +10001635#elif defined(CONFIG_M532x)
1636/*
1637 * Code specific for M532x
1638 */
1639static void __inline__ fec_request_intrs(struct net_device *dev)
1640{
1641 struct fec_enet_private *fep;
1642 int b;
1643 static const struct idesc {
1644 char *name;
1645 unsigned short irq;
1646 } *idp, id[] = {
1647 { "fec(TXF)", 36 },
1648 { "fec(TXB)", 37 },
1649 { "fec(TXFIFO)", 38 },
1650 { "fec(TXCR)", 39 },
1651 { "fec(RXF)", 40 },
1652 { "fec(RXB)", 41 },
1653 { "fec(MII)", 42 },
1654 { "fec(LC)", 43 },
1655 { "fec(HBERR)", 44 },
1656 { "fec(GRA)", 45 },
1657 { "fec(EBERR)", 46 },
1658 { "fec(BABT)", 47 },
1659 { "fec(BABR)", 48 },
1660 { NULL },
1661 };
1662
1663 fep = netdev_priv(dev);
1664 b = (fep->index) ? 128 : 64;
1665
1666 /* Setup interrupt handlers. */
1667 for (idp = id; idp->name; idp++) {
1668 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001669 printk("FEC: Could not allocate %s IRQ(%d)!\n",
Matt Waddel6b265292006-06-27 13:10:56 +10001670 idp->name, b+idp->irq);
1671 }
1672
1673 /* Unmask interrupts */
1674 MCF_INTC0_ICR36 = 0x2;
1675 MCF_INTC0_ICR37 = 0x2;
1676 MCF_INTC0_ICR38 = 0x2;
1677 MCF_INTC0_ICR39 = 0x2;
1678 MCF_INTC0_ICR40 = 0x2;
1679 MCF_INTC0_ICR41 = 0x2;
1680 MCF_INTC0_ICR42 = 0x2;
1681 MCF_INTC0_ICR43 = 0x2;
1682 MCF_INTC0_ICR44 = 0x2;
1683 MCF_INTC0_ICR45 = 0x2;
1684 MCF_INTC0_ICR46 = 0x2;
1685 MCF_INTC0_ICR47 = 0x2;
1686 MCF_INTC0_ICR48 = 0x2;
1687
1688 MCF_INTC0_IMRH &= ~(
1689 MCF_INTC_IMRH_INT_MASK36 |
1690 MCF_INTC_IMRH_INT_MASK37 |
1691 MCF_INTC_IMRH_INT_MASK38 |
1692 MCF_INTC_IMRH_INT_MASK39 |
1693 MCF_INTC_IMRH_INT_MASK40 |
1694 MCF_INTC_IMRH_INT_MASK41 |
1695 MCF_INTC_IMRH_INT_MASK42 |
1696 MCF_INTC_IMRH_INT_MASK43 |
1697 MCF_INTC_IMRH_INT_MASK44 |
1698 MCF_INTC_IMRH_INT_MASK45 |
1699 MCF_INTC_IMRH_INT_MASK46 |
1700 MCF_INTC_IMRH_INT_MASK47 |
1701 MCF_INTC_IMRH_INT_MASK48 );
1702
1703 /* Set up gpio outputs for MII lines */
1704 MCF_GPIO_PAR_FECI2C |= (0 |
1705 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1706 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1707 MCF_GPIO_PAR_FEC = (0 |
1708 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1709 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1710}
1711
1712static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1713{
1714 volatile fec_t *fecp;
1715
1716 fecp = fep->hwp;
1717 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1718 fecp->fec_x_cntrl = 0x00;
1719
1720 /*
1721 * Set MII speed to 2.5 MHz
1722 */
1723 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1724 fecp->fec_mii_speed = fep->phy_speed;
1725
1726 fec_restart(dev, 0);
1727}
1728
1729static void __inline__ fec_get_mac(struct net_device *dev)
1730{
1731 struct fec_enet_private *fep = netdev_priv(dev);
1732 volatile fec_t *fecp;
1733 unsigned char *iap, tmpaddr[ETH_ALEN];
1734
1735 fecp = fep->hwp;
1736
1737 if (FEC_FLASHMAC) {
1738 /*
1739 * Get MAC address from FLASH.
1740 * If it is all 1's or 0's, use the default.
1741 */
1742 iap = FEC_FLASHMAC;
1743 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1744 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1745 iap = fec_mac_default;
1746 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1747 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1748 iap = fec_mac_default;
1749 } else {
1750 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1751 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1752 iap = &tmpaddr[0];
1753 }
1754
1755 memcpy(dev->dev_addr, iap, ETH_ALEN);
1756
1757 /* Adjust MAC if using default MAC address */
1758 if (iap == fec_mac_default)
1759 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1760}
1761
1762static void __inline__ fec_enable_phy_intr(void)
1763{
1764}
1765
1766static void __inline__ fec_disable_phy_intr(void)
1767{
1768}
1769
1770static void __inline__ fec_phy_ack_intr(void)
1771{
1772}
1773
1774static void __inline__ fec_localhw_setup(void)
1775{
1776}
1777
1778/*
1779 * Do not need to make region uncached on 532x.
1780 */
1781static void __inline__ fec_uncache(unsigned long addr)
1782{
1783}
1784
1785/* ------------------------------------------------------------------------- */
1786
1787
Linus Torvalds1da177e2005-04-16 15:20:36 -07001788#else
1789
1790/*
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001791 * Code specific to the MPC860T setup.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792 */
1793static void __inline__ fec_request_intrs(struct net_device *dev)
1794{
1795 volatile immap_t *immap;
1796
1797 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1798
1799 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1800 panic("Could not allocate FEC IRQ!");
1801
1802#ifdef CONFIG_RPXCLASSIC
1803 /* Make Port C, bit 15 an input that causes interrupts.
1804 */
1805 immap->im_ioport.iop_pcpar &= ~0x0001;
1806 immap->im_ioport.iop_pcdir &= ~0x0001;
1807 immap->im_ioport.iop_pcso &= ~0x0001;
1808 immap->im_ioport.iop_pcint |= 0x0001;
1809 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1810
1811 /* Make LEDS reflect Link status.
1812 */
1813 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1814#endif
1815#ifdef CONFIG_FADS
1816 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1817 panic("Could not allocate MII IRQ!");
1818#endif
1819}
1820
1821static void __inline__ fec_get_mac(struct net_device *dev)
1822{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823 bd_t *bd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001824
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825 bd = (bd_t *)__res;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001826 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001827
1828#ifdef CONFIG_RPXCLASSIC
1829 /* The Embedded Planet boards have only one MAC address in
1830 * the EEPROM, but can have two Ethernet ports. For the
1831 * FEC port, we create another address by setting one of
1832 * the address bits above something that would have (up to
1833 * now) been allocated.
1834 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001835 dev->dev_adrd[3] |= 0x80;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001836#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001837}
1838
1839static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1840{
1841 extern uint _get_IMMR(void);
1842 volatile immap_t *immap;
1843 volatile fec_t *fecp;
1844
1845 fecp = fep->hwp;
1846 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1847
1848 /* Configure all of port D for MII.
1849 */
1850 immap->im_ioport.iop_pdpar = 0x1fff;
1851
1852 /* Bits moved from Rev. D onward.
1853 */
1854 if ((_get_IMMR() & 0xffff) < 0x0501)
1855 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1856 else
1857 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001858
Linus Torvalds1da177e2005-04-16 15:20:36 -07001859 /* Set MII speed to 2.5 MHz
1860 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001861 fecp->fec_mii_speed = fep->phy_speed =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001862 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1863}
1864
1865static void __inline__ fec_enable_phy_intr(void)
1866{
1867 volatile fec_t *fecp;
1868
1869 fecp = fep->hwp;
1870
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001871 /* Enable MII command finished interrupt
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872 */
1873 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1874}
1875
1876static void __inline__ fec_disable_phy_intr(void)
1877{
1878}
1879
1880static void __inline__ fec_phy_ack_intr(void)
1881{
1882}
1883
1884static void __inline__ fec_localhw_setup(void)
1885{
1886 volatile fec_t *fecp;
1887
1888 fecp = fep->hwp;
1889 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1890 /* Enable big endian and don't care about SDMA FC.
1891 */
1892 fecp->fec_fun_code = 0x78000000;
1893}
1894
1895static void __inline__ fec_uncache(unsigned long addr)
1896{
1897 pte_t *pte;
1898 pte = va_to_pte(mem_addr);
1899 pte_val(*pte) |= _PAGE_NO_CACHE;
1900 flush_tlb_page(init_mm.mmap, mem_addr);
1901}
1902
1903#endif
1904
1905/* ------------------------------------------------------------------------- */
1906
1907static void mii_display_status(struct net_device *dev)
1908{
1909 struct fec_enet_private *fep = netdev_priv(dev);
1910 volatile uint *s = &(fep->phy_status);
1911
1912 if (!fep->link && !fep->old_link) {
1913 /* Link is still down - don't print anything */
1914 return;
1915 }
1916
1917 printk("%s: status: ", dev->name);
1918
1919 if (!fep->link) {
1920 printk("link down");
1921 } else {
1922 printk("link up");
1923
1924 switch(*s & PHY_STAT_SPMASK) {
1925 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1926 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1927 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1928 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1929 default:
1930 printk(", Unknown speed/duplex");
1931 }
1932
1933 if (*s & PHY_STAT_ANC)
1934 printk(", auto-negotiation complete");
1935 }
1936
1937 if (*s & PHY_STAT_FAULT)
1938 printk(", remote fault");
1939
1940 printk(".\n");
1941}
1942
1943static void mii_display_config(struct net_device *dev)
1944{
1945 struct fec_enet_private *fep = netdev_priv(dev);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001946 uint status = fep->phy_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947
1948 /*
1949 ** When we get here, phy_task is already removed from
1950 ** the workqueue. It is thus safe to allow to reuse it.
1951 */
1952 fep->mii_phy_task_queued = 0;
1953 printk("%s: config: auto-negotiation ", dev->name);
1954
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001955 if (status & PHY_CONF_ANE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001956 printk("on");
1957 else
1958 printk("off");
1959
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001960 if (status & PHY_CONF_100FDX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961 printk(", 100FDX");
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001962 if (status & PHY_CONF_100HDX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001963 printk(", 100HDX");
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001964 if (status & PHY_CONF_10FDX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001965 printk(", 10FDX");
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001966 if (status & PHY_CONF_10HDX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967 printk(", 10HDX");
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001968 if (!(status & PHY_CONF_SPMASK))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001969 printk(", No speed/duplex selected?");
1970
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001971 if (status & PHY_CONF_LOOP)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001972 printk(", loopback enabled");
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001973
Linus Torvalds1da177e2005-04-16 15:20:36 -07001974 printk(".\n");
1975
1976 fep->sequence_done = 1;
1977}
1978
1979static void mii_relink(struct net_device *dev)
1980{
1981 struct fec_enet_private *fep = netdev_priv(dev);
1982 int duplex;
1983
1984 /*
1985 ** When we get here, phy_task is already removed from
1986 ** the workqueue. It is thus safe to allow to reuse it.
1987 */
1988 fep->mii_phy_task_queued = 0;
1989 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1990 mii_display_status(dev);
1991 fep->old_link = fep->link;
1992
1993 if (fep->link) {
1994 duplex = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001995 if (fep->phy_status
Linus Torvalds1da177e2005-04-16 15:20:36 -07001996 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1997 duplex = 1;
1998 fec_restart(dev, duplex);
1999 }
2000 else
2001 fec_stop(dev);
2002
2003#if 0
2004 enable_irq(fep->mii_irq);
2005#endif
2006
2007}
2008
2009/* mii_queue_relink is called in interrupt context from mii_link_interrupt */
2010static void mii_queue_relink(uint mii_reg, struct net_device *dev)
2011{
2012 struct fec_enet_private *fep = netdev_priv(dev);
2013
2014 /*
2015 ** We cannot queue phy_task twice in the workqueue. It
2016 ** would cause an endless loop in the workqueue.
2017 ** Fortunately, if the last mii_relink entry has not yet been
2018 ** executed now, it will do the job for the current interrupt,
2019 ** which is just what we want.
2020 */
2021 if (fep->mii_phy_task_queued)
2022 return;
2023
2024 fep->mii_phy_task_queued = 1;
2025 INIT_WORK(&fep->phy_task, (void*)mii_relink, dev);
2026 schedule_work(&fep->phy_task);
2027}
2028
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002029/* mii_queue_config is called in interrupt context from fec_enet_mii */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002030static void mii_queue_config(uint mii_reg, struct net_device *dev)
2031{
2032 struct fec_enet_private *fep = netdev_priv(dev);
2033
2034 if (fep->mii_phy_task_queued)
2035 return;
2036
2037 fep->mii_phy_task_queued = 1;
2038 INIT_WORK(&fep->phy_task, (void*)mii_display_config, dev);
2039 schedule_work(&fep->phy_task);
2040}
2041
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002042phy_cmd_t const phy_cmd_relink[] = {
2043 { mk_mii_read(MII_REG_CR), mii_queue_relink },
2044 { mk_mii_end, }
2045 };
2046phy_cmd_t const phy_cmd_config[] = {
2047 { mk_mii_read(MII_REG_CR), mii_queue_config },
2048 { mk_mii_end, }
2049 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07002050
2051/* Read remainder of PHY ID.
2052*/
2053static void
2054mii_discover_phy3(uint mii_reg, struct net_device *dev)
2055{
2056 struct fec_enet_private *fep;
2057 int i;
2058
2059 fep = netdev_priv(dev);
2060 fep->phy_id |= (mii_reg & 0xffff);
2061 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2062
2063 for(i = 0; phy_info[i]; i++) {
2064 if(phy_info[i]->id == (fep->phy_id >> 4))
2065 break;
2066 }
2067
2068 if (phy_info[i])
2069 printk(" -- %s\n", phy_info[i]->name);
2070 else
2071 printk(" -- unknown PHY!\n");
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002072
Linus Torvalds1da177e2005-04-16 15:20:36 -07002073 fep->phy = phy_info[i];
2074 fep->phy_id_done = 1;
2075}
2076
2077/* Scan all of the MII PHY addresses looking for someone to respond
2078 * with a valid ID. This usually happens quickly.
2079 */
2080static void
2081mii_discover_phy(uint mii_reg, struct net_device *dev)
2082{
2083 struct fec_enet_private *fep;
2084 volatile fec_t *fecp;
2085 uint phytype;
2086
2087 fep = netdev_priv(dev);
2088 fecp = fep->hwp;
2089
2090 if (fep->phy_addr < 32) {
2091 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002092
Linus Torvalds1da177e2005-04-16 15:20:36 -07002093 /* Got first part of ID, now get remainder.
2094 */
2095 fep->phy_id = phytype << 16;
2096 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2097 mii_discover_phy3);
2098 }
2099 else {
2100 fep->phy_addr++;
2101 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2102 mii_discover_phy);
2103 }
2104 } else {
2105 printk("FEC: No PHY device found.\n");
2106 /* Disable external MII interface */
2107 fecp->fec_mii_speed = fep->phy_speed = 0;
2108 fec_disable_phy_intr();
2109 }
2110}
2111
2112/* This interrupt occurs when the PHY detects a link change.
2113*/
2114#ifdef CONFIG_RPXCLASSIC
2115static void
2116mii_link_interrupt(void *dev_id)
2117#else
2118static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01002119mii_link_interrupt(int irq, void * dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002120#endif
2121{
2122 struct net_device *dev = dev_id;
2123 struct fec_enet_private *fep = netdev_priv(dev);
2124
2125 fec_phy_ack_intr();
2126
2127#if 0
2128 disable_irq(fep->mii_irq); /* disable now, enable later */
2129#endif
2130
2131 mii_do_cmd(dev, fep->phy->ack_int);
2132 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2133
2134 return IRQ_HANDLED;
2135}
2136
2137static int
2138fec_enet_open(struct net_device *dev)
2139{
2140 struct fec_enet_private *fep = netdev_priv(dev);
2141
2142 /* I should reset the ring buffers here, but I don't yet know
2143 * a simple way to do that.
2144 */
2145 fec_set_mac_address(dev);
2146
2147 fep->sequence_done = 0;
2148 fep->link = 0;
2149
2150 if (fep->phy) {
2151 mii_do_cmd(dev, fep->phy->ack_int);
2152 mii_do_cmd(dev, fep->phy->config);
2153 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2154
Matt Waddel6b265292006-06-27 13:10:56 +10002155 /* Poll until the PHY tells us its configuration
2156 * (not link state).
2157 * Request is initiated by mii_do_cmd above, but answer
2158 * comes by interrupt.
2159 * This should take about 25 usec per register at 2.5 MHz,
2160 * and we read approximately 5 registers.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002161 */
2162 while(!fep->sequence_done)
2163 schedule();
2164
2165 mii_do_cmd(dev, fep->phy->startup);
2166
2167 /* Set the initial link state to true. A lot of hardware
2168 * based on this device does not implement a PHY interrupt,
2169 * so we are never notified of link change.
2170 */
2171 fep->link = 1;
2172 } else {
2173 fep->link = 1; /* lets just try it and see */
2174 /* no phy, go full duplex, it's most likely a hub chip */
2175 fec_restart(dev, 1);
2176 }
2177
2178 netif_start_queue(dev);
2179 fep->opened = 1;
2180 return 0; /* Success */
2181}
2182
2183static int
2184fec_enet_close(struct net_device *dev)
2185{
2186 struct fec_enet_private *fep = netdev_priv(dev);
2187
2188 /* Don't know what to do yet.
2189 */
2190 fep->opened = 0;
2191 netif_stop_queue(dev);
2192 fec_stop(dev);
2193
2194 return 0;
2195}
2196
2197static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
2198{
2199 struct fec_enet_private *fep = netdev_priv(dev);
2200
2201 return &fep->stats;
2202}
2203
2204/* Set or clear the multicast filter for this adaptor.
2205 * Skeleton taken from sunlance driver.
2206 * The CPM Ethernet implementation allows Multicast as well as individual
2207 * MAC address filtering. Some of the drivers check to make sure it is
2208 * a group multicast address, and discard those that are not. I guess I
2209 * will do the same for now, but just remove the test if you want
2210 * individual filtering as well (do the upper net layers want or support
2211 * this kind of feature?).
2212 */
2213
2214#define HASH_BITS 6 /* #bits in hash */
2215#define CRC32_POLY 0xEDB88320
2216
2217static void set_multicast_list(struct net_device *dev)
2218{
2219 struct fec_enet_private *fep;
2220 volatile fec_t *ep;
2221 struct dev_mc_list *dmi;
2222 unsigned int i, j, bit, data, crc;
2223 unsigned char hash;
2224
2225 fep = netdev_priv(dev);
2226 ep = fep->hwp;
2227
2228 if (dev->flags&IFF_PROMISC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002229 ep->fec_r_cntrl |= 0x0008;
2230 } else {
2231
2232 ep->fec_r_cntrl &= ~0x0008;
2233
2234 if (dev->flags & IFF_ALLMULTI) {
2235 /* Catch all multicast addresses, so set the
2236 * filter to all 1's.
2237 */
2238 ep->fec_hash_table_high = 0xffffffff;
2239 ep->fec_hash_table_low = 0xffffffff;
2240 } else {
2241 /* Clear filter and add the addresses in hash register.
2242 */
2243 ep->fec_hash_table_high = 0;
2244 ep->fec_hash_table_low = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002245
Linus Torvalds1da177e2005-04-16 15:20:36 -07002246 dmi = dev->mc_list;
2247
2248 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2249 {
2250 /* Only support group multicast for now.
2251 */
2252 if (!(dmi->dmi_addr[0] & 1))
2253 continue;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002254
Linus Torvalds1da177e2005-04-16 15:20:36 -07002255 /* calculate crc32 value of mac address
2256 */
2257 crc = 0xffffffff;
2258
2259 for (i = 0; i < dmi->dmi_addrlen; i++)
2260 {
2261 data = dmi->dmi_addr[i];
2262 for (bit = 0; bit < 8; bit++, data >>= 1)
2263 {
2264 crc = (crc >> 1) ^
2265 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2266 }
2267 }
2268
2269 /* only upper 6 bits (HASH_BITS) are used
2270 which point to specific bit in he hash registers
2271 */
2272 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002273
Linus Torvalds1da177e2005-04-16 15:20:36 -07002274 if (hash > 31)
2275 ep->fec_hash_table_high |= 1 << (hash - 32);
2276 else
2277 ep->fec_hash_table_low |= 1 << hash;
2278 }
2279 }
2280 }
2281}
2282
2283/* Set a MAC change in hardware.
2284 */
2285static void
2286fec_set_mac_address(struct net_device *dev)
2287{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002288 volatile fec_t *fecp;
2289
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002290 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002291
2292 /* Set station address. */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002293 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2294 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2295 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2296 (dev->dev_addr[4] << 24);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002297
2298}
2299
2300/* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2301 */
2302 /*
2303 * XXX: We need to clean up on failure exits here.
2304 */
2305int __init fec_enet_init(struct net_device *dev)
2306{
2307 struct fec_enet_private *fep = netdev_priv(dev);
2308 unsigned long mem_addr;
2309 volatile cbd_t *bdp;
2310 cbd_t *cbd_base;
2311 volatile fec_t *fecp;
2312 int i, j;
2313 static int index = 0;
2314
2315 /* Only allow us to be probed once. */
2316 if (index >= FEC_MAX_PORTS)
2317 return -ENXIO;
2318
Greg Ungerer562d2f82005-11-07 14:09:50 +10002319 /* Allocate memory for buffer descriptors.
2320 */
2321 mem_addr = __get_free_page(GFP_KERNEL);
2322 if (mem_addr == 0) {
2323 printk("FEC: allocate descriptor memory failed?\n");
2324 return -ENOMEM;
2325 }
2326
Linus Torvalds1da177e2005-04-16 15:20:36 -07002327 /* Create an Ethernet device instance.
2328 */
2329 fecp = (volatile fec_t *) fec_hw[index];
2330
2331 fep->index = index;
2332 fep->hwp = fecp;
2333
2334 /* Whack a reset. We should wait for this.
2335 */
2336 fecp->fec_ecntrl = 1;
2337 udelay(10);
2338
Linus Torvalds1da177e2005-04-16 15:20:36 -07002339 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2340 * this needs some work to get unique addresses.
2341 *
2342 * This is our default MAC address unless the user changes
2343 * it via eth_mac_addr (our dev->set_mac_addr handler).
2344 */
2345 fec_get_mac(dev);
2346
Linus Torvalds1da177e2005-04-16 15:20:36 -07002347 cbd_base = (cbd_t *)mem_addr;
2348 /* XXX: missing check for allocation failure */
2349
2350 fec_uncache(mem_addr);
2351
2352 /* Set receive and transmit descriptor base.
2353 */
2354 fep->rx_bd_base = cbd_base;
2355 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2356
2357 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2358 fep->cur_rx = fep->rx_bd_base;
2359
2360 fep->skb_cur = fep->skb_dirty = 0;
2361
2362 /* Initialize the receive buffer descriptors.
2363 */
2364 bdp = fep->rx_bd_base;
2365 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2366
2367 /* Allocate a page.
2368 */
2369 mem_addr = __get_free_page(GFP_KERNEL);
2370 /* XXX: missing check for allocation failure */
2371
2372 fec_uncache(mem_addr);
2373
2374 /* Initialize the BD for every fragment in the page.
2375 */
2376 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2377 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2378 bdp->cbd_bufaddr = __pa(mem_addr);
2379 mem_addr += FEC_ENET_RX_FRSIZE;
2380 bdp++;
2381 }
2382 }
2383
2384 /* Set the last buffer to wrap.
2385 */
2386 bdp--;
2387 bdp->cbd_sc |= BD_SC_WRAP;
2388
2389 /* ...and the same for transmmit.
2390 */
2391 bdp = fep->tx_bd_base;
2392 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2393 if (j >= FEC_ENET_TX_FRPPG) {
2394 mem_addr = __get_free_page(GFP_KERNEL);
2395 j = 1;
2396 } else {
2397 mem_addr += FEC_ENET_TX_FRSIZE;
2398 j++;
2399 }
2400 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2401
2402 /* Initialize the BD for every fragment in the page.
2403 */
2404 bdp->cbd_sc = 0;
2405 bdp->cbd_bufaddr = 0;
2406 bdp++;
2407 }
2408
2409 /* Set the last buffer to wrap.
2410 */
2411 bdp--;
2412 bdp->cbd_sc |= BD_SC_WRAP;
2413
2414 /* Set receive and transmit descriptor base.
2415 */
2416 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2417 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2418
2419 /* Install our interrupt handlers. This varies depending on
2420 * the architecture.
2421 */
2422 fec_request_intrs(dev);
2423
Greg Ungerer562d2f82005-11-07 14:09:50 +10002424 fecp->fec_hash_table_high = 0;
2425 fecp->fec_hash_table_low = 0;
2426 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2427 fecp->fec_ecntrl = 2;
Matt Waddel6b265292006-06-27 13:10:56 +10002428 fecp->fec_r_des_active = 0;
Greg Ungerer562d2f82005-11-07 14:09:50 +10002429
Linus Torvalds1da177e2005-04-16 15:20:36 -07002430 dev->base_addr = (unsigned long)fecp;
2431
2432 /* The FEC Ethernet specific entries in the device structure. */
2433 dev->open = fec_enet_open;
2434 dev->hard_start_xmit = fec_enet_start_xmit;
2435 dev->tx_timeout = fec_timeout;
2436 dev->watchdog_timeo = TX_TIMEOUT;
2437 dev->stop = fec_enet_close;
2438 dev->get_stats = fec_enet_get_stats;
2439 dev->set_multicast_list = set_multicast_list;
2440
2441 for (i=0; i<NMII-1; i++)
2442 mii_cmds[i].mii_next = &mii_cmds[i+1];
2443 mii_free = mii_cmds;
2444
2445 /* setup MII interface */
2446 fec_set_mii(dev, fep);
2447
Matt Waddel6b265292006-06-27 13:10:56 +10002448 /* Clear and enable interrupts */
2449 fecp->fec_ievent = 0xffc00000;
2450 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2451 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2452
Linus Torvalds1da177e2005-04-16 15:20:36 -07002453 /* Queue up command to detect the PHY and initialize the
2454 * remainder of the interface.
2455 */
2456 fep->phy_id_done = 0;
2457 fep->phy_addr = 0;
2458 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2459
2460 index++;
2461 return 0;
2462}
2463
2464/* This function is called to start or restart the FEC during a link
2465 * change. This only happens when switching between half and full
2466 * duplex.
2467 */
2468static void
2469fec_restart(struct net_device *dev, int duplex)
2470{
2471 struct fec_enet_private *fep;
2472 volatile cbd_t *bdp;
2473 volatile fec_t *fecp;
2474 int i;
2475
2476 fep = netdev_priv(dev);
2477 fecp = fep->hwp;
2478
2479 /* Whack a reset. We should wait for this.
2480 */
2481 fecp->fec_ecntrl = 1;
2482 udelay(10);
2483
Linus Torvalds1da177e2005-04-16 15:20:36 -07002484 /* Clear any outstanding interrupt.
2485 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002486 fecp->fec_ievent = 0xffc00000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002487 fec_enable_phy_intr();
2488
2489 /* Set station address.
2490 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002491 fec_set_mac_address(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002492
2493 /* Reset all multicast.
2494 */
2495 fecp->fec_hash_table_high = 0;
2496 fecp->fec_hash_table_low = 0;
2497
2498 /* Set maximum receive buffer size.
2499 */
2500 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2501
2502 fec_localhw_setup();
2503
2504 /* Set receive and transmit descriptor base.
2505 */
2506 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2507 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2508
2509 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2510 fep->cur_rx = fep->rx_bd_base;
2511
2512 /* Reset SKB transmit buffers.
2513 */
2514 fep->skb_cur = fep->skb_dirty = 0;
2515 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2516 if (fep->tx_skbuff[i] != NULL) {
2517 dev_kfree_skb_any(fep->tx_skbuff[i]);
2518 fep->tx_skbuff[i] = NULL;
2519 }
2520 }
2521
2522 /* Initialize the receive buffer descriptors.
2523 */
2524 bdp = fep->rx_bd_base;
2525 for (i=0; i<RX_RING_SIZE; i++) {
2526
2527 /* Initialize the BD for every fragment in the page.
2528 */
2529 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2530 bdp++;
2531 }
2532
2533 /* Set the last buffer to wrap.
2534 */
2535 bdp--;
2536 bdp->cbd_sc |= BD_SC_WRAP;
2537
2538 /* ...and the same for transmmit.
2539 */
2540 bdp = fep->tx_bd_base;
2541 for (i=0; i<TX_RING_SIZE; i++) {
2542
2543 /* Initialize the BD for every fragment in the page.
2544 */
2545 bdp->cbd_sc = 0;
2546 bdp->cbd_bufaddr = 0;
2547 bdp++;
2548 }
2549
2550 /* Set the last buffer to wrap.
2551 */
2552 bdp--;
2553 bdp->cbd_sc |= BD_SC_WRAP;
2554
2555 /* Enable MII mode.
2556 */
2557 if (duplex) {
2558 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2559 fecp->fec_x_cntrl = 0x04; /* FD enable */
2560 }
2561 else {
2562 /* MII enable|No Rcv on Xmit */
2563 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2564 fecp->fec_x_cntrl = 0x00;
2565 }
2566 fep->full_duplex = duplex;
2567
2568 /* Set MII speed.
2569 */
2570 fecp->fec_mii_speed = fep->phy_speed;
2571
2572 /* And last, enable the transmit and receive processing.
2573 */
2574 fecp->fec_ecntrl = 2;
Matt Waddel6b265292006-06-27 13:10:56 +10002575 fecp->fec_r_des_active = 0;
2576
2577 /* Enable interrupts we wish to service.
2578 */
2579 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2580 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002581}
2582
2583static void
2584fec_stop(struct net_device *dev)
2585{
2586 volatile fec_t *fecp;
2587 struct fec_enet_private *fep;
2588
2589 fep = netdev_priv(dev);
2590 fecp = fep->hwp;
2591
Philippe De Muyter677177c2006-06-27 13:05:33 +10002592 /*
2593 ** We cannot expect a graceful transmit stop without link !!!
2594 */
2595 if (fep->link)
2596 {
2597 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2598 udelay(10);
2599 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2600 printk("fec_stop : Graceful transmit stop did not complete !\n");
2601 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002602
2603 /* Whack a reset. We should wait for this.
2604 */
2605 fecp->fec_ecntrl = 1;
2606 udelay(10);
2607
2608 /* Clear outstanding MII command interrupts.
2609 */
2610 fecp->fec_ievent = FEC_ENET_MII;
2611 fec_enable_phy_intr();
2612
2613 fecp->fec_imask = FEC_ENET_MII;
2614 fecp->fec_mii_speed = fep->phy_speed;
2615}
2616
2617static int __init fec_enet_module_init(void)
2618{
2619 struct net_device *dev;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002620 int i, j, err;
2621
2622 printk("FEC ENET Version 0.2\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002623
2624 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2625 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2626 if (!dev)
2627 return -ENOMEM;
2628 err = fec_enet_init(dev);
2629 if (err) {
2630 free_netdev(dev);
2631 continue;
2632 }
2633 if (register_netdev(dev) != 0) {
2634 /* XXX: missing cleanup here */
2635 free_netdev(dev);
2636 return -EIO;
2637 }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002638
2639 printk("%s: ethernet ", dev->name);
2640 for (j = 0; (j < 5); j++)
2641 printk("%02x:", dev->dev_addr[j]);
2642 printk("%02x\n", dev->dev_addr[5]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002643 }
2644 return 0;
2645}
2646
2647module_init(fec_enet_module_init);
2648
2649MODULE_LICENSE("GPL");