John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify it |
| 3 | * under the terms of the GNU General Public License version 2 as published |
| 4 | * by the Free Software Foundation. |
| 5 | * |
| 6 | * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> |
| 7 | * Copyright (C) 2011 John Crispin <blogic@openwrt.org> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/ioport.h> |
| 11 | #include <linux/export.h> |
| 12 | #include <linux/clkdev.h> |
| 13 | #include <linux/of_address.h> |
| 14 | #include <asm/delay.h> |
| 15 | |
| 16 | #include <lantiq_soc.h> |
| 17 | |
| 18 | #include "../clk.h" |
| 19 | |
| 20 | /* infrastructure control register */ |
| 21 | #define SYS1_INFRAC 0x00bc |
| 22 | /* Configuration fuses for drivers and pll */ |
| 23 | #define STATUS_CONFIG 0x0040 |
| 24 | |
| 25 | /* GPE frequency selection */ |
| 26 | #define GPPC_OFFSET 24 |
| 27 | #define GPEFREQ_MASK 0x00000C0 |
| 28 | #define GPEFREQ_OFFSET 10 |
| 29 | /* Clock status register */ |
| 30 | #define SYSCTL_CLKS 0x0000 |
| 31 | /* Clock enable register */ |
| 32 | #define SYSCTL_CLKEN 0x0004 |
| 33 | /* Clock clear register */ |
| 34 | #define SYSCTL_CLKCLR 0x0008 |
| 35 | /* Activation Status Register */ |
| 36 | #define SYSCTL_ACTS 0x0020 |
| 37 | /* Activation Register */ |
| 38 | #define SYSCTL_ACT 0x0024 |
| 39 | /* Deactivation Register */ |
| 40 | #define SYSCTL_DEACT 0x0028 |
| 41 | /* reboot Register */ |
| 42 | #define SYSCTL_RBT 0x002c |
| 43 | /* CPU0 Clock Control Register */ |
| 44 | #define SYS1_CPU0CC 0x0040 |
| 45 | /* HRST_OUT_N Control Register */ |
| 46 | #define SYS1_HRSTOUTC 0x00c0 |
| 47 | /* clock divider bit */ |
| 48 | #define CPU0CC_CPUDIV 0x0001 |
| 49 | |
| 50 | /* Activation Status Register */ |
Thomas Langer | df8b5be | 2013-08-08 11:07:26 +0200 | [diff] [blame] | 51 | #define ACTS_ASC0_ACT 0x00001000 |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 52 | #define ACTS_ASC1_ACT 0x00000800 |
| 53 | #define ACTS_I2C_ACT 0x00004000 |
| 54 | #define ACTS_P0 0x00010000 |
| 55 | #define ACTS_P1 0x00010000 |
| 56 | #define ACTS_P2 0x00020000 |
| 57 | #define ACTS_P3 0x00020000 |
| 58 | #define ACTS_P4 0x00040000 |
| 59 | #define ACTS_PADCTRL0 0x00100000 |
| 60 | #define ACTS_PADCTRL1 0x00100000 |
| 61 | #define ACTS_PADCTRL2 0x00200000 |
| 62 | #define ACTS_PADCTRL3 0x00200000 |
| 63 | #define ACTS_PADCTRL4 0x00400000 |
| 64 | |
| 65 | #define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y)) |
| 66 | #define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x)) |
| 67 | #define sysctl_w32_mask(m, clear, set, reg) \ |
| 68 | sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg) |
| 69 | |
| 70 | #define status_w32(x, y) ltq_w32((x), status_membase + (y)) |
| 71 | #define status_r32(x) ltq_r32(status_membase + (x)) |
| 72 | |
| 73 | static void __iomem *sysctl_membase[3], *status_membase; |
| 74 | void __iomem *ltq_sys1_membase, *ltq_ebu_membase; |
| 75 | |
| 76 | void falcon_trigger_hrst(int level) |
| 77 | { |
| 78 | sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC); |
| 79 | } |
| 80 | |
| 81 | static inline void sysctl_wait(struct clk *clk, |
| 82 | unsigned int test, unsigned int reg) |
| 83 | { |
| 84 | int err = 1000000; |
| 85 | |
| 86 | do {} while (--err && ((sysctl_r32(clk->module, reg) |
| 87 | & clk->bits) != test)); |
| 88 | if (!err) |
| 89 | pr_err("module de/activation failed %d %08X %08X %08X\n", |
| 90 | clk->module, clk->bits, test, |
| 91 | sysctl_r32(clk->module, reg) & clk->bits); |
| 92 | } |
| 93 | |
| 94 | static int sysctl_activate(struct clk *clk) |
| 95 | { |
| 96 | sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); |
| 97 | sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); |
| 98 | sysctl_wait(clk, clk->bits, SYSCTL_ACTS); |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | static void sysctl_deactivate(struct clk *clk) |
| 103 | { |
| 104 | sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); |
| 105 | sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT); |
| 106 | sysctl_wait(clk, 0, SYSCTL_ACTS); |
| 107 | } |
| 108 | |
| 109 | static int sysctl_clken(struct clk *clk) |
| 110 | { |
| 111 | sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); |
Thomas Langer | df8b5be | 2013-08-08 11:07:26 +0200 | [diff] [blame] | 112 | sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 113 | sysctl_wait(clk, clk->bits, SYSCTL_CLKS); |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | static void sysctl_clkdis(struct clk *clk) |
| 118 | { |
| 119 | sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); |
| 120 | sysctl_wait(clk, 0, SYSCTL_CLKS); |
| 121 | } |
| 122 | |
| 123 | static void sysctl_reboot(struct clk *clk) |
| 124 | { |
| 125 | unsigned int act; |
| 126 | unsigned int bits; |
| 127 | |
| 128 | act = sysctl_r32(clk->module, SYSCTL_ACT); |
| 129 | bits = ~act & clk->bits; |
| 130 | if (bits != 0) { |
| 131 | sysctl_w32(clk->module, bits, SYSCTL_CLKEN); |
| 132 | sysctl_w32(clk->module, bits, SYSCTL_ACT); |
| 133 | sysctl_wait(clk, bits, SYSCTL_ACTS); |
| 134 | } |
| 135 | sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT); |
| 136 | sysctl_wait(clk, clk->bits, SYSCTL_ACTS); |
| 137 | } |
| 138 | |
| 139 | /* enable the ONU core */ |
| 140 | static void falcon_gpe_enable(void) |
| 141 | { |
| 142 | unsigned int freq; |
| 143 | unsigned int status; |
| 144 | |
| 145 | /* if if the clock is already enabled */ |
| 146 | status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC); |
| 147 | if (status & (1 << (GPPC_OFFSET + 1))) |
| 148 | return; |
| 149 | |
John Crispin | eb5dbd2 | 2014-10-10 23:37:52 +0200 | [diff] [blame^] | 150 | freq = (status_r32(STATUS_CONFIG) & |
| 151 | GPEFREQ_MASK) >> |
| 152 | GPEFREQ_OFFSET; |
| 153 | if (freq == 0) |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 154 | freq = 1; /* use 625MHz on unfused chip */ |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 155 | |
| 156 | /* apply new frequency */ |
| 157 | sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), |
| 158 | freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); |
| 159 | udelay(1); |
| 160 | |
| 161 | /* enable new frequency */ |
| 162 | sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); |
| 163 | udelay(1); |
| 164 | } |
| 165 | |
| 166 | static inline void clkdev_add_sys(const char *dev, unsigned int module, |
| 167 | unsigned int bits) |
| 168 | { |
| 169 | struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); |
| 170 | |
| 171 | clk->cl.dev_id = dev; |
| 172 | clk->cl.con_id = NULL; |
| 173 | clk->cl.clk = clk; |
| 174 | clk->module = module; |
John Crispin | 3a6ac50 | 2012-08-16 08:25:41 +0000 | [diff] [blame] | 175 | clk->bits = bits; |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 176 | clk->activate = sysctl_activate; |
| 177 | clk->deactivate = sysctl_deactivate; |
| 178 | clk->enable = sysctl_clken; |
| 179 | clk->disable = sysctl_clkdis; |
| 180 | clk->reboot = sysctl_reboot; |
| 181 | clkdev_add(&clk->cl); |
| 182 | } |
| 183 | |
| 184 | void __init ltq_soc_init(void) |
| 185 | { |
| 186 | struct device_node *np_status = |
| 187 | of_find_compatible_node(NULL, NULL, "lantiq,status-falcon"); |
| 188 | struct device_node *np_ebu = |
| 189 | of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon"); |
| 190 | struct device_node *np_sys1 = |
| 191 | of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon"); |
| 192 | struct device_node *np_syseth = |
| 193 | of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon"); |
| 194 | struct device_node *np_sysgpe = |
| 195 | of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon"); |
| 196 | struct resource res_status, res_ebu, res_sys[3]; |
| 197 | int i; |
| 198 | |
| 199 | /* check if all the core register ranges are available */ |
| 200 | if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe) |
| 201 | panic("Failed to load core nodes from devicetree"); |
| 202 | |
| 203 | if (of_address_to_resource(np_status, 0, &res_status) || |
| 204 | of_address_to_resource(np_ebu, 0, &res_ebu) || |
| 205 | of_address_to_resource(np_sys1, 0, &res_sys[0]) || |
| 206 | of_address_to_resource(np_syseth, 0, &res_sys[1]) || |
| 207 | of_address_to_resource(np_sysgpe, 0, &res_sys[2])) |
| 208 | panic("Failed to get core resources"); |
| 209 | |
| 210 | if ((request_mem_region(res_status.start, resource_size(&res_status), |
| 211 | res_status.name) < 0) || |
| 212 | (request_mem_region(res_ebu.start, resource_size(&res_ebu), |
| 213 | res_ebu.name) < 0) || |
| 214 | (request_mem_region(res_sys[0].start, |
| 215 | resource_size(&res_sys[0]), |
| 216 | res_sys[0].name) < 0) || |
| 217 | (request_mem_region(res_sys[1].start, |
| 218 | resource_size(&res_sys[1]), |
| 219 | res_sys[1].name) < 0) || |
| 220 | (request_mem_region(res_sys[2].start, |
| 221 | resource_size(&res_sys[2]), |
| 222 | res_sys[2].name) < 0)) |
Masanari Iida | 1a84db5 | 2014-08-29 23:37:33 +0900 | [diff] [blame] | 223 | pr_err("Failed to request core resources"); |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 224 | |
| 225 | status_membase = ioremap_nocache(res_status.start, |
| 226 | resource_size(&res_status)); |
| 227 | ltq_ebu_membase = ioremap_nocache(res_ebu.start, |
| 228 | resource_size(&res_ebu)); |
| 229 | |
| 230 | if (!status_membase || !ltq_ebu_membase) |
| 231 | panic("Failed to remap core resources"); |
| 232 | |
| 233 | for (i = 0; i < 3; i++) { |
| 234 | sysctl_membase[i] = ioremap_nocache(res_sys[i].start, |
| 235 | resource_size(&res_sys[i])); |
| 236 | if (!sysctl_membase[i]) |
| 237 | panic("Failed to remap sysctrl resources"); |
| 238 | } |
| 239 | ltq_sys1_membase = sysctl_membase[0]; |
| 240 | |
| 241 | falcon_gpe_enable(); |
| 242 | |
| 243 | /* get our 3 static rates for cpu, fpi and io clocks */ |
| 244 | if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV) |
John Crispin | 740c606e | 2013-01-19 08:54:24 +0000 | [diff] [blame] | 245 | clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0); |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 246 | else |
John Crispin | 740c606e | 2013-01-19 08:54:24 +0000 | [diff] [blame] | 247 | clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0); |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 248 | |
| 249 | /* add our clock domains */ |
| 250 | clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0); |
| 251 | clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2); |
| 252 | clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1); |
| 253 | clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3); |
| 254 | clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4); |
| 255 | clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0); |
| 256 | clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2); |
| 257 | clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1); |
| 258 | clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3); |
| 259 | clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4); |
Thomas Langer | df8b5be | 2013-08-08 11:07:26 +0200 | [diff] [blame] | 260 | clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT); |
| 261 | clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT); |
John Crispin | d41ced0 | 2012-04-19 16:16:11 +0200 | [diff] [blame] | 262 | clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT); |
| 263 | } |