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Wei WANG4c4b8c12013-04-11 10:43:40 +08001/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/mfd/rtsx_pci.h>
26
27#include "rtsx_pcr.h"
28
29static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
30{
31 u8 val;
32
33 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
34 return val & 0x0F;
35}
36
Wei WANG773ccdf2013-08-20 14:18:51 +080037static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
38{
39 u8 driving_3v3[4][3] = {
40 {0x11, 0x11, 0x11},
41 {0x55, 0x55, 0x5C},
42 {0x99, 0x99, 0x92},
43 {0x99, 0x99, 0x92},
44 };
45 u8 driving_1v8[4][3] = {
46 {0x3C, 0x3C, 0x3C},
47 {0xB3, 0xB3, 0xB3},
48 {0xFE, 0xFE, 0xFE},
49 {0xC4, 0xC4, 0xC4},
50 };
51 u8 (*driving)[3], drive_sel;
52
53 if (voltage == OUTPUT_3V3) {
54 driving = driving_3v3;
55 drive_sel = pcr->sd30_drive_sel_3v3;
56 } else {
57 driving = driving_1v8;
58 drive_sel = pcr->sd30_drive_sel_1v8;
59 }
60
61 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
62 0xFF, driving[drive_sel][0]);
63 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
64 0xFF, driving[drive_sel][1]);
65 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
66 0xFF, driving[drive_sel][2]);
67}
68
69static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
70{
71 u32 reg;
72
73 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
74 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
75
76 if (!rtsx_vendor_setting_valid(reg))
77 return;
78
79 pcr->aspm_en = rtsx_reg_to_aspm(reg);
80 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
81 pcr->card_drive_sel &= 0x3F;
82 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
83
84 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
85 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
86 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
87 if (rtsx_reg_check_reverse_socket(reg))
88 pcr->flags |= PCR_REVERSE_SOCKET;
89}
90
Wei WANGeb891c62013-08-20 14:18:55 +080091static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
Wei WANG5947c162013-08-20 14:18:52 +080092{
93 /* Set relink_time to 0 */
94 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
95 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
96 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
97
Wei WANGeb891c62013-08-20 14:18:55 +080098 if (pm_state == HOST_ENTER_S3)
99 rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
100
Wei WANG5947c162013-08-20 14:18:52 +0800101 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
102}
103
Wei WANG4c4b8c12013-04-11 10:43:40 +0800104static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
105{
106 rtsx_pci_init_cmd(pcr);
107
108 /* Configure GPIO as output */
109 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
Wei WANG71408122013-08-20 14:18:53 +0800110 /* Reset ASPM state to default value */
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
Wei WANG4c4b8c12013-04-11 10:43:40 +0800112 /* Switch LDO3318 source from DV33 to card_3v3 */
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
114 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
115 /* LED shine disabled, set initial shine cycle period */
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
Wei WANG773ccdf2013-08-20 14:18:51 +0800117 /* Configure driving */
118 rts5249_fill_driving(pcr, OUTPUT_3V3);
119 if (pcr->flags & PCR_REVERSE_SOCKET)
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
121 AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
122 else
123 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
124 AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
Wei WANGeb891c62013-08-20 14:18:55 +0800125 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
Wei WANG4c4b8c12013-04-11 10:43:40 +0800126
127 return rtsx_pci_send_cmd(pcr, 100);
128}
129
130static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
131{
132 int err;
133
134 err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
135 if (err < 0)
136 return err;
137
138 msleep(1);
139
140 return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
141}
142
143static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
144{
145 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
146}
147
148static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
149{
150 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
151}
152
153static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
154{
155 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
156}
157
158static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
159{
160 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
161}
162
163static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
164{
165 int err;
166
167 rtsx_pci_init_cmd(pcr);
168 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
169 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
170 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
171 LDO3318_PWR_MASK, 0x02);
172 err = rtsx_pci_send_cmd(pcr, 100);
173 if (err < 0)
174 return err;
175
176 msleep(5);
177
178 rtsx_pci_init_cmd(pcr);
179 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
180 SD_POWER_MASK, SD_VCC_POWER_ON);
181 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
182 LDO3318_PWR_MASK, 0x06);
183 err = rtsx_pci_send_cmd(pcr, 100);
184 if (err < 0)
185 return err;
186
187 return 0;
188}
189
190static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
191{
192 rtsx_pci_init_cmd(pcr);
193 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
194 SD_POWER_MASK, SD_POWER_OFF);
195 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
196 LDO3318_PWR_MASK, 0x00);
197 return rtsx_pci_send_cmd(pcr, 100);
198}
199
200static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
201{
202 int err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800203
204 if (voltage == OUTPUT_3V3) {
205 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
206 if (err < 0)
207 return err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800208 } else if (voltage == OUTPUT_1V8) {
209 err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
210 if (err < 0)
211 return err;
212 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
213 if (err < 0)
214 return err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800215 } else {
216 return -EINVAL;
217 }
218
219 /* set pad drive */
220 rtsx_pci_init_cmd(pcr);
Wei WANG773ccdf2013-08-20 14:18:51 +0800221 rts5249_fill_driving(pcr, voltage);
Wei WANG4c4b8c12013-04-11 10:43:40 +0800222 return rtsx_pci_send_cmd(pcr, 100);
223}
224
225static const struct pcr_ops rts5249_pcr_ops = {
Wei WANG773ccdf2013-08-20 14:18:51 +0800226 .fetch_vendor_settings = rts5249_fetch_vendor_settings,
Wei WANG4c4b8c12013-04-11 10:43:40 +0800227 .extra_init_hw = rts5249_extra_init_hw,
228 .optimize_phy = rts5249_optimize_phy,
229 .turn_on_led = rts5249_turn_on_led,
230 .turn_off_led = rts5249_turn_off_led,
231 .enable_auto_blink = rts5249_enable_auto_blink,
232 .disable_auto_blink = rts5249_disable_auto_blink,
233 .card_power_on = rts5249_card_power_on,
234 .card_power_off = rts5249_card_power_off,
235 .switch_output_voltage = rts5249_switch_output_voltage,
Wei WANG5947c162013-08-20 14:18:52 +0800236 .force_power_down = rts5249_force_power_down,
Wei WANG4c4b8c12013-04-11 10:43:40 +0800237};
238
239/* SD Pull Control Enable:
240 * SD_DAT[3:0] ==> pull up
241 * SD_CD ==> pull up
242 * SD_WP ==> pull up
243 * SD_CMD ==> pull up
244 * SD_CLK ==> pull down
245 */
246static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
247 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
248 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
249 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
250 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
251 0,
252};
253
254/* SD Pull Control Disable:
255 * SD_DAT[3:0] ==> pull down
256 * SD_CD ==> pull up
257 * SD_WP ==> pull down
258 * SD_CMD ==> pull down
259 * SD_CLK ==> pull down
260 */
261static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
262 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
263 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
264 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
265 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
266 0,
267};
268
269/* MS Pull Control Enable:
270 * MS CD ==> pull up
271 * others ==> pull down
272 */
273static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
274 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
275 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
276 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
277 0,
278};
279
280/* MS Pull Control Disable:
281 * MS CD ==> pull up
282 * others ==> pull down
283 */
284static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
285 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
286 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
287 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
288 0,
289};
290
291void rts5249_init_params(struct rtsx_pcr *pcr)
292{
293 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
294 pcr->num_slots = 2;
295 pcr->ops = &rts5249_pcr_ops;
296
Wei WANG773ccdf2013-08-20 14:18:51 +0800297 pcr->flags = 0;
298 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
299 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
300 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
301 pcr->aspm_en = ASPM_L1_EN;
302
Wei WANG4c4b8c12013-04-11 10:43:40 +0800303 pcr->ic_version = rts5249_get_ic_version(pcr);
304 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
305 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
306 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
307 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
308}