blob: 0a0b5b29d81ead016ac0828966ad2fd6f05a1ca2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/************************************************************************
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -07002 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
17#define BIT(loc) (0x8000000000000000ULL >> (loc))
18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#ifndef BOOL
22#define BOOL int
23#endif
24
25#ifndef TRUE
26#define TRUE 1
27#define FALSE 0
28#endif
29
30#undef SUCCESS
31#define SUCCESS 0
32#define FAILURE -1
33
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070034/* Maximum time to flicker LED when asked to identify NIC using ethtool */
35#define MAX_FLICKER_TIME 60000 /* 60 Secs */
36
Linus Torvalds1da177e2005-04-16 15:20:36 -070037/* Maximum outstanding splits to be configured into xena. */
38typedef enum xena_max_outstanding_splits {
39 XENA_ONE_SPLIT_TRANSACTION = 0,
40 XENA_TWO_SPLIT_TRANSACTION = 1,
41 XENA_THREE_SPLIT_TRANSACTION = 2,
42 XENA_FOUR_SPLIT_TRANSACTION = 3,
43 XENA_EIGHT_SPLIT_TRANSACTION = 4,
44 XENA_TWELVE_SPLIT_TRANSACTION = 5,
45 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
46 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
47} xena_max_outstanding_splits;
48#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
49
50/* OS concerned variables and constants */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070051#define WATCH_DOG_TIMEOUT 15*HZ
52#define EFILL 0x1234
53#define ALIGN_SIZE 127
54#define PCIX_COMMAND_REGISTER 0x62
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
56/*
57 * Debug related variables.
58 */
59/* different debug levels. */
60#define ERR_DBG 0
61#define INIT_DBG 1
62#define INFO_DBG 2
63#define TX_DBG 3
64#define INTR_DBG 4
65
66/* Global variable that defines the present debug level of the driver. */
Adrian Bunk26df54b2006-01-14 03:09:40 +010067static int debug_level = ERR_DBG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
69/* DEBUG message print. */
70#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
71
72/* Protocol assist features of the NIC */
73#define L3_CKSUM_OK 0xFFFF
74#define L4_CKSUM_OK 0xFFFF
75#define S2IO_JUMBO_SIZE 9600
76
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070077/* Driver statistics maintained by driver */
78typedef struct {
79 unsigned long long single_ecc_errs;
80 unsigned long long double_ecc_errs;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -050081 /* LRO statistics */
82 unsigned long long clubbed_frms_cnt;
83 unsigned long long sending_both;
84 unsigned long long outof_sequence_pkts;
85 unsigned long long flush_max_pkts;
86 unsigned long long sum_avg_pkts_aggregated;
87 unsigned long long num_aggregations;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070088} swStat_t;
89
Linus Torvalds1da177e2005-04-16 15:20:36 -070090/* The statistics block of Xena */
91typedef struct stat_block {
92/* Tx MAC statistics counters. */
93 u32 tmac_data_octets;
94 u32 tmac_frms;
95 u64 tmac_drop_frms;
96 u32 tmac_bcst_frms;
97 u32 tmac_mcst_frms;
98 u64 tmac_pause_ctrl_frms;
99 u32 tmac_ucst_frms;
100 u32 tmac_ttl_octets;
101 u32 tmac_any_err_frms;
102 u32 tmac_nucst_frms;
103 u64 tmac_ttl_less_fb_octets;
104 u64 tmac_vld_ip_octets;
105 u32 tmac_drop_ip;
106 u32 tmac_vld_ip;
107 u32 tmac_rst_tcp;
108 u32 tmac_icmp;
109 u64 tmac_tcp;
110 u32 reserved_0;
111 u32 tmac_udp;
112
113/* Rx MAC Statistics counters. */
114 u32 rmac_data_octets;
115 u32 rmac_vld_frms;
116 u64 rmac_fcs_err_frms;
117 u64 rmac_drop_frms;
118 u32 rmac_vld_bcst_frms;
119 u32 rmac_vld_mcst_frms;
120 u32 rmac_out_rng_len_err_frms;
121 u32 rmac_in_rng_len_err_frms;
122 u64 rmac_long_frms;
123 u64 rmac_pause_ctrl_frms;
124 u64 rmac_unsup_ctrl_frms;
125 u32 rmac_accepted_ucst_frms;
126 u32 rmac_ttl_octets;
127 u32 rmac_discarded_frms;
128 u32 rmac_accepted_nucst_frms;
129 u32 reserved_1;
130 u32 rmac_drop_events;
131 u64 rmac_ttl_less_fb_octets;
132 u64 rmac_ttl_frms;
133 u64 reserved_2;
134 u32 rmac_usized_frms;
135 u32 reserved_3;
136 u32 rmac_frag_frms;
137 u32 rmac_osized_frms;
138 u32 reserved_4;
139 u32 rmac_jabber_frms;
140 u64 rmac_ttl_64_frms;
141 u64 rmac_ttl_65_127_frms;
142 u64 reserved_5;
143 u64 rmac_ttl_128_255_frms;
144 u64 rmac_ttl_256_511_frms;
145 u64 reserved_6;
146 u64 rmac_ttl_512_1023_frms;
147 u64 rmac_ttl_1024_1518_frms;
148 u32 rmac_ip;
149 u32 reserved_7;
150 u64 rmac_ip_octets;
151 u32 rmac_drop_ip;
152 u32 rmac_hdr_err_ip;
153 u32 reserved_8;
154 u32 rmac_icmp;
155 u64 rmac_tcp;
156 u32 rmac_err_drp_udp;
157 u32 rmac_udp;
158 u64 rmac_xgmii_err_sym;
159 u64 rmac_frms_q0;
160 u64 rmac_frms_q1;
161 u64 rmac_frms_q2;
162 u64 rmac_frms_q3;
163 u64 rmac_frms_q4;
164 u64 rmac_frms_q5;
165 u64 rmac_frms_q6;
166 u64 rmac_frms_q7;
167 u16 rmac_full_q3;
168 u16 rmac_full_q2;
169 u16 rmac_full_q1;
170 u16 rmac_full_q0;
171 u16 rmac_full_q7;
172 u16 rmac_full_q6;
173 u16 rmac_full_q5;
174 u16 rmac_full_q4;
175 u32 reserved_9;
176 u32 rmac_pause_cnt;
177 u64 rmac_xgmii_data_err_cnt;
178 u64 rmac_xgmii_ctrl_err_cnt;
179 u32 rmac_err_tcp;
180 u32 rmac_accepted_ip;
181
182/* PCI/PCI-X Read transaction statistics. */
183 u32 new_rd_req_cnt;
184 u32 rd_req_cnt;
185 u32 rd_rtry_cnt;
186 u32 new_rd_req_rtry_cnt;
187
188/* PCI/PCI-X Write/Read transaction statistics. */
189 u32 wr_req_cnt;
190 u32 wr_rtry_rd_ack_cnt;
191 u32 new_wr_req_rtry_cnt;
192 u32 new_wr_req_cnt;
193 u32 wr_disc_cnt;
194 u32 wr_rtry_cnt;
195
196/* PCI/PCI-X Write / DMA Transaction statistics. */
197 u32 txp_wr_cnt;
198 u32 rd_rtry_wr_ack_cnt;
199 u32 txd_wr_cnt;
200 u32 txd_rd_cnt;
201 u32 rxd_wr_cnt;
202 u32 rxd_rd_cnt;
203 u32 rxf_wr_cnt;
204 u32 txf_rd_cnt;
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700205
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700206/* Tx MAC statistics overflow counters. */
207 u32 tmac_data_octets_oflow;
208 u32 tmac_frms_oflow;
209 u32 tmac_bcst_frms_oflow;
210 u32 tmac_mcst_frms_oflow;
211 u32 tmac_ucst_frms_oflow;
212 u32 tmac_ttl_octets_oflow;
213 u32 tmac_any_err_frms_oflow;
214 u32 tmac_nucst_frms_oflow;
215 u64 tmac_vlan_frms;
216 u32 tmac_drop_ip_oflow;
217 u32 tmac_vld_ip_oflow;
218 u32 tmac_rst_tcp_oflow;
219 u32 tmac_icmp_oflow;
220 u32 tpa_unknown_protocol;
221 u32 tmac_udp_oflow;
222 u32 reserved_10;
223 u32 tpa_parse_failure;
224
225/* Rx MAC Statistics overflow counters. */
226 u32 rmac_data_octets_oflow;
227 u32 rmac_vld_frms_oflow;
228 u32 rmac_vld_bcst_frms_oflow;
229 u32 rmac_vld_mcst_frms_oflow;
230 u32 rmac_accepted_ucst_frms_oflow;
231 u32 rmac_ttl_octets_oflow;
232 u32 rmac_discarded_frms_oflow;
233 u32 rmac_accepted_nucst_frms_oflow;
234 u32 rmac_usized_frms_oflow;
235 u32 rmac_drop_events_oflow;
236 u32 rmac_frag_frms_oflow;
237 u32 rmac_osized_frms_oflow;
238 u32 rmac_ip_oflow;
239 u32 rmac_jabber_frms_oflow;
240 u32 rmac_icmp_oflow;
241 u32 rmac_drop_ip_oflow;
242 u32 rmac_err_drp_udp_oflow;
243 u32 rmac_udp_oflow;
244 u32 reserved_11;
245 u32 rmac_pause_cnt_oflow;
246 u64 rmac_ttl_1519_4095_frms;
247 u64 rmac_ttl_4096_8191_frms;
248 u64 rmac_ttl_8192_max_frms;
249 u64 rmac_ttl_gt_max_frms;
250 u64 rmac_osized_alt_frms;
251 u64 rmac_jabber_alt_frms;
252 u64 rmac_gt_max_alt_frms;
253 u64 rmac_vlan_frms;
254 u32 rmac_len_discard;
255 u32 rmac_fcs_discard;
256 u32 rmac_pf_discard;
257 u32 rmac_da_discard;
258 u32 rmac_red_discard;
259 u32 rmac_rts_discard;
260 u32 reserved_12;
261 u32 rmac_ingm_full_discard;
262 u32 reserved_13;
263 u32 rmac_accepted_ip_oflow;
264 u32 reserved_14;
265 u32 link_fault_cnt;
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700266 swStat_t sw_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267} StatInfo_t;
268
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700269/*
270 * Structures representing different init time configuration
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 * parameters of the NIC.
272 */
273
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700274#define MAX_TX_FIFOS 8
275#define MAX_RX_RINGS 8
276
277/* FIFO mappings for all possible number of fifos configured */
Adrian Bunk26df54b2006-01-14 03:09:40 +0100278static int fifo_map[][MAX_TX_FIFOS] = {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700279 {0, 0, 0, 0, 0, 0, 0, 0},
280 {0, 0, 0, 0, 1, 1, 1, 1},
281 {0, 0, 0, 1, 1, 1, 2, 2},
282 {0, 0, 1, 1, 2, 2, 3, 3},
283 {0, 0, 1, 1, 2, 2, 3, 4},
284 {0, 0, 1, 1, 2, 3, 4, 5},
285 {0, 0, 1, 2, 3, 4, 5, 6},
286 {0, 1, 2, 3, 4, 5, 6, 7},
287};
288
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289/* Maintains Per FIFO related information. */
290typedef struct tx_fifo_config {
291#define MAX_AVAILABLE_TXDS 8192
292 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
293/* Priority definition */
294#define TX_FIFO_PRI_0 0 /*Highest */
295#define TX_FIFO_PRI_1 1
296#define TX_FIFO_PRI_2 2
297#define TX_FIFO_PRI_3 3
298#define TX_FIFO_PRI_4 4
299#define TX_FIFO_PRI_5 5
300#define TX_FIFO_PRI_6 6
301#define TX_FIFO_PRI_7 7 /*lowest */
302 u8 fifo_priority; /* specifies pointer level for FIFO */
303 /* user should not set twos fifos with same pri */
304 u8 f_no_snoop;
305#define NO_SNOOP_TXD 0x01
306#define NO_SNOOP_TXD_BUFFER 0x02
307} tx_fifo_config_t;
308
309
310/* Maintains per Ring related information */
311typedef struct rx_ring_config {
312 u32 num_rxd; /*No of RxDs per Rx Ring */
313#define RX_RING_PRI_0 0 /* highest */
314#define RX_RING_PRI_1 1
315#define RX_RING_PRI_2 2
316#define RX_RING_PRI_3 3
317#define RX_RING_PRI_4 4
318#define RX_RING_PRI_5 5
319#define RX_RING_PRI_6 6
320#define RX_RING_PRI_7 7 /* lowest */
321
322 u8 ring_priority; /*Specifies service priority of ring */
323 /* OSM should not set any two rings with same priority */
324 u8 ring_org; /*Organization of ring */
325#define RING_ORG_BUFF1 0x01
326#define RX_RING_ORG_BUFF3 0x03
327#define RX_RING_ORG_BUFF5 0x05
328
329 u8 f_no_snoop;
330#define NO_SNOOP_RXD 0x01
331#define NO_SNOOP_RXD_BUFFER 0x02
332} rx_ring_config_t;
333
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700334/* This structure provides contains values of the tunable parameters
335 * of the H/W
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 */
337struct config_param {
338/* Tx Side */
339 u32 tx_fifo_num; /*Number of Tx FIFOs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700341 u8 fifo_mapping[MAX_TX_FIFOS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
343 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
344 u64 tx_intr_type;
345 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
346
347/* Rx Side */
348 u32 rx_ring_num; /*Number of receive rings */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349#define MAX_RX_BLOCKS_PER_RING 150
350
351 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
raghavendra.koushik@neterion.comb6e3f982005-08-03 12:38:01 -0700352 u8 bimodal; /*Flag for setting bimodal interrupts*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353
354#define HEADER_ETHERNET_II_802_3_SIZE 14
355#define HEADER_802_2_SIZE 3
356#define HEADER_SNAP_SIZE 5
357#define HEADER_VLAN_SIZE 4
358
359#define MIN_MTU 46
360#define MAX_PYLD 1500
361#define MAX_MTU (MAX_PYLD+18)
362#define MAX_MTU_VLAN (MAX_PYLD+22)
363#define MAX_PYLD_JUMBO 9600
364#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
365#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700366 u16 bus_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367};
368
369/* Structure representing MAC Addrs */
370typedef struct mac_addr {
371 u8 mac_addr[ETH_ALEN];
372} macaddr_t;
373
374/* Structure that represent every FIFO element in the BAR1
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700375 * Address location.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 */
377typedef struct _TxFIFO_element {
378 u64 TxDL_Pointer;
379
380 u64 List_Control;
381#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
382#define TX_FIFO_FIRST_LIST BIT(14)
383#define TX_FIFO_LAST_LIST BIT(15)
384#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
385#define TX_FIFO_SPECIAL_FUNC BIT(23)
386#define TX_FIFO_DS_NO_SNOOP BIT(31)
387#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
388} TxFIFO_element_t;
389
390/* Tx descriptor structure */
391typedef struct _TxD {
392 u64 Control_1;
393/* bit mask */
394#define TXD_LIST_OWN_XENA BIT(7)
395#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
396#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
397#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
398#define TXD_GATHER_CODE (BIT(22) | BIT(23))
399#define TXD_GATHER_CODE_FIRST BIT(22)
400#define TXD_GATHER_CODE_LAST BIT(23)
401#define TXD_TCP_LSO_EN BIT(30)
402#define TXD_UDP_COF_EN BIT(31)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500403#define TXD_UFO_EN BIT(31) | BIT(30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500405#define TXD_UFO_MSS(val) vBIT(val,34,14)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
407
408 u64 Control_2;
409#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
410#define TXD_TX_CKO_IPV4_EN BIT(5)
411#define TXD_TX_CKO_TCP_EN BIT(6)
412#define TXD_TX_CKO_UDP_EN BIT(7)
413#define TXD_VLAN_ENABLE BIT(15)
414#define TXD_VLAN_TAG(val) vBIT(val,16,16)
415#define TXD_INT_NUMBER(val) vBIT(val,34,6)
416#define TXD_INT_TYPE_PER_LIST BIT(47)
417#define TXD_INT_TYPE_UTILZ BIT(46)
418#define TXD_SET_MARKER vBIT(0x6,0,4)
419
420 u64 Buffer_Pointer;
421 u64 Host_Control; /* reserved for host */
422} TxD_t;
423
424/* Structure to hold the phy and virt addr of every TxDL. */
425typedef struct list_info_hold {
426 dma_addr_t list_phy_addr;
427 void *list_virt_addr;
428} list_info_hold_t;
429
Ananda Rajuda6971d2005-10-31 16:55:31 -0500430/* Rx descriptor structure for 1 buffer mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431typedef struct _RxD_t {
432 u64 Host_Control; /* reserved for host */
433 u64 Control_1;
434#define RXD_OWN_XENA BIT(7)
435#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
436#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
437#define RXD_FRAME_PROTO_IPV4 BIT(27)
438#define RXD_FRAME_PROTO_IPV6 BIT(28)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700439#define RXD_FRAME_IP_FRAG BIT(29)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440#define RXD_FRAME_PROTO_TCP BIT(30)
441#define RXD_FRAME_PROTO_UDP BIT(31)
442#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
443#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
444#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
445
446 u64 Control_2;
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700447#define THE_RXD_MARK 0x3
448#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
449#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
450
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
452#define SET_VLAN_TAG(val) vBIT(val,48,16)
453#define SET_NUM_TAG(val) vBIT(val,16,32)
454
Ananda Rajuda6971d2005-10-31 16:55:31 -0500455
456} RxD_t;
457/* Rx descriptor structure for 1 buffer mode */
458typedef struct _RxD1_t {
459 struct _RxD_t h;
460
461#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
462#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
463#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
464 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
465 u64 Buffer0_ptr;
466} RxD1_t;
467/* Rx descriptor structure for 3 or 2 buffer mode */
468
469typedef struct _RxD3_t {
470 struct _RxD_t h;
471
472#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
473#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
474#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
475#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
476#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
477#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
478#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
479 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
480#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
481 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
482#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
483 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484#define BUF0_LEN 40
485#define BUF1_LEN 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486
487 u64 Buffer0_ptr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 u64 Buffer1_ptr;
489 u64 Buffer2_ptr;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500490} RxD3_t;
491
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700493/* Structure that represents the Rx descriptor block which contains
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 * 128 Rx descriptors.
495 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496typedef struct _RxD_block {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500497#define MAX_RXDS_PER_BLOCK_1 127
498 RxD1_t rxd[MAX_RXDS_PER_BLOCK_1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499
500 u64 reserved_0;
501#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700502 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503 * Rxd in this blk */
504 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
505 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700506 * the upper 32 bits should
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507 * be 0 */
508} RxD_block_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510#define SIZE_OF_BLOCK 4096
511
Ananda Rajuda6971d2005-10-31 16:55:31 -0500512#define RXD_MODE_1 0
513#define RXD_MODE_3A 1
514#define RXD_MODE_3B 2
515
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700516/* Structure to hold virtual addresses of Buf0 and Buf1 in
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 * 2buf mode. */
518typedef struct bufAdd {
519 void *ba_0_org;
520 void *ba_1_org;
521 void *ba_0;
522 void *ba_1;
523} buffAdd_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524
525/* Structure which stores all the MAC control parameters */
526
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700527/* This structure stores the offset of the RxD in the ring
528 * from which the Rx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529 * up the RxDs for processing.
530 */
531typedef struct _rx_curr_get_info_t {
532 u32 block_index;
533 u32 offset;
534 u32 ring_len;
535} rx_curr_get_info_t;
536
537typedef rx_curr_get_info_t rx_curr_put_info_t;
538
539/* This structure stores the offset of the TxDl in the FIFO
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700540 * from which the Tx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 * up the TxDLs for send complete interrupt processing.
542 */
543typedef struct {
544 u32 offset;
545 u32 fifo_len;
546} tx_curr_get_info_t;
547
548typedef tx_curr_get_info_t tx_curr_put_info_t;
549
Ananda Rajuda6971d2005-10-31 16:55:31 -0500550
551typedef struct rxd_info {
552 void *virt_addr;
553 dma_addr_t dma_addr;
554}rxd_info_t;
555
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700556/* Structure that holds the Phy and virt addresses of the Blocks */
557typedef struct rx_block_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500558 void *block_virt_addr;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700559 dma_addr_t block_dma_addr;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500560 rxd_info_t *rxds;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700561} rx_block_info_t;
562
563/* pre declaration of the nic structure */
564typedef struct s2io_nic nic_t;
565
566/* Ring specific structure */
567typedef struct ring_info {
568 /* The ring number */
569 int ring_no;
570
571 /*
572 * Place holders for the virtual and physical addresses of
573 * all the Rx Blocks
574 */
575 rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
576 int block_count;
577 int pkt_cnt;
578
579 /*
580 * Put pointer info which indictes which RxD has to be replenished
581 * with a new buffer.
582 */
583 rx_curr_put_info_t rx_curr_put_info;
584
585 /*
586 * Get pointer info which indictes which is the last RxD that was
587 * processed by the driver.
588 */
589 rx_curr_get_info_t rx_curr_get_info;
590
591#ifndef CONFIG_S2IO_NAPI
592 /* Index to the absolute position of the put pointer of Rx ring */
593 int put_pos;
594#endif
595
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700596 /* Buffer Address store. */
597 buffAdd_t **ba;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700598 nic_t *nic;
599} ring_info_t;
600
601/* Fifo specific structure */
602typedef struct fifo_info {
603 /* FIFO number */
604 int fifo_no;
605
606 /* Maximum TxDs per TxDL */
607 int max_txds;
608
609 /* Place holder of all the TX List's Phy and Virt addresses. */
610 list_info_hold_t *list_info;
611
612 /*
613 * Current offset within the tx FIFO where driver would write
614 * new Tx frame
615 */
616 tx_curr_put_info_t tx_curr_put_info;
617
618 /*
619 * Current offset within tx FIFO from where the driver would start freeing
620 * the buffers
621 */
622 tx_curr_get_info_t tx_curr_get_info;
623
624 nic_t *nic;
625}fifo_info_t;
626
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
628 * is maintained in this structure.
629 */
630typedef struct mac_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631/* tx side stuff */
632 /* logical pointer of start of each Tx FIFO */
633 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
634
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700635 /* Fifo specific structure */
636 fifo_info_t fifos[MAX_TX_FIFOS];
637
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -0700638 /* Save virtual address of TxD page with zero DMA addr(if any) */
639 void *zerodma_virt_addr;
640
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700641/* rx side stuff */
642 /* Ring specific structure */
643 ring_info_t rings[MAX_RX_RINGS];
644
645 u16 rmac_pause_time;
646 u16 mc_pause_threshold_q0q3;
647 u16 mc_pause_threshold_q4q7;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648
649 void *stats_mem; /* orignal pointer to allocated mem */
650 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
651 u32 stats_mem_sz;
652 StatInfo_t *stats_info; /* Logical address of the stat block */
653} mac_info_t;
654
655/* structure representing the user defined MAC addresses */
656typedef struct {
657 char addr[ETH_ALEN];
658 int usage_cnt;
659} usr_addr_t;
660
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661/* Default Tunable parameters of the NIC. */
662#define DEFAULT_FIFO_LEN 4096
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663#define SMALL_BLK_CNT 30
664#define LARGE_BLK_CNT 100
665
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400666/*
667 * Structure to keep track of the MSI-X vectors and the corresponding
668 * argument registered against each vector
669 */
670#define MAX_REQUESTED_MSI_X 17
671struct s2io_msix_entry
672{
673 u16 vector;
674 u16 entry;
675 void *arg;
676
677 u8 type;
678#define MSIX_FIFO_TYPE 1
679#define MSIX_RING_TYPE 2
680
681 u8 in_use;
682#define MSIX_REGISTERED_SUCCESS 0xAA
683};
684
685struct msix_info_st {
686 u64 addr;
687 u64 data;
688};
689
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500690/* Data structure to represent a LRO session */
691typedef struct lro {
692 struct sk_buff *parent;
693 u8 *l2h;
694 struct iphdr *iph;
695 struct tcphdr *tcph;
696 u32 tcp_next_seq;
697 u32 tcp_ack;
698 int total_len;
699 int frags_len;
700 int sg_num;
701 int in_use;
702 u16 window;
703 u32 cur_tsval;
704 u32 cur_tsecr;
705 u8 saw_ts;
706}lro_t;
707
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708/* Structure representing one instance of the NIC */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700709struct s2io_nic {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500710 int rxd_mode;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700711#ifdef CONFIG_S2IO_NAPI
712 /*
713 * Count of packets to be processed in a given iteration, it will be indicated
714 * by the quota field of the device structure when NAPI is enabled.
715 */
716 int pkts_to_process;
717#endif
718 struct net_device *dev;
719 mac_info_t mac_control;
720 struct config_param config;
721 struct pci_dev *pdev;
722 void __iomem *bar0;
723 void __iomem *bar1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724#define MAX_MAC_SUPPORTED 16
725#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
726
727 macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
728 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
729
730 struct net_device_stats stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731 int high_dma_flag;
732 int device_close_flag;
733 int device_enabled_once;
734
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700735 char name[50];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736 struct tasklet_struct task;
737 volatile unsigned long tasklet_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -0700739 /* Timer that handles I/O errors/exceptions */
740 struct timer_list alarm_timer;
741
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700742 /* Space to back up the PCI config space */
743 u32 config_space[256 / sizeof(u32)];
744
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 atomic_t rx_bufs_left[MAX_RX_RINGS];
746
747 spinlock_t tx_lock;
748#ifndef CONFIG_S2IO_NAPI
749 spinlock_t put_lock;
750#endif
751
752#define PROMISC 1
753#define ALL_MULTI 2
754
755#define MAX_ADDRS_SUPPORTED 64
756 u16 usr_addr_count;
757 u16 mc_addr_count;
758 usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
759
760 u16 m_cast_flg;
761 u16 all_multi_pos;
762 u16 promisc_flg;
763
764 u16 tx_pkt_count;
765 u16 rx_pkt_count;
766 u16 tx_err_count;
767 u16 rx_err_count;
768
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 /* Id timer, used to blink NIC to physically identify NIC. */
770 struct timer_list id_timer;
771
772 /* Restart timer, used to restart NIC if the device is stuck and
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700773 * a schedule task that will set the correct Link state once the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 * NIC's PHY has stabilized after a state change.
775 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 struct work_struct rst_timer_task;
777 struct work_struct set_link_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700779 /* Flag that can be used to turn on or turn off the Rx checksum
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 * offload feature.
781 */
782 int rx_csum;
783
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700784 /* after blink, the adapter must be restored with original
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785 * values.
786 */
787 u64 adapt_ctrl_org;
788
789 /* Last known link state. */
790 u16 last_link_state;
791#define LINK_DOWN 1
792#define LINK_UP 2
793
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 int task_flag;
795#define CARD_DOWN 1
796#define CARD_UP 2
797 atomic_t card_state;
798 volatile unsigned long link_state;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700799 struct vlan_group *vlgrp;
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400800#define MSIX_FLG 0xA5
801 struct msix_entry *entries;
802 struct s2io_msix_entry *s2io_entries;
803 char desc1[35];
804 char desc2[35];
805
806 struct msix_info_st msix_info[0x3f];
807
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700808#define XFRAME_I_DEVICE 1
809#define XFRAME_II_DEVICE 2
810 u8 device_type;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700811
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500812#define MAX_LRO_SESSIONS 32
813 lro_t lro0_n[MAX_LRO_SESSIONS];
814 unsigned long clubbed_frms_cnt;
815 unsigned long sending_both;
816 u8 lro;
817 u16 lro_max_aggr_per_sess;
818
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400819#define INTA 0
820#define MSI 1
821#define MSI_X 2
822 u8 intr_type;
823
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700824 spinlock_t rx_lock;
825 atomic_t isr_cnt;
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500826 u64 *ufo_in_band_v;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700827};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828
829#define RESET_ERROR 1;
830#define CMD_ERROR 2;
831
832/* OS related system calls */
833#ifndef readq
834static inline u64 readq(void __iomem *addr)
835{
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700836 u64 ret = 0;
837 ret = readl(addr + 4);
Andrew Morton7ef24b62005-08-25 17:14:46 -0700838 ret <<= 32;
839 ret |= readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840
841 return ret;
842}
843#endif
844
845#ifndef writeq
846static inline void writeq(u64 val, void __iomem *addr)
847{
848 writel((u32) (val), addr);
849 writel((u32) (val >> 32), (addr + 4));
850}
851
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700852/* In 32 bit modes, some registers have to be written in a
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 * particular order to expect correct hardware operation. The
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700854 * macro SPECIAL_REG_WRITE is used to perform such ordered
855 * writes. Defines UF (Upper First) and LF (Lower First) will
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 * be used to specify the required write order.
857 */
858#define UF 1
859#define LF 2
860static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
861{
862 if (order == LF) {
863 writel((u32) (val), addr);
864 writel((u32) (val >> 32), (addr + 4));
865 } else {
866 writel((u32) (val >> 32), (addr + 4));
867 writel((u32) (val), addr);
868 }
869}
870#else
871#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
872#endif
873
874/* Interrupt related values of Xena */
875
876#define ENABLE_INTRS 1
877#define DISABLE_INTRS 2
878
879/* Highest level interrupt blocks */
880#define TX_PIC_INTR (0x0001<<0)
881#define TX_DMA_INTR (0x0001<<1)
882#define TX_MAC_INTR (0x0001<<2)
883#define TX_XGXS_INTR (0x0001<<3)
884#define TX_TRAFFIC_INTR (0x0001<<4)
885#define RX_PIC_INTR (0x0001<<5)
886#define RX_DMA_INTR (0x0001<<6)
887#define RX_MAC_INTR (0x0001<<7)
888#define RX_XGXS_INTR (0x0001<<8)
889#define RX_TRAFFIC_INTR (0x0001<<9)
890#define MC_INTR (0x0001<<10)
891#define ENA_ALL_INTRS ( TX_PIC_INTR | \
892 TX_DMA_INTR | \
893 TX_MAC_INTR | \
894 TX_XGXS_INTR | \
895 TX_TRAFFIC_INTR | \
896 RX_PIC_INTR | \
897 RX_DMA_INTR | \
898 RX_MAC_INTR | \
899 RX_XGXS_INTR | \
900 RX_TRAFFIC_INTR | \
901 MC_INTR )
902
903/* Interrupt masks for the general interrupt mask register */
904#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
905
906#define TXPIC_INT_M BIT(0)
907#define TXDMA_INT_M BIT(1)
908#define TXMAC_INT_M BIT(2)
909#define TXXGXS_INT_M BIT(3)
910#define TXTRAFFIC_INT_M BIT(8)
911#define PIC_RX_INT_M BIT(32)
912#define RXDMA_INT_M BIT(33)
913#define RXMAC_INT_M BIT(34)
914#define MC_INT_M BIT(35)
915#define RXXGXS_INT_M BIT(36)
916#define RXTRAFFIC_INT_M BIT(40)
917
918/* PIC level Interrupts TODO*/
919
920/* DMA level Inressupts */
921#define TXDMA_PFC_INT_M BIT(0)
922#define TXDMA_PCC_INT_M BIT(2)
923
924/* PFC block interrupts */
925#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
926
927/* PCC block interrupts. */
928#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
929 PCC_FB_ECC Error. */
930
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700931#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932/*
933 * Prototype declaration.
934 */
935static int __devinit s2io_init_nic(struct pci_dev *pdev,
936 const struct pci_device_id *pre);
937static void __devexit s2io_rem_nic(struct pci_dev *pdev);
938static int init_shared_mem(struct s2io_nic *sp);
939static void free_shared_mem(struct s2io_nic *sp);
940static int init_nic(struct s2io_nic *nic);
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700941static void rx_intr_handler(ring_info_t *ring_data);
942static void tx_intr_handler(fifo_info_t *fifo_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943static void alarm_intr_handler(struct s2io_nic *sp);
944
945static int s2io_starter(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946static void s2io_tx_watchdog(struct net_device *dev);
947static void s2io_tasklet(unsigned long dev_addr);
948static void s2io_set_multicast(struct net_device *dev);
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700949static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
Adrian Bunk26df54b2006-01-14 03:09:40 +0100950static void s2io_link(nic_t * sp, int link);
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700951#if defined(CONFIG_S2IO_NAPI)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952static int s2io_poll(struct net_device *dev, int *budget);
953#endif
954static void s2io_init_pci(nic_t * sp);
Adrian Bunk26df54b2006-01-14 03:09:40 +0100955static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -0700956static void s2io_alarm_handle(unsigned long data);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400957static int s2io_enable_msi(nic_t *nic);
958static irqreturn_t s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs);
959static irqreturn_t
960s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs);
961static irqreturn_t
962s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700963static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700964static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965static struct ethtool_ops netdev_ethtool_ops;
966static void s2io_set_link(unsigned long data);
Adrian Bunk26df54b2006-01-14 03:09:40 +0100967static int s2io_set_swapper(nic_t * sp);
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700968static void s2io_card_down(nic_t *nic);
969static int s2io_card_up(nic_t *nic);
Adrian Bunk26df54b2006-01-14 03:09:40 +0100970static int get_xena_rev_id(struct pci_dev *pdev);
971static void restore_xmsi_data(nic_t *nic);
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500972
973static int s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro, RxD_t *rxdp, nic_t *sp);
974static void clear_lro_session(lro_t *lro);
975static void queue_rx_frame(struct sk_buff *skb);
976static void update_L3L4_header(nic_t *sp, lro_t *lro);
977static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, u32 tcp_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978#endif /* _S2IO_H */