Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx> |
| 3 | * Copyright (C) 2004 Intel Corp. |
| 4 | * |
| 5 | * This code is released under the GNU General Public License version 2. |
| 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * mmconfig.c - Low-level direct PCI config space access via MMCONFIG |
| 10 | */ |
| 11 | |
| 12 | #include <linux/pci.h> |
| 13 | #include <linux/init.h> |
Greg Kroah-Hartman | 5454939 | 2005-06-23 17:35:56 -0700 | [diff] [blame] | 14 | #include <linux/acpi.h> |
Arjan van de Ven | 946f2ee | 2006-04-07 19:49:30 +0200 | [diff] [blame] | 15 | #include <asm/e820.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include "pci.h" |
| 17 | |
Arjan van de Ven | 946f2ee | 2006-04-07 19:49:30 +0200 | [diff] [blame] | 18 | #define MMCONFIG_APER_SIZE (256*1024*1024) |
| 19 | |
Andi Kleen | 8c30b1a74 | 2006-04-07 19:50:12 +0200 | [diff] [blame] | 20 | /* Assume systems with more busses have correct MCFG */ |
| 21 | #define MAX_CHECK_BUS 16 |
| 22 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG)) |
| 24 | |
| 25 | /* The base address of the last MMCONFIG device accessed */ |
| 26 | static u32 mmcfg_last_accessed_device; |
| 27 | |
Andi Kleen | 8c30b1a74 | 2006-04-07 19:50:12 +0200 | [diff] [blame] | 28 | static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32); |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 29 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | /* |
| 31 | * Functions for accessing PCI configuration space with MMCONFIG accesses |
| 32 | */ |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 33 | static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | { |
Greg Kroah-Hartman | d57e26c | 2005-06-23 17:35:56 -0700 | [diff] [blame] | 35 | int cfg_num = -1; |
| 36 | struct acpi_table_mcfg_config *cfg; |
| 37 | |
Andi Kleen | 8c30b1a74 | 2006-04-07 19:50:12 +0200 | [diff] [blame] | 38 | if (seg == 0 && bus < MAX_CHECK_BUS && |
| 39 | test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots)) |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 40 | return 0; |
| 41 | |
Greg Kroah-Hartman | d57e26c | 2005-06-23 17:35:56 -0700 | [diff] [blame] | 42 | while (1) { |
| 43 | ++cfg_num; |
| 44 | if (cfg_num >= pci_mmcfg_config_num) { |
Andi Kleen | 3103039 | 2006-01-27 02:03:50 +0100 | [diff] [blame] | 45 | break; |
Greg Kroah-Hartman | d57e26c | 2005-06-23 17:35:56 -0700 | [diff] [blame] | 46 | } |
| 47 | cfg = &pci_mmcfg_config[cfg_num]; |
| 48 | if (cfg->pci_segment_group_number != seg) |
| 49 | continue; |
| 50 | if ((cfg->start_bus_number <= bus) && |
| 51 | (cfg->end_bus_number >= bus)) |
| 52 | return cfg->base_address; |
| 53 | } |
Andi Kleen | 3103039 | 2006-01-27 02:03:50 +0100 | [diff] [blame] | 54 | |
| 55 | /* Handle more broken MCFG tables on Asus etc. |
| 56 | They only contain a single entry for bus 0-0. Assume |
| 57 | this applies to all busses. */ |
| 58 | cfg = &pci_mmcfg_config[0]; |
| 59 | if (pci_mmcfg_config_num == 1 && |
| 60 | cfg->pci_segment_group_number == 0 && |
| 61 | (cfg->start_bus_number | cfg->end_bus_number) == 0) |
| 62 | return cfg->base_address; |
| 63 | |
| 64 | /* Fall back to type 0 */ |
| 65 | return 0; |
Greg Kroah-Hartman | d57e26c | 2005-06-23 17:35:56 -0700 | [diff] [blame] | 66 | } |
| 67 | |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 68 | static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn) |
Greg Kroah-Hartman | d57e26c | 2005-06-23 17:35:56 -0700 | [diff] [blame] | 69 | { |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 70 | u32 dev_base = base | (bus << 20) | (devfn << 12); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | if (dev_base != mmcfg_last_accessed_device) { |
| 72 | mmcfg_last_accessed_device = dev_base; |
| 73 | set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | static int pci_mmcfg_read(unsigned int seg, unsigned int bus, |
| 78 | unsigned int devfn, int reg, int len, u32 *value) |
| 79 | { |
| 80 | unsigned long flags; |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 81 | u32 base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | |
Andi Kleen | 49c93e8 | 2006-04-07 19:50:15 +0200 | [diff] [blame] | 83 | if (!value || (bus > 255) || (devfn > 255) || (reg > 4095)) { |
| 84 | *value = -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | return -EINVAL; |
Andi Kleen | 49c93e8 | 2006-04-07 19:50:15 +0200 | [diff] [blame] | 86 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 88 | base = get_base_addr(seg, bus, devfn); |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 89 | if (!base) |
| 90 | return pci_conf1_read(seg,bus,devfn,reg,len,value); |
| 91 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | spin_lock_irqsave(&pci_config_lock, flags); |
| 93 | |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 94 | pci_exp_set_dev_base(base, bus, devfn); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | |
| 96 | switch (len) { |
| 97 | case 1: |
| 98 | *value = readb(mmcfg_virt_addr + reg); |
| 99 | break; |
| 100 | case 2: |
| 101 | *value = readw(mmcfg_virt_addr + reg); |
| 102 | break; |
| 103 | case 4: |
| 104 | *value = readl(mmcfg_virt_addr + reg); |
| 105 | break; |
| 106 | } |
| 107 | |
| 108 | spin_unlock_irqrestore(&pci_config_lock, flags); |
| 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | static int pci_mmcfg_write(unsigned int seg, unsigned int bus, |
| 114 | unsigned int devfn, int reg, int len, u32 value) |
| 115 | { |
| 116 | unsigned long flags; |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 117 | u32 base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | |
| 119 | if ((bus > 255) || (devfn > 255) || (reg > 4095)) |
| 120 | return -EINVAL; |
| 121 | |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 122 | base = get_base_addr(seg, bus, devfn); |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 123 | if (!base) |
| 124 | return pci_conf1_write(seg,bus,devfn,reg,len,value); |
| 125 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | spin_lock_irqsave(&pci_config_lock, flags); |
| 127 | |
Andi Kleen | 928cf8c | 2005-12-12 22:17:10 -0800 | [diff] [blame] | 128 | pci_exp_set_dev_base(base, bus, devfn); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | |
| 130 | switch (len) { |
| 131 | case 1: |
| 132 | writeb(value, mmcfg_virt_addr + reg); |
| 133 | break; |
| 134 | case 2: |
| 135 | writew(value, mmcfg_virt_addr + reg); |
| 136 | break; |
| 137 | case 4: |
| 138 | writel(value, mmcfg_virt_addr + reg); |
| 139 | break; |
| 140 | } |
| 141 | |
| 142 | spin_unlock_irqrestore(&pci_config_lock, flags); |
| 143 | |
| 144 | return 0; |
| 145 | } |
| 146 | |
| 147 | static struct pci_raw_ops pci_mmcfg = { |
| 148 | .read = pci_mmcfg_read, |
| 149 | .write = pci_mmcfg_write, |
| 150 | }; |
| 151 | |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 152 | /* K8 systems have some devices (typically in the builtin northbridge) |
| 153 | that are only accessible using type1 |
| 154 | Normally this can be expressed in the MCFG by not listing them |
| 155 | and assigning suitable _SEGs, but this isn't implemented in some BIOS. |
| 156 | Instead try to discover all devices on bus 0 that are unreachable using MM |
Andi Kleen | 8c30b1a74 | 2006-04-07 19:50:12 +0200 | [diff] [blame] | 157 | and fallback for them. */ |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 158 | static __init void unreachable_devices(void) |
| 159 | { |
Andi Kleen | 8c30b1a74 | 2006-04-07 19:50:12 +0200 | [diff] [blame] | 160 | int i, k; |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 161 | unsigned long flags; |
| 162 | |
Andi Kleen | 8c30b1a74 | 2006-04-07 19:50:12 +0200 | [diff] [blame] | 163 | for (k = 0; k < MAX_CHECK_BUS; k++) { |
| 164 | for (i = 0; i < 32; i++) { |
| 165 | u32 val1; |
| 166 | u32 addr; |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 167 | |
Andi Kleen | 8c30b1a74 | 2006-04-07 19:50:12 +0200 | [diff] [blame] | 168 | pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1); |
| 169 | if (val1 == 0xffffffff) |
| 170 | continue; |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 171 | |
Andi Kleen | 8c30b1a74 | 2006-04-07 19:50:12 +0200 | [diff] [blame] | 172 | /* Locking probably not needed, but safer */ |
| 173 | spin_lock_irqsave(&pci_config_lock, flags); |
| 174 | addr = get_base_addr(0, k, PCI_DEVFN(i, 0)); |
| 175 | if (addr != 0) |
| 176 | pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0)); |
| 177 | if (addr == 0 || |
| 178 | readl((u32 __iomem *)mmcfg_virt_addr) != val1) { |
| 179 | set_bit(i, fallback_slots); |
| 180 | printk(KERN_NOTICE |
| 181 | "PCI: No mmconfig possible on %x:%x\n", k, i); |
| 182 | } |
| 183 | spin_unlock_irqrestore(&pci_config_lock, flags); |
| 184 | } |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 185 | } |
| 186 | } |
| 187 | |
Andi Kleen | 92c05fc | 2006-03-23 14:35:12 -0800 | [diff] [blame] | 188 | void __init pci_mmcfg_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | { |
| 190 | if ((pci_probe & PCI_PROBE_MMCONF) == 0) |
Andi Kleen | 92c05fc | 2006-03-23 14:35:12 -0800 | [diff] [blame] | 191 | return; |
Greg Kroah-Hartman | 5454939 | 2005-06-23 17:35:56 -0700 | [diff] [blame] | 192 | |
| 193 | acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg); |
| 194 | if ((pci_mmcfg_config_num == 0) || |
| 195 | (pci_mmcfg_config == NULL) || |
| 196 | (pci_mmcfg_config[0].base_address == 0)) |
Andi Kleen | 92c05fc | 2006-03-23 14:35:12 -0800 | [diff] [blame] | 197 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 198 | |
Arjan van de Ven | 946f2ee | 2006-04-07 19:49:30 +0200 | [diff] [blame] | 199 | if (!e820_all_mapped(pci_mmcfg_config[0].base_address, |
| 200 | pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE, |
| 201 | E820_RESERVED)) { |
| 202 | printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n"); |
| 203 | printk(KERN_ERR "PCI: Not using MMCONFIG.\n"); |
| 204 | return; |
| 205 | } |
| 206 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | printk(KERN_INFO "PCI: Using MMCONFIG\n"); |
| 208 | raw_pci_ops = &pci_mmcfg; |
| 209 | pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; |
| 210 | |
Andi Kleen | d6ece54 | 2005-12-12 22:17:11 -0800 | [diff] [blame] | 211 | unreachable_devices(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | } |