Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 29 | #include <drm/drm_vma_manager.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 34 | #include <linux/oom.h> |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 35 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 36 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 37 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 39 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 40 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 43 | bool force); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 44 | static __must_check int |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 46 | bool readonly); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 47 | static void |
| 48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); |
| 49 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 51 | struct drm_i915_gem_object *obj); |
| 52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 53 | struct drm_i915_fence_reg *fence, |
| 54 | bool enable); |
| 55 | |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 57 | struct shrink_control *sc); |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 59 | struct shrink_control *sc); |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
| 61 | unsigned long event, |
| 62 | void *ptr); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 63 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
| 64 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 65 | |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 66 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 67 | enum i915_cache_level level) |
| 68 | { |
| 69 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 70 | } |
| 71 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 72 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 73 | { |
| 74 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 75 | return true; |
| 76 | |
| 77 | return obj->pin_display; |
| 78 | } |
| 79 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 80 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 81 | { |
| 82 | if (obj->tiling_mode) |
| 83 | i915_gem_release_mmap(obj); |
| 84 | |
| 85 | /* As we do not have an associated fence register, we will force |
| 86 | * a tiling change if we ever need to acquire one. |
| 87 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 88 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 89 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 90 | } |
| 91 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 92 | /* some bookkeeping */ |
| 93 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 94 | size_t size) |
| 95 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 97 | dev_priv->mm.object_count++; |
| 98 | dev_priv->mm.object_memory += size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 103 | size_t size) |
| 104 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 105 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 106 | dev_priv->mm.object_count--; |
| 107 | dev_priv->mm.object_memory -= size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 108 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 109 | } |
| 110 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 111 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 112 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 113 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 114 | int ret; |
| 115 | |
Daniel Vetter | 7abb690 | 2013-05-24 21:29:32 +0200 | [diff] [blame] | 116 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
| 117 | i915_terminally_wedged(error)) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 118 | if (EXIT_COND) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 119 | return 0; |
| 120 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 121 | /* |
| 122 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 123 | * userspace. If it takes that long something really bad is going on and |
| 124 | * we should simply try to bail out and fail as gracefully as possible. |
| 125 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 126 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 127 | EXIT_COND, |
| 128 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 129 | if (ret == 0) { |
| 130 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 131 | return -EIO; |
| 132 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 133 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 134 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 135 | #undef EXIT_COND |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 136 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 137 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 138 | } |
| 139 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 140 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 141 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 143 | int ret; |
| 144 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 145 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 146 | if (ret) |
| 147 | return ret; |
| 148 | |
| 149 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 150 | if (ret) |
| 151 | return ret; |
| 152 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 153 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 154 | return 0; |
| 155 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 156 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 157 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 158 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 159 | { |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 160 | return i915_gem_obj_bound_any(obj) && !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 161 | } |
| 162 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 163 | int |
| 164 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 165 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 166 | { |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 168 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 169 | |
Daniel Vetter | 7bb6fb8 | 2012-04-24 08:22:52 +0200 | [diff] [blame] | 170 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 171 | return -ENODEV; |
| 172 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 173 | if (args->gtt_start >= args->gtt_end || |
| 174 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 175 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 176 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 177 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 178 | if (INTEL_INFO(dev)->gen >= 5) |
| 179 | return -ENODEV; |
| 180 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 181 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 182 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
| 183 | args->gtt_end); |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 184 | dev_priv->gtt.mappable_end = args->gtt_end; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 185 | mutex_unlock(&dev->struct_mutex); |
| 186 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 187 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 188 | } |
| 189 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 190 | int |
| 191 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 192 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 193 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 194 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 195 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 196 | struct drm_i915_gem_object *obj; |
| 197 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 198 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 199 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 200 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 201 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 202 | if (i915_gem_obj_is_pinned(obj)) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 203 | pinned += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 204 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 205 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 206 | args->aper_size = dev_priv->gtt.base.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 207 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 208 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 209 | return 0; |
| 210 | } |
| 211 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 212 | static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj) |
| 213 | { |
| 214 | drm_dma_handle_t *phys = obj->phys_handle; |
| 215 | |
| 216 | if (!phys) |
| 217 | return; |
| 218 | |
| 219 | if (obj->madv == I915_MADV_WILLNEED) { |
| 220 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 221 | char *vaddr = phys->vaddr; |
| 222 | int i; |
| 223 | |
| 224 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 225 | struct page *page = shmem_read_mapping_page(mapping, i); |
| 226 | if (!IS_ERR(page)) { |
| 227 | char *dst = kmap_atomic(page); |
| 228 | memcpy(dst, vaddr, PAGE_SIZE); |
| 229 | drm_clflush_virt_range(dst, PAGE_SIZE); |
| 230 | kunmap_atomic(dst); |
| 231 | |
| 232 | set_page_dirty(page); |
| 233 | mark_page_accessed(page); |
| 234 | page_cache_release(page); |
| 235 | } |
| 236 | vaddr += PAGE_SIZE; |
| 237 | } |
| 238 | i915_gem_chipset_flush(obj->base.dev); |
| 239 | } |
| 240 | |
| 241 | #ifdef CONFIG_X86 |
| 242 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); |
| 243 | #endif |
| 244 | drm_pci_free(obj->base.dev, phys); |
| 245 | obj->phys_handle = NULL; |
| 246 | } |
| 247 | |
| 248 | int |
| 249 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
| 250 | int align) |
| 251 | { |
| 252 | drm_dma_handle_t *phys; |
| 253 | struct address_space *mapping; |
| 254 | char *vaddr; |
| 255 | int i; |
| 256 | |
| 257 | if (obj->phys_handle) { |
| 258 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) |
| 259 | return -EBUSY; |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | if (obj->madv != I915_MADV_WILLNEED) |
| 265 | return -EFAULT; |
| 266 | |
| 267 | if (obj->base.filp == NULL) |
| 268 | return -EINVAL; |
| 269 | |
| 270 | /* create a new object */ |
| 271 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); |
| 272 | if (!phys) |
| 273 | return -ENOMEM; |
| 274 | |
| 275 | vaddr = phys->vaddr; |
| 276 | #ifdef CONFIG_X86 |
| 277 | set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE); |
| 278 | #endif |
| 279 | mapping = file_inode(obj->base.filp)->i_mapping; |
| 280 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 281 | struct page *page; |
| 282 | char *src; |
| 283 | |
| 284 | page = shmem_read_mapping_page(mapping, i); |
| 285 | if (IS_ERR(page)) { |
| 286 | #ifdef CONFIG_X86 |
| 287 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); |
| 288 | #endif |
| 289 | drm_pci_free(obj->base.dev, phys); |
| 290 | return PTR_ERR(page); |
| 291 | } |
| 292 | |
| 293 | src = kmap_atomic(page); |
| 294 | memcpy(vaddr, src, PAGE_SIZE); |
| 295 | kunmap_atomic(src); |
| 296 | |
| 297 | mark_page_accessed(page); |
| 298 | page_cache_release(page); |
| 299 | |
| 300 | vaddr += PAGE_SIZE; |
| 301 | } |
| 302 | |
| 303 | obj->phys_handle = phys; |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | static int |
| 308 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, |
| 309 | struct drm_i915_gem_pwrite *args, |
| 310 | struct drm_file *file_priv) |
| 311 | { |
| 312 | struct drm_device *dev = obj->base.dev; |
| 313 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
| 314 | char __user *user_data = to_user_ptr(args->data_ptr); |
| 315 | |
| 316 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 317 | unsigned long unwritten; |
| 318 | |
| 319 | /* The physical object once assigned is fixed for the lifetime |
| 320 | * of the obj, so we can safely drop the lock and continue |
| 321 | * to access vaddr. |
| 322 | */ |
| 323 | mutex_unlock(&dev->struct_mutex); |
| 324 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 325 | mutex_lock(&dev->struct_mutex); |
| 326 | if (unwritten) |
| 327 | return -EFAULT; |
| 328 | } |
| 329 | |
| 330 | i915_gem_chipset_flush(dev); |
| 331 | return 0; |
| 332 | } |
| 333 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 334 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 335 | { |
| 336 | struct drm_i915_private *dev_priv = dev->dev_private; |
Joe Perches | fac15c1 | 2013-08-29 13:11:07 -0700 | [diff] [blame] | 337 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 338 | } |
| 339 | |
| 340 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 341 | { |
| 342 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 343 | kmem_cache_free(dev_priv->slab, obj); |
| 344 | } |
| 345 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 346 | static int |
| 347 | i915_gem_create(struct drm_file *file, |
| 348 | struct drm_device *dev, |
| 349 | uint64_t size, |
| 350 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 351 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 352 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 353 | int ret; |
| 354 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 355 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 356 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 357 | if (size == 0) |
| 358 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 359 | |
| 360 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 361 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 362 | if (obj == NULL) |
| 363 | return -ENOMEM; |
| 364 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 365 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 366 | /* drop reference from allocate - handle holds it now */ |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 367 | drm_gem_object_unreference_unlocked(&obj->base); |
| 368 | if (ret) |
| 369 | return ret; |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 370 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 371 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 372 | return 0; |
| 373 | } |
| 374 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 375 | int |
| 376 | i915_gem_dumb_create(struct drm_file *file, |
| 377 | struct drm_device *dev, |
| 378 | struct drm_mode_create_dumb *args) |
| 379 | { |
| 380 | /* have to work out size/pitch and return them */ |
Paulo Zanoni | de45eaf | 2013-10-18 18:48:24 -0300 | [diff] [blame] | 381 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 382 | args->size = args->pitch * args->height; |
| 383 | return i915_gem_create(file, dev, |
| 384 | args->size, &args->handle); |
| 385 | } |
| 386 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 387 | /** |
| 388 | * Creates a new mm object and returns a handle to it. |
| 389 | */ |
| 390 | int |
| 391 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 392 | struct drm_file *file) |
| 393 | { |
| 394 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 395 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 396 | return i915_gem_create(file, dev, |
| 397 | args->size, &args->handle); |
| 398 | } |
| 399 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 400 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 401 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 402 | const char *gpu_vaddr, int gpu_offset, |
| 403 | int length) |
| 404 | { |
| 405 | int ret, cpu_offset = 0; |
| 406 | |
| 407 | while (length > 0) { |
| 408 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 409 | int this_length = min(cacheline_end - gpu_offset, length); |
| 410 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 411 | |
| 412 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 413 | gpu_vaddr + swizzled_gpu_offset, |
| 414 | this_length); |
| 415 | if (ret) |
| 416 | return ret + length; |
| 417 | |
| 418 | cpu_offset += this_length; |
| 419 | gpu_offset += this_length; |
| 420 | length -= this_length; |
| 421 | } |
| 422 | |
| 423 | return 0; |
| 424 | } |
| 425 | |
| 426 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 427 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 428 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 429 | int length) |
| 430 | { |
| 431 | int ret, cpu_offset = 0; |
| 432 | |
| 433 | while (length > 0) { |
| 434 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 435 | int this_length = min(cacheline_end - gpu_offset, length); |
| 436 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 437 | |
| 438 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 439 | cpu_vaddr + cpu_offset, |
| 440 | this_length); |
| 441 | if (ret) |
| 442 | return ret + length; |
| 443 | |
| 444 | cpu_offset += this_length; |
| 445 | gpu_offset += this_length; |
| 446 | length -= this_length; |
| 447 | } |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 452 | /* |
| 453 | * Pins the specified object's pages and synchronizes the object with |
| 454 | * GPU accesses. Sets needs_clflush to non-zero if the caller should |
| 455 | * flush the object from the CPU cache. |
| 456 | */ |
| 457 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 458 | int *needs_clflush) |
| 459 | { |
| 460 | int ret; |
| 461 | |
| 462 | *needs_clflush = 0; |
| 463 | |
| 464 | if (!obj->base.filp) |
| 465 | return -EINVAL; |
| 466 | |
| 467 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 468 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 469 | * read domain and manually flush cachelines (if required). This |
| 470 | * optimizes for the case when the gpu will dirty the data |
| 471 | * anyway again before the next pread happens. */ |
| 472 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
| 473 | obj->cache_level); |
| 474 | ret = i915_gem_object_wait_rendering(obj, true); |
| 475 | if (ret) |
| 476 | return ret; |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 477 | |
| 478 | i915_gem_object_retire(obj); |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 479 | } |
| 480 | |
| 481 | ret = i915_gem_object_get_pages(obj); |
| 482 | if (ret) |
| 483 | return ret; |
| 484 | |
| 485 | i915_gem_object_pin_pages(obj); |
| 486 | |
| 487 | return ret; |
| 488 | } |
| 489 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 490 | /* Per-page copy function for the shmem pread fastpath. |
| 491 | * Flushes invalid cachelines before reading the target if |
| 492 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 493 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 494 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 495 | char __user *user_data, |
| 496 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 497 | { |
| 498 | char *vaddr; |
| 499 | int ret; |
| 500 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 501 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 502 | return -EINVAL; |
| 503 | |
| 504 | vaddr = kmap_atomic(page); |
| 505 | if (needs_clflush) |
| 506 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 507 | page_length); |
| 508 | ret = __copy_to_user_inatomic(user_data, |
| 509 | vaddr + shmem_page_offset, |
| 510 | page_length); |
| 511 | kunmap_atomic(vaddr); |
| 512 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 513 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 514 | } |
| 515 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 516 | static void |
| 517 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 518 | bool swizzled) |
| 519 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 520 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 521 | unsigned long start = (unsigned long) addr; |
| 522 | unsigned long end = (unsigned long) addr + length; |
| 523 | |
| 524 | /* For swizzling simply ensure that we always flush both |
| 525 | * channels. Lame, but simple and it works. Swizzled |
| 526 | * pwrite/pread is far from a hotpath - current userspace |
| 527 | * doesn't use it at all. */ |
| 528 | start = round_down(start, 128); |
| 529 | end = round_up(end, 128); |
| 530 | |
| 531 | drm_clflush_virt_range((void *)start, end - start); |
| 532 | } else { |
| 533 | drm_clflush_virt_range(addr, length); |
| 534 | } |
| 535 | |
| 536 | } |
| 537 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 538 | /* Only difference to the fast-path function is that this can handle bit17 |
| 539 | * and uses non-atomic copy and kmap functions. */ |
| 540 | static int |
| 541 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 542 | char __user *user_data, |
| 543 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 544 | { |
| 545 | char *vaddr; |
| 546 | int ret; |
| 547 | |
| 548 | vaddr = kmap(page); |
| 549 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 550 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 551 | page_length, |
| 552 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 553 | |
| 554 | if (page_do_bit17_swizzling) |
| 555 | ret = __copy_to_user_swizzled(user_data, |
| 556 | vaddr, shmem_page_offset, |
| 557 | page_length); |
| 558 | else |
| 559 | ret = __copy_to_user(user_data, |
| 560 | vaddr + shmem_page_offset, |
| 561 | page_length); |
| 562 | kunmap(page); |
| 563 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 564 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 565 | } |
| 566 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 567 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 568 | i915_gem_shmem_pread(struct drm_device *dev, |
| 569 | struct drm_i915_gem_object *obj, |
| 570 | struct drm_i915_gem_pread *args, |
| 571 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 572 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 573 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 574 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 575 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 576 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 577 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 578 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 579 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 580 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 581 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 582 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 583 | remain = args->size; |
| 584 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 585 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 586 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 587 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 588 | if (ret) |
| 589 | return ret; |
| 590 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 591 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 592 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 593 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 594 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 595 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 596 | |
| 597 | if (remain <= 0) |
| 598 | break; |
| 599 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 600 | /* Operation in this page |
| 601 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 602 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 603 | * page_length = bytes to copy for this page |
| 604 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 605 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 606 | page_length = remain; |
| 607 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 608 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 609 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 610 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 611 | (page_to_phys(page) & (1 << 17)) != 0; |
| 612 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 613 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 614 | user_data, page_do_bit17_swizzling, |
| 615 | needs_clflush); |
| 616 | if (ret == 0) |
| 617 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 618 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 619 | mutex_unlock(&dev->struct_mutex); |
| 620 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 621 | if (likely(!i915.prefault_disable) && !prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 622 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 623 | /* Userspace is tricking us, but we've already clobbered |
| 624 | * its pages with the prefault and promised to write the |
| 625 | * data up to the first fault. Hence ignore any errors |
| 626 | * and just continue. */ |
| 627 | (void)ret; |
| 628 | prefaulted = 1; |
| 629 | } |
| 630 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 631 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 632 | user_data, page_do_bit17_swizzling, |
| 633 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 634 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 635 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 636 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 637 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 638 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 639 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 640 | next_page: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 641 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 642 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 643 | offset += page_length; |
| 644 | } |
| 645 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 646 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 647 | i915_gem_object_unpin_pages(obj); |
| 648 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 649 | return ret; |
| 650 | } |
| 651 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 652 | /** |
| 653 | * Reads data from the object referenced by handle. |
| 654 | * |
| 655 | * On error, the contents of *data are undefined. |
| 656 | */ |
| 657 | int |
| 658 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 659 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 660 | { |
| 661 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 662 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 663 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 664 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 665 | if (args->size == 0) |
| 666 | return 0; |
| 667 | |
| 668 | if (!access_ok(VERIFY_WRITE, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 669 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 670 | args->size)) |
| 671 | return -EFAULT; |
| 672 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 673 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 674 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 675 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 676 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 677 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 678 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 679 | ret = -ENOENT; |
| 680 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 681 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 682 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 683 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 684 | if (args->offset > obj->base.size || |
| 685 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 686 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 687 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 688 | } |
| 689 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 690 | /* prime objects have no backing filp to GEM pread/pwrite |
| 691 | * pages from. |
| 692 | */ |
| 693 | if (!obj->base.filp) { |
| 694 | ret = -EINVAL; |
| 695 | goto out; |
| 696 | } |
| 697 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 698 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 699 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 700 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 701 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 702 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 703 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 704 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 705 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 706 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 707 | } |
| 708 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 709 | /* This is the fast write path which cannot handle |
| 710 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 711 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 712 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 713 | static inline int |
| 714 | fast_user_write(struct io_mapping *mapping, |
| 715 | loff_t page_base, int page_offset, |
| 716 | char __user *user_data, |
| 717 | int length) |
| 718 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 719 | void __iomem *vaddr_atomic; |
| 720 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 721 | unsigned long unwritten; |
| 722 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 723 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 724 | /* We can use the cpu mem copy function because this is X86. */ |
| 725 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 726 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 727 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 728 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 729 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 730 | } |
| 731 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 732 | /** |
| 733 | * This is the fast pwrite path, where we copy the data directly from the |
| 734 | * user into the GTT, uncached. |
| 735 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 736 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 737 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 738 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 739 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 740 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 741 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 742 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 743 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 744 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 745 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 746 | int page_offset, page_length, ret; |
| 747 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 748 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 749 | if (ret) |
| 750 | goto out; |
| 751 | |
| 752 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 753 | if (ret) |
| 754 | goto out_unpin; |
| 755 | |
| 756 | ret = i915_gem_object_put_fence(obj); |
| 757 | if (ret) |
| 758 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 759 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 760 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 761 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 762 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 763 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 764 | |
| 765 | while (remain > 0) { |
| 766 | /* Operation in this page |
| 767 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 768 | * page_base = page offset within aperture |
| 769 | * page_offset = offset within page |
| 770 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 771 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 772 | page_base = offset & PAGE_MASK; |
| 773 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 774 | page_length = remain; |
| 775 | if ((page_offset + remain) > PAGE_SIZE) |
| 776 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 777 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 778 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 779 | * source page isn't available. Return the error and we'll |
| 780 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 781 | */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 782 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 783 | page_offset, user_data, page_length)) { |
| 784 | ret = -EFAULT; |
| 785 | goto out_unpin; |
| 786 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 787 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 788 | remain -= page_length; |
| 789 | user_data += page_length; |
| 790 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 791 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 792 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 793 | out_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 794 | i915_gem_object_ggtt_unpin(obj); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 795 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 796 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 797 | } |
| 798 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 799 | /* Per-page copy function for the shmem pwrite fastpath. |
| 800 | * Flushes invalid cachelines before writing to the target if |
| 801 | * needs_clflush_before is set and flushes out any written cachelines after |
| 802 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 803 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 804 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 805 | char __user *user_data, |
| 806 | bool page_do_bit17_swizzling, |
| 807 | bool needs_clflush_before, |
| 808 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 809 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 810 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 811 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 812 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 813 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 814 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 815 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 816 | vaddr = kmap_atomic(page); |
| 817 | if (needs_clflush_before) |
| 818 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 819 | page_length); |
Chris Wilson | c2831a9 | 2014-03-07 08:30:37 +0000 | [diff] [blame] | 820 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
| 821 | user_data, page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 822 | if (needs_clflush_after) |
| 823 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 824 | page_length); |
| 825 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 826 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 827 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 828 | } |
| 829 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 830 | /* Only difference to the fast-path function is that this can handle bit17 |
| 831 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 832 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 833 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 834 | char __user *user_data, |
| 835 | bool page_do_bit17_swizzling, |
| 836 | bool needs_clflush_before, |
| 837 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 838 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 839 | char *vaddr; |
| 840 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 841 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 842 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 843 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 844 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 845 | page_length, |
| 846 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 847 | if (page_do_bit17_swizzling) |
| 848 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 849 | user_data, |
| 850 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 851 | else |
| 852 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 853 | user_data, |
| 854 | page_length); |
| 855 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 856 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 857 | page_length, |
| 858 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 859 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 860 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 861 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 862 | } |
| 863 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 864 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 865 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 866 | struct drm_i915_gem_object *obj, |
| 867 | struct drm_i915_gem_pwrite *args, |
| 868 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 869 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 870 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 871 | loff_t offset; |
| 872 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 873 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 874 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 875 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 876 | int needs_clflush_after = 0; |
| 877 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 878 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 879 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 880 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 881 | remain = args->size; |
| 882 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 883 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 884 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 885 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 886 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 887 | * write domain and manually flush cachelines (if required). This |
| 888 | * optimizes for the case when the gpu will use the data |
| 889 | * right away and we therefore have to clflush anyway. */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 890 | needs_clflush_after = cpu_write_needs_clflush(obj); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 891 | ret = i915_gem_object_wait_rendering(obj, false); |
| 892 | if (ret) |
| 893 | return ret; |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 894 | |
| 895 | i915_gem_object_retire(obj); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 896 | } |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 897 | /* Same trick applies to invalidate partially written cachelines read |
| 898 | * before writing. */ |
| 899 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 900 | needs_clflush_before = |
| 901 | !cpu_cache_is_coherent(dev, obj->cache_level); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 902 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 903 | ret = i915_gem_object_get_pages(obj); |
| 904 | if (ret) |
| 905 | return ret; |
| 906 | |
| 907 | i915_gem_object_pin_pages(obj); |
| 908 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 909 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 910 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 911 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 912 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 913 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 914 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 915 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 916 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 917 | if (remain <= 0) |
| 918 | break; |
| 919 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 920 | /* Operation in this page |
| 921 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 922 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 923 | * page_length = bytes to copy for this page |
| 924 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 925 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 926 | |
| 927 | page_length = remain; |
| 928 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 929 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 930 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 931 | /* If we don't overwrite a cacheline completely we need to be |
| 932 | * careful to have up-to-date data by first clflushing. Don't |
| 933 | * overcomplicate things and flush the entire patch. */ |
| 934 | partial_cacheline_write = needs_clflush_before && |
| 935 | ((shmem_page_offset | page_length) |
| 936 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 937 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 938 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 939 | (page_to_phys(page) & (1 << 17)) != 0; |
| 940 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 941 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 942 | user_data, page_do_bit17_swizzling, |
| 943 | partial_cacheline_write, |
| 944 | needs_clflush_after); |
| 945 | if (ret == 0) |
| 946 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 947 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 948 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 949 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 950 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 951 | user_data, page_do_bit17_swizzling, |
| 952 | partial_cacheline_write, |
| 953 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 954 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 955 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 956 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 957 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 958 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 959 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 960 | next_page: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 961 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 962 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 963 | offset += page_length; |
| 964 | } |
| 965 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 966 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 967 | i915_gem_object_unpin_pages(obj); |
| 968 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 969 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 970 | /* |
| 971 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 972 | * cachelines in-line while writing and the object moved |
| 973 | * out of the cpu write domain while we've dropped the lock. |
| 974 | */ |
| 975 | if (!needs_clflush_after && |
| 976 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 977 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 978 | i915_gem_chipset_flush(dev); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 979 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 980 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 981 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 982 | if (needs_clflush_after) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 983 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 984 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 985 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 986 | } |
| 987 | |
| 988 | /** |
| 989 | * Writes data to the object referenced by handle. |
| 990 | * |
| 991 | * On error, the contents of the buffer that were to be modified are undefined. |
| 992 | */ |
| 993 | int |
| 994 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 995 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 996 | { |
| 997 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 998 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 999 | int ret; |
| 1000 | |
| 1001 | if (args->size == 0) |
| 1002 | return 0; |
| 1003 | |
| 1004 | if (!access_ok(VERIFY_READ, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 1005 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1006 | args->size)) |
| 1007 | return -EFAULT; |
| 1008 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1009 | if (likely(!i915.prefault_disable)) { |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 1010 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 1011 | args->size); |
| 1012 | if (ret) |
| 1013 | return -EFAULT; |
| 1014 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1015 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1016 | ret = i915_mutex_lock_interruptible(dev); |
| 1017 | if (ret) |
| 1018 | return ret; |
| 1019 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1020 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1021 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1022 | ret = -ENOENT; |
| 1023 | goto unlock; |
| 1024 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1025 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1026 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1027 | if (args->offset > obj->base.size || |
| 1028 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1029 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1030 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1031 | } |
| 1032 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1033 | /* prime objects have no backing filp to GEM pread/pwrite |
| 1034 | * pages from. |
| 1035 | */ |
| 1036 | if (!obj->base.filp) { |
| 1037 | ret = -EINVAL; |
| 1038 | goto out; |
| 1039 | } |
| 1040 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1041 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 1042 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1043 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1044 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1045 | * it would end up going through the fenced access, and we'll get |
| 1046 | * different detiling behavior between reading and writing. |
| 1047 | * pread/pwrite currently are reading and writing from the CPU |
| 1048 | * perspective, requiring manual detiling by the client. |
| 1049 | */ |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 1050 | if (obj->phys_handle) { |
| 1051 | ret = i915_gem_phys_pwrite(obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 1052 | goto out; |
| 1053 | } |
| 1054 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1055 | if (obj->tiling_mode == I915_TILING_NONE && |
| 1056 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 1057 | cpu_write_needs_clflush(obj)) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1058 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1059 | /* Note that the gtt paths might fail with non-page-backed user |
| 1060 | * pointers (e.g. gtt mappings when moving data between |
| 1061 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1062 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1063 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 1064 | if (ret == -EFAULT || ret == -ENOSPC) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1065 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 1066 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1067 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1068 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1069 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1070 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1071 | return ret; |
| 1072 | } |
| 1073 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1074 | int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1075 | i915_gem_check_wedge(struct i915_gpu_error *error, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1076 | bool interruptible) |
| 1077 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1078 | if (i915_reset_in_progress(error)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1079 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1080 | * -EIO unconditionally for these. */ |
| 1081 | if (!interruptible) |
| 1082 | return -EIO; |
| 1083 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1084 | /* Recovery complete, but the reset failed ... */ |
| 1085 | if (i915_terminally_wedged(error)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1086 | return -EIO; |
| 1087 | |
McAulay, Alistair | 6689c16 | 2014-08-15 18:51:35 +0100 | [diff] [blame] | 1088 | /* |
| 1089 | * Check if GPU Reset is in progress - we need intel_ring_begin |
| 1090 | * to work properly to reinit the hw state while the gpu is |
| 1091 | * still marked as reset-in-progress. Handle this with a flag. |
| 1092 | */ |
| 1093 | if (!error->reload_in_reset) |
| 1094 | return -EAGAIN; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1095 | } |
| 1096 | |
| 1097 | return 0; |
| 1098 | } |
| 1099 | |
| 1100 | /* |
| 1101 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 1102 | * equal. |
| 1103 | */ |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 1104 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1105 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1106 | { |
| 1107 | int ret; |
| 1108 | |
| 1109 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 1110 | |
| 1111 | ret = 0; |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1112 | if (seqno == ring->outstanding_lazy_seqno) |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 1113 | ret = i915_add_request(ring, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1114 | |
| 1115 | return ret; |
| 1116 | } |
| 1117 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1118 | static void fake_irq(unsigned long data) |
| 1119 | { |
| 1120 | wake_up_process((struct task_struct *)data); |
| 1121 | } |
| 1122 | |
| 1123 | static bool missed_irq(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1124 | struct intel_engine_cs *ring) |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1125 | { |
| 1126 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); |
| 1127 | } |
| 1128 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1129 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
| 1130 | { |
| 1131 | if (file_priv == NULL) |
| 1132 | return true; |
| 1133 | |
| 1134 | return !atomic_xchg(&file_priv->rps_wait_boost, true); |
| 1135 | } |
| 1136 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1137 | /** |
| 1138 | * __wait_seqno - wait until execution of seqno has finished |
| 1139 | * @ring: the ring expected to report seqno |
| 1140 | * @seqno: duh! |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1141 | * @reset_counter: reset sequence associated with the given seqno |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1142 | * @interruptible: do an interruptible wait (normally yes) |
| 1143 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1144 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1145 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1146 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1147 | * locks are involved, it is sufficient to read the reset_counter before |
| 1148 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1149 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1150 | * inserted. |
| 1151 | * |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1152 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 1153 | * errno with remaining time filled in timeout argument. |
| 1154 | */ |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1155 | static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1156 | unsigned reset_counter, |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1157 | bool interruptible, |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1158 | s64 *timeout, |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1159 | struct drm_i915_file_private *file_priv) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1160 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1161 | struct drm_device *dev = ring->dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 1162 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1163 | const bool irq_test_in_progress = |
| 1164 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1165 | DEFINE_WAIT(wait); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1166 | unsigned long timeout_expire; |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1167 | s64 before, now; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1168 | int ret; |
| 1169 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 1170 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1171 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1172 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
| 1173 | return 0; |
| 1174 | |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1175 | timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1176 | |
Chris Wilson | ec5cc0f | 2014-06-12 10:28:55 +0100 | [diff] [blame] | 1177 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1178 | gen6_rps_boost(dev_priv); |
| 1179 | if (file_priv) |
| 1180 | mod_delayed_work(dev_priv->wq, |
| 1181 | &file_priv->mm.idle_work, |
| 1182 | msecs_to_jiffies(100)); |
| 1183 | } |
| 1184 | |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1185 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1186 | return -ENODEV; |
| 1187 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1188 | /* Record current time in case interrupted by signal, or wedged */ |
| 1189 | trace_i915_gem_request_wait_begin(ring, seqno); |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1190 | before = ktime_get_raw_ns(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1191 | for (;;) { |
| 1192 | struct timer_list timer; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1193 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1194 | prepare_to_wait(&ring->irq_queue, &wait, |
| 1195 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1196 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1197 | /* We need to check whether any gpu reset happened in between |
| 1198 | * the caller grabbing the seqno and now ... */ |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1199 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
| 1200 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu |
| 1201 | * is truely gone. */ |
| 1202 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
| 1203 | if (ret == 0) |
| 1204 | ret = -EAGAIN; |
| 1205 | break; |
| 1206 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1207 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1208 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
| 1209 | ret = 0; |
| 1210 | break; |
| 1211 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1212 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1213 | if (interruptible && signal_pending(current)) { |
| 1214 | ret = -ERESTARTSYS; |
| 1215 | break; |
| 1216 | } |
| 1217 | |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1218 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1219 | ret = -ETIME; |
| 1220 | break; |
| 1221 | } |
| 1222 | |
| 1223 | timer.function = NULL; |
| 1224 | if (timeout || missed_irq(dev_priv, ring)) { |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1225 | unsigned long expire; |
| 1226 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1227 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1228 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1229 | mod_timer(&timer, expire); |
| 1230 | } |
| 1231 | |
Chris Wilson | 5035c27 | 2013-10-04 09:58:46 +0100 | [diff] [blame] | 1232 | io_schedule(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1233 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1234 | if (timer.function) { |
| 1235 | del_singleshot_timer_sync(&timer); |
| 1236 | destroy_timer_on_stack(&timer); |
| 1237 | } |
| 1238 | } |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1239 | now = ktime_get_raw_ns(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1240 | trace_i915_gem_request_wait_end(ring, seqno); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1241 | |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1242 | if (!irq_test_in_progress) |
| 1243 | ring->irq_put(ring); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1244 | |
| 1245 | finish_wait(&ring->irq_queue, &wait); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1246 | |
| 1247 | if (timeout) { |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1248 | s64 tres = *timeout - (now - before); |
| 1249 | |
| 1250 | *timeout = tres < 0 ? 0 : tres; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1251 | } |
| 1252 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1253 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1254 | } |
| 1255 | |
| 1256 | /** |
| 1257 | * Waits for a sequence number to be signaled, and cleans up the |
| 1258 | * request and object lists appropriately for that event. |
| 1259 | */ |
| 1260 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1261 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1262 | { |
| 1263 | struct drm_device *dev = ring->dev; |
| 1264 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1265 | bool interruptible = dev_priv->mm.interruptible; |
| 1266 | int ret; |
| 1267 | |
| 1268 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1269 | BUG_ON(seqno == 0); |
| 1270 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1271 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1272 | if (ret) |
| 1273 | return ret; |
| 1274 | |
| 1275 | ret = i915_gem_check_olr(ring, seqno); |
| 1276 | if (ret) |
| 1277 | return ret; |
| 1278 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1279 | return __wait_seqno(ring, seqno, |
| 1280 | atomic_read(&dev_priv->gpu_error.reset_counter), |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1281 | interruptible, NULL, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1282 | } |
| 1283 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1284 | static int |
| 1285 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1286 | struct intel_engine_cs *ring) |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1287 | { |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 1288 | if (!obj->active) |
| 1289 | return 0; |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1290 | |
| 1291 | /* Manually manage the write flush as we may have not yet |
| 1292 | * retired the buffer. |
| 1293 | * |
| 1294 | * Note that the last_write_seqno is always the earlier of |
| 1295 | * the two (read/write) seqno, so if we haved successfully waited, |
| 1296 | * we know we have passed the last write. |
| 1297 | */ |
| 1298 | obj->last_write_seqno = 0; |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1299 | |
| 1300 | return 0; |
| 1301 | } |
| 1302 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1303 | /** |
| 1304 | * Ensures that all rendering to the object has completed and the object is |
| 1305 | * safe to unbind from the GTT or access from the CPU. |
| 1306 | */ |
| 1307 | static __must_check int |
| 1308 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1309 | bool readonly) |
| 1310 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1311 | struct intel_engine_cs *ring = obj->ring; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1312 | u32 seqno; |
| 1313 | int ret; |
| 1314 | |
| 1315 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1316 | if (seqno == 0) |
| 1317 | return 0; |
| 1318 | |
| 1319 | ret = i915_wait_seqno(ring, seqno); |
| 1320 | if (ret) |
| 1321 | return ret; |
| 1322 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1323 | return i915_gem_object_wait_rendering__tail(obj, ring); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1324 | } |
| 1325 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1326 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1327 | * as the object state may change during this call. |
| 1328 | */ |
| 1329 | static __must_check int |
| 1330 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1331 | struct drm_i915_file_private *file_priv, |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1332 | bool readonly) |
| 1333 | { |
| 1334 | struct drm_device *dev = obj->base.dev; |
| 1335 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1336 | struct intel_engine_cs *ring = obj->ring; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1337 | unsigned reset_counter; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1338 | u32 seqno; |
| 1339 | int ret; |
| 1340 | |
| 1341 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1342 | BUG_ON(!dev_priv->mm.interruptible); |
| 1343 | |
| 1344 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1345 | if (seqno == 0) |
| 1346 | return 0; |
| 1347 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1348 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1349 | if (ret) |
| 1350 | return ret; |
| 1351 | |
| 1352 | ret = i915_gem_check_olr(ring, seqno); |
| 1353 | if (ret) |
| 1354 | return ret; |
| 1355 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1356 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1357 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1358 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1359 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1360 | if (ret) |
| 1361 | return ret; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1362 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1363 | return i915_gem_object_wait_rendering__tail(obj, ring); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1364 | } |
| 1365 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1366 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1367 | * Called when user space prepares to use an object with the CPU, either |
| 1368 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1369 | */ |
| 1370 | int |
| 1371 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1372 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1373 | { |
| 1374 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1375 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1376 | uint32_t read_domains = args->read_domains; |
| 1377 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1378 | int ret; |
| 1379 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1380 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1381 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1382 | return -EINVAL; |
| 1383 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1384 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1385 | return -EINVAL; |
| 1386 | |
| 1387 | /* Having something in the write domain implies it's in the read |
| 1388 | * domain, and only that read domain. Enforce that in the request. |
| 1389 | */ |
| 1390 | if (write_domain != 0 && read_domains != write_domain) |
| 1391 | return -EINVAL; |
| 1392 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1393 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1394 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1395 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1396 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1397 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1398 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1399 | ret = -ENOENT; |
| 1400 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1401 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1402 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1403 | /* Try to flush the object off the GPU without holding the lock. |
| 1404 | * We will repeat the flush holding the lock in the normal manner |
| 1405 | * to catch cases where we are gazumped. |
| 1406 | */ |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1407 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
| 1408 | file->driver_priv, |
| 1409 | !write_domain); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1410 | if (ret) |
| 1411 | goto unref; |
| 1412 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1413 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1414 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1415 | |
| 1416 | /* Silently promote "you're not bound, there was nothing to do" |
| 1417 | * to success, since the client was just asking us to |
| 1418 | * make sure everything was done. |
| 1419 | */ |
| 1420 | if (ret == -EINVAL) |
| 1421 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1422 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1423 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1424 | } |
| 1425 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1426 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1427 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1428 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1429 | mutex_unlock(&dev->struct_mutex); |
| 1430 | return ret; |
| 1431 | } |
| 1432 | |
| 1433 | /** |
| 1434 | * Called when user space has done writes to this buffer |
| 1435 | */ |
| 1436 | int |
| 1437 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1438 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1439 | { |
| 1440 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1441 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1442 | int ret = 0; |
| 1443 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1444 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1445 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1446 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1447 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1448 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1449 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1450 | ret = -ENOENT; |
| 1451 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1452 | } |
| 1453 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1454 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1455 | if (obj->pin_display) |
| 1456 | i915_gem_object_flush_cpu_write_domain(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1457 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1458 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1459 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1460 | mutex_unlock(&dev->struct_mutex); |
| 1461 | return ret; |
| 1462 | } |
| 1463 | |
| 1464 | /** |
| 1465 | * Maps the contents of an object, returning the address it is mapped |
| 1466 | * into. |
| 1467 | * |
| 1468 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1469 | * imply a ref on the object itself. |
| 1470 | */ |
| 1471 | int |
| 1472 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1473 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1474 | { |
| 1475 | struct drm_i915_gem_mmap *args = data; |
| 1476 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1477 | unsigned long addr; |
| 1478 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1479 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1480 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1481 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1482 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1483 | /* prime objects have no backing filp to GEM mmap |
| 1484 | * pages from. |
| 1485 | */ |
| 1486 | if (!obj->filp) { |
| 1487 | drm_gem_object_unreference_unlocked(obj); |
| 1488 | return -EINVAL; |
| 1489 | } |
| 1490 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1491 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1492 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1493 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1494 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1495 | if (IS_ERR((void *)addr)) |
| 1496 | return addr; |
| 1497 | |
| 1498 | args->addr_ptr = (uint64_t) addr; |
| 1499 | |
| 1500 | return 0; |
| 1501 | } |
| 1502 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1503 | /** |
| 1504 | * i915_gem_fault - fault a page into the GTT |
| 1505 | * vma: VMA in question |
| 1506 | * vmf: fault info |
| 1507 | * |
| 1508 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1509 | * from userspace. The fault handler takes care of binding the object to |
| 1510 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1511 | * only if needed based on whether the old reg is still valid or the object |
| 1512 | * is tiled) and inserting a new PTE into the faulting process. |
| 1513 | * |
| 1514 | * Note that the faulting process may involve evicting existing objects |
| 1515 | * from the GTT and/or fence registers to make room. So performance may |
| 1516 | * suffer if the GTT working set is large or there are few fence registers |
| 1517 | * left. |
| 1518 | */ |
| 1519 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1520 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1521 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1522 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 1523 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1524 | pgoff_t page_offset; |
| 1525 | unsigned long pfn; |
| 1526 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1527 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1528 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1529 | intel_runtime_pm_get(dev_priv); |
| 1530 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1531 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1532 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1533 | PAGE_SHIFT; |
| 1534 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1535 | ret = i915_mutex_lock_interruptible(dev); |
| 1536 | if (ret) |
| 1537 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1538 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1539 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1540 | |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1541 | /* Try to flush the object off the GPU first without holding the lock. |
| 1542 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1543 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1544 | * where we are gazumped. |
| 1545 | */ |
| 1546 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1547 | if (ret) |
| 1548 | goto unlock; |
| 1549 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1550 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1551 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
Chris Wilson | ddeff6e | 2014-05-28 16:16:41 +0100 | [diff] [blame] | 1552 | ret = -EFAULT; |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1553 | goto unlock; |
| 1554 | } |
| 1555 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1556 | /* Now bind it into the GTT if needed */ |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 1557 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1558 | if (ret) |
| 1559 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1560 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1561 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1562 | if (ret) |
| 1563 | goto unpin; |
| 1564 | |
| 1565 | ret = i915_gem_object_get_fence(obj); |
| 1566 | if (ret) |
| 1567 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1568 | |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1569 | /* Finally, remap it using the new GTT offset */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1570 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
| 1571 | pfn >>= PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1572 | |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1573 | if (!obj->fault_mappable) { |
Ville Syrjälä | beff0d0 | 2014-06-17 21:03:00 +0300 | [diff] [blame] | 1574 | unsigned long size = min_t(unsigned long, |
| 1575 | vma->vm_end - vma->vm_start, |
| 1576 | obj->base.size); |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1577 | int i; |
| 1578 | |
Ville Syrjälä | beff0d0 | 2014-06-17 21:03:00 +0300 | [diff] [blame] | 1579 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1580 | ret = vm_insert_pfn(vma, |
| 1581 | (unsigned long)vma->vm_start + i * PAGE_SIZE, |
| 1582 | pfn + i); |
| 1583 | if (ret) |
| 1584 | break; |
| 1585 | } |
| 1586 | |
| 1587 | obj->fault_mappable = true; |
| 1588 | } else |
| 1589 | ret = vm_insert_pfn(vma, |
| 1590 | (unsigned long)vmf->virtual_address, |
| 1591 | pfn + page_offset); |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1592 | unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1593 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1594 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1595 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1596 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1597 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1598 | case -EIO: |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1599 | /* If this -EIO is due to a gpu hang, give the reset code a |
| 1600 | * chance to clean up the mess. Otherwise return the proper |
| 1601 | * SIGBUS. */ |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1602 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
| 1603 | ret = VM_FAULT_SIGBUS; |
| 1604 | break; |
| 1605 | } |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1606 | case -EAGAIN: |
Daniel Vetter | 571c608 | 2013-09-12 17:57:28 +0200 | [diff] [blame] | 1607 | /* |
| 1608 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1609 | * handler to reset everything when re-faulting in |
| 1610 | * i915_mutex_lock_interruptible. |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1611 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1612 | case 0: |
| 1613 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1614 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1615 | case -EBUSY: |
| 1616 | /* |
| 1617 | * EBUSY is ok: this just means that another thread |
| 1618 | * already did the job. |
| 1619 | */ |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1620 | ret = VM_FAULT_NOPAGE; |
| 1621 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1622 | case -ENOMEM: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1623 | ret = VM_FAULT_OOM; |
| 1624 | break; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1625 | case -ENOSPC: |
Chris Wilson | 45d6781 | 2014-01-31 11:34:57 +0000 | [diff] [blame] | 1626 | case -EFAULT: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1627 | ret = VM_FAULT_SIGBUS; |
| 1628 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1629 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1630 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1631 | ret = VM_FAULT_SIGBUS; |
| 1632 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1633 | } |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1634 | |
| 1635 | intel_runtime_pm_put(dev_priv); |
| 1636 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1637 | } |
| 1638 | |
| 1639 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1640 | * i915_gem_release_mmap - remove physical page mappings |
| 1641 | * @obj: obj in question |
| 1642 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1643 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1644 | * relinquish ownership of the pages back to the system. |
| 1645 | * |
| 1646 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1647 | * object through the GTT and then lose the fence register due to |
| 1648 | * resource pressure. Similarly if the object has been moved out of the |
| 1649 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1650 | * mapping will then trigger a page fault on the next user access, allowing |
| 1651 | * fixup by i915_gem_fault(). |
| 1652 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1653 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1654 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1655 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1656 | if (!obj->fault_mappable) |
| 1657 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1658 | |
David Herrmann | 6796cb1 | 2014-01-03 14:24:19 +0100 | [diff] [blame] | 1659 | drm_vma_node_unmap(&obj->base.vma_node, |
| 1660 | obj->base.dev->anon_inode->i_mapping); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1661 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1662 | } |
| 1663 | |
Chris Wilson | eedd10f | 2014-06-16 08:57:44 +0100 | [diff] [blame] | 1664 | void |
| 1665 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 1666 | { |
| 1667 | struct drm_i915_gem_object *obj; |
| 1668 | |
| 1669 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 1670 | i915_gem_release_mmap(obj); |
| 1671 | } |
| 1672 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 1673 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1674 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1675 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1676 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1677 | |
| 1678 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1679 | tiling_mode == I915_TILING_NONE) |
| 1680 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1681 | |
| 1682 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1683 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1684 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1685 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1686 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1687 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1688 | while (gtt_size < size) |
| 1689 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1690 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1691 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1692 | } |
| 1693 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1694 | /** |
| 1695 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1696 | * @obj: object to check |
| 1697 | * |
| 1698 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1699 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1700 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1701 | uint32_t |
| 1702 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1703 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1704 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1705 | /* |
| 1706 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1707 | * if a fence register is needed for the object. |
| 1708 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1709 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1710 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1711 | return 4096; |
| 1712 | |
| 1713 | /* |
| 1714 | * Previous chips need to be aligned to the size of the smallest |
| 1715 | * fence register that can contain the object. |
| 1716 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1717 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1718 | } |
| 1719 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1720 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1721 | { |
| 1722 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1723 | int ret; |
| 1724 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1725 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1726 | return 0; |
| 1727 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1728 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1729 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1730 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1731 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1732 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1733 | |
| 1734 | /* Badly fragmented mmap space? The only way we can recover |
| 1735 | * space is by destroying unwanted objects. We can't randomly release |
| 1736 | * mmap_offsets as userspace expects them to be persistent for the |
| 1737 | * lifetime of the objects. The closest we can is to release the |
| 1738 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1739 | * which prevents userspace from ever using that object again. |
| 1740 | */ |
| 1741 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); |
| 1742 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1743 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1744 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1745 | |
| 1746 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1747 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1748 | out: |
| 1749 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 1750 | |
| 1751 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1752 | } |
| 1753 | |
| 1754 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 1755 | { |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1756 | drm_gem_free_mmap_offset(&obj->base); |
| 1757 | } |
| 1758 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1759 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1760 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1761 | struct drm_device *dev, |
| 1762 | uint32_t handle, |
| 1763 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1764 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1765 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1766 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1767 | int ret; |
| 1768 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1769 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1770 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1771 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1772 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1773 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1774 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1775 | ret = -ENOENT; |
| 1776 | goto unlock; |
| 1777 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1778 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1779 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1780 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1781 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1782 | } |
| 1783 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1784 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 1785 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 1786 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1787 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1788 | } |
| 1789 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1790 | ret = i915_gem_object_create_mmap_offset(obj); |
| 1791 | if (ret) |
| 1792 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1793 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1794 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1795 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1796 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1797 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1798 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1799 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1800 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1801 | } |
| 1802 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1803 | /** |
| 1804 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1805 | * @dev: DRM device |
| 1806 | * @data: GTT mapping ioctl data |
| 1807 | * @file: GEM object info |
| 1808 | * |
| 1809 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1810 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1811 | * up so we can get faults in the handler above. |
| 1812 | * |
| 1813 | * The fault handler will take care of binding the object into the GTT |
| 1814 | * (since it may have been evicted to make room for something), allocating |
| 1815 | * a fence register, and mapping the appropriate aperture address into |
| 1816 | * userspace. |
| 1817 | */ |
| 1818 | int |
| 1819 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1820 | struct drm_file *file) |
| 1821 | { |
| 1822 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1823 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1824 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1825 | } |
| 1826 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1827 | static inline int |
| 1828 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
| 1829 | { |
| 1830 | return obj->madv == I915_MADV_DONTNEED; |
| 1831 | } |
| 1832 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1833 | /* Immediately discard the backing storage */ |
| 1834 | static void |
| 1835 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1836 | { |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1837 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1838 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1839 | if (obj->base.filp == NULL) |
| 1840 | return; |
| 1841 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1842 | /* Our goal here is to return as much of the memory as |
| 1843 | * is possible back to the system as we are called from OOM. |
| 1844 | * To do this we must instruct the shmfs to drop all of its |
| 1845 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1846 | */ |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1847 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1848 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1849 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1850 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1851 | /* Try to discard unwanted pages */ |
| 1852 | static void |
| 1853 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1854 | { |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1855 | struct address_space *mapping; |
| 1856 | |
| 1857 | switch (obj->madv) { |
| 1858 | case I915_MADV_DONTNEED: |
| 1859 | i915_gem_object_truncate(obj); |
| 1860 | case __I915_MADV_PURGED: |
| 1861 | return; |
| 1862 | } |
| 1863 | |
| 1864 | if (obj->base.filp == NULL) |
| 1865 | return; |
| 1866 | |
| 1867 | mapping = file_inode(obj->base.filp)->i_mapping, |
| 1868 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1869 | } |
| 1870 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1871 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1872 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1873 | { |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1874 | struct sg_page_iter sg_iter; |
| 1875 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1876 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1877 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1878 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1879 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 1880 | if (ret) { |
| 1881 | /* In the event of a disaster, abandon all caches and |
| 1882 | * hope for the best. |
| 1883 | */ |
| 1884 | WARN_ON(ret != -EIO); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1885 | i915_gem_clflush_object(obj, true); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1886 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 1887 | } |
| 1888 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1889 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1890 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1891 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1892 | if (obj->madv == I915_MADV_DONTNEED) |
| 1893 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1894 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1895 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1896 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1897 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1898 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1899 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1900 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1901 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1902 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1903 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1904 | page_cache_release(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1905 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1906 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1907 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1908 | sg_free_table(obj->pages); |
| 1909 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1910 | } |
| 1911 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1912 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1913 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 1914 | { |
| 1915 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1916 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1917 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1918 | return 0; |
| 1919 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1920 | if (obj->pages_pin_count) |
| 1921 | return -EBUSY; |
| 1922 | |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 1923 | BUG_ON(i915_gem_obj_bound_any(obj)); |
Ben Widawsky | 3e12302 | 2013-07-31 17:00:04 -0700 | [diff] [blame] | 1924 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1925 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 1926 | * array, hence protect them from being reaped by removing them from gtt |
| 1927 | * lists early. */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1928 | list_del(&obj->global_list); |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1929 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1930 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1931 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1932 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1933 | i915_gem_object_invalidate(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1934 | |
| 1935 | return 0; |
| 1936 | } |
| 1937 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 1938 | static unsigned long |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1939 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
| 1940 | bool purgeable_only) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1941 | { |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 1942 | struct list_head still_in_list; |
| 1943 | struct drm_i915_gem_object *obj; |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 1944 | unsigned long count = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1945 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1946 | /* |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 1947 | * As we may completely rewrite the (un)bound list whilst unbinding |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1948 | * (due to retiring requests) we have to strictly process only |
| 1949 | * one element of the list at the time, and recheck the list |
| 1950 | * on every iteration. |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 1951 | * |
| 1952 | * In particular, we must hold a reference whilst removing the |
| 1953 | * object as we may end up waiting for and/or retiring the objects. |
| 1954 | * This might release the final reference (held by the active list) |
| 1955 | * and result in the object being freed from under us. This is |
| 1956 | * similar to the precautions the eviction code must take whilst |
| 1957 | * removing objects. |
| 1958 | * |
| 1959 | * Also note that although these lists do not hold a reference to |
| 1960 | * the object we can safely grab one here: The final object |
| 1961 | * unreferencing and the bound_list are both protected by the |
| 1962 | * dev->struct_mutex and so we won't ever be able to observe an |
| 1963 | * object on the bound_list with a reference count equals 0. |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1964 | */ |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 1965 | INIT_LIST_HEAD(&still_in_list); |
| 1966 | while (count < target && !list_empty(&dev_priv->mm.unbound_list)) { |
| 1967 | obj = list_first_entry(&dev_priv->mm.unbound_list, |
| 1968 | typeof(*obj), global_list); |
| 1969 | list_move_tail(&obj->global_list, &still_in_list); |
| 1970 | |
| 1971 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
| 1972 | continue; |
| 1973 | |
| 1974 | drm_gem_object_reference(&obj->base); |
| 1975 | |
| 1976 | if (i915_gem_object_put_pages(obj) == 0) |
| 1977 | count += obj->base.size >> PAGE_SHIFT; |
| 1978 | |
| 1979 | drm_gem_object_unreference(&obj->base); |
| 1980 | } |
| 1981 | list_splice(&still_in_list, &dev_priv->mm.unbound_list); |
| 1982 | |
| 1983 | INIT_LIST_HEAD(&still_in_list); |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1984 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 1985 | struct i915_vma *vma, *v; |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 1986 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1987 | obj = list_first_entry(&dev_priv->mm.bound_list, |
| 1988 | typeof(*obj), global_list); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 1989 | list_move_tail(&obj->global_list, &still_in_list); |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1990 | |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 1991 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
| 1992 | continue; |
| 1993 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1994 | drm_gem_object_reference(&obj->base); |
| 1995 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 1996 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
| 1997 | if (i915_vma_unbind(vma)) |
| 1998 | break; |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 1999 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 2000 | if (i915_gem_object_put_pages(obj) == 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2001 | count += obj->base.size >> PAGE_SHIFT; |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 2002 | |
| 2003 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2004 | } |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2005 | list_splice(&still_in_list, &dev_priv->mm.bound_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2006 | |
| 2007 | return count; |
| 2008 | } |
| 2009 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 2010 | static unsigned long |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 2011 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
| 2012 | { |
| 2013 | return __i915_gem_shrink(dev_priv, target, true); |
| 2014 | } |
| 2015 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 2016 | static unsigned long |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2017 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
| 2018 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2019 | i915_gem_evict_everything(dev_priv->dev); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2020 | return __i915_gem_shrink(dev_priv, LONG_MAX, false); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2021 | } |
| 2022 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2023 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2024 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2025 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2026 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2027 | int page_count, i; |
| 2028 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2029 | struct sg_table *st; |
| 2030 | struct scatterlist *sg; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2031 | struct sg_page_iter sg_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2032 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2033 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2034 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2035 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2036 | /* Assert that the object is not currently in any GPU domain. As it |
| 2037 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2038 | * a GPU cache |
| 2039 | */ |
| 2040 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2041 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 2042 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2043 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2044 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2045 | return -ENOMEM; |
| 2046 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2047 | page_count = obj->base.size / PAGE_SIZE; |
| 2048 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2049 | kfree(st); |
| 2050 | return -ENOMEM; |
| 2051 | } |
| 2052 | |
| 2053 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2054 | * at this point until we release them. |
| 2055 | * |
| 2056 | * Fail silently without starting the shrinker |
| 2057 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 2058 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2059 | gfp = mapping_gfp_mask(mapping); |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 2060 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2061 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2062 | sg = st->sgl; |
| 2063 | st->nents = 0; |
| 2064 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2065 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2066 | if (IS_ERR(page)) { |
| 2067 | i915_gem_purge(dev_priv, page_count); |
| 2068 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2069 | } |
| 2070 | if (IS_ERR(page)) { |
| 2071 | /* We've tried hard to allocate the memory by reaping |
| 2072 | * our own buffer, now let the real VM do its job and |
| 2073 | * go down in flames if truly OOM. |
| 2074 | */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2075 | i915_gem_shrink_all(dev_priv); |
David Herrmann | f461d1b | 2014-05-25 14:34:10 +0200 | [diff] [blame] | 2076 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2077 | if (IS_ERR(page)) |
| 2078 | goto err_pages; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2079 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2080 | #ifdef CONFIG_SWIOTLB |
| 2081 | if (swiotlb_nr_tbl()) { |
| 2082 | st->nents++; |
| 2083 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2084 | sg = sg_next(sg); |
| 2085 | continue; |
| 2086 | } |
| 2087 | #endif |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2088 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 2089 | if (i) |
| 2090 | sg = sg_next(sg); |
| 2091 | st->nents++; |
| 2092 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2093 | } else { |
| 2094 | sg->length += PAGE_SIZE; |
| 2095 | } |
| 2096 | last_pfn = page_to_pfn(page); |
Daniel Vetter | 3bbbe70 | 2013-10-07 17:15:45 -0300 | [diff] [blame] | 2097 | |
| 2098 | /* Check that the i965g/gm workaround works. */ |
| 2099 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2100 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2101 | #ifdef CONFIG_SWIOTLB |
| 2102 | if (!swiotlb_nr_tbl()) |
| 2103 | #endif |
| 2104 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 2105 | obj->pages = st; |
| 2106 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2107 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2108 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2109 | |
| 2110 | return 0; |
| 2111 | |
| 2112 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2113 | sg_mark_end(sg); |
| 2114 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 2115 | page_cache_release(sg_page_iter_page(&sg_iter)); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2116 | sg_free_table(st); |
| 2117 | kfree(st); |
Chris Wilson | 0820baf | 2014-03-25 13:23:03 +0000 | [diff] [blame] | 2118 | |
| 2119 | /* shmemfs first checks if there is enough memory to allocate the page |
| 2120 | * and reports ENOSPC should there be insufficient, along with the usual |
| 2121 | * ENOMEM for a genuine allocation failure. |
| 2122 | * |
| 2123 | * We use ENOSPC in our driver to mean that we have run out of aperture |
| 2124 | * space and so want to translate the error from shmemfs back to our |
| 2125 | * usual understanding of ENOMEM. |
| 2126 | */ |
| 2127 | if (PTR_ERR(page) == -ENOSPC) |
| 2128 | return -ENOMEM; |
| 2129 | else |
| 2130 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2131 | } |
| 2132 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2133 | /* Ensure that the associated pages are gathered from the backing storage |
| 2134 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 2135 | * multiple times before they are released by a single call to |
| 2136 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 2137 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 2138 | * or as the object is itself released. |
| 2139 | */ |
| 2140 | int |
| 2141 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 2142 | { |
| 2143 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2144 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2145 | int ret; |
| 2146 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 2147 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2148 | return 0; |
| 2149 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2150 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 2151 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 2152 | return -EFAULT; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2153 | } |
| 2154 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2155 | BUG_ON(obj->pages_pin_count); |
| 2156 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2157 | ret = ops->get_pages(obj); |
| 2158 | if (ret) |
| 2159 | return ret; |
| 2160 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2161 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2162 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2163 | } |
| 2164 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2165 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2166 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2167 | struct intel_engine_cs *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2168 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2169 | u32 seqno = intel_ring_get_seqno(ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 2170 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2171 | BUG_ON(ring == NULL); |
Chris Wilson | 02978ff | 2013-07-09 09:22:39 +0100 | [diff] [blame] | 2172 | if (obj->ring != ring && obj->last_write_seqno) { |
| 2173 | /* Keep the seqno relative to the current ring */ |
| 2174 | obj->last_write_seqno = seqno; |
| 2175 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2176 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2177 | |
| 2178 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2179 | if (!obj->active) { |
| 2180 | drm_gem_object_reference(&obj->base); |
| 2181 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2182 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2183 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2184 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2185 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2186 | obj->last_read_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2187 | } |
| 2188 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2189 | void i915_vma_move_to_active(struct i915_vma *vma, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2190 | struct intel_engine_cs *ring) |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2191 | { |
| 2192 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
| 2193 | return i915_gem_object_move_to_active(vma->obj, ring); |
| 2194 | } |
| 2195 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2196 | static void |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2197 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 2198 | { |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 2199 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2200 | struct i915_address_space *vm; |
| 2201 | struct i915_vma *vma; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2202 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2203 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2204 | BUG_ON(!obj->active); |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2205 | |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2206 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 2207 | vma = i915_gem_obj_to_vma(obj, vm); |
| 2208 | if (vma && !list_empty(&vma->mm_list)) |
| 2209 | list_move_tail(&vma->mm_list, &vm->inactive_list); |
| 2210 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2211 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 2212 | intel_fb_obj_flush(obj, true); |
| 2213 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2214 | list_del_init(&obj->ring_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2215 | obj->ring = NULL; |
| 2216 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2217 | obj->last_read_seqno = 0; |
| 2218 | obj->last_write_seqno = 0; |
| 2219 | obj->base.write_domain = 0; |
| 2220 | |
| 2221 | obj->last_fenced_seqno = 0; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2222 | |
| 2223 | obj->active = 0; |
| 2224 | drm_gem_object_unreference(&obj->base); |
| 2225 | |
| 2226 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 2227 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2228 | |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2229 | static void |
| 2230 | i915_gem_object_retire(struct drm_i915_gem_object *obj) |
| 2231 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2232 | struct intel_engine_cs *ring = obj->ring; |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2233 | |
| 2234 | if (ring == NULL) |
| 2235 | return; |
| 2236 | |
| 2237 | if (i915_seqno_passed(ring->get_seqno(ring, true), |
| 2238 | obj->last_read_seqno)) |
| 2239 | i915_gem_object_move_to_inactive(obj); |
| 2240 | } |
| 2241 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2242 | static int |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2243 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2244 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2245 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2246 | struct intel_engine_cs *ring; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2247 | int ret, i, j; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2248 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2249 | /* Carefully retire all requests without writing to the rings */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2250 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2251 | ret = intel_ring_idle(ring); |
| 2252 | if (ret) |
| 2253 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2254 | } |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2255 | i915_gem_retire_requests(dev); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2256 | |
| 2257 | /* Finally reset hw state */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2258 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2259 | intel_ring_init_seqno(ring, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2260 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2261 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
| 2262 | ring->semaphore.sync_seqno[j] = 0; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2263 | } |
| 2264 | |
| 2265 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2266 | } |
| 2267 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2268 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2269 | { |
| 2270 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2271 | int ret; |
| 2272 | |
| 2273 | if (seqno == 0) |
| 2274 | return -EINVAL; |
| 2275 | |
| 2276 | /* HWS page needs to be set less than what we |
| 2277 | * will inject to ring |
| 2278 | */ |
| 2279 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 2280 | if (ret) |
| 2281 | return ret; |
| 2282 | |
| 2283 | /* Carefully set the last_seqno value so that wrap |
| 2284 | * detection still works |
| 2285 | */ |
| 2286 | dev_priv->next_seqno = seqno; |
| 2287 | dev_priv->last_seqno = seqno - 1; |
| 2288 | if (dev_priv->last_seqno == 0) |
| 2289 | dev_priv->last_seqno--; |
| 2290 | |
| 2291 | return 0; |
| 2292 | } |
| 2293 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2294 | int |
| 2295 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2296 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2297 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2298 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2299 | /* reserve 0 for non-seqno */ |
| 2300 | if (dev_priv->next_seqno == 0) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2301 | int ret = i915_gem_init_seqno(dev, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2302 | if (ret) |
| 2303 | return ret; |
| 2304 | |
| 2305 | dev_priv->next_seqno = 1; |
| 2306 | } |
| 2307 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 2308 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2309 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2310 | } |
| 2311 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2312 | int __i915_add_request(struct intel_engine_cs *ring, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2313 | struct drm_file *file, |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2314 | struct drm_i915_gem_object *obj, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2315 | u32 *out_seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2316 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2317 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2318 | struct drm_i915_gem_request *request; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2319 | struct intel_ringbuffer *ringbuf; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2320 | u32 request_ring_position, request_start; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2321 | int ret; |
| 2322 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2323 | request = ring->preallocated_lazy_request; |
| 2324 | if (WARN_ON(request == NULL)) |
| 2325 | return -ENOMEM; |
| 2326 | |
| 2327 | if (i915.enable_execlists) { |
| 2328 | struct intel_context *ctx = request->ctx; |
| 2329 | ringbuf = ctx->engine[ring->id].ringbuf; |
| 2330 | } else |
| 2331 | ringbuf = ring->buffer; |
| 2332 | |
| 2333 | request_start = intel_ring_get_tail(ringbuf); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2334 | /* |
| 2335 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2336 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2337 | * things up similar to emitting the lazy request. The difference here |
| 2338 | * is that the flush _must_ happen before the next request, no matter |
| 2339 | * what. |
| 2340 | */ |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2341 | if (i915.enable_execlists) { |
| 2342 | ret = logical_ring_flush_all_caches(ringbuf); |
| 2343 | if (ret) |
| 2344 | return ret; |
| 2345 | } else { |
| 2346 | ret = intel_ring_flush_all_caches(ring); |
| 2347 | if (ret) |
| 2348 | return ret; |
| 2349 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2350 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2351 | /* Record the position of the start of the request so that |
| 2352 | * should we detect the updated seqno part-way through the |
| 2353 | * GPU processing the request, we never over-estimate the |
| 2354 | * position of the head. |
| 2355 | */ |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2356 | request_ring_position = intel_ring_get_tail(ringbuf); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2357 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2358 | if (i915.enable_execlists) { |
| 2359 | ret = ring->emit_request(ringbuf); |
| 2360 | if (ret) |
| 2361 | return ret; |
| 2362 | } else { |
| 2363 | ret = ring->add_request(ring); |
| 2364 | if (ret) |
| 2365 | return ret; |
| 2366 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2367 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2368 | request->seqno = intel_ring_get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2369 | request->ring = ring; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2370 | request->head = request_start; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2371 | request->tail = request_ring_position; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2372 | |
| 2373 | /* Whilst this request exists, batch_obj will be on the |
| 2374 | * active_list, and so will hold the active reference. Only when this |
| 2375 | * request is retired will the the batch_obj be moved onto the |
| 2376 | * inactive_list and lose its active reference. Hence we do not need |
| 2377 | * to explicitly hold another reference here. |
| 2378 | */ |
Chris Wilson | 9a7e0c2 | 2013-08-26 19:50:54 -0300 | [diff] [blame] | 2379 | request->batch_obj = obj; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2380 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2381 | if (!i915.enable_execlists) { |
| 2382 | /* Hold a reference to the current context so that we can inspect |
| 2383 | * it later in case a hangcheck error event fires. |
| 2384 | */ |
| 2385 | request->ctx = ring->last_context; |
| 2386 | if (request->ctx) |
| 2387 | i915_gem_context_reference(request->ctx); |
| 2388 | } |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2389 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2390 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2391 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2392 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2393 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2394 | if (file) { |
| 2395 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2396 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2397 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2398 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2399 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2400 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2401 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2402 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2403 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2404 | trace_i915_gem_request_add(ring, request->seqno); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2405 | ring->outstanding_lazy_seqno = 0; |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2406 | ring->preallocated_lazy_request = NULL; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2407 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 2408 | if (!dev_priv->ums.mm_suspended) { |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2409 | i915_queue_hangcheck(ring->dev); |
| 2410 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 2411 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
| 2412 | queue_delayed_work(dev_priv->wq, |
| 2413 | &dev_priv->mm.retire_work, |
| 2414 | round_jiffies_up_relative(HZ)); |
| 2415 | intel_mark_busy(dev_priv->dev); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2416 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2417 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2418 | if (out_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2419 | *out_seqno = request->seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2420 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2421 | } |
| 2422 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2423 | static inline void |
| 2424 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2425 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2426 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2427 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2428 | if (!file_priv) |
| 2429 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2430 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2431 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2432 | list_del(&request->client_list); |
| 2433 | request->file_priv = NULL; |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2434 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2435 | } |
| 2436 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2437 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2438 | const struct intel_context *ctx) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2439 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2440 | unsigned long elapsed; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2441 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2442 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2443 | |
| 2444 | if (ctx->hang_stats.banned) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2445 | return true; |
| 2446 | |
| 2447 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2448 | if (!i915_gem_context_is_default(ctx)) { |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2449 | DRM_DEBUG("context hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2450 | return true; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 2451 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
| 2452 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 2453 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2454 | return true; |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2455 | } |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2456 | } |
| 2457 | |
| 2458 | return false; |
| 2459 | } |
| 2460 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2461 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2462 | struct intel_context *ctx, |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2463 | const bool guilty) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2464 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2465 | struct i915_ctx_hang_stats *hs; |
| 2466 | |
| 2467 | if (WARN_ON(!ctx)) |
| 2468 | return; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2469 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2470 | hs = &ctx->hang_stats; |
| 2471 | |
| 2472 | if (guilty) { |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2473 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2474 | hs->batch_active++; |
| 2475 | hs->guilty_ts = get_seconds(); |
| 2476 | } else { |
| 2477 | hs->batch_pending++; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2478 | } |
| 2479 | } |
| 2480 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2481 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
| 2482 | { |
| 2483 | list_del(&request->list); |
| 2484 | i915_gem_request_remove_from_client(request); |
| 2485 | |
| 2486 | if (request->ctx) |
| 2487 | i915_gem_context_unreference(request->ctx); |
| 2488 | |
| 2489 | kfree(request); |
| 2490 | } |
| 2491 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2492 | struct drm_i915_gem_request * |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2493 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2494 | { |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2495 | struct drm_i915_gem_request *request; |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2496 | u32 completed_seqno; |
| 2497 | |
| 2498 | completed_seqno = ring->get_seqno(ring, false); |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2499 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2500 | list_for_each_entry(request, &ring->request_list, list) { |
| 2501 | if (i915_seqno_passed(completed_seqno, request->seqno)) |
| 2502 | continue; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2503 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2504 | return request; |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2505 | } |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2506 | |
| 2507 | return NULL; |
| 2508 | } |
| 2509 | |
| 2510 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2511 | struct intel_engine_cs *ring) |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2512 | { |
| 2513 | struct drm_i915_gem_request *request; |
| 2514 | bool ring_hung; |
| 2515 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2516 | request = i915_gem_find_active_request(ring); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2517 | |
| 2518 | if (request == NULL) |
| 2519 | return; |
| 2520 | |
| 2521 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
| 2522 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2523 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2524 | |
| 2525 | list_for_each_entry_continue(request, &ring->request_list, list) |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2526 | i915_set_reset_status(dev_priv, request->ctx, false); |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2527 | } |
| 2528 | |
| 2529 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2530 | struct intel_engine_cs *ring) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2531 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2532 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2533 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2534 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2535 | obj = list_first_entry(&ring->active_list, |
| 2536 | struct drm_i915_gem_object, |
| 2537 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2538 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2539 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2540 | } |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2541 | |
| 2542 | /* |
| 2543 | * We must free the requests after all the corresponding objects have |
| 2544 | * been moved off active lists. Which is the same order as the normal |
| 2545 | * retire_requests function does. This is important if object hold |
| 2546 | * implicit references on things like e.g. ppgtt address spaces through |
| 2547 | * the request. |
| 2548 | */ |
| 2549 | while (!list_empty(&ring->request_list)) { |
| 2550 | struct drm_i915_gem_request *request; |
| 2551 | |
| 2552 | request = list_first_entry(&ring->request_list, |
| 2553 | struct drm_i915_gem_request, |
| 2554 | list); |
| 2555 | |
| 2556 | i915_gem_free_request(request); |
| 2557 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2558 | |
Oscar Mateo | cc9130b | 2014-07-24 17:04:42 +0100 | [diff] [blame] | 2559 | while (!list_empty(&ring->execlist_queue)) { |
| 2560 | struct intel_ctx_submit_request *submit_req; |
| 2561 | |
| 2562 | submit_req = list_first_entry(&ring->execlist_queue, |
| 2563 | struct intel_ctx_submit_request, |
| 2564 | execlist_link); |
| 2565 | list_del(&submit_req->execlist_link); |
| 2566 | intel_runtime_pm_put(dev_priv); |
| 2567 | i915_gem_context_unreference(submit_req->ctx); |
| 2568 | kfree(submit_req); |
| 2569 | } |
| 2570 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2571 | /* These may not have been flush before the reset, do so now */ |
| 2572 | kfree(ring->preallocated_lazy_request); |
| 2573 | ring->preallocated_lazy_request = NULL; |
| 2574 | ring->outstanding_lazy_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2575 | } |
| 2576 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2577 | void i915_gem_restore_fences(struct drm_device *dev) |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2578 | { |
| 2579 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2580 | int i; |
| 2581 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 2582 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2583 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2584 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 2585 | /* |
| 2586 | * Commit delayed tiling changes if we have an object still |
| 2587 | * attached to the fence, otherwise just clear the fence. |
| 2588 | */ |
| 2589 | if (reg->obj) { |
| 2590 | i915_gem_object_update_fence(reg->obj, reg, |
| 2591 | reg->obj->tiling_mode); |
| 2592 | } else { |
| 2593 | i915_gem_write_fence(dev, i, NULL); |
| 2594 | } |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2595 | } |
| 2596 | } |
| 2597 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2598 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2599 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2600 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2601 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2602 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2603 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2604 | /* |
| 2605 | * Before we free the objects from the requests, we need to inspect |
| 2606 | * them for finding the guilty party. As the requests only borrow |
| 2607 | * their reference to the objects, the inspection must be done first. |
| 2608 | */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2609 | for_each_ring(ring, dev_priv, i) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2610 | i915_gem_reset_ring_status(dev_priv, ring); |
| 2611 | |
| 2612 | for_each_ring(ring, dev_priv, i) |
| 2613 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2614 | |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2615 | i915_gem_context_reset(dev); |
| 2616 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2617 | i915_gem_restore_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2618 | } |
| 2619 | |
| 2620 | /** |
| 2621 | * This function clears the request list as sequence numbers are passed. |
| 2622 | */ |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 2623 | void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2624 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2625 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2626 | uint32_t seqno; |
| 2627 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2628 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 2629 | return; |
| 2630 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2631 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2632 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 2633 | seqno = ring->get_seqno(ring, true); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2634 | |
Chris Wilson | e910303 | 2014-01-07 11:45:14 +0000 | [diff] [blame] | 2635 | /* Move any buffers on the active list that are no longer referenced |
| 2636 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 2637 | * before we free the context associated with the requests. |
| 2638 | */ |
| 2639 | while (!list_empty(&ring->active_list)) { |
| 2640 | struct drm_i915_gem_object *obj; |
| 2641 | |
| 2642 | obj = list_first_entry(&ring->active_list, |
| 2643 | struct drm_i915_gem_object, |
| 2644 | ring_list); |
| 2645 | |
| 2646 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
| 2647 | break; |
| 2648 | |
| 2649 | i915_gem_object_move_to_inactive(obj); |
| 2650 | } |
| 2651 | |
| 2652 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2653 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2654 | struct drm_i915_gem_request *request; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2655 | struct intel_ringbuffer *ringbuf; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2656 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2657 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2658 | struct drm_i915_gem_request, |
| 2659 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2660 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2661 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2662 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2663 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2664 | trace_i915_gem_request_retire(ring, request->seqno); |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2665 | |
| 2666 | /* This is one of the few common intersection points |
| 2667 | * between legacy ringbuffer submission and execlists: |
| 2668 | * we need to tell them apart in order to find the correct |
| 2669 | * ringbuffer to which the request belongs to. |
| 2670 | */ |
| 2671 | if (i915.enable_execlists) { |
| 2672 | struct intel_context *ctx = request->ctx; |
| 2673 | ringbuf = ctx->engine[ring->id].ringbuf; |
| 2674 | } else |
| 2675 | ringbuf = ring->buffer; |
| 2676 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2677 | /* We know the GPU must have read the request to have |
| 2678 | * sent us the seqno + interrupt, so use the position |
| 2679 | * of tail of the request to update the last known position |
| 2680 | * of the GPU head. |
| 2681 | */ |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2682 | ringbuf->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2683 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2684 | i915_gem_free_request(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2685 | } |
| 2686 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2687 | if (unlikely(ring->trace_irq_seqno && |
| 2688 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2689 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2690 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2691 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2692 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2693 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2694 | } |
| 2695 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2696 | bool |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2697 | i915_gem_retire_requests(struct drm_device *dev) |
| 2698 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2699 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2700 | struct intel_engine_cs *ring; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2701 | bool idle = true; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2702 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2703 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2704 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2705 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2706 | idle &= list_empty(&ring->request_list); |
| 2707 | } |
| 2708 | |
| 2709 | if (idle) |
| 2710 | mod_delayed_work(dev_priv->wq, |
| 2711 | &dev_priv->mm.idle_work, |
| 2712 | msecs_to_jiffies(100)); |
| 2713 | |
| 2714 | return idle; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2715 | } |
| 2716 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2717 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2718 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2719 | { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2720 | struct drm_i915_private *dev_priv = |
| 2721 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 2722 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2723 | bool idle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2724 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2725 | /* Come back later if the device is busy... */ |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2726 | idle = false; |
| 2727 | if (mutex_trylock(&dev->struct_mutex)) { |
| 2728 | idle = i915_gem_retire_requests(dev); |
| 2729 | mutex_unlock(&dev->struct_mutex); |
| 2730 | } |
| 2731 | if (!idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2732 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2733 | round_jiffies_up_relative(HZ)); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2734 | } |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2735 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2736 | static void |
| 2737 | i915_gem_idle_work_handler(struct work_struct *work) |
| 2738 | { |
| 2739 | struct drm_i915_private *dev_priv = |
| 2740 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2741 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2742 | intel_mark_idle(dev_priv->dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2743 | } |
| 2744 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2745 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2746 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2747 | * write domains, emitting any outstanding lazy request and retiring and |
| 2748 | * completed requests. |
| 2749 | */ |
| 2750 | static int |
| 2751 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2752 | { |
| 2753 | int ret; |
| 2754 | |
| 2755 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2756 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2757 | if (ret) |
| 2758 | return ret; |
| 2759 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2760 | i915_gem_retire_requests_ring(obj->ring); |
| 2761 | } |
| 2762 | |
| 2763 | return 0; |
| 2764 | } |
| 2765 | |
| 2766 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2767 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2768 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2769 | * |
| 2770 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2771 | * the timeout parameter. |
| 2772 | * -ETIME: object is still busy after timeout |
| 2773 | * -ERESTARTSYS: signal interrupted the wait |
| 2774 | * -ENONENT: object doesn't exist |
| 2775 | * Also possible, but rare: |
| 2776 | * -EAGAIN: GPU wedged |
| 2777 | * -ENOMEM: damn |
| 2778 | * -ENODEV: Internal IRQ fail |
| 2779 | * -E?: The add request failed |
| 2780 | * |
| 2781 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2782 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2783 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2784 | * without holding struct_mutex the object may become re-busied before this |
| 2785 | * function completes. A similar but shorter * race condition exists in the busy |
| 2786 | * ioctl |
| 2787 | */ |
| 2788 | int |
| 2789 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2790 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2791 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2792 | struct drm_i915_gem_wait *args = data; |
| 2793 | struct drm_i915_gem_object *obj; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2794 | struct intel_engine_cs *ring = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2795 | unsigned reset_counter; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2796 | u32 seqno = 0; |
| 2797 | int ret = 0; |
| 2798 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2799 | ret = i915_mutex_lock_interruptible(dev); |
| 2800 | if (ret) |
| 2801 | return ret; |
| 2802 | |
| 2803 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2804 | if (&obj->base == NULL) { |
| 2805 | mutex_unlock(&dev->struct_mutex); |
| 2806 | return -ENOENT; |
| 2807 | } |
| 2808 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2809 | /* Need to make sure the object gets inactive eventually. */ |
| 2810 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2811 | if (ret) |
| 2812 | goto out; |
| 2813 | |
| 2814 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2815 | seqno = obj->last_read_seqno; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2816 | ring = obj->ring; |
| 2817 | } |
| 2818 | |
| 2819 | if (seqno == 0) |
| 2820 | goto out; |
| 2821 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2822 | /* Do this after OLR check to make sure we make forward progress polling |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 2823 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2824 | */ |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 2825 | if (args->timeout_ns <= 0) { |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2826 | ret = -ETIME; |
| 2827 | goto out; |
| 2828 | } |
| 2829 | |
| 2830 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2831 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2832 | mutex_unlock(&dev->struct_mutex); |
| 2833 | |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 2834 | return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns, |
| 2835 | file->driver_priv); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2836 | |
| 2837 | out: |
| 2838 | drm_gem_object_unreference(&obj->base); |
| 2839 | mutex_unlock(&dev->struct_mutex); |
| 2840 | return ret; |
| 2841 | } |
| 2842 | |
| 2843 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2844 | * i915_gem_object_sync - sync an object to a ring. |
| 2845 | * |
| 2846 | * @obj: object which may be in use on another ring. |
| 2847 | * @to: ring we wish to use the object on. May be NULL. |
| 2848 | * |
| 2849 | * This code is meant to abstract object synchronization with the GPU. |
| 2850 | * Calling with NULL implies synchronizing the object with the CPU |
| 2851 | * rather than a particular GPU ring. |
| 2852 | * |
| 2853 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2854 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2855 | int |
| 2856 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2857 | struct intel_engine_cs *to) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2858 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2859 | struct intel_engine_cs *from = obj->ring; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2860 | u32 seqno; |
| 2861 | int ret, idx; |
| 2862 | |
| 2863 | if (from == NULL || to == from) |
| 2864 | return 0; |
| 2865 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2866 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2867 | return i915_gem_object_wait_rendering(obj, false); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2868 | |
| 2869 | idx = intel_ring_sync_index(from, to); |
| 2870 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2871 | seqno = obj->last_read_seqno; |
Rodrigo Vivi | ddd4dbc | 2014-06-30 09:51:11 -0700 | [diff] [blame] | 2872 | /* Optimization: Avoid semaphore sync when we are sure we already |
| 2873 | * waited for an object with higher seqno */ |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2874 | if (seqno <= from->semaphore.sync_seqno[idx]) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2875 | return 0; |
| 2876 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2877 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2878 | if (ret) |
| 2879 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2880 | |
Chris Wilson | b52b89d | 2013-09-25 11:43:28 +0100 | [diff] [blame] | 2881 | trace_i915_gem_ring_sync_to(from, to, seqno); |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2882 | ret = to->semaphore.sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2883 | if (!ret) |
Mika Kuoppala | 7b01e26 | 2012-11-28 17:18:45 +0200 | [diff] [blame] | 2884 | /* We use last_read_seqno because sync_to() |
| 2885 | * might have just caused seqno wrap under |
| 2886 | * the radar. |
| 2887 | */ |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2888 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2889 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2890 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2891 | } |
| 2892 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2893 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2894 | { |
| 2895 | u32 old_write_domain, old_read_domains; |
| 2896 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2897 | /* Force a pagefault for domain tracking on next user access */ |
| 2898 | i915_gem_release_mmap(obj); |
| 2899 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2900 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2901 | return; |
| 2902 | |
Chris Wilson | 97c809fd | 2012-10-09 19:24:38 +0100 | [diff] [blame] | 2903 | /* Wait for any direct GTT access to complete */ |
| 2904 | mb(); |
| 2905 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2906 | old_read_domains = obj->base.read_domains; |
| 2907 | old_write_domain = obj->base.write_domain; |
| 2908 | |
| 2909 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2910 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2911 | |
| 2912 | trace_i915_gem_object_change_domain(obj, |
| 2913 | old_read_domains, |
| 2914 | old_write_domain); |
| 2915 | } |
| 2916 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2917 | int i915_vma_unbind(struct i915_vma *vma) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2918 | { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2919 | struct drm_i915_gem_object *obj = vma->obj; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2920 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2921 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2922 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2923 | if (list_empty(&vma->vma_link)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2924 | return 0; |
| 2925 | |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 2926 | if (!drm_mm_node_allocated(&vma->node)) { |
| 2927 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 2928 | return 0; |
| 2929 | } |
Ben Widawsky | 433544b | 2013-08-13 18:09:06 -0700 | [diff] [blame] | 2930 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2931 | if (vma->pin_count) |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 2932 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2933 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 2934 | BUG_ON(obj->pages == NULL); |
| 2935 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2936 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2937 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2938 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2939 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2940 | * should be safe and we need to cleanup or else we might |
| 2941 | * cause memory corruption through use-after-free. |
| 2942 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2943 | |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 2944 | if (i915_is_ggtt(vma->vm)) { |
| 2945 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2946 | |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 2947 | /* release the fence reg _after_ flushing */ |
| 2948 | ret = i915_gem_object_put_fence(obj); |
| 2949 | if (ret) |
| 2950 | return ret; |
| 2951 | } |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2952 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2953 | trace_i915_vma_unbind(vma); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2954 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2955 | vma->unbind_vma(vma); |
| 2956 | |
Chris Wilson | 64bf930 | 2014-02-25 14:23:28 +0000 | [diff] [blame] | 2957 | list_del_init(&vma->mm_list); |
Ben Widawsky | 5cacaac | 2013-07-31 17:00:13 -0700 | [diff] [blame] | 2958 | if (i915_is_ggtt(vma->vm)) |
Chris Wilson | e6a8446 | 2014-08-11 12:00:12 +0200 | [diff] [blame] | 2959 | obj->map_and_fenceable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2960 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2961 | drm_mm_remove_node(&vma->node); |
| 2962 | i915_gem_vma_destroy(vma); |
| 2963 | |
| 2964 | /* Since the unbound list is global, only move to that list if |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 2965 | * no more VMAs exist. */ |
Armin Reese | 9490edb | 2014-07-11 10:20:07 -0700 | [diff] [blame] | 2966 | if (list_empty(&obj->vma_list)) { |
| 2967 | i915_gem_gtt_finish_object(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2968 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Armin Reese | 9490edb | 2014-07-11 10:20:07 -0700 | [diff] [blame] | 2969 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2970 | |
Chris Wilson | 70903c3 | 2013-12-04 09:59:09 +0000 | [diff] [blame] | 2971 | /* And finally now the object is completely decoupled from this vma, |
| 2972 | * we can drop its hold on the backing storage and allow it to be |
| 2973 | * reaped by the shrinker. |
| 2974 | */ |
| 2975 | i915_gem_object_unpin_pages(obj); |
| 2976 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2977 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2978 | } |
| 2979 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2980 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2981 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2982 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2983 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2984 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2985 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2986 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2987 | for_each_ring(ring, dev_priv, i) { |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame^] | 2988 | if (!i915.enable_execlists) { |
| 2989 | ret = i915_switch_context(ring, ring->default_context); |
| 2990 | if (ret) |
| 2991 | return ret; |
| 2992 | } |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 2993 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2994 | ret = intel_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2995 | if (ret) |
| 2996 | return ret; |
| 2997 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2998 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2999 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3000 | } |
| 3001 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3002 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 3003 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3004 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3005 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3006 | int fence_reg; |
| 3007 | int fence_pitch_shift; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3008 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3009 | if (INTEL_INFO(dev)->gen >= 6) { |
| 3010 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 3011 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 3012 | } else { |
| 3013 | fence_reg = FENCE_REG_965_0; |
| 3014 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 3015 | } |
| 3016 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3017 | fence_reg += reg * 8; |
| 3018 | |
| 3019 | /* To w/a incoherency with non-atomic 64-bit register updates, |
| 3020 | * we split the 64-bit update into two 32-bit writes. In order |
| 3021 | * for a partial fence not to be evaluated between writes, we |
| 3022 | * precede the update with write to turn off the fence register, |
| 3023 | * and only enable the fence as the last step. |
| 3024 | * |
| 3025 | * For extra levels of paranoia, we make sure each step lands |
| 3026 | * before applying the next step. |
| 3027 | */ |
| 3028 | I915_WRITE(fence_reg, 0); |
| 3029 | POSTING_READ(fence_reg); |
| 3030 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3031 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3032 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3033 | uint64_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3034 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3035 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3036 | 0xfffff000) << 32; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3037 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3038 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3039 | if (obj->tiling_mode == I915_TILING_Y) |
| 3040 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 3041 | val |= I965_FENCE_REG_VALID; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 3042 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3043 | I915_WRITE(fence_reg + 4, val >> 32); |
| 3044 | POSTING_READ(fence_reg + 4); |
| 3045 | |
| 3046 | I915_WRITE(fence_reg + 0, val); |
| 3047 | POSTING_READ(fence_reg); |
| 3048 | } else { |
| 3049 | I915_WRITE(fence_reg + 4, 0); |
| 3050 | POSTING_READ(fence_reg + 4); |
| 3051 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3052 | } |
| 3053 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3054 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 3055 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3056 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3057 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3058 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3059 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3060 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3061 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3062 | int pitch_val; |
| 3063 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3064 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3065 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3066 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3067 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3068 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 3069 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3070 | |
| 3071 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 3072 | tile_width = 128; |
| 3073 | else |
| 3074 | tile_width = 512; |
| 3075 | |
| 3076 | /* Note: pitch better be a power of two tile widths */ |
| 3077 | pitch_val = obj->stride / tile_width; |
| 3078 | pitch_val = ffs(pitch_val) - 1; |
| 3079 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3080 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3081 | if (obj->tiling_mode == I915_TILING_Y) |
| 3082 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3083 | val |= I915_FENCE_SIZE_BITS(size); |
| 3084 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3085 | val |= I830_FENCE_REG_VALID; |
| 3086 | } else |
| 3087 | val = 0; |
| 3088 | |
| 3089 | if (reg < 8) |
| 3090 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3091 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3092 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 3093 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3094 | I915_WRITE(reg, val); |
| 3095 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3096 | } |
| 3097 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3098 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 3099 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3100 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3101 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3102 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3103 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3104 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3105 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3106 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3107 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3108 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3109 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3110 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3111 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
| 3112 | i915_gem_obj_ggtt_offset(obj), size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 3113 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3114 | pitch_val = obj->stride / 128; |
| 3115 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3116 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3117 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3118 | if (obj->tiling_mode == I915_TILING_Y) |
| 3119 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3120 | val |= I830_FENCE_SIZE_BITS(size); |
| 3121 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3122 | val |= I830_FENCE_REG_VALID; |
| 3123 | } else |
| 3124 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 3125 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3126 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 3127 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 3128 | } |
| 3129 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3130 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 3131 | { |
| 3132 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 3133 | } |
| 3134 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3135 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 3136 | struct drm_i915_gem_object *obj) |
| 3137 | { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3138 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3139 | |
| 3140 | /* Ensure that all CPU reads are completed before installing a fence |
| 3141 | * and all writes before removing the fence. |
| 3142 | */ |
| 3143 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 3144 | mb(); |
| 3145 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 3146 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
| 3147 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
| 3148 | obj->stride, obj->tiling_mode); |
| 3149 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3150 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | 5ab3133 | 2013-11-02 21:07:03 -0700 | [diff] [blame] | 3151 | case 8: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3152 | case 7: |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3153 | case 6: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3154 | case 5: |
| 3155 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 3156 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 3157 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
Ben Widawsky | 7dbf9d6 | 2012-12-18 10:31:22 -0800 | [diff] [blame] | 3158 | default: BUG(); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3159 | } |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3160 | |
| 3161 | /* And similarly be paranoid that no direct access to this region |
| 3162 | * is reordered to before the fence is installed. |
| 3163 | */ |
| 3164 | if (i915_gem_object_needs_mb(obj)) |
| 3165 | mb(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3166 | } |
| 3167 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3168 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 3169 | struct drm_i915_fence_reg *fence) |
| 3170 | { |
| 3171 | return fence - dev_priv->fence_regs; |
| 3172 | } |
| 3173 | |
| 3174 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 3175 | struct drm_i915_fence_reg *fence, |
| 3176 | bool enable) |
| 3177 | { |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 3178 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3179 | int reg = fence_number(dev_priv, fence); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3180 | |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3181 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3182 | |
| 3183 | if (enable) { |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3184 | obj->fence_reg = reg; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3185 | fence->obj = obj; |
| 3186 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 3187 | } else { |
| 3188 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3189 | fence->obj = NULL; |
| 3190 | list_del_init(&fence->lru_list); |
| 3191 | } |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 3192 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3193 | } |
| 3194 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3195 | static int |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3196 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3197 | { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 3198 | if (obj->last_fenced_seqno) { |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 3199 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 3200 | if (ret) |
| 3201 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3202 | |
| 3203 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3204 | } |
| 3205 | |
| 3206 | return 0; |
| 3207 | } |
| 3208 | |
| 3209 | int |
| 3210 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 3211 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3212 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3213 | struct drm_i915_fence_reg *fence; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3214 | int ret; |
| 3215 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3216 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3217 | if (ret) |
| 3218 | return ret; |
| 3219 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3220 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 3221 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3222 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3223 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 3224 | |
Daniel Vetter | aff10b30 | 2014-02-14 14:06:05 +0100 | [diff] [blame] | 3225 | if (WARN_ON(fence->pin_count)) |
| 3226 | return -EBUSY; |
| 3227 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3228 | i915_gem_object_fence_lost(obj); |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3229 | i915_gem_object_update_fence(obj, fence, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3230 | |
| 3231 | return 0; |
| 3232 | } |
| 3233 | |
| 3234 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 3235 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3236 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3237 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 3238 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3239 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3240 | |
| 3241 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3242 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3243 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 3244 | reg = &dev_priv->fence_regs[i]; |
| 3245 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3246 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3247 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3248 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3249 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3250 | } |
| 3251 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3252 | if (avail == NULL) |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3253 | goto deadlock; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3254 | |
| 3255 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3256 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3257 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3258 | continue; |
| 3259 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 3260 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3261 | } |
| 3262 | |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3263 | deadlock: |
| 3264 | /* Wait for completion of pending flips which consume fences */ |
| 3265 | if (intel_has_pending_fb_unpin(dev)) |
| 3266 | return ERR_PTR(-EAGAIN); |
| 3267 | |
| 3268 | return ERR_PTR(-EDEADLK); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3269 | } |
| 3270 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3271 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3272 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3273 | * @obj: object to map through a fence reg |
| 3274 | * |
| 3275 | * When mapping objects through the GTT, userspace wants to be able to write |
| 3276 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3277 | * This function walks the fence regs looking for a free one for @obj, |
| 3278 | * stealing one if it can't find any. |
| 3279 | * |
| 3280 | * It then sets up the reg based on the object's properties: address, pitch |
| 3281 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3282 | * |
| 3283 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3284 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 3285 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 3286 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3287 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3288 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3289 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3290 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3291 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3292 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3293 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3294 | /* Have we updated the tiling parameters upon the object and so |
| 3295 | * will need to serialise the write to the associated fence register? |
| 3296 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3297 | if (obj->fence_dirty) { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3298 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3299 | if (ret) |
| 3300 | return ret; |
| 3301 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3302 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3303 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3304 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 3305 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3306 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3307 | list_move_tail(®->lru_list, |
| 3308 | &dev_priv->mm.fence_list); |
| 3309 | return 0; |
| 3310 | } |
| 3311 | } else if (enable) { |
Chris Wilson | e6a8446 | 2014-08-11 12:00:12 +0200 | [diff] [blame] | 3312 | if (WARN_ON(!obj->map_and_fenceable)) |
| 3313 | return -EINVAL; |
| 3314 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3315 | reg = i915_find_fence_reg(dev); |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3316 | if (IS_ERR(reg)) |
| 3317 | return PTR_ERR(reg); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3318 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3319 | if (reg->obj) { |
| 3320 | struct drm_i915_gem_object *old = reg->obj; |
| 3321 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3322 | ret = i915_gem_object_wait_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3323 | if (ret) |
| 3324 | return ret; |
| 3325 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3326 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3327 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3328 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3329 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3330 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3331 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3332 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3333 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3334 | } |
| 3335 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3336 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
| 3337 | struct drm_mm_node *gtt_space, |
| 3338 | unsigned long cache_level) |
| 3339 | { |
| 3340 | struct drm_mm_node *other; |
| 3341 | |
| 3342 | /* On non-LLC machines we have to be careful when putting differing |
| 3343 | * types of snoopable memory together to avoid the prefetcher |
Damien Lespiau | 4239ca7 | 2012-12-03 16:26:16 +0000 | [diff] [blame] | 3344 | * crossing memory domains and dying. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3345 | */ |
| 3346 | if (HAS_LLC(dev)) |
| 3347 | return true; |
| 3348 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3349 | if (!drm_mm_node_allocated(gtt_space)) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3350 | return true; |
| 3351 | |
| 3352 | if (list_empty(>t_space->node_list)) |
| 3353 | return true; |
| 3354 | |
| 3355 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3356 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3357 | return false; |
| 3358 | |
| 3359 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3360 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3361 | return false; |
| 3362 | |
| 3363 | return true; |
| 3364 | } |
| 3365 | |
| 3366 | static void i915_gem_verify_gtt(struct drm_device *dev) |
| 3367 | { |
| 3368 | #if WATCH_GTT |
| 3369 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3370 | struct drm_i915_gem_object *obj; |
| 3371 | int err = 0; |
| 3372 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3373 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3374 | if (obj->gtt_space == NULL) { |
| 3375 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
| 3376 | err++; |
| 3377 | continue; |
| 3378 | } |
| 3379 | |
| 3380 | if (obj->cache_level != obj->gtt_space->color) { |
| 3381 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3382 | i915_gem_obj_ggtt_offset(obj), |
| 3383 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3384 | obj->cache_level, |
| 3385 | obj->gtt_space->color); |
| 3386 | err++; |
| 3387 | continue; |
| 3388 | } |
| 3389 | |
| 3390 | if (!i915_gem_valid_gtt_space(dev, |
| 3391 | obj->gtt_space, |
| 3392 | obj->cache_level)) { |
| 3393 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3394 | i915_gem_obj_ggtt_offset(obj), |
| 3395 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3396 | obj->cache_level); |
| 3397 | err++; |
| 3398 | continue; |
| 3399 | } |
| 3400 | } |
| 3401 | |
| 3402 | WARN_ON(err); |
| 3403 | #endif |
| 3404 | } |
| 3405 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3406 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3407 | * Finds free space in the GTT aperture and binds the object there. |
| 3408 | */ |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3409 | static struct i915_vma * |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3410 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3411 | struct i915_address_space *vm, |
| 3412 | unsigned alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3413 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3414 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3415 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3416 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3417 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3418 | unsigned long start = |
| 3419 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
| 3420 | unsigned long end = |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3421 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3422 | struct i915_vma *vma; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3423 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3424 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3425 | fence_size = i915_gem_get_gtt_size(dev, |
| 3426 | obj->base.size, |
| 3427 | obj->tiling_mode); |
| 3428 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3429 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3430 | obj->tiling_mode, true); |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3431 | unfenced_alignment = |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3432 | i915_gem_get_gtt_alignment(dev, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3433 | obj->base.size, |
| 3434 | obj->tiling_mode, false); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3435 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3436 | if (alignment == 0) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3437 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3438 | unfenced_alignment; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3439 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 3440 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3441 | return ERR_PTR(-EINVAL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3442 | } |
| 3443 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3444 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3445 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3446 | /* If the object is bigger than the entire aperture, reject it early |
| 3447 | * before evicting everything in a vain attempt to find space. |
| 3448 | */ |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3449 | if (obj->base.size > end) { |
| 3450 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", |
Chris Wilson | a36689c | 2013-05-21 16:58:49 +0100 | [diff] [blame] | 3451 | obj->base.size, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3452 | flags & PIN_MAPPABLE ? "mappable" : "total", |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3453 | end); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3454 | return ERR_PTR(-E2BIG); |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3455 | } |
| 3456 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3457 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3458 | if (ret) |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3459 | return ERR_PTR(ret); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3460 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3461 | i915_gem_object_pin_pages(obj); |
| 3462 | |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 3463 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3464 | if (IS_ERR(vma)) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3465 | goto err_unpin; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3466 | |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3467 | search_free: |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3468 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3469 | size, alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3470 | obj->cache_level, |
| 3471 | start, end, |
Lauri Kasanen | 62347f9 | 2014-04-02 20:03:57 +0300 | [diff] [blame] | 3472 | DRM_MM_SEARCH_DEFAULT, |
| 3473 | DRM_MM_CREATE_DEFAULT); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3474 | if (ret) { |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 3475 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3476 | obj->cache_level, |
| 3477 | start, end, |
| 3478 | flags); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3479 | if (ret == 0) |
| 3480 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3481 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3482 | goto err_free_vma; |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3483 | } |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3484 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3485 | obj->cache_level))) { |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3486 | ret = -EINVAL; |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3487 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3488 | } |
| 3489 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 3490 | ret = i915_gem_gtt_prepare_object(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3491 | if (ret) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3492 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3493 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3494 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3495 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3496 | |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3497 | if (i915_is_ggtt(vm)) { |
| 3498 | bool mappable, fenceable; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3499 | |
Daniel Vetter | 4998709 | 2013-08-14 10:21:23 +0200 | [diff] [blame] | 3500 | fenceable = (vma->node.size == fence_size && |
| 3501 | (vma->node.start & (fence_alignment - 1)) == 0); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3502 | |
Daniel Vetter | 4998709 | 2013-08-14 10:21:23 +0200 | [diff] [blame] | 3503 | mappable = (vma->node.start + obj->base.size <= |
| 3504 | dev_priv->gtt.mappable_end); |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3505 | |
Ben Widawsky | 5cacaac | 2013-07-31 17:00:13 -0700 | [diff] [blame] | 3506 | obj->map_and_fenceable = mappable && fenceable; |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3507 | } |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3508 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3509 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3510 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3511 | trace_i915_vma_bind(vma, flags); |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 3512 | vma->bind_vma(vma, obj->cache_level, |
| 3513 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); |
| 3514 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3515 | i915_gem_verify_gtt(dev); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3516 | return vma; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3517 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3518 | err_remove_node: |
Dan Carpenter | 6286ef9 | 2013-07-19 08:46:27 +0300 | [diff] [blame] | 3519 | drm_mm_remove_node(&vma->node); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3520 | err_free_vma: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3521 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3522 | vma = ERR_PTR(ret); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3523 | err_unpin: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3524 | i915_gem_object_unpin_pages(obj); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3525 | return vma; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3526 | } |
| 3527 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3528 | bool |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3529 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3530 | bool force) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3531 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3532 | /* If we don't have a page list set up, then we're not pinned |
| 3533 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3534 | * again at bind time. |
| 3535 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3536 | if (obj->pages == NULL) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3537 | return false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3538 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3539 | /* |
| 3540 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3541 | * marked as wc by the system, or the system is cache-coherent. |
| 3542 | */ |
| 3543 | if (obj->stolen) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3544 | return false; |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3545 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3546 | /* If the GPU is snooping the contents of the CPU cache, |
| 3547 | * we do not need to manually clear the CPU cache lines. However, |
| 3548 | * the caches are only snooped when the render cache is |
| 3549 | * flushed/invalidated. As we always have to emit invalidations |
| 3550 | * and flushes when moving into and out of the RENDER domain, correct |
| 3551 | * snooping behaviour occurs naturally as the result of our domain |
| 3552 | * tracking. |
| 3553 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3554 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3555 | return false; |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3556 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3557 | trace_i915_gem_object_clflush(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3558 | drm_clflush_sg(obj->pages); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3559 | |
| 3560 | return true; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3561 | } |
| 3562 | |
| 3563 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3564 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3565 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3566 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3567 | uint32_t old_write_domain; |
| 3568 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3569 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3570 | return; |
| 3571 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3572 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3573 | * to it immediately go to main memory as far as we know, so there's |
| 3574 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3575 | * |
| 3576 | * However, we do have to enforce the order so that all writes through |
| 3577 | * the GTT land before any writes to the device, such as updates to |
| 3578 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3579 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3580 | wmb(); |
| 3581 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3582 | old_write_domain = obj->base.write_domain; |
| 3583 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3584 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3585 | intel_fb_obj_flush(obj, false); |
| 3586 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3587 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3588 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3589 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3590 | } |
| 3591 | |
| 3592 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3593 | static void |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3594 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 3595 | bool force) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3596 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3597 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3598 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3599 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3600 | return; |
| 3601 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3602 | if (i915_gem_clflush_object(obj, force)) |
| 3603 | i915_gem_chipset_flush(obj->base.dev); |
| 3604 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3605 | old_write_domain = obj->base.write_domain; |
| 3606 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3607 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3608 | intel_fb_obj_flush(obj, false); |
| 3609 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3610 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3611 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3612 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3613 | } |
| 3614 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3615 | /** |
| 3616 | * Moves a single object to the GTT read, and possibly write domain. |
| 3617 | * |
| 3618 | * This function returns when the move is complete, including waiting on |
| 3619 | * flushes to occur. |
| 3620 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3621 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3622 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3623 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3624 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | dc8cd1e | 2014-08-09 17:37:22 +0100 | [diff] [blame] | 3625 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3626 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3627 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3628 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3629 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | dc8cd1e | 2014-08-09 17:37:22 +0100 | [diff] [blame] | 3630 | if (vma == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3631 | return -EINVAL; |
| 3632 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3633 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3634 | return 0; |
| 3635 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3636 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3637 | if (ret) |
| 3638 | return ret; |
| 3639 | |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 3640 | i915_gem_object_retire(obj); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3641 | i915_gem_object_flush_cpu_write_domain(obj, false); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3642 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3643 | /* Serialise direct access to this object with the barriers for |
| 3644 | * coherent writes from the GPU, by effectively invalidating the |
| 3645 | * GTT domain upon first access. |
| 3646 | */ |
| 3647 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3648 | mb(); |
| 3649 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3650 | old_write_domain = obj->base.write_domain; |
| 3651 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3652 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3653 | /* It should now be out of any other write domains, and we can update |
| 3654 | * the domain values for our changes. |
| 3655 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3656 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3657 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3658 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3659 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3660 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3661 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3662 | } |
| 3663 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3664 | if (write) |
| 3665 | intel_fb_obj_invalidate(obj, NULL); |
| 3666 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3667 | trace_i915_gem_object_change_domain(obj, |
| 3668 | old_read_domains, |
| 3669 | old_write_domain); |
| 3670 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3671 | /* And bump the LRU for this access */ |
Chris Wilson | dc8cd1e | 2014-08-09 17:37:22 +0100 | [diff] [blame] | 3672 | if (i915_gem_object_is_inactive(obj)) |
| 3673 | list_move_tail(&vma->mm_list, |
| 3674 | &dev_priv->gtt.base.inactive_list); |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3675 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3676 | return 0; |
| 3677 | } |
| 3678 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3679 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3680 | enum i915_cache_level cache_level) |
| 3681 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3682 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | df6f783 | 2014-03-21 07:40:56 +0000 | [diff] [blame] | 3683 | struct i915_vma *vma, *next; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3684 | int ret; |
| 3685 | |
| 3686 | if (obj->cache_level == cache_level) |
| 3687 | return 0; |
| 3688 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3689 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3690 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3691 | return -EBUSY; |
| 3692 | } |
| 3693 | |
Chris Wilson | df6f783 | 2014-03-21 07:40:56 +0000 | [diff] [blame] | 3694 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3695 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3696 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3697 | if (ret) |
| 3698 | return ret; |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3699 | } |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3700 | } |
| 3701 | |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3702 | if (i915_gem_obj_bound_any(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3703 | ret = i915_gem_object_finish_gpu(obj); |
| 3704 | if (ret) |
| 3705 | return ret; |
| 3706 | |
| 3707 | i915_gem_object_finish_gtt(obj); |
| 3708 | |
| 3709 | /* Before SandyBridge, you could not use tiling or fence |
| 3710 | * registers with snooped memory, so relinquish any fences |
| 3711 | * currently pointing to our region in the aperture. |
| 3712 | */ |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3713 | if (INTEL_INFO(dev)->gen < 6) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3714 | ret = i915_gem_object_put_fence(obj); |
| 3715 | if (ret) |
| 3716 | return ret; |
| 3717 | } |
| 3718 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3719 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 3720 | if (drm_mm_node_allocated(&vma->node)) |
| 3721 | vma->bind_vma(vma, cache_level, |
| 3722 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3723 | } |
| 3724 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3725 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 3726 | vma->node.color = cache_level; |
| 3727 | obj->cache_level = cache_level; |
| 3728 | |
| 3729 | if (cpu_write_needs_clflush(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3730 | u32 old_read_domains, old_write_domain; |
| 3731 | |
| 3732 | /* If we're coming from LLC cached, then we haven't |
| 3733 | * actually been tracking whether the data is in the |
| 3734 | * CPU cache or not, since we only allow one bit set |
| 3735 | * in obj->write_domain and have been skipping the clflushes. |
| 3736 | * Just set it to the CPU cache for now. |
| 3737 | */ |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 3738 | i915_gem_object_retire(obj); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3739 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3740 | |
| 3741 | old_read_domains = obj->base.read_domains; |
| 3742 | old_write_domain = obj->base.write_domain; |
| 3743 | |
| 3744 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3745 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3746 | |
| 3747 | trace_i915_gem_object_change_domain(obj, |
| 3748 | old_read_domains, |
| 3749 | old_write_domain); |
| 3750 | } |
| 3751 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3752 | i915_gem_verify_gtt(dev); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3753 | return 0; |
| 3754 | } |
| 3755 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3756 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3757 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3758 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3759 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3760 | struct drm_i915_gem_object *obj; |
| 3761 | int ret; |
| 3762 | |
| 3763 | ret = i915_mutex_lock_interruptible(dev); |
| 3764 | if (ret) |
| 3765 | return ret; |
| 3766 | |
| 3767 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3768 | if (&obj->base == NULL) { |
| 3769 | ret = -ENOENT; |
| 3770 | goto unlock; |
| 3771 | } |
| 3772 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3773 | switch (obj->cache_level) { |
| 3774 | case I915_CACHE_LLC: |
| 3775 | case I915_CACHE_L3_LLC: |
| 3776 | args->caching = I915_CACHING_CACHED; |
| 3777 | break; |
| 3778 | |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3779 | case I915_CACHE_WT: |
| 3780 | args->caching = I915_CACHING_DISPLAY; |
| 3781 | break; |
| 3782 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3783 | default: |
| 3784 | args->caching = I915_CACHING_NONE; |
| 3785 | break; |
| 3786 | } |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3787 | |
| 3788 | drm_gem_object_unreference(&obj->base); |
| 3789 | unlock: |
| 3790 | mutex_unlock(&dev->struct_mutex); |
| 3791 | return ret; |
| 3792 | } |
| 3793 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3794 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3795 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3796 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3797 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3798 | struct drm_i915_gem_object *obj; |
| 3799 | enum i915_cache_level level; |
| 3800 | int ret; |
| 3801 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3802 | switch (args->caching) { |
| 3803 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3804 | level = I915_CACHE_NONE; |
| 3805 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3806 | case I915_CACHING_CACHED: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3807 | level = I915_CACHE_LLC; |
| 3808 | break; |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3809 | case I915_CACHING_DISPLAY: |
| 3810 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 3811 | break; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3812 | default: |
| 3813 | return -EINVAL; |
| 3814 | } |
| 3815 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 3816 | ret = i915_mutex_lock_interruptible(dev); |
| 3817 | if (ret) |
| 3818 | return ret; |
| 3819 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3820 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3821 | if (&obj->base == NULL) { |
| 3822 | ret = -ENOENT; |
| 3823 | goto unlock; |
| 3824 | } |
| 3825 | |
| 3826 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3827 | |
| 3828 | drm_gem_object_unreference(&obj->base); |
| 3829 | unlock: |
| 3830 | mutex_unlock(&dev->struct_mutex); |
| 3831 | return ret; |
| 3832 | } |
| 3833 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3834 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
| 3835 | { |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3836 | struct i915_vma *vma; |
| 3837 | |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3838 | vma = i915_gem_obj_to_ggtt(obj); |
| 3839 | if (!vma) |
| 3840 | return false; |
| 3841 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3842 | /* There are 3 sources that pin objects: |
| 3843 | * 1. The display engine (scanouts, sprites, cursors); |
| 3844 | * 2. Reservations for execbuffer; |
| 3845 | * 3. The user. |
| 3846 | * |
| 3847 | * We can ignore reservations as we hold the struct_mutex and |
| 3848 | * are only called outside of the reservation path. The user |
| 3849 | * can only increment pin_count once, and so if after |
| 3850 | * subtracting the potential reference by the user, any pin_count |
| 3851 | * remains, it must be due to another use by the display engine. |
| 3852 | */ |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3853 | return vma->pin_count - !!obj->user_pin_count; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3854 | } |
| 3855 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3856 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3857 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3858 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3859 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3860 | */ |
| 3861 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3862 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3863 | u32 alignment, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3864 | struct intel_engine_cs *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3865 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3866 | u32 old_read_domains, old_write_domain; |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3867 | bool was_pin_display; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3868 | int ret; |
| 3869 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3870 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3871 | ret = i915_gem_object_sync(obj, pipelined); |
| 3872 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3873 | return ret; |
| 3874 | } |
| 3875 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3876 | /* Mark the pin_display early so that we account for the |
| 3877 | * display coherency whilst setting up the cache domains. |
| 3878 | */ |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3879 | was_pin_display = obj->pin_display; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3880 | obj->pin_display = true; |
| 3881 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3882 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3883 | * a result, we make sure that the pinning that is about to occur is |
| 3884 | * done with uncached PTEs. This is lowest common denominator for all |
| 3885 | * chipsets. |
| 3886 | * |
| 3887 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3888 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3889 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3890 | */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3891 | ret = i915_gem_object_set_cache_level(obj, |
| 3892 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3893 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3894 | goto err_unpin_display; |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3895 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3896 | /* As the user may map the buffer once pinned in the display plane |
| 3897 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3898 | * always use map_and_fenceable for all scanout buffers. |
| 3899 | */ |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3900 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3901 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3902 | goto err_unpin_display; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3903 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3904 | i915_gem_object_flush_cpu_write_domain(obj, true); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3905 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3906 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3907 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3908 | |
| 3909 | /* It should now be out of any other write domains, and we can update |
| 3910 | * the domain values for our changes. |
| 3911 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 3912 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3913 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3914 | |
| 3915 | trace_i915_gem_object_change_domain(obj, |
| 3916 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3917 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3918 | |
| 3919 | return 0; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3920 | |
| 3921 | err_unpin_display: |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3922 | WARN_ON(was_pin_display != is_pin_display(obj)); |
| 3923 | obj->pin_display = was_pin_display; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3924 | return ret; |
| 3925 | } |
| 3926 | |
| 3927 | void |
| 3928 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
| 3929 | { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3930 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3931 | obj->pin_display = is_pin_display(obj); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3932 | } |
| 3933 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3934 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3935 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3936 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3937 | int ret; |
| 3938 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3939 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3940 | return 0; |
| 3941 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3942 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3943 | if (ret) |
| 3944 | return ret; |
| 3945 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3946 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3947 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3948 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3949 | } |
| 3950 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3951 | /** |
| 3952 | * Moves a single object to the CPU read, and possibly write domain. |
| 3953 | * |
| 3954 | * This function returns when the move is complete, including waiting on |
| 3955 | * flushes to occur. |
| 3956 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3957 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3958 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3959 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3960 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3961 | int ret; |
| 3962 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3963 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3964 | return 0; |
| 3965 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3966 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3967 | if (ret) |
| 3968 | return ret; |
| 3969 | |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 3970 | i915_gem_object_retire(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3971 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3972 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3973 | old_write_domain = obj->base.write_domain; |
| 3974 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3975 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3976 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3977 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3978 | i915_gem_clflush_object(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3979 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3980 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3981 | } |
| 3982 | |
| 3983 | /* It should now be out of any other write domains, and we can update |
| 3984 | * the domain values for our changes. |
| 3985 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3986 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3987 | |
| 3988 | /* If we're writing through the CPU, then the GPU read domains will |
| 3989 | * need to be invalidated at next use. |
| 3990 | */ |
| 3991 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3992 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3993 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3994 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3995 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3996 | if (write) |
| 3997 | intel_fb_obj_invalidate(obj, NULL); |
| 3998 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3999 | trace_i915_gem_object_change_domain(obj, |
| 4000 | old_read_domains, |
| 4001 | old_write_domain); |
| 4002 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4003 | return 0; |
| 4004 | } |
| 4005 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4006 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 4007 | * emitted over 20 msec ago. |
| 4008 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4009 | * Note that if we were to use the current jiffies each time around the loop, |
| 4010 | * we wouldn't escape the function with any frames outstanding if the time to |
| 4011 | * render a frame was over 20ms. |
| 4012 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4013 | * This should get us reasonable parallelism between CPU and GPU but also |
| 4014 | * relatively low latency when blocking on a particular request to finish. |
| 4015 | */ |
| 4016 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4017 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4018 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4019 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4020 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4021 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4022 | struct drm_i915_gem_request *request; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4023 | struct intel_engine_cs *ring = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 4024 | unsigned reset_counter; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4025 | u32 seqno = 0; |
| 4026 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4027 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 4028 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 4029 | if (ret) |
| 4030 | return ret; |
| 4031 | |
| 4032 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 4033 | if (ret) |
| 4034 | return ret; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 4035 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4036 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4037 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4038 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 4039 | break; |
| 4040 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4041 | ring = request->ring; |
| 4042 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4043 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 4044 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4045 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4046 | |
| 4047 | if (seqno == 0) |
| 4048 | return 0; |
| 4049 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4050 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4051 | if (ret == 0) |
| 4052 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4053 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4054 | return ret; |
| 4055 | } |
| 4056 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4057 | static bool |
| 4058 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
| 4059 | { |
| 4060 | struct drm_i915_gem_object *obj = vma->obj; |
| 4061 | |
| 4062 | if (alignment && |
| 4063 | vma->node.start & (alignment - 1)) |
| 4064 | return true; |
| 4065 | |
| 4066 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
| 4067 | return true; |
| 4068 | |
| 4069 | if (flags & PIN_OFFSET_BIAS && |
| 4070 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
| 4071 | return true; |
| 4072 | |
| 4073 | return false; |
| 4074 | } |
| 4075 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4076 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4077 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 4078 | struct i915_address_space *vm, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4079 | uint32_t alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4080 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4081 | { |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4082 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4083 | struct i915_vma *vma; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4084 | int ret; |
| 4085 | |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4086 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
| 4087 | return -ENODEV; |
| 4088 | |
Daniel Vetter | bf3d149 | 2014-02-14 14:01:12 +0100 | [diff] [blame] | 4089 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4090 | return -EINVAL; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4091 | |
| 4092 | vma = i915_gem_obj_to_vma(obj, vm); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4093 | if (vma) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4094 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 4095 | return -EBUSY; |
| 4096 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4097 | if (i915_vma_misplaced(vma, alignment, flags)) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4098 | WARN(vma->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4099 | "bo is already pinned with incorrect alignment:" |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 4100 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4101 | " obj->map_and_fenceable=%d\n", |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4102 | i915_gem_obj_offset(obj, vm), alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4103 | !!(flags & PIN_MAPPABLE), |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4104 | obj->map_and_fenceable); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4105 | ret = i915_vma_unbind(vma); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4106 | if (ret) |
| 4107 | return ret; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4108 | |
| 4109 | vma = NULL; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4110 | } |
| 4111 | } |
| 4112 | |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4113 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 4114 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
| 4115 | if (IS_ERR(vma)) |
| 4116 | return PTR_ERR(vma); |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4117 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4118 | |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4119 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
| 4120 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 4121 | |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4122 | vma->pin_count++; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4123 | if (flags & PIN_MAPPABLE) |
| 4124 | obj->pin_mappable |= true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4125 | |
| 4126 | return 0; |
| 4127 | } |
| 4128 | |
| 4129 | void |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4130 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4131 | { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4132 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4133 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4134 | BUG_ON(!vma); |
| 4135 | BUG_ON(vma->pin_count == 0); |
| 4136 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
| 4137 | |
| 4138 | if (--vma->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 4139 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4140 | } |
| 4141 | |
Daniel Vetter | d8ffa60 | 2014-05-13 12:11:26 +0200 | [diff] [blame] | 4142 | bool |
| 4143 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 4144 | { |
| 4145 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4146 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4147 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); |
| 4148 | |
| 4149 | WARN_ON(!ggtt_vma || |
| 4150 | dev_priv->fence_regs[obj->fence_reg].pin_count > |
| 4151 | ggtt_vma->pin_count); |
| 4152 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
| 4153 | return true; |
| 4154 | } else |
| 4155 | return false; |
| 4156 | } |
| 4157 | |
| 4158 | void |
| 4159 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 4160 | { |
| 4161 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4162 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4163 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
| 4164 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 4165 | } |
| 4166 | } |
| 4167 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4168 | int |
| 4169 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4170 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4171 | { |
| 4172 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4173 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4174 | int ret; |
| 4175 | |
Daniel Vetter | 02f6bcc | 2013-12-18 16:30:22 +0100 | [diff] [blame] | 4176 | if (INTEL_INFO(dev)->gen >= 6) |
| 4177 | return -ENODEV; |
| 4178 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4179 | ret = i915_mutex_lock_interruptible(dev); |
| 4180 | if (ret) |
| 4181 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4182 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4183 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4184 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4185 | ret = -ENOENT; |
| 4186 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4187 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4188 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4189 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 4190 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 4191 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4192 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4193 | } |
| 4194 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4195 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 4196 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4197 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4198 | ret = -EINVAL; |
| 4199 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4200 | } |
| 4201 | |
Daniel Vetter | aa5f802 | 2013-10-10 14:46:37 +0200 | [diff] [blame] | 4202 | if (obj->user_pin_count == ULONG_MAX) { |
| 4203 | ret = -EBUSY; |
| 4204 | goto out; |
| 4205 | } |
| 4206 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 4207 | if (obj->user_pin_count == 0) { |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4208 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4209 | if (ret) |
| 4210 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4211 | } |
| 4212 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 4213 | obj->user_pin_count++; |
| 4214 | obj->pin_filp = file; |
| 4215 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 4216 | args->offset = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4217 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4218 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4219 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4220 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4221 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4222 | } |
| 4223 | |
| 4224 | int |
| 4225 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4226 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4227 | { |
| 4228 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4229 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4230 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4231 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4232 | ret = i915_mutex_lock_interruptible(dev); |
| 4233 | if (ret) |
| 4234 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4235 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4236 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4237 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4238 | ret = -ENOENT; |
| 4239 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4240 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4241 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4242 | if (obj->pin_filp != file) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 4243 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4244 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4245 | ret = -EINVAL; |
| 4246 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4247 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4248 | obj->user_pin_count--; |
| 4249 | if (obj->user_pin_count == 0) { |
| 4250 | obj->pin_filp = NULL; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4251 | i915_gem_object_ggtt_unpin(obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4252 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4253 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4254 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4255 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4256 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4257 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4258 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4259 | } |
| 4260 | |
| 4261 | int |
| 4262 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4263 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4264 | { |
| 4265 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4266 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4267 | int ret; |
| 4268 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4269 | ret = i915_mutex_lock_interruptible(dev); |
| 4270 | if (ret) |
| 4271 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4272 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4273 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4274 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4275 | ret = -ENOENT; |
| 4276 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4277 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4278 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4279 | /* Count all active objects as busy, even if they are currently not used |
| 4280 | * by the gpu. Users of this interface expect objects to eventually |
| 4281 | * become non-busy without any further actions, therefore emit any |
| 4282 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4283 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4284 | ret = i915_gem_object_flush_active(obj); |
| 4285 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4286 | args->busy = obj->active; |
Chris Wilson | e9808ed | 2012-07-04 12:25:08 +0100 | [diff] [blame] | 4287 | if (obj->ring) { |
| 4288 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 4289 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 4290 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4291 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4292 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4293 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4294 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4295 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4296 | } |
| 4297 | |
| 4298 | int |
| 4299 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4300 | struct drm_file *file_priv) |
| 4301 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 4302 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4303 | } |
| 4304 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4305 | int |
| 4306 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4307 | struct drm_file *file_priv) |
| 4308 | { |
| 4309 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4310 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4311 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4312 | |
| 4313 | switch (args->madv) { |
| 4314 | case I915_MADV_DONTNEED: |
| 4315 | case I915_MADV_WILLNEED: |
| 4316 | break; |
| 4317 | default: |
| 4318 | return -EINVAL; |
| 4319 | } |
| 4320 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4321 | ret = i915_mutex_lock_interruptible(dev); |
| 4322 | if (ret) |
| 4323 | return ret; |
| 4324 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4325 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4326 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4327 | ret = -ENOENT; |
| 4328 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4329 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4330 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4331 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4332 | ret = -EINVAL; |
| 4333 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4334 | } |
| 4335 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4336 | if (obj->madv != __I915_MADV_PURGED) |
| 4337 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4338 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4339 | /* if the object is no longer attached, discard its backing storage */ |
| 4340 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4341 | i915_gem_object_truncate(obj); |
| 4342 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4343 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4344 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4345 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4346 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4347 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4348 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4349 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4350 | } |
| 4351 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4352 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4353 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4354 | { |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4355 | INIT_LIST_HEAD(&obj->global_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4356 | INIT_LIST_HEAD(&obj->ring_list); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 4357 | INIT_LIST_HEAD(&obj->obj_exec_link); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4358 | INIT_LIST_HEAD(&obj->vma_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4359 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4360 | obj->ops = ops; |
| 4361 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4362 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4363 | obj->madv = I915_MADV_WILLNEED; |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4364 | |
| 4365 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4366 | } |
| 4367 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4368 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 4369 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4370 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4371 | }; |
| 4372 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4373 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4374 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4375 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4376 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4377 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 4378 | gfp_t mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4379 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4380 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4381 | if (obj == NULL) |
| 4382 | return NULL; |
| 4383 | |
| 4384 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4385 | i915_gem_object_free(obj); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4386 | return NULL; |
| 4387 | } |
| 4388 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4389 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4390 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4391 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4392 | mask &= ~__GFP_HIGHMEM; |
| 4393 | mask |= __GFP_DMA32; |
| 4394 | } |
| 4395 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4396 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4397 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4398 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4399 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4400 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4401 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4402 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4403 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 4404 | if (HAS_LLC(dev)) { |
| 4405 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 4406 | * cache) for about a 10% performance improvement |
| 4407 | * compared to uncached. Graphics requests other than |
| 4408 | * display scanout are coherent with the CPU in |
| 4409 | * accessing this cache. This means in this mode we |
| 4410 | * don't need to clflush on the CPU side, and on the |
| 4411 | * GPU side we only need to flush internal caches to |
| 4412 | * get data visible to the CPU. |
| 4413 | * |
| 4414 | * However, we maintain the display planes as UC, and so |
| 4415 | * need to rebind when first used as such. |
| 4416 | */ |
| 4417 | obj->cache_level = I915_CACHE_LLC; |
| 4418 | } else |
| 4419 | obj->cache_level = I915_CACHE_NONE; |
| 4420 | |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 4421 | trace_i915_gem_object_create(obj); |
| 4422 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4423 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4424 | } |
| 4425 | |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4426 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
| 4427 | { |
| 4428 | /* If we are the last user of the backing storage (be it shmemfs |
| 4429 | * pages or stolen etc), we know that the pages are going to be |
| 4430 | * immediately released. In this case, we can then skip copying |
| 4431 | * back the contents from the GPU. |
| 4432 | */ |
| 4433 | |
| 4434 | if (obj->madv != I915_MADV_WILLNEED) |
| 4435 | return false; |
| 4436 | |
| 4437 | if (obj->base.filp == NULL) |
| 4438 | return true; |
| 4439 | |
| 4440 | /* At first glance, this looks racy, but then again so would be |
| 4441 | * userspace racing mmap against close. However, the first external |
| 4442 | * reference to the filp can only be obtained through the |
| 4443 | * i915_gem_mmap_ioctl() which safeguards us against the user |
| 4444 | * acquiring such a reference whilst we are in the middle of |
| 4445 | * freeing the object. |
| 4446 | */ |
| 4447 | return atomic_long_read(&obj->base.filp->f_count) == 1; |
| 4448 | } |
| 4449 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4450 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4451 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4452 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4453 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4454 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4455 | struct i915_vma *vma, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4456 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4457 | intel_runtime_pm_get(dev_priv); |
| 4458 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 4459 | trace_i915_gem_object_destroy(obj); |
| 4460 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4461 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4462 | int ret; |
| 4463 | |
| 4464 | vma->pin_count = 0; |
| 4465 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4466 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4467 | bool was_interruptible; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4468 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4469 | was_interruptible = dev_priv->mm.interruptible; |
| 4470 | dev_priv->mm.interruptible = false; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4471 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4472 | WARN_ON(i915_vma_unbind(vma)); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4473 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4474 | dev_priv->mm.interruptible = was_interruptible; |
| 4475 | } |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4476 | } |
| 4477 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 4478 | i915_gem_object_detach_phys(obj); |
| 4479 | |
Ben Widawsky | 1d64ae7 | 2013-05-31 14:46:20 -0700 | [diff] [blame] | 4480 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4481 | * before progressing. */ |
| 4482 | if (obj->stolen) |
| 4483 | i915_gem_object_unpin_pages(obj); |
| 4484 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 4485 | WARN_ON(obj->frontbuffer_bits); |
| 4486 | |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 4487 | if (WARN_ON(obj->pages_pin_count)) |
| 4488 | obj->pages_pin_count = 0; |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4489 | if (discard_backing_storage(obj)) |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 4490 | obj->madv = I915_MADV_DONTNEED; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4491 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 4492 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4493 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 4494 | BUG_ON(obj->pages); |
| 4495 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 4496 | if (obj->base.import_attach) |
| 4497 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4498 | |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 4499 | if (obj->ops->release) |
| 4500 | obj->ops->release(obj); |
| 4501 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4502 | drm_gem_object_release(&obj->base); |
| 4503 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4504 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4505 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4506 | i915_gem_object_free(obj); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4507 | |
| 4508 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4509 | } |
| 4510 | |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4511 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4512 | struct i915_address_space *vm) |
| 4513 | { |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4514 | struct i915_vma *vma; |
| 4515 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4516 | if (vma->vm == vm) |
| 4517 | return vma; |
| 4518 | |
| 4519 | return NULL; |
| 4520 | } |
| 4521 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4522 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4523 | { |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4524 | struct i915_address_space *vm = NULL; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4525 | WARN_ON(vma->node.allocated); |
Chris Wilson | aaa0566 | 2013-08-20 12:56:40 +0100 | [diff] [blame] | 4526 | |
| 4527 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4528 | if (!list_empty(&vma->exec_list)) |
| 4529 | return; |
| 4530 | |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4531 | vm = vma->vm; |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4532 | |
Daniel Vetter | 841cd77 | 2014-08-06 15:04:48 +0200 | [diff] [blame] | 4533 | if (!i915_is_ggtt(vm)) |
| 4534 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4535 | |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 4536 | list_del(&vma->vma_link); |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 4537 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4538 | kfree(vma); |
| 4539 | } |
| 4540 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4541 | static void |
| 4542 | i915_gem_stop_ringbuffers(struct drm_device *dev) |
| 4543 | { |
| 4544 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4545 | struct intel_engine_cs *ring; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4546 | int i; |
| 4547 | |
| 4548 | for_each_ring(ring, dev_priv, i) |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4549 | dev_priv->gt.stop_ring(ring); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4550 | } |
| 4551 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4552 | int |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4553 | i915_gem_suspend(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4554 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4555 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4556 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4557 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4558 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4559 | if (dev_priv->ums.mm_suspended) |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4560 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4561 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4562 | ret = i915_gpu_idle(dev); |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4563 | if (ret) |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4564 | goto err; |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4565 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4566 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4567 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4568 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 4569 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4570 | i915_gem_evict_everything(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4571 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4572 | i915_kernel_lost_context(dev); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4573 | i915_gem_stop_ringbuffers(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4574 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4575 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4576 | * We need to replace this with a semaphore, or something. |
| 4577 | * And not confound ums.mm_suspended! |
| 4578 | */ |
| 4579 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, |
| 4580 | DRIVER_MODESET); |
| 4581 | mutex_unlock(&dev->struct_mutex); |
| 4582 | |
| 4583 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4584 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
Deepak S | 274fa1c | 2014-08-05 07:51:20 -0700 | [diff] [blame] | 4585 | flush_delayed_work(&dev_priv->mm.idle_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4586 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4587 | return 0; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4588 | |
| 4589 | err: |
| 4590 | mutex_unlock(&dev->struct_mutex); |
| 4591 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4592 | } |
| 4593 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4594 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4595 | { |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4596 | struct drm_device *dev = ring->dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4597 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 4598 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
| 4599 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4600 | int i, ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4601 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 4602 | if (!HAS_L3_DPF(dev) || !remap_info) |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4603 | return 0; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4604 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4605 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
| 4606 | if (ret) |
| 4607 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4608 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4609 | /* |
| 4610 | * Note: We do not worry about the concurrent register cacheline hang |
| 4611 | * here because no other code should access these registers other than |
| 4612 | * at initialization time. |
| 4613 | */ |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4614 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4615 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 4616 | intel_ring_emit(ring, reg_base + i); |
| 4617 | intel_ring_emit(ring, remap_info[i/4]); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4618 | } |
| 4619 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4620 | intel_ring_advance(ring); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4621 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4622 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4623 | } |
| 4624 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4625 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4626 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4627 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4628 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4629 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4630 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4631 | return; |
| 4632 | |
| 4633 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4634 | DISP_TILE_SURFACE_SWIZZLING); |
| 4635 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4636 | if (IS_GEN5(dev)) |
| 4637 | return; |
| 4638 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4639 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4640 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4641 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4642 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4643 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 31a5336 | 2013-11-02 21:07:04 -0700 | [diff] [blame] | 4644 | else if (IS_GEN8(dev)) |
| 4645 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4646 | else |
| 4647 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4648 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4649 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4650 | static bool |
| 4651 | intel_enable_blt(struct drm_device *dev) |
| 4652 | { |
| 4653 | if (!HAS_BLT(dev)) |
| 4654 | return false; |
| 4655 | |
| 4656 | /* The blitter was dysfunctional on early prototypes */ |
| 4657 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 4658 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 4659 | " graphics performance will be degraded.\n"); |
| 4660 | return false; |
| 4661 | } |
| 4662 | |
| 4663 | return true; |
| 4664 | } |
| 4665 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4666 | int i915_gem_init_rings(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4667 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4668 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4669 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4670 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4671 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4672 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4673 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4674 | |
| 4675 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4676 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4677 | if (ret) |
| 4678 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4679 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4680 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4681 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4682 | ret = intel_init_blt_ring_buffer(dev); |
| 4683 | if (ret) |
| 4684 | goto cleanup_bsd_ring; |
| 4685 | } |
| 4686 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4687 | if (HAS_VEBOX(dev)) { |
| 4688 | ret = intel_init_vebox_ring_buffer(dev); |
| 4689 | if (ret) |
| 4690 | goto cleanup_blt_ring; |
| 4691 | } |
| 4692 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4693 | if (HAS_BSD2(dev)) { |
| 4694 | ret = intel_init_bsd2_ring_buffer(dev); |
| 4695 | if (ret) |
| 4696 | goto cleanup_vebox_ring; |
| 4697 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4698 | |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4699 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 4700 | if (ret) |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4701 | goto cleanup_bsd2_ring; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4702 | |
| 4703 | return 0; |
| 4704 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4705 | cleanup_bsd2_ring: |
| 4706 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4707 | cleanup_vebox_ring: |
| 4708 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4709 | cleanup_blt_ring: |
| 4710 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 4711 | cleanup_bsd_ring: |
| 4712 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 4713 | cleanup_render_ring: |
| 4714 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 4715 | |
| 4716 | return ret; |
| 4717 | } |
| 4718 | |
| 4719 | int |
| 4720 | i915_gem_init_hw(struct drm_device *dev) |
| 4721 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4722 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 4723 | int ret, i; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4724 | |
| 4725 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 4726 | return -EIO; |
| 4727 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 4728 | if (dev_priv->ellc_size) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 4729 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4730 | |
Ville Syrjälä | 0bf2134 | 2013-11-29 14:56:12 +0200 | [diff] [blame] | 4731 | if (IS_HASWELL(dev)) |
| 4732 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 4733 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 4734 | |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4735 | if (HAS_PCH_NOP(dev)) { |
Daniel Vetter | 6ba844b | 2014-01-22 23:39:30 +0100 | [diff] [blame] | 4736 | if (IS_IVYBRIDGE(dev)) { |
| 4737 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4738 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4739 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4740 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 4741 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 4742 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 4743 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 4744 | } |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4745 | } |
| 4746 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4747 | i915_gem_init_swizzling(dev); |
| 4748 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4749 | ret = dev_priv->gt.init_rings(dev); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4750 | if (ret) |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4751 | return ret; |
| 4752 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4753 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
| 4754 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); |
| 4755 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4756 | /* |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4757 | * XXX: Contexts should only be initialized once. Doing a switch to the |
| 4758 | * default context switch however is something we'd like to do after |
| 4759 | * reset or thaw (the latter may not actually be necessary for HW, but |
| 4760 | * goes with our code better). Context switching requires rings (for |
| 4761 | * the do_switch), but before enabling PPGTT. So don't move this. |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4762 | */ |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4763 | ret = i915_gem_context_enable(dev_priv); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4764 | if (ret && ret != -EIO) { |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4765 | DRM_ERROR("Context enable failed %d\n", ret); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4766 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 4767 | |
| 4768 | return ret; |
| 4769 | } |
| 4770 | |
| 4771 | ret = i915_ppgtt_init_hw(dev); |
| 4772 | if (ret && ret != -EIO) { |
| 4773 | DRM_ERROR("PPGTT enable failed %d\n", ret); |
| 4774 | i915_gem_cleanup_ringbuffer(dev); |
Ben Widawsky | b7c36d2 | 2013-04-08 18:43:56 -0700 | [diff] [blame] | 4775 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4776 | |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4777 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4778 | } |
| 4779 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4780 | int i915_gem_init(struct drm_device *dev) |
| 4781 | { |
| 4782 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4783 | int ret; |
| 4784 | |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 4785 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
| 4786 | i915.enable_execlists); |
| 4787 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4788 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4789 | |
| 4790 | if (IS_VALLEYVIEW(dev)) { |
| 4791 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
Imre Deak | 981a5ae | 2014-04-14 20:24:22 +0300 | [diff] [blame] | 4792 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
| 4793 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & |
| 4794 | VLV_GTLC_ALLOWWAKEACK), 10)) |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4795 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 4796 | } |
| 4797 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4798 | if (!i915.enable_execlists) { |
| 4799 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; |
| 4800 | dev_priv->gt.init_rings = i915_gem_init_rings; |
| 4801 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; |
| 4802 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 4803 | } else { |
| 4804 | dev_priv->gt.do_execbuf = intel_execlists_submission; |
| 4805 | dev_priv->gt.init_rings = intel_logical_rings_init; |
| 4806 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; |
| 4807 | dev_priv->gt.stop_ring = intel_logical_ring_stop; |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4808 | } |
| 4809 | |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 4810 | ret = i915_gem_init_userptr(dev); |
| 4811 | if (ret) { |
| 4812 | mutex_unlock(&dev->struct_mutex); |
| 4813 | return ret; |
| 4814 | } |
| 4815 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 4816 | i915_gem_init_global_gtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4817 | |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4818 | ret = i915_gem_context_init(dev); |
Mika Kuoppala | e384869 | 2014-01-31 17:14:02 +0200 | [diff] [blame] | 4819 | if (ret) { |
| 4820 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4821 | return ret; |
Mika Kuoppala | e384869 | 2014-01-31 17:14:02 +0200 | [diff] [blame] | 4822 | } |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4823 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4824 | ret = i915_gem_init_hw(dev); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4825 | if (ret == -EIO) { |
| 4826 | /* Allow ring initialisation to fail by marking the GPU as |
| 4827 | * wedged. But we only want to do this where the GPU is angry, |
| 4828 | * for all other failure, such as an allocation failure, bail. |
| 4829 | */ |
| 4830 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
| 4831 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
| 4832 | ret = 0; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4833 | } |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4834 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4835 | |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 4836 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 4837 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4838 | dev_priv->dri1.allow_batchbuffer = 1; |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4839 | return ret; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4840 | } |
| 4841 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4842 | void |
| 4843 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4844 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4845 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4846 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4847 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4848 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4849 | for_each_ring(ring, dev_priv, i) |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4850 | dev_priv->gt.cleanup_ring(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4851 | } |
| 4852 | |
| 4853 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4854 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4855 | struct drm_file *file_priv) |
| 4856 | { |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4857 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4858 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4859 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4860 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4861 | return 0; |
| 4862 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4863 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4864 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4865 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4866 | } |
| 4867 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4868 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4869 | dev_priv->ums.mm_suspended = 0; |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4870 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4871 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4872 | if (ret != 0) { |
| 4873 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4874 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4875 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4876 | |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 4877 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4878 | |
Daniel Vetter | bb0f1b5 | 2013-11-03 21:09:27 +0100 | [diff] [blame] | 4879 | ret = drm_irq_install(dev, dev->pdev->irq); |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4880 | if (ret) |
| 4881 | goto cleanup_ringbuffer; |
Daniel Vetter | e090c53 | 2013-11-03 20:27:05 +0100 | [diff] [blame] | 4882 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4883 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4884 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4885 | |
| 4886 | cleanup_ringbuffer: |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4887 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4888 | dev_priv->ums.mm_suspended = 1; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4889 | mutex_unlock(&dev->struct_mutex); |
| 4890 | |
| 4891 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4892 | } |
| 4893 | |
| 4894 | int |
| 4895 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4896 | struct drm_file *file_priv) |
| 4897 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4898 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4899 | return 0; |
| 4900 | |
Daniel Vetter | e090c53 | 2013-11-03 20:27:05 +0100 | [diff] [blame] | 4901 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4902 | drm_irq_uninstall(dev); |
Daniel Vetter | e090c53 | 2013-11-03 20:27:05 +0100 | [diff] [blame] | 4903 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4904 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4905 | return i915_gem_suspend(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4906 | } |
| 4907 | |
| 4908 | void |
| 4909 | i915_gem_lastclose(struct drm_device *dev) |
| 4910 | { |
| 4911 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4912 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4913 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4914 | return; |
| 4915 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4916 | ret = i915_gem_suspend(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4917 | if (ret) |
| 4918 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4919 | } |
| 4920 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4921 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4922 | init_ring_lists(struct intel_engine_cs *ring) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4923 | { |
| 4924 | INIT_LIST_HEAD(&ring->active_list); |
| 4925 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4926 | } |
| 4927 | |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 4928 | void i915_init_vm(struct drm_i915_private *dev_priv, |
| 4929 | struct i915_address_space *vm) |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4930 | { |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 4931 | if (!i915_is_ggtt(vm)) |
| 4932 | drm_mm_init(&vm->mm, vm->start, vm->total); |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4933 | vm->dev = dev_priv->dev; |
| 4934 | INIT_LIST_HEAD(&vm->active_list); |
| 4935 | INIT_LIST_HEAD(&vm->inactive_list); |
| 4936 | INIT_LIST_HEAD(&vm->global_link); |
Chris Wilson | f72d21e | 2014-01-09 22:57:22 +0000 | [diff] [blame] | 4937 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4938 | } |
| 4939 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4940 | void |
| 4941 | i915_gem_load(struct drm_device *dev) |
| 4942 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4943 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4944 | int i; |
| 4945 | |
| 4946 | dev_priv->slab = |
| 4947 | kmem_cache_create("i915_gem_object", |
| 4948 | sizeof(struct drm_i915_gem_object), 0, |
| 4949 | SLAB_HWCACHE_ALIGN, |
| 4950 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4951 | |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4952 | INIT_LIST_HEAD(&dev_priv->vm_list); |
| 4953 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
| 4954 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 4955 | INIT_LIST_HEAD(&dev_priv->context_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4956 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 4957 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4958 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4959 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4960 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 4961 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4962 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4963 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4964 | i915_gem_retire_work_handler); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4965 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 4966 | i915_gem_idle_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4967 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4968 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4969 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
Ville Syrjälä | dbb4274 | 2014-02-25 15:13:41 +0200 | [diff] [blame] | 4970 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 4971 | I915_WRITE(MI_ARB_STATE, |
| 4972 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4973 | } |
| 4974 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 4975 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 4976 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4977 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4978 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4979 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4980 | |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 4981 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
| 4982 | dev_priv->num_fence_regs = 32; |
| 4983 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4984 | dev_priv->num_fence_regs = 16; |
| 4985 | else |
| 4986 | dev_priv->num_fence_regs = 8; |
| 4987 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4988 | /* Initialize fence registers to zero */ |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 4989 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 4990 | i915_gem_restore_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 4991 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4992 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4993 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4994 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 4995 | dev_priv->mm.interruptible = true; |
| 4996 | |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 4997 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
| 4998 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; |
| 4999 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; |
| 5000 | register_shrinker(&dev_priv->mm.shrinker); |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5001 | |
| 5002 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; |
| 5003 | register_oom_notifier(&dev_priv->mm.oom_notifier); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 5004 | |
| 5005 | mutex_init(&dev_priv->fb_tracking.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5006 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5007 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5008 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5009 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5010 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5011 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5012 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
| 5013 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5014 | /* Clean up our request list when the client is going away, so that |
| 5015 | * later retire_requests won't dereference our soon-to-be-gone |
| 5016 | * file_priv. |
| 5017 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5018 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5019 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5020 | struct drm_i915_gem_request *request; |
| 5021 | |
| 5022 | request = list_first_entry(&file_priv->mm.request_list, |
| 5023 | struct drm_i915_gem_request, |
| 5024 | client_list); |
| 5025 | list_del(&request->client_list); |
| 5026 | request->file_priv = NULL; |
| 5027 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5028 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5029 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5030 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5031 | static void |
| 5032 | i915_gem_file_idle_work_handler(struct work_struct *work) |
| 5033 | { |
| 5034 | struct drm_i915_file_private *file_priv = |
| 5035 | container_of(work, typeof(*file_priv), mm.idle_work.work); |
| 5036 | |
| 5037 | atomic_set(&file_priv->rps_wait_boost, false); |
| 5038 | } |
| 5039 | |
| 5040 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 5041 | { |
| 5042 | struct drm_i915_file_private *file_priv; |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5043 | int ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5044 | |
| 5045 | DRM_DEBUG_DRIVER("\n"); |
| 5046 | |
| 5047 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 5048 | if (!file_priv) |
| 5049 | return -ENOMEM; |
| 5050 | |
| 5051 | file->driver_priv = file_priv; |
| 5052 | file_priv->dev_priv = dev->dev_private; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 5053 | file_priv->file = file; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5054 | |
| 5055 | spin_lock_init(&file_priv->mm.lock); |
| 5056 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
| 5057 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, |
| 5058 | i915_gem_file_idle_work_handler); |
| 5059 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5060 | ret = i915_gem_context_open(dev, file); |
| 5061 | if (ret) |
| 5062 | kfree(file_priv); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5063 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5064 | return ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5065 | } |
| 5066 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 5067 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 5068 | struct drm_i915_gem_object *new, |
| 5069 | unsigned frontbuffer_bits) |
| 5070 | { |
| 5071 | if (old) { |
| 5072 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
| 5073 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
| 5074 | old->frontbuffer_bits &= ~frontbuffer_bits; |
| 5075 | } |
| 5076 | |
| 5077 | if (new) { |
| 5078 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
| 5079 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
| 5080 | new->frontbuffer_bits |= frontbuffer_bits; |
| 5081 | } |
| 5082 | } |
| 5083 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 5084 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
| 5085 | { |
| 5086 | if (!mutex_is_locked(mutex)) |
| 5087 | return false; |
| 5088 | |
| 5089 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
| 5090 | return mutex->owner == task; |
| 5091 | #else |
| 5092 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
| 5093 | return false; |
| 5094 | #endif |
| 5095 | } |
| 5096 | |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5097 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
| 5098 | { |
| 5099 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 5100 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) |
| 5101 | return false; |
| 5102 | |
| 5103 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) |
| 5104 | return false; |
| 5105 | |
| 5106 | *unlock = false; |
| 5107 | } else |
| 5108 | *unlock = true; |
| 5109 | |
| 5110 | return true; |
| 5111 | } |
| 5112 | |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5113 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
| 5114 | { |
| 5115 | struct i915_vma *vma; |
| 5116 | int count = 0; |
| 5117 | |
| 5118 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 5119 | if (drm_mm_node_allocated(&vma->node)) |
| 5120 | count++; |
| 5121 | |
| 5122 | return count; |
| 5123 | } |
| 5124 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5125 | static unsigned long |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5126 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5127 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5128 | struct drm_i915_private *dev_priv = |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5129 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5130 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 5131 | struct drm_i915_gem_object *obj; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5132 | unsigned long count; |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5133 | bool unlock; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5134 | |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5135 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
| 5136 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5137 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5138 | count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 5139 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 5140 | if (obj->pages_pin_count == 0) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5141 | count += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | fcb4a57 | 2013-07-31 16:59:57 -0700 | [diff] [blame] | 5142 | |
| 5143 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5144 | if (!i915_gem_obj_is_pinned(obj) && |
| 5145 | obj->pages_pin_count == num_vma_bound(obj)) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5146 | count += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | fcb4a57 | 2013-07-31 16:59:57 -0700 | [diff] [blame] | 5147 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5148 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 5149 | if (unlock) |
| 5150 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 5151 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5152 | return count; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5153 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5154 | |
| 5155 | /* All the new VM stuff */ |
| 5156 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 5157 | struct i915_address_space *vm) |
| 5158 | { |
| 5159 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5160 | struct i915_vma *vma; |
| 5161 | |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 5162 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5163 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5164 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 5165 | if (vma->vm == vm) |
| 5166 | return vma->node.start; |
| 5167 | |
| 5168 | } |
Daniel Vetter | f25748ea | 2014-06-17 22:34:38 +0200 | [diff] [blame] | 5169 | WARN(1, "%s vma for this object not found.\n", |
| 5170 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5171 | return -1; |
| 5172 | } |
| 5173 | |
| 5174 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 5175 | struct i915_address_space *vm) |
| 5176 | { |
| 5177 | struct i915_vma *vma; |
| 5178 | |
| 5179 | list_for_each_entry(vma, &o->vma_list, vma_link) |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 5180 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5181 | return true; |
| 5182 | |
| 5183 | return false; |
| 5184 | } |
| 5185 | |
| 5186 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 5187 | { |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5188 | struct i915_vma *vma; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5189 | |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5190 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5191 | if (drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5192 | return true; |
| 5193 | |
| 5194 | return false; |
| 5195 | } |
| 5196 | |
| 5197 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 5198 | struct i915_address_space *vm) |
| 5199 | { |
| 5200 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5201 | struct i915_vma *vma; |
| 5202 | |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 5203 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5204 | |
| 5205 | BUG_ON(list_empty(&o->vma_list)); |
| 5206 | |
| 5207 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5208 | if (vma->vm == vm) |
| 5209 | return vma->node.size; |
| 5210 | |
| 5211 | return 0; |
| 5212 | } |
| 5213 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5214 | static unsigned long |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5215 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5216 | { |
| 5217 | struct drm_i915_private *dev_priv = |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5218 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5219 | struct drm_device *dev = dev_priv->dev; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5220 | unsigned long freed; |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5221 | bool unlock; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5222 | |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5223 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
| 5224 | return SHRINK_STOP; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5225 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 5226 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
| 5227 | if (freed < sc->nr_to_scan) |
| 5228 | freed += __i915_gem_shrink(dev_priv, |
| 5229 | sc->nr_to_scan - freed, |
| 5230 | false); |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5231 | if (unlock) |
| 5232 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 5233 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5234 | return freed; |
| 5235 | } |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5236 | |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5237 | static int |
| 5238 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) |
| 5239 | { |
| 5240 | struct drm_i915_private *dev_priv = |
| 5241 | container_of(nb, struct drm_i915_private, mm.oom_notifier); |
| 5242 | struct drm_device *dev = dev_priv->dev; |
| 5243 | struct drm_i915_gem_object *obj; |
| 5244 | unsigned long timeout = msecs_to_jiffies(5000) + 1; |
| 5245 | unsigned long pinned, bound, unbound, freed; |
| 5246 | bool was_interruptible; |
| 5247 | bool unlock; |
| 5248 | |
Chris Wilson | a1db2fa | 2014-07-11 11:28:00 +0100 | [diff] [blame] | 5249 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5250 | schedule_timeout_killable(1); |
Chris Wilson | a1db2fa | 2014-07-11 11:28:00 +0100 | [diff] [blame] | 5251 | if (fatal_signal_pending(current)) |
| 5252 | return NOTIFY_DONE; |
| 5253 | } |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5254 | if (timeout == 0) { |
| 5255 | pr_err("Unable to purge GPU memory due lock contention.\n"); |
| 5256 | return NOTIFY_DONE; |
| 5257 | } |
| 5258 | |
| 5259 | was_interruptible = dev_priv->mm.interruptible; |
| 5260 | dev_priv->mm.interruptible = false; |
| 5261 | |
| 5262 | freed = i915_gem_shrink_all(dev_priv); |
| 5263 | |
| 5264 | dev_priv->mm.interruptible = was_interruptible; |
| 5265 | |
| 5266 | /* Because we may be allocating inside our own driver, we cannot |
| 5267 | * assert that there are no objects with pinned pages that are not |
| 5268 | * being pointed to by hardware. |
| 5269 | */ |
| 5270 | unbound = bound = pinned = 0; |
| 5271 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 5272 | if (!obj->base.filp) /* not backed by a freeable object */ |
| 5273 | continue; |
| 5274 | |
| 5275 | if (obj->pages_pin_count) |
| 5276 | pinned += obj->base.size; |
| 5277 | else |
| 5278 | unbound += obj->base.size; |
| 5279 | } |
| 5280 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 5281 | if (!obj->base.filp) |
| 5282 | continue; |
| 5283 | |
| 5284 | if (obj->pages_pin_count) |
| 5285 | pinned += obj->base.size; |
| 5286 | else |
| 5287 | bound += obj->base.size; |
| 5288 | } |
| 5289 | |
| 5290 | if (unlock) |
| 5291 | mutex_unlock(&dev->struct_mutex); |
| 5292 | |
| 5293 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", |
| 5294 | freed, pinned); |
| 5295 | if (unbound || bound) |
| 5296 | pr_err("%lu and %lu bytes still available in the " |
| 5297 | "bound and unbound GPU page lists.\n", |
| 5298 | bound, unbound); |
| 5299 | |
| 5300 | *(unsigned long *)ptr += freed; |
| 5301 | return NOTIFY_DONE; |
| 5302 | } |
| 5303 | |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5304 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
| 5305 | { |
| 5306 | struct i915_vma *vma; |
| 5307 | |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5308 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
Daniel Vetter | 5dc383b | 2014-08-06 15:04:49 +0200 | [diff] [blame] | 5309 | if (vma->vm != i915_obj_to_ggtt(obj)) |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5310 | return NULL; |
| 5311 | |
| 5312 | return vma; |
| 5313 | } |