Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 1 | #undef DEBUG |
| 2 | |
| 3 | /* |
| 4 | * ARM performance counter support. |
| 5 | * |
| 6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles |
Will Deacon | 43eab87 | 2010-11-13 19:04:32 +0000 | [diff] [blame] | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
Jean PIHET | 796d129 | 2010-01-26 18:51:05 +0100 | [diff] [blame] | 8 | * |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 9 | * This code is based on the sparc64 perf event code, which is in turn based |
Mark Rutland | d39976f | 2014-09-29 17:15:32 +0100 | [diff] [blame] | 10 | * on the x86 code. |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 11 | */ |
| 12 | #define pr_fmt(fmt) "hw perfevents: " fmt |
| 13 | |
Mark Rutland | cc88116 | 2015-05-13 17:12:25 +0100 | [diff] [blame] | 14 | #include <linux/cpumask.h> |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 15 | #include <linux/kernel.h> |
Will Deacon | 49c006b | 2010-04-29 17:13:24 +0100 | [diff] [blame] | 16 | #include <linux/platform_device.h> |
Stephen Boyd | bbd6455 | 2014-02-07 21:01:19 +0000 | [diff] [blame] | 17 | #include <linux/irq.h> |
| 18 | #include <linux/irqdesc.h> |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 19 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 20 | #include <asm/irq_regs.h> |
| 21 | #include <asm/pmu.h> |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 22 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 23 | static int |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 24 | armpmu_map_cache_event(const unsigned (*cache_map) |
| 25 | [PERF_COUNT_HW_CACHE_MAX] |
| 26 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 27 | [PERF_COUNT_HW_CACHE_RESULT_MAX], |
| 28 | u64 config) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 29 | { |
| 30 | unsigned int cache_type, cache_op, cache_result, ret; |
| 31 | |
| 32 | cache_type = (config >> 0) & 0xff; |
| 33 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 34 | return -EINVAL; |
| 35 | |
| 36 | cache_op = (config >> 8) & 0xff; |
| 37 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 38 | return -EINVAL; |
| 39 | |
| 40 | cache_result = (config >> 16) & 0xff; |
| 41 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 42 | return -EINVAL; |
| 43 | |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 44 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 45 | |
| 46 | if (ret == CACHE_OP_UNSUPPORTED) |
| 47 | return -ENOENT; |
| 48 | |
| 49 | return ret; |
| 50 | } |
| 51 | |
| 52 | static int |
Will Deacon | 6dbc002 | 2012-07-29 12:36:28 +0100 | [diff] [blame] | 53 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 54 | { |
Stephen Boyd | d9f9663 | 2013-08-08 18:41:59 +0100 | [diff] [blame] | 55 | int mapping; |
| 56 | |
| 57 | if (config >= PERF_COUNT_HW_MAX) |
| 58 | return -EINVAL; |
| 59 | |
| 60 | mapping = (*event_map)[config]; |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 61 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | static int |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 65 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 66 | { |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 67 | return (int)(config & raw_event_mask); |
| 68 | } |
| 69 | |
Will Deacon | 6dbc002 | 2012-07-29 12:36:28 +0100 | [diff] [blame] | 70 | int |
| 71 | armpmu_map_event(struct perf_event *event, |
| 72 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], |
| 73 | const unsigned (*cache_map) |
| 74 | [PERF_COUNT_HW_CACHE_MAX] |
| 75 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 76 | [PERF_COUNT_HW_CACHE_RESULT_MAX], |
| 77 | u32 raw_event_mask) |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 78 | { |
| 79 | u64 config = event->attr.config; |
Mark Rutland | 67b4305 | 2012-09-12 10:53:23 +0100 | [diff] [blame] | 80 | int type = event->attr.type; |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 81 | |
Mark Rutland | 67b4305 | 2012-09-12 10:53:23 +0100 | [diff] [blame] | 82 | if (type == event->pmu->type) |
| 83 | return armpmu_map_raw_event(raw_event_mask, config); |
| 84 | |
| 85 | switch (type) { |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 86 | case PERF_TYPE_HARDWARE: |
Will Deacon | 6dbc002 | 2012-07-29 12:36:28 +0100 | [diff] [blame] | 87 | return armpmu_map_hw_event(event_map, config); |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 88 | case PERF_TYPE_HW_CACHE: |
| 89 | return armpmu_map_cache_event(cache_map, config); |
| 90 | case PERF_TYPE_RAW: |
| 91 | return armpmu_map_raw_event(raw_event_mask, config); |
| 92 | } |
| 93 | |
| 94 | return -ENOENT; |
Will Deacon | 84fee97 | 2010-11-13 17:13:56 +0000 | [diff] [blame] | 95 | } |
| 96 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 97 | int armpmu_event_set_period(struct perf_event *event) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 98 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 99 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 100 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 101 | s64 left = local64_read(&hwc->period_left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 102 | s64 period = hwc->sample_period; |
| 103 | int ret = 0; |
| 104 | |
| 105 | if (unlikely(left <= -period)) { |
| 106 | left = period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 107 | local64_set(&hwc->period_left, left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 108 | hwc->last_period = period; |
| 109 | ret = 1; |
| 110 | } |
| 111 | |
| 112 | if (unlikely(left <= 0)) { |
| 113 | left += period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 114 | local64_set(&hwc->period_left, left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 115 | hwc->last_period = period; |
| 116 | ret = 1; |
| 117 | } |
| 118 | |
Daniel Thompson | 2d9ed74 | 2015-01-05 15:58:54 +0100 | [diff] [blame] | 119 | /* |
| 120 | * Limit the maximum period to prevent the counter value |
| 121 | * from overtaking the one we are about to program. In |
| 122 | * effect we are reducing max_period to account for |
| 123 | * interrupt latency (and we are being very conservative). |
| 124 | */ |
| 125 | if (left > (armpmu->max_period >> 1)) |
| 126 | left = armpmu->max_period >> 1; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 127 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 128 | local64_set(&hwc->prev_count, (u64)-left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 129 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 130 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 131 | |
| 132 | perf_event_update_userpage(event); |
| 133 | |
| 134 | return ret; |
| 135 | } |
| 136 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 137 | u64 armpmu_event_update(struct perf_event *event) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 138 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 139 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 140 | struct hw_perf_event *hwc = &event->hw; |
Will Deacon | a737823 | 2011-03-25 17:12:37 +0100 | [diff] [blame] | 141 | u64 delta, prev_raw_count, new_raw_count; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 142 | |
| 143 | again: |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 144 | prev_raw_count = local64_read(&hwc->prev_count); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 145 | new_raw_count = armpmu->read_counter(event); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 146 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 147 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 148 | new_raw_count) != prev_raw_count) |
| 149 | goto again; |
| 150 | |
Will Deacon | 5727347 | 2012-03-06 17:33:17 +0100 | [diff] [blame] | 151 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 152 | |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 153 | local64_add(delta, &event->count); |
| 154 | local64_sub(delta, &hwc->period_left); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 155 | |
| 156 | return new_raw_count; |
| 157 | } |
| 158 | |
| 159 | static void |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 160 | armpmu_read(struct perf_event *event) |
| 161 | { |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 162 | armpmu_event_update(event); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | static void |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 166 | armpmu_stop(struct perf_event *event, int flags) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 167 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 168 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 169 | struct hw_perf_event *hwc = &event->hw; |
| 170 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 171 | /* |
| 172 | * ARM pmu always has to update the counter, so ignore |
| 173 | * PERF_EF_UPDATE, see comments in armpmu_start(). |
| 174 | */ |
| 175 | if (!(hwc->state & PERF_HES_STOPPED)) { |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 176 | armpmu->disable(event); |
| 177 | armpmu_event_update(event); |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 178 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 179 | } |
| 180 | } |
| 181 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 182 | static void armpmu_start(struct perf_event *event, int flags) |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 183 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 184 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 185 | struct hw_perf_event *hwc = &event->hw; |
| 186 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 187 | /* |
| 188 | * ARM pmu always has to reprogram the period, so ignore |
| 189 | * PERF_EF_RELOAD, see the comment below. |
| 190 | */ |
| 191 | if (flags & PERF_EF_RELOAD) |
| 192 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); |
| 193 | |
| 194 | hwc->state = 0; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 195 | /* |
| 196 | * Set the period again. Some counters can't be stopped, so when we |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 197 | * were stopped we simply disabled the IRQ source and the counter |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 198 | * may have been left counting. If we don't do this step then we may |
| 199 | * get an interrupt too soon or *way* too late if the overflow has |
| 200 | * happened since disabling. |
| 201 | */ |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 202 | armpmu_event_set_period(event); |
| 203 | armpmu->enable(event); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 204 | } |
| 205 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 206 | static void |
| 207 | armpmu_del(struct perf_event *event, int flags) |
| 208 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 209 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 210 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 211 | struct hw_perf_event *hwc = &event->hw; |
| 212 | int idx = hwc->idx; |
| 213 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 214 | armpmu_stop(event, PERF_EF_UPDATE); |
Mark Rutland | 8be3f9a | 2011-05-17 11:20:11 +0100 | [diff] [blame] | 215 | hw_events->events[idx] = NULL; |
| 216 | clear_bit(idx, hw_events->used_mask); |
Stephen Boyd | eab443e | 2014-02-07 21:01:22 +0000 | [diff] [blame] | 217 | if (armpmu->clear_event_idx) |
| 218 | armpmu->clear_event_idx(hw_events, event); |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 219 | |
| 220 | perf_event_update_userpage(event); |
| 221 | } |
| 222 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 223 | static int |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 224 | armpmu_add(struct perf_event *event, int flags) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 225 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 226 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 227 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 228 | struct hw_perf_event *hwc = &event->hw; |
| 229 | int idx; |
| 230 | int err = 0; |
| 231 | |
Mark Rutland | cc88116 | 2015-05-13 17:12:25 +0100 | [diff] [blame] | 232 | /* An event following a process won't be stopped earlier */ |
| 233 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) |
| 234 | return -ENOENT; |
| 235 | |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 236 | perf_pmu_disable(event->pmu); |
Peter Zijlstra | 24cd7f5 | 2010-06-11 17:32:03 +0200 | [diff] [blame] | 237 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 238 | /* If we don't have a space for the counter then finish early. */ |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 239 | idx = armpmu->get_event_idx(hw_events, event); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 240 | if (idx < 0) { |
| 241 | err = idx; |
| 242 | goto out; |
| 243 | } |
| 244 | |
| 245 | /* |
| 246 | * If there is an event in the counter we are going to use then make |
| 247 | * sure it is disabled. |
| 248 | */ |
| 249 | event->hw.idx = idx; |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 250 | armpmu->disable(event); |
Mark Rutland | 8be3f9a | 2011-05-17 11:20:11 +0100 | [diff] [blame] | 251 | hw_events->events[idx] = event; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 252 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 253 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 254 | if (flags & PERF_EF_START) |
| 255 | armpmu_start(event, PERF_EF_RELOAD); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 256 | |
| 257 | /* Propagate our changes to the userspace mapping. */ |
| 258 | perf_event_update_userpage(event); |
| 259 | |
| 260 | out: |
Peter Zijlstra | 33696fc | 2010-06-14 08:49:00 +0200 | [diff] [blame] | 261 | perf_pmu_enable(event->pmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 262 | return err; |
| 263 | } |
| 264 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 265 | static int |
Suzuki K. Poulose | e429817 | 2015-03-17 18:14:58 +0000 | [diff] [blame] | 266 | validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events, |
| 267 | struct perf_event *event) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 268 | { |
Suzuki K. Poulose | e429817 | 2015-03-17 18:14:58 +0000 | [diff] [blame] | 269 | struct arm_pmu *armpmu; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 270 | |
Will Deacon | c95eb31 | 2013-08-07 23:39:41 +0100 | [diff] [blame] | 271 | if (is_software_event(event)) |
| 272 | return 1; |
| 273 | |
Suzuki K. Poulose | e429817 | 2015-03-17 18:14:58 +0000 | [diff] [blame] | 274 | /* |
| 275 | * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The |
| 276 | * core perf code won't check that the pmu->ctx == leader->ctx |
| 277 | * until after pmu->event_init(event). |
| 278 | */ |
| 279 | if (event->pmu != pmu) |
| 280 | return 0; |
| 281 | |
Will Deacon | 2dfcb80 | 2013-10-09 13:51:29 +0100 | [diff] [blame] | 282 | if (event->state < PERF_EVENT_STATE_OFF) |
Will Deacon | cb2d8b3 | 2013-04-12 19:04:19 +0100 | [diff] [blame] | 283 | return 1; |
| 284 | |
| 285 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) |
Will Deacon | 65b4711 | 2010-09-02 09:32:08 +0100 | [diff] [blame] | 286 | return 1; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 287 | |
Suzuki K. Poulose | e429817 | 2015-03-17 18:14:58 +0000 | [diff] [blame] | 288 | armpmu = to_arm_pmu(event->pmu); |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 289 | return armpmu->get_event_idx(hw_events, event) >= 0; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | static int |
| 293 | validate_group(struct perf_event *event) |
| 294 | { |
| 295 | struct perf_event *sibling, *leader = event->group_leader; |
Mark Rutland | 8be3f9a | 2011-05-17 11:20:11 +0100 | [diff] [blame] | 296 | struct pmu_hw_events fake_pmu; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 297 | |
Will Deacon | bce34d1 | 2011-11-17 15:05:14 +0000 | [diff] [blame] | 298 | /* |
| 299 | * Initialise the fake PMU. We only need to populate the |
| 300 | * used_mask for the purposes of validation. |
| 301 | */ |
Mark Rutland | a456084 | 2014-05-13 19:08:19 +0100 | [diff] [blame] | 302 | memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask)); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 303 | |
Suzuki K. Poulose | e429817 | 2015-03-17 18:14:58 +0000 | [diff] [blame] | 304 | if (!validate_event(event->pmu, &fake_pmu, leader)) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 305 | return -EINVAL; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 306 | |
| 307 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { |
Suzuki K. Poulose | e429817 | 2015-03-17 18:14:58 +0000 | [diff] [blame] | 308 | if (!validate_event(event->pmu, &fake_pmu, sibling)) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 309 | return -EINVAL; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 310 | } |
| 311 | |
Suzuki K. Poulose | e429817 | 2015-03-17 18:14:58 +0000 | [diff] [blame] | 312 | if (!validate_event(event->pmu, &fake_pmu, event)) |
Peter Zijlstra | aa2bc1a | 2011-11-09 17:56:37 +0100 | [diff] [blame] | 313 | return -EINVAL; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 314 | |
| 315 | return 0; |
| 316 | } |
| 317 | |
Sudeep KarkadaNagesha | 051f1b1 | 2012-07-31 10:34:25 +0100 | [diff] [blame] | 318 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame] | 319 | { |
Stephen Boyd | bbd6455 | 2014-02-07 21:01:19 +0000 | [diff] [blame] | 320 | struct arm_pmu *armpmu; |
| 321 | struct platform_device *plat_device; |
| 322 | struct arm_pmu_platdata *plat; |
Will Deacon | 5f5092e | 2014-02-11 18:08:41 +0000 | [diff] [blame] | 323 | int ret; |
| 324 | u64 start_clock, finish_clock; |
Stephen Boyd | bbd6455 | 2014-02-07 21:01:19 +0000 | [diff] [blame] | 325 | |
Mark Rutland | 5ebd920 | 2014-05-13 19:46:10 +0100 | [diff] [blame] | 326 | /* |
| 327 | * we request the IRQ with a (possibly percpu) struct arm_pmu**, but |
| 328 | * the handlers expect a struct arm_pmu*. The percpu_irq framework will |
| 329 | * do any necessary shifting, we just need to perform the first |
| 330 | * dereference. |
| 331 | */ |
| 332 | armpmu = *(void **)dev; |
Stephen Boyd | bbd6455 | 2014-02-07 21:01:19 +0000 | [diff] [blame] | 333 | plat_device = armpmu->plat_device; |
| 334 | plat = dev_get_platdata(&plat_device->dev); |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame] | 335 | |
Will Deacon | 5f5092e | 2014-02-11 18:08:41 +0000 | [diff] [blame] | 336 | start_clock = sched_clock(); |
Sudeep KarkadaNagesha | 051f1b1 | 2012-07-31 10:34:25 +0100 | [diff] [blame] | 337 | if (plat && plat->handle_irq) |
Mark Rutland | 5ebd920 | 2014-05-13 19:46:10 +0100 | [diff] [blame] | 338 | ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq); |
Sudeep KarkadaNagesha | 051f1b1 | 2012-07-31 10:34:25 +0100 | [diff] [blame] | 339 | else |
Mark Rutland | 5ebd920 | 2014-05-13 19:46:10 +0100 | [diff] [blame] | 340 | ret = armpmu->handle_irq(irq, armpmu); |
Will Deacon | 5f5092e | 2014-02-11 18:08:41 +0000 | [diff] [blame] | 341 | finish_clock = sched_clock(); |
| 342 | |
| 343 | perf_sample_event_took(finish_clock - start_clock); |
| 344 | return ret; |
Rabin Vincent | 0e25a5c | 2011-02-08 09:24:36 +0530 | [diff] [blame] | 345 | } |
| 346 | |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 347 | static void |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 348 | armpmu_release_hardware(struct arm_pmu *armpmu) |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 349 | { |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 350 | armpmu->free_irq(armpmu); |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 351 | } |
| 352 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 353 | static int |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 354 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 355 | { |
Mark Rutland | ed61f98 | 2015-05-26 17:23:34 +0100 | [diff] [blame^] | 356 | int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq); |
Sudeep KarkadaNagesha | 051f1b1 | 2012-07-31 10:34:25 +0100 | [diff] [blame] | 357 | if (err) { |
| 358 | armpmu_release_hardware(armpmu); |
| 359 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 360 | } |
| 361 | |
Will Deacon | 0b390e2 | 2011-07-27 15:18:59 +0100 | [diff] [blame] | 362 | return 0; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 363 | } |
| 364 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 365 | static void |
| 366 | hw_perf_event_destroy(struct perf_event *event) |
| 367 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 368 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame] | 369 | atomic_t *active_events = &armpmu->active_events; |
| 370 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; |
| 371 | |
| 372 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 373 | armpmu_release_hardware(armpmu); |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame] | 374 | mutex_unlock(pmu_reserve_mutex); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 375 | } |
| 376 | } |
| 377 | |
| 378 | static int |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 379 | event_requires_mode_exclusion(struct perf_event_attr *attr) |
| 380 | { |
| 381 | return attr->exclude_idle || attr->exclude_user || |
| 382 | attr->exclude_kernel || attr->exclude_hv; |
| 383 | } |
| 384 | |
| 385 | static int |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 386 | __hw_perf_event_init(struct perf_event *event) |
| 387 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 388 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 389 | struct hw_perf_event *hwc = &event->hw; |
Mark Rutland | 9dcbf46 | 2013-01-18 16:10:06 +0000 | [diff] [blame] | 390 | int mapping; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 391 | |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 392 | mapping = armpmu->map_event(event); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 393 | |
| 394 | if (mapping < 0) { |
| 395 | pr_debug("event %x:%llx not supported\n", event->attr.type, |
| 396 | event->attr.config); |
| 397 | return mapping; |
| 398 | } |
| 399 | |
| 400 | /* |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 401 | * We don't assign an index until we actually place the event onto |
| 402 | * hardware. Use -1 to signify that we haven't decided where to put it |
| 403 | * yet. For SMP systems, each core has it's own PMU so we can't do any |
| 404 | * clever allocation or constraints checking at this point. |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 405 | */ |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 406 | hwc->idx = -1; |
| 407 | hwc->config_base = 0; |
| 408 | hwc->config = 0; |
| 409 | hwc->event_base = 0; |
| 410 | |
| 411 | /* |
| 412 | * Check whether we need to exclude the counter from certain modes. |
| 413 | */ |
| 414 | if ((!armpmu->set_event_filter || |
| 415 | armpmu->set_event_filter(hwc, &event->attr)) && |
| 416 | event_requires_mode_exclusion(&event->attr)) { |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 417 | pr_debug("ARM performance counters do not support " |
| 418 | "mode exclusion\n"); |
Will Deacon | fdeb8e3 | 2012-07-04 18:15:42 +0100 | [diff] [blame] | 419 | return -EOPNOTSUPP; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | /* |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 423 | * Store the event encoding into the config_base field. |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 424 | */ |
Will Deacon | 05d22fd | 2011-07-19 11:57:30 +0100 | [diff] [blame] | 425 | hwc->config_base |= (unsigned long)mapping; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 426 | |
Vince Weaver | edcb4d3 | 2014-05-16 17:15:49 -0400 | [diff] [blame] | 427 | if (!is_sampling_event(event)) { |
Will Deacon | 5727347 | 2012-03-06 17:33:17 +0100 | [diff] [blame] | 428 | /* |
| 429 | * For non-sampling runs, limit the sample_period to half |
| 430 | * of the counter width. That way, the new counter value |
| 431 | * is far less likely to overtake the previous one unless |
| 432 | * you have some serious IRQ latency issues. |
| 433 | */ |
| 434 | hwc->sample_period = armpmu->max_period >> 1; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 435 | hwc->last_period = hwc->sample_period; |
Peter Zijlstra | e785059 | 2010-05-21 14:43:08 +0200 | [diff] [blame] | 436 | local64_set(&hwc->period_left, hwc->sample_period); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 437 | } |
| 438 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 439 | if (event->group_leader != event) { |
Chen Gang | e595ede | 2013-02-28 17:51:29 +0100 | [diff] [blame] | 440 | if (validate_group(event) != 0) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 441 | return -EINVAL; |
| 442 | } |
| 443 | |
Mark Rutland | 9dcbf46 | 2013-01-18 16:10:06 +0000 | [diff] [blame] | 444 | return 0; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 445 | } |
| 446 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 447 | static int armpmu_event_init(struct perf_event *event) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 448 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 449 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 450 | int err = 0; |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame] | 451 | atomic_t *active_events = &armpmu->active_events; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 452 | |
Mark Rutland | cc88116 | 2015-05-13 17:12:25 +0100 | [diff] [blame] | 453 | /* |
| 454 | * Reject CPU-affine events for CPUs that are of a different class to |
| 455 | * that which this PMU handles. Process-following events (where |
| 456 | * event->cpu == -1) can be migrated between CPUs, and thus we have to |
| 457 | * reject them later (in armpmu_add) if they're scheduled on a |
| 458 | * different class of CPU. |
| 459 | */ |
| 460 | if (event->cpu != -1 && |
| 461 | !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus)) |
| 462 | return -ENOENT; |
| 463 | |
Stephane Eranian | 2481c5f | 2012-02-09 23:20:59 +0100 | [diff] [blame] | 464 | /* does not support taken branch sampling */ |
| 465 | if (has_branch_stack(event)) |
| 466 | return -EOPNOTSUPP; |
| 467 | |
Mark Rutland | e1f431b | 2011-04-28 15:47:10 +0100 | [diff] [blame] | 468 | if (armpmu->map_event(event) == -ENOENT) |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 469 | return -ENOENT; |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 470 | |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 471 | event->destroy = hw_perf_event_destroy; |
| 472 | |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame] | 473 | if (!atomic_inc_not_zero(active_events)) { |
| 474 | mutex_lock(&armpmu->reserve_mutex); |
| 475 | if (atomic_read(active_events) == 0) |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 476 | err = armpmu_reserve_hardware(armpmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 477 | |
| 478 | if (!err) |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame] | 479 | atomic_inc(active_events); |
| 480 | mutex_unlock(&armpmu->reserve_mutex); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 481 | } |
| 482 | |
| 483 | if (err) |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 484 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 485 | |
| 486 | err = __hw_perf_event_init(event); |
| 487 | if (err) |
| 488 | hw_perf_event_destroy(event); |
| 489 | |
Peter Zijlstra | b0a873e | 2010-06-11 13:35:08 +0200 | [diff] [blame] | 490 | return err; |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 491 | } |
| 492 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 493 | static void armpmu_enable(struct pmu *pmu) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 494 | { |
Mark Rutland | 8be3f9a | 2011-05-17 11:20:11 +0100 | [diff] [blame] | 495 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
Mark Rutland | 1167925 | 2014-05-13 19:36:31 +0100 | [diff] [blame] | 496 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
Mark Rutland | 7325eae | 2011-08-23 11:59:49 +0100 | [diff] [blame] | 497 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 498 | |
Mark Rutland | cc88116 | 2015-05-13 17:12:25 +0100 | [diff] [blame] | 499 | /* For task-bound events we may be called on other CPUs */ |
| 500 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) |
| 501 | return; |
| 502 | |
Will Deacon | f4f3843 | 2011-07-01 14:38:12 +0100 | [diff] [blame] | 503 | if (enabled) |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 504 | armpmu->start(armpmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 505 | } |
| 506 | |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 507 | static void armpmu_disable(struct pmu *pmu) |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 508 | { |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 509 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
Mark Rutland | cc88116 | 2015-05-13 17:12:25 +0100 | [diff] [blame] | 510 | |
| 511 | /* For task-bound events we may be called on other CPUs */ |
| 512 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) |
| 513 | return; |
| 514 | |
Sudeep KarkadaNagesha | ed6f2a5 | 2012-07-30 12:00:02 +0100 | [diff] [blame] | 515 | armpmu->stop(armpmu); |
Jamie Iles | 1b8873a | 2010-02-02 20:25:44 +0100 | [diff] [blame] | 516 | } |
| 517 | |
Mark Rutland | c904e32 | 2015-05-13 17:12:26 +0100 | [diff] [blame] | 518 | /* |
| 519 | * In heterogeneous systems, events are specific to a particular |
| 520 | * microarchitecture, and aren't suitable for another. Thus, only match CPUs of |
| 521 | * the same microarchitecture. |
| 522 | */ |
| 523 | static int armpmu_filter_match(struct perf_event *event) |
| 524 | { |
| 525 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
| 526 | unsigned int cpu = smp_processor_id(); |
| 527 | return cpumask_test_cpu(cpu, &armpmu->supported_cpus); |
| 528 | } |
| 529 | |
Stephen Boyd | 44d6b1f | 2013-03-05 03:54:06 +0100 | [diff] [blame] | 530 | static void armpmu_init(struct arm_pmu *armpmu) |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame] | 531 | { |
| 532 | atomic_set(&armpmu->active_events, 0); |
| 533 | mutex_init(&armpmu->reserve_mutex); |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 534 | |
| 535 | armpmu->pmu = (struct pmu) { |
| 536 | .pmu_enable = armpmu_enable, |
| 537 | .pmu_disable = armpmu_disable, |
| 538 | .event_init = armpmu_event_init, |
| 539 | .add = armpmu_add, |
| 540 | .del = armpmu_del, |
| 541 | .start = armpmu_start, |
| 542 | .stop = armpmu_stop, |
| 543 | .read = armpmu_read, |
Mark Rutland | c904e32 | 2015-05-13 17:12:26 +0100 | [diff] [blame] | 544 | .filter_match = armpmu_filter_match, |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 545 | }; |
| 546 | } |
| 547 | |
Will Deacon | 0305230 | 2012-09-21 14:23:47 +0100 | [diff] [blame] | 548 | int armpmu_register(struct arm_pmu *armpmu, int type) |
Mark Rutland | 8a16b34 | 2011-04-28 16:27:54 +0100 | [diff] [blame] | 549 | { |
| 550 | armpmu_init(armpmu); |
Will Deacon | 04236f9 | 2012-07-28 17:42:22 +0100 | [diff] [blame] | 551 | pr_info("enabled with %s PMU driver, %d counters available\n", |
| 552 | armpmu->name, armpmu->num_events); |
Will Deacon | 0305230 | 2012-09-21 14:23:47 +0100 | [diff] [blame] | 553 | return perf_pmu_register(&armpmu->pmu, armpmu->name, type); |
Mark Rutland | 03b7898 | 2011-04-27 11:20:11 +0100 | [diff] [blame] | 554 | } |
| 555 | |