Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ahci.c - AHCI SATA support |
| 3 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2004-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
domen@coderock.org | 87507cf | 2005-04-08 09:53:06 +0200 | [diff] [blame] | 42 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 43 | #include <linux/device.h> |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame^] | 44 | #include <linux/dmi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 46 | #include <scsi/scsi_cmnd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | #include <linux/libata.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
| 49 | #define DRV_NAME "ahci" |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 50 | #define DRV_VERSION "3.0" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
| 52 | |
| 53 | enum { |
| 54 | AHCI_PCI_BAR = 5, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 55 | AHCI_MAX_PORTS = 32, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 57 | AHCI_DMA_BOUNDARY = 0xffffffff, |
Jens Axboe | be5d821 | 2007-05-22 09:45:39 +0200 | [diff] [blame] | 58 | AHCI_USE_CLUSTERING = 1, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 59 | AHCI_MAX_CMDS = 32, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 60 | AHCI_CMD_SZ = 32, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 61 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | AHCI_RX_FIS_SZ = 256, |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 63 | AHCI_CMD_TBL_CDB = 0x40, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 64 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
| 65 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
| 66 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
| 67 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | AHCI_RX_FIS_SZ, |
| 69 | AHCI_IRQ_ON_SG = (1 << 31), |
| 70 | AHCI_CMD_ATAPI = (1 << 5), |
| 71 | AHCI_CMD_WRITE = (1 << 6), |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 72 | AHCI_CMD_PREFETCH = (1 << 7), |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 73 | AHCI_CMD_RESET = (1 << 8), |
| 74 | AHCI_CMD_CLR_BUSY = (1 << 10), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | |
| 76 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 77 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 78 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | |
| 80 | board_ahci = 0, |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 81 | board_ahci_vt8251 = 1, |
| 82 | board_ahci_ign_iferr = 2, |
| 83 | board_ahci_sb600 = 3, |
| 84 | board_ahci_mv = 4, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | |
| 86 | /* global controller registers */ |
| 87 | HOST_CAP = 0x00, /* host capabilities */ |
| 88 | HOST_CTL = 0x04, /* global host control */ |
| 89 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 90 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 91 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
| 92 | |
| 93 | /* HOST_CTL bits */ |
| 94 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 95 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
| 96 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 97 | |
| 98 | /* HOST_CAP bits */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 99 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 100 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 101 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 102 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 103 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
Tejun Heo | 979db80 | 2006-05-15 21:03:52 +0900 | [diff] [blame] | 104 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 105 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | |
| 107 | /* registers for each SATA port */ |
| 108 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 109 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 110 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 111 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 112 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 113 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 114 | PORT_CMD = 0x18, /* port command */ |
| 115 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 116 | PORT_SIG = 0x24, /* device TF signature */ |
| 117 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 119 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 120 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 121 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 122 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | |
| 124 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 125 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 126 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 127 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 128 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 129 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 130 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 131 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 132 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 133 | |
| 134 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 135 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 136 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 137 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 138 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 139 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 140 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 141 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 142 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 143 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 144 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
| 145 | PORT_IRQ_IF_ERR | |
| 146 | PORT_IRQ_CONNECT | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 147 | PORT_IRQ_PHYRDY | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 148 | PORT_IRQ_UNK_FIS | |
| 149 | PORT_IRQ_BAD_PMP, |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 150 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
| 151 | PORT_IRQ_TF_ERR | |
| 152 | PORT_IRQ_HBUS_DATA_ERR, |
| 153 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
| 154 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
| 155 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | |
| 157 | /* PORT_CMD bits */ |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 158 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 159 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 161 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 162 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 163 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 165 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 166 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 167 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 168 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 170 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 171 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 172 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 173 | /* hpriv->flags bits */ |
| 174 | AHCI_HFLAG_NO_NCQ = (1 << 0), |
| 175 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ |
| 176 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ |
| 177 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ |
| 178 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ |
| 179 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 180 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 181 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 182 | /* ap->flags bits */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 183 | AHCI_FLAG_NO_HOTPLUG = (1 << 24), /* ignore PxSERR.DIAG.N */ |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 184 | |
| 185 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 186 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
Tejun Heo | 854c73a | 2007-09-23 13:14:11 +0900 | [diff] [blame] | 187 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 188 | AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | }; |
| 190 | |
| 191 | struct ahci_cmd_hdr { |
| 192 | u32 opts; |
| 193 | u32 status; |
| 194 | u32 tbl_addr; |
| 195 | u32 tbl_addr_hi; |
| 196 | u32 reserved[4]; |
| 197 | }; |
| 198 | |
| 199 | struct ahci_sg { |
| 200 | u32 addr; |
| 201 | u32 addr_hi; |
| 202 | u32 reserved; |
| 203 | u32 flags_size; |
| 204 | }; |
| 205 | |
| 206 | struct ahci_host_priv { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 207 | unsigned int flags; /* AHCI_HFLAG_* */ |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 208 | u32 cap; /* cap to use */ |
| 209 | u32 port_map; /* port map to use */ |
| 210 | u32 saved_cap; /* saved initial cap */ |
| 211 | u32 saved_port_map; /* saved initial port_map */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | struct ahci_port_priv { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 215 | struct ata_link *active_link; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | struct ahci_cmd_hdr *cmd_slot; |
| 217 | dma_addr_t cmd_slot_dma; |
| 218 | void *cmd_tbl; |
| 219 | dma_addr_t cmd_tbl_dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | void *rx_fis; |
| 221 | dma_addr_t rx_fis_dma; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 222 | /* for NCQ spurious interrupt analysis */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 223 | unsigned int ncq_saw_d2h:1; |
| 224 | unsigned int ncq_saw_dmas:1; |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 225 | unsigned int ncq_saw_sdb:1; |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 226 | u32 intr_mask; /* interrupts to enable */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 229 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
| 230 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 231 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 232 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | static void ahci_irq_clear(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | static int ahci_port_start(struct ata_port *ap); |
| 235 | static void ahci_port_stop(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
| 237 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
| 238 | static u8 ahci_check_status(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 239 | static void ahci_freeze(struct ata_port *ap); |
| 240 | static void ahci_thaw(struct ata_port *ap); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 241 | static void ahci_pmp_attach(struct ata_port *ap); |
| 242 | static void ahci_pmp_detach(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 243 | static void ahci_error_handler(struct ata_port *ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 244 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame^] | 245 | static void ahci_p5wdh_error_handler(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 246 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 247 | static int ahci_port_resume(struct ata_port *ap); |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 248 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
| 249 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 250 | u32 opts); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 251 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 252 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 253 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
| 254 | static int ahci_pci_device_resume(struct pci_dev *pdev); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 255 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 257 | static struct scsi_host_template ahci_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | .module = THIS_MODULE, |
| 259 | .name = DRV_NAME, |
| 260 | .ioctl = ata_scsi_ioctl, |
| 261 | .queuecommand = ata_scsi_queuecmd, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 262 | .change_queue_depth = ata_scsi_change_queue_depth, |
| 263 | .can_queue = AHCI_MAX_CMDS - 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | .this_id = ATA_SHT_THIS_ID, |
| 265 | .sg_tablesize = AHCI_MAX_SG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 267 | .emulated = ATA_SHT_EMULATED, |
| 268 | .use_clustering = AHCI_USE_CLUSTERING, |
| 269 | .proc_name = DRV_NAME, |
| 270 | .dma_boundary = AHCI_DMA_BOUNDARY, |
| 271 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 272 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 273 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | }; |
| 275 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 276 | static const struct ata_port_operations ahci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | .check_status = ahci_check_status, |
| 278 | .check_altstatus = ahci_check_status, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | .dev_select = ata_noop_dev_select, |
| 280 | |
| 281 | .tf_read = ahci_tf_read, |
| 282 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 283 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 284 | .qc_prep = ahci_qc_prep, |
| 285 | .qc_issue = ahci_qc_issue, |
| 286 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | .irq_clear = ahci_irq_clear, |
| 288 | |
| 289 | .scr_read = ahci_scr_read, |
| 290 | .scr_write = ahci_scr_write, |
| 291 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 292 | .freeze = ahci_freeze, |
| 293 | .thaw = ahci_thaw, |
| 294 | |
| 295 | .error_handler = ahci_error_handler, |
| 296 | .post_internal_cmd = ahci_post_internal_cmd, |
| 297 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 298 | .pmp_attach = ahci_pmp_attach, |
| 299 | .pmp_detach = ahci_pmp_detach, |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 300 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 301 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 302 | .port_suspend = ahci_port_suspend, |
| 303 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 304 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 305 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | .port_start = ahci_port_start, |
| 307 | .port_stop = ahci_port_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | }; |
| 309 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 310 | static const struct ata_port_operations ahci_vt8251_ops = { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 311 | .check_status = ahci_check_status, |
| 312 | .check_altstatus = ahci_check_status, |
| 313 | .dev_select = ata_noop_dev_select, |
| 314 | |
| 315 | .tf_read = ahci_tf_read, |
| 316 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 317 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 318 | .qc_prep = ahci_qc_prep, |
| 319 | .qc_issue = ahci_qc_issue, |
| 320 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 321 | .irq_clear = ahci_irq_clear, |
| 322 | |
| 323 | .scr_read = ahci_scr_read, |
| 324 | .scr_write = ahci_scr_write, |
| 325 | |
| 326 | .freeze = ahci_freeze, |
| 327 | .thaw = ahci_thaw, |
| 328 | |
| 329 | .error_handler = ahci_vt8251_error_handler, |
| 330 | .post_internal_cmd = ahci_post_internal_cmd, |
| 331 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 332 | .pmp_attach = ahci_pmp_attach, |
| 333 | .pmp_detach = ahci_pmp_detach, |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 334 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 335 | #ifdef CONFIG_PM |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 336 | .port_suspend = ahci_port_suspend, |
| 337 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 338 | #endif |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 339 | |
| 340 | .port_start = ahci_port_start, |
| 341 | .port_stop = ahci_port_stop, |
| 342 | }; |
| 343 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame^] | 344 | static const struct ata_port_operations ahci_p5wdh_ops = { |
| 345 | .check_status = ahci_check_status, |
| 346 | .check_altstatus = ahci_check_status, |
| 347 | .dev_select = ata_noop_dev_select, |
| 348 | |
| 349 | .tf_read = ahci_tf_read, |
| 350 | |
| 351 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
| 352 | .qc_prep = ahci_qc_prep, |
| 353 | .qc_issue = ahci_qc_issue, |
| 354 | |
| 355 | .irq_clear = ahci_irq_clear, |
| 356 | |
| 357 | .scr_read = ahci_scr_read, |
| 358 | .scr_write = ahci_scr_write, |
| 359 | |
| 360 | .freeze = ahci_freeze, |
| 361 | .thaw = ahci_thaw, |
| 362 | |
| 363 | .error_handler = ahci_p5wdh_error_handler, |
| 364 | .post_internal_cmd = ahci_post_internal_cmd, |
| 365 | |
| 366 | .pmp_attach = ahci_pmp_attach, |
| 367 | .pmp_detach = ahci_pmp_detach, |
| 368 | |
| 369 | #ifdef CONFIG_PM |
| 370 | .port_suspend = ahci_port_suspend, |
| 371 | .port_resume = ahci_port_resume, |
| 372 | #endif |
| 373 | |
| 374 | .port_start = ahci_port_start, |
| 375 | .port_stop = ahci_port_stop, |
| 376 | }; |
| 377 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 378 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
| 379 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 380 | static const struct ata_port_info ahci_port_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | /* board_ahci */ |
| 382 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 383 | .flags = AHCI_FLAG_COMMON, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 384 | .link_flags = AHCI_LFLAG_COMMON, |
Brett Russ | 7da7931 | 2005-09-01 21:53:34 -0400 | [diff] [blame] | 385 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 386 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 387 | .port_ops = &ahci_ops, |
| 388 | }, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 389 | /* board_ahci_vt8251 */ |
| 390 | { |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 391 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 392 | .flags = AHCI_FLAG_COMMON, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 393 | .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 394 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 395 | .udma_mask = ATA_UDMA6, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 396 | .port_ops = &ahci_vt8251_ops, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 397 | }, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 398 | /* board_ahci_ign_iferr */ |
| 399 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 400 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
| 401 | .flags = AHCI_FLAG_COMMON, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 402 | .link_flags = AHCI_LFLAG_COMMON, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 403 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 404 | .udma_mask = ATA_UDMA6, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 405 | .port_ops = &ahci_ops, |
| 406 | }, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 407 | /* board_ahci_sb600 */ |
| 408 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 409 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 410 | AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP), |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 411 | .flags = AHCI_FLAG_COMMON, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 412 | .link_flags = AHCI_LFLAG_COMMON, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 413 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 414 | .udma_mask = ATA_UDMA6, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 415 | .port_ops = &ahci_ops, |
| 416 | }, |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 417 | /* board_ahci_mv */ |
| 418 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 419 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
| 420 | AHCI_HFLAG_MV_PATA), |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 421 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 422 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 423 | .link_flags = AHCI_LFLAG_COMMON, |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 424 | .pio_mask = 0x1f, /* pio0-4 */ |
| 425 | .udma_mask = ATA_UDMA6, |
| 426 | .port_ops = &ahci_ops, |
| 427 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 428 | }; |
| 429 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 430 | static const struct pci_device_id ahci_pci_tbl[] = { |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 431 | /* Intel */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 432 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
| 433 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ |
| 434 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ |
| 435 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ |
| 436 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ |
Tejun Heo | 82490c0 | 2007-01-23 15:13:39 +0900 | [diff] [blame] | 437 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 438 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
| 439 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ |
| 440 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ |
| 441 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 442 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
| 443 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ |
| 444 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
| 445 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ |
| 446 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ |
| 447 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ |
| 448 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ |
| 449 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ |
| 450 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ |
| 451 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ |
| 452 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ |
| 453 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ |
| 454 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ |
| 455 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ |
| 456 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ |
| 457 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ |
| 458 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ |
Jason Gaston | d4155e6 | 2007-09-20 17:35:00 -0400 | [diff] [blame] | 459 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
| 460 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 461 | |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 462 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
| 463 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 464 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 465 | |
| 466 | /* ATI */ |
Conke Hu | c65ec1c | 2007-04-11 18:23:14 +0800 | [diff] [blame] | 467 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
henry su | c69c089 | 2007-09-20 16:07:33 -0400 | [diff] [blame] | 468 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */ |
| 469 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */ |
| 470 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */ |
| 471 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */ |
| 472 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */ |
| 473 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 474 | |
| 475 | /* VIA */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 476 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
Tejun Heo | bf33554 | 2007-04-11 17:27:14 +0900 | [diff] [blame] | 477 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 478 | |
| 479 | /* NVIDIA */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 480 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
| 481 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ |
| 482 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ |
| 483 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ |
Peer Chen | 6fbf5ba | 2006-12-20 14:18:00 -0500 | [diff] [blame] | 484 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
| 485 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ |
| 486 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ |
| 487 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ |
| 488 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ |
| 489 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ |
| 490 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ |
| 491 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ |
Peer Chen | 895663c | 2006-11-02 17:59:46 -0500 | [diff] [blame] | 492 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
| 493 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ |
| 494 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ |
| 495 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ |
| 496 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ |
| 497 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ |
| 498 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ |
| 499 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ |
Peer Chen | 0522b28 | 2007-06-07 18:05:12 +0800 | [diff] [blame] | 500 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
| 501 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ |
| 502 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ |
| 503 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ |
| 504 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ |
| 505 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ |
| 506 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ |
| 507 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ |
| 508 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ |
| 509 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ |
| 510 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ |
| 511 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ |
| 512 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ |
| 513 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ |
| 514 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ |
| 515 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ |
| 516 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ |
| 517 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ |
| 518 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ |
| 519 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ |
| 520 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ |
| 521 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ |
| 522 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ |
| 523 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ |
Peer Chen | 7100819 | 2007-09-24 10:16:25 +0800 | [diff] [blame] | 524 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
| 525 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ |
| 526 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ |
| 527 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ |
| 528 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ |
| 529 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ |
| 530 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ |
| 531 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 532 | |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 533 | /* SiS */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 534 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
| 535 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ |
| 536 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 537 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 538 | /* Marvell */ |
| 539 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ |
| 540 | |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 541 | /* Generic, PCI class code for AHCI */ |
| 542 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 543 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 544 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | { } /* terminate list */ |
| 546 | }; |
| 547 | |
| 548 | |
| 549 | static struct pci_driver ahci_pci_driver = { |
| 550 | .name = DRV_NAME, |
| 551 | .id_table = ahci_pci_tbl, |
| 552 | .probe = ahci_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 553 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 554 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 555 | .suspend = ahci_pci_device_suspend, |
| 556 | .resume = ahci_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 557 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 558 | }; |
| 559 | |
| 560 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 561 | static inline int ahci_nr_ports(u32 cap) |
| 562 | { |
| 563 | return (cap & 0x1f) + 1; |
| 564 | } |
| 565 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 566 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
| 567 | unsigned int port_no) |
| 568 | { |
| 569 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 570 | |
| 571 | return mmio + 0x100 + (port_no * 0x80); |
| 572 | } |
| 573 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 574 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 576 | return __ahci_port_base(ap->host, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | } |
| 578 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 579 | /** |
| 580 | * ahci_save_initial_config - Save and fixup initial config values |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 581 | * @pdev: target PCI device |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 582 | * @hpriv: host private area to store config values |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 583 | * |
| 584 | * Some registers containing configuration info might be setup by |
| 585 | * BIOS and might be cleared on reset. This function saves the |
| 586 | * initial values of those registers into @hpriv such that they |
| 587 | * can be restored after controller reset. |
| 588 | * |
| 589 | * If inconsistent, config values are fixed up by this function. |
| 590 | * |
| 591 | * LOCKING: |
| 592 | * None. |
| 593 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 594 | static void ahci_save_initial_config(struct pci_dev *pdev, |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 595 | struct ahci_host_priv *hpriv) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 596 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 597 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 598 | u32 cap, port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 599 | int i; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 600 | |
| 601 | /* Values prefixed with saved_ are written back to host after |
| 602 | * reset. Values without are used for driver operation. |
| 603 | */ |
| 604 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); |
| 605 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); |
| 606 | |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 607 | /* some chips have errata preventing 64bit use */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 608 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 609 | dev_printk(KERN_INFO, &pdev->dev, |
| 610 | "controller can't do 64bit DMA, forcing 32bit\n"); |
| 611 | cap &= ~HOST_CAP_64; |
| 612 | } |
| 613 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 614 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 615 | dev_printk(KERN_INFO, &pdev->dev, |
| 616 | "controller can't do NCQ, turning off CAP_NCQ\n"); |
| 617 | cap &= ~HOST_CAP_NCQ; |
| 618 | } |
| 619 | |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 620 | if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
| 621 | dev_printk(KERN_INFO, &pdev->dev, |
| 622 | "controller can't do PMP, turning off CAP_PMP\n"); |
| 623 | cap &= ~HOST_CAP_PMP; |
| 624 | } |
| 625 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 626 | /* |
| 627 | * Temporary Marvell 6145 hack: PATA port presence |
| 628 | * is asserted through the standard AHCI port |
| 629 | * presence register, as bit 4 (counting from 0) |
| 630 | */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 631 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 632 | dev_printk(KERN_ERR, &pdev->dev, |
| 633 | "MV_AHCI HACK: port_map %x -> %x\n", |
| 634 | hpriv->port_map, |
| 635 | hpriv->port_map & 0xf); |
| 636 | |
| 637 | port_map &= 0xf; |
| 638 | } |
| 639 | |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 640 | /* cross check port_map and cap.n_ports */ |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 641 | if (port_map) { |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 642 | u32 tmp_port_map = port_map; |
| 643 | int n_ports = ahci_nr_ports(cap); |
| 644 | |
| 645 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { |
| 646 | if (tmp_port_map & (1 << i)) { |
| 647 | n_ports--; |
| 648 | tmp_port_map &= ~(1 << i); |
| 649 | } |
| 650 | } |
| 651 | |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 652 | /* If n_ports and port_map are inconsistent, whine and |
| 653 | * clear port_map and let it be generated from n_ports. |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 654 | */ |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 655 | if (n_ports || tmp_port_map) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 656 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 657 | "nr_ports (%u) and implemented port map " |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 658 | "(0x%x) don't match, using nr_ports\n", |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 659 | ahci_nr_ports(cap), port_map); |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 660 | port_map = 0; |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | /* fabricate port_map from cap.nr_ports */ |
| 665 | if (!port_map) { |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 666 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 667 | dev_printk(KERN_WARNING, &pdev->dev, |
| 668 | "forcing PORTS_IMPL to 0x%x\n", port_map); |
| 669 | |
| 670 | /* write the fixed up value to the PI register */ |
| 671 | hpriv->saved_port_map = port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 672 | } |
| 673 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 674 | /* record values to use during operation */ |
| 675 | hpriv->cap = cap; |
| 676 | hpriv->port_map = port_map; |
| 677 | } |
| 678 | |
| 679 | /** |
| 680 | * ahci_restore_initial_config - Restore initial config |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 681 | * @host: target ATA host |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 682 | * |
| 683 | * Restore initial config stored by ahci_save_initial_config(). |
| 684 | * |
| 685 | * LOCKING: |
| 686 | * None. |
| 687 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 688 | static void ahci_restore_initial_config(struct ata_host *host) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 689 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 690 | struct ahci_host_priv *hpriv = host->private_data; |
| 691 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 692 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 693 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
| 694 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); |
| 695 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
| 696 | } |
| 697 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 698 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 699 | { |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 700 | static const int offset[] = { |
| 701 | [SCR_STATUS] = PORT_SCR_STAT, |
| 702 | [SCR_CONTROL] = PORT_SCR_CTL, |
| 703 | [SCR_ERROR] = PORT_SCR_ERR, |
| 704 | [SCR_ACTIVE] = PORT_SCR_ACT, |
| 705 | [SCR_NOTIFICATION] = PORT_SCR_NTF, |
| 706 | }; |
| 707 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 708 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 709 | if (sc_reg < ARRAY_SIZE(offset) && |
| 710 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) |
| 711 | return offset[sc_reg]; |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 712 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | } |
| 714 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 715 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 716 | { |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 717 | void __iomem *port_mmio = ahci_port_base(ap); |
| 718 | int offset = ahci_scr_offset(ap, sc_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 719 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 720 | if (offset) { |
| 721 | *val = readl(port_mmio + offset); |
| 722 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 723 | } |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 724 | return -EINVAL; |
| 725 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 726 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 727 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
| 728 | { |
| 729 | void __iomem *port_mmio = ahci_port_base(ap); |
| 730 | int offset = ahci_scr_offset(ap, sc_reg); |
| 731 | |
| 732 | if (offset) { |
| 733 | writel(val, port_mmio + offset); |
| 734 | return 0; |
| 735 | } |
| 736 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 737 | } |
| 738 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 739 | static void ahci_start_engine(struct ata_port *ap) |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 740 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 741 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 742 | u32 tmp; |
| 743 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 744 | /* start DMA */ |
Tejun Heo | 9f59205 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 745 | tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 746 | tmp |= PORT_CMD_START; |
| 747 | writel(tmp, port_mmio + PORT_CMD); |
| 748 | readl(port_mmio + PORT_CMD); /* flush */ |
| 749 | } |
| 750 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 751 | static int ahci_stop_engine(struct ata_port *ap) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 752 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 753 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 754 | u32 tmp; |
| 755 | |
| 756 | tmp = readl(port_mmio + PORT_CMD); |
| 757 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 758 | /* check if the HBA is idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 759 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
| 760 | return 0; |
| 761 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 762 | /* setting HBA to idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 763 | tmp &= ~PORT_CMD_START; |
| 764 | writel(tmp, port_mmio + PORT_CMD); |
| 765 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 766 | /* wait for engine to stop. This could be as long as 500 msec */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 767 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 768 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 769 | if (tmp & PORT_CMD_LIST_ON) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 770 | return -EIO; |
| 771 | |
| 772 | return 0; |
| 773 | } |
| 774 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 775 | static void ahci_start_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 776 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 777 | void __iomem *port_mmio = ahci_port_base(ap); |
| 778 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 779 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 780 | u32 tmp; |
| 781 | |
| 782 | /* set FIS registers */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 783 | if (hpriv->cap & HOST_CAP_64) |
| 784 | writel((pp->cmd_slot_dma >> 16) >> 16, |
| 785 | port_mmio + PORT_LST_ADDR_HI); |
| 786 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 787 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 788 | if (hpriv->cap & HOST_CAP_64) |
| 789 | writel((pp->rx_fis_dma >> 16) >> 16, |
| 790 | port_mmio + PORT_FIS_ADDR_HI); |
| 791 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 792 | |
| 793 | /* enable FIS reception */ |
| 794 | tmp = readl(port_mmio + PORT_CMD); |
| 795 | tmp |= PORT_CMD_FIS_RX; |
| 796 | writel(tmp, port_mmio + PORT_CMD); |
| 797 | |
| 798 | /* flush */ |
| 799 | readl(port_mmio + PORT_CMD); |
| 800 | } |
| 801 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 802 | static int ahci_stop_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 803 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 804 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 805 | u32 tmp; |
| 806 | |
| 807 | /* disable FIS reception */ |
| 808 | tmp = readl(port_mmio + PORT_CMD); |
| 809 | tmp &= ~PORT_CMD_FIS_RX; |
| 810 | writel(tmp, port_mmio + PORT_CMD); |
| 811 | |
| 812 | /* wait for completion, spec says 500ms, give it 1000 */ |
| 813 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, |
| 814 | PORT_CMD_FIS_ON, 10, 1000); |
| 815 | if (tmp & PORT_CMD_FIS_ON) |
| 816 | return -EBUSY; |
| 817 | |
| 818 | return 0; |
| 819 | } |
| 820 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 821 | static void ahci_power_up(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 822 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 823 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 824 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 825 | u32 cmd; |
| 826 | |
| 827 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
| 828 | |
| 829 | /* spin up device */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 830 | if (hpriv->cap & HOST_CAP_SSS) { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 831 | cmd |= PORT_CMD_SPIN_UP; |
| 832 | writel(cmd, port_mmio + PORT_CMD); |
| 833 | } |
| 834 | |
| 835 | /* wake up link */ |
| 836 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); |
| 837 | } |
| 838 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 839 | #ifdef CONFIG_PM |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 840 | static void ahci_power_down(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 841 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 842 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 843 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 844 | u32 cmd, scontrol; |
| 845 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 846 | if (!(hpriv->cap & HOST_CAP_SSS)) |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 847 | return; |
| 848 | |
| 849 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
| 850 | scontrol = readl(port_mmio + PORT_SCR_CTL); |
| 851 | scontrol &= ~0xf; |
| 852 | writel(scontrol, port_mmio + PORT_SCR_CTL); |
| 853 | |
| 854 | /* then set PxCMD.SUD to 0 */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 855 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 856 | cmd &= ~PORT_CMD_SPIN_UP; |
| 857 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 858 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 859 | #endif |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 860 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 861 | static void ahci_start_port(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 862 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 863 | /* enable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 864 | ahci_start_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 865 | |
| 866 | /* enable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 867 | ahci_start_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 868 | } |
| 869 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 870 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 871 | { |
| 872 | int rc; |
| 873 | |
| 874 | /* disable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 875 | rc = ahci_stop_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 876 | if (rc) { |
| 877 | *emsg = "failed to stop engine"; |
| 878 | return rc; |
| 879 | } |
| 880 | |
| 881 | /* disable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 882 | rc = ahci_stop_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 883 | if (rc) { |
| 884 | *emsg = "failed stop FIS RX"; |
| 885 | return rc; |
| 886 | } |
| 887 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 888 | return 0; |
| 889 | } |
| 890 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 891 | static int ahci_reset_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 892 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 893 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 894 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 895 | u32 tmp; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 896 | |
Jeff Garzik | 3cc3eb1 | 2007-09-26 00:02:41 -0400 | [diff] [blame] | 897 | /* we must be in AHCI mode, before using anything |
| 898 | * AHCI-specific, such as HOST_RESET. |
| 899 | */ |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 900 | tmp = readl(mmio + HOST_CTL); |
Jeff Garzik | 3cc3eb1 | 2007-09-26 00:02:41 -0400 | [diff] [blame] | 901 | if (!(tmp & HOST_AHCI_EN)) |
| 902 | writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL); |
| 903 | |
| 904 | /* global controller reset */ |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 905 | if ((tmp & HOST_RESET) == 0) { |
| 906 | writel(tmp | HOST_RESET, mmio + HOST_CTL); |
| 907 | readl(mmio + HOST_CTL); /* flush */ |
| 908 | } |
| 909 | |
| 910 | /* reset must complete within 1 second, or |
| 911 | * the hardware should be considered fried. |
| 912 | */ |
| 913 | ssleep(1); |
| 914 | |
| 915 | tmp = readl(mmio + HOST_CTL); |
| 916 | if (tmp & HOST_RESET) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 917 | dev_printk(KERN_ERR, host->dev, |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 918 | "controller reset failed (0x%x)\n", tmp); |
| 919 | return -EIO; |
| 920 | } |
| 921 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 922 | /* turn on AHCI mode */ |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 923 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
| 924 | (void) readl(mmio + HOST_CTL); /* flush */ |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 925 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 926 | /* some registers might be cleared on reset. restore initial values */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 927 | ahci_restore_initial_config(host); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 928 | |
| 929 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 930 | u16 tmp16; |
| 931 | |
| 932 | /* configure PCS */ |
| 933 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 934 | tmp16 |= 0xf; |
| 935 | pci_write_config_word(pdev, 0x92, tmp16); |
| 936 | } |
| 937 | |
| 938 | return 0; |
| 939 | } |
| 940 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 941 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
| 942 | int port_no, void __iomem *mmio, |
| 943 | void __iomem *port_mmio) |
| 944 | { |
| 945 | const char *emsg = NULL; |
| 946 | int rc; |
| 947 | u32 tmp; |
| 948 | |
| 949 | /* make sure port is not active */ |
| 950 | rc = ahci_deinit_port(ap, &emsg); |
| 951 | if (rc) |
| 952 | dev_printk(KERN_WARNING, &pdev->dev, |
| 953 | "%s (%d)\n", emsg, rc); |
| 954 | |
| 955 | /* clear SError */ |
| 956 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 957 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); |
| 958 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 959 | |
| 960 | /* clear port IRQ */ |
| 961 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 962 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 963 | if (tmp) |
| 964 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 965 | |
| 966 | writel(1 << port_no, mmio + HOST_IRQ_STAT); |
| 967 | } |
| 968 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 969 | static void ahci_init_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 970 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 971 | struct ahci_host_priv *hpriv = host->private_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 972 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 973 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 974 | int i; |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 975 | void __iomem *port_mmio; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 976 | u32 tmp; |
| 977 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 978 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 979 | port_mmio = __ahci_port_base(host, 4); |
| 980 | |
| 981 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 982 | |
| 983 | /* clear port IRQ */ |
| 984 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 985 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 986 | if (tmp) |
| 987 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 988 | } |
| 989 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 990 | for (i = 0; i < host->n_ports; i++) { |
| 991 | struct ata_port *ap = host->ports[i]; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 992 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 993 | port_mmio = ahci_port_base(ap); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 994 | if (ata_port_is_dummy(ap)) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 995 | continue; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 996 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 997 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 998 | } |
| 999 | |
| 1000 | tmp = readl(mmio + HOST_CTL); |
| 1001 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 1002 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 1003 | tmp = readl(mmio + HOST_CTL); |
| 1004 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 1005 | } |
| 1006 | |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1007 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1008 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1009 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1010 | struct ata_taskfile tf; |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1011 | u32 tmp; |
| 1012 | |
| 1013 | tmp = readl(port_mmio + PORT_SIG); |
| 1014 | tf.lbah = (tmp >> 24) & 0xff; |
| 1015 | tf.lbam = (tmp >> 16) & 0xff; |
| 1016 | tf.lbal = (tmp >> 8) & 0xff; |
| 1017 | tf.nsect = (tmp) & 0xff; |
| 1018 | |
| 1019 | return ata_dev_classify(&tf); |
| 1020 | } |
| 1021 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1022 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 1023 | u32 opts) |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1024 | { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1025 | dma_addr_t cmd_tbl_dma; |
| 1026 | |
| 1027 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; |
| 1028 | |
| 1029 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); |
| 1030 | pp->cmd_slot[tag].status = 0; |
| 1031 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); |
| 1032 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1033 | } |
| 1034 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1035 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1036 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1037 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1038 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1039 | u32 tmp; |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1040 | int busy, rc; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1041 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1042 | /* do we need to kick the port? */ |
| 1043 | busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ); |
| 1044 | if (!busy && !force_restart) |
| 1045 | return 0; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1046 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1047 | /* stop engine */ |
| 1048 | rc = ahci_stop_engine(ap); |
| 1049 | if (rc) |
| 1050 | goto out_restart; |
| 1051 | |
| 1052 | /* need to do CLO? */ |
| 1053 | if (!busy) { |
| 1054 | rc = 0; |
| 1055 | goto out_restart; |
| 1056 | } |
| 1057 | |
| 1058 | if (!(hpriv->cap & HOST_CAP_CLO)) { |
| 1059 | rc = -EOPNOTSUPP; |
| 1060 | goto out_restart; |
| 1061 | } |
| 1062 | |
| 1063 | /* perform CLO */ |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1064 | tmp = readl(port_mmio + PORT_CMD); |
| 1065 | tmp |= PORT_CMD_CLO; |
| 1066 | writel(tmp, port_mmio + PORT_CMD); |
| 1067 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1068 | rc = 0; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1069 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 1070 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); |
| 1071 | if (tmp & PORT_CMD_CLO) |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1072 | rc = -EIO; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1073 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1074 | /* restart engine */ |
| 1075 | out_restart: |
| 1076 | ahci_start_engine(ap); |
| 1077 | return rc; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1078 | } |
| 1079 | |
Tejun Heo | 91c4a2e | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1080 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
| 1081 | struct ata_taskfile *tf, int is_cmd, u16 flags, |
| 1082 | unsigned long timeout_msec) |
| 1083 | { |
| 1084 | const u32 cmd_fis_len = 5; /* five dwords */ |
| 1085 | struct ahci_port_priv *pp = ap->private_data; |
| 1086 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1087 | u8 *fis = pp->cmd_tbl; |
| 1088 | u32 tmp; |
| 1089 | |
| 1090 | /* prep the command */ |
| 1091 | ata_tf_to_fis(tf, pmp, is_cmd, fis); |
| 1092 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); |
| 1093 | |
| 1094 | /* issue & wait */ |
| 1095 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 1096 | |
| 1097 | if (timeout_msec) { |
| 1098 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, |
| 1099 | 1, timeout_msec); |
| 1100 | if (tmp & 0x1) { |
| 1101 | ahci_kick_engine(ap, 1); |
| 1102 | return -EBUSY; |
| 1103 | } |
| 1104 | } else |
| 1105 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1106 | |
| 1107 | return 0; |
| 1108 | } |
| 1109 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1110 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1111 | int pmp, unsigned long deadline) |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1112 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1113 | struct ata_port *ap = link->ap; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1114 | const char *reason = NULL; |
Tejun Heo | 2cbb79e | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1115 | unsigned long now, msecs; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1116 | struct ata_taskfile tf; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1117 | int rc; |
| 1118 | |
| 1119 | DPRINTK("ENTER\n"); |
| 1120 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1121 | if (ata_link_offline(link)) { |
Tejun Heo | c2a6585 | 2006-04-03 01:58:06 +0900 | [diff] [blame] | 1122 | DPRINTK("PHY reports no device\n"); |
| 1123 | *class = ATA_DEV_NONE; |
| 1124 | return 0; |
| 1125 | } |
| 1126 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1127 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1128 | rc = ahci_kick_engine(ap, 1); |
| 1129 | if (rc) |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1130 | ata_link_printk(link, KERN_WARNING, |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1131 | "failed to reset engine (errno=%d)", rc); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1132 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1133 | ata_tf_init(link->device, &tf); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1134 | |
| 1135 | /* issue the first D2H Register FIS */ |
Tejun Heo | 2cbb79e | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1136 | msecs = 0; |
| 1137 | now = jiffies; |
| 1138 | if (time_after(now, deadline)) |
| 1139 | msecs = jiffies_to_msecs(deadline - now); |
| 1140 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1141 | tf.ctl |= ATA_SRST; |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1142 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
Tejun Heo | 91c4a2e | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1143 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1144 | rc = -EIO; |
| 1145 | reason = "1st FIS failed"; |
| 1146 | goto fail; |
| 1147 | } |
| 1148 | |
| 1149 | /* spec says at least 5us, but be generous and sleep for 1ms */ |
| 1150 | msleep(1); |
| 1151 | |
| 1152 | /* issue the second D2H Register FIS */ |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1153 | tf.ctl &= ~ATA_SRST; |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1154 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1155 | |
| 1156 | /* spec mandates ">= 2ms" before checking status. |
| 1157 | * We wait 150ms, because that was the magic delay used for |
| 1158 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time |
| 1159 | * between when the ATA command register is written, and then |
| 1160 | * status is checked. Because waiting for "a while" before |
| 1161 | * checking status is fine, post SRST, we perform this magic |
| 1162 | * delay here as well. |
| 1163 | */ |
| 1164 | msleep(150); |
| 1165 | |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1166 | rc = ata_wait_ready(ap, deadline); |
| 1167 | /* link occupied, -ENODEV too is an error */ |
| 1168 | if (rc) { |
| 1169 | reason = "device not ready"; |
| 1170 | goto fail; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1171 | } |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1172 | *class = ahci_dev_classify(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1173 | |
| 1174 | DPRINTK("EXIT, class=%u\n", *class); |
| 1175 | return 0; |
| 1176 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1177 | fail: |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1178 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1179 | return rc; |
| 1180 | } |
| 1181 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1182 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1183 | unsigned long deadline) |
| 1184 | { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1185 | int pmp = 0; |
| 1186 | |
| 1187 | if (link->ap->flags & ATA_FLAG_PMP) |
| 1188 | pmp = SATA_PMP_CTRL_PORT; |
| 1189 | |
| 1190 | return ahci_do_softreset(link, class, pmp, deadline); |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1191 | } |
| 1192 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1193 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1194 | unsigned long deadline) |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1195 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1196 | struct ata_port *ap = link->ap; |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1197 | struct ahci_port_priv *pp = ap->private_data; |
| 1198 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1199 | struct ata_taskfile tf; |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1200 | int rc; |
| 1201 | |
| 1202 | DPRINTK("ENTER\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1203 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1204 | ahci_stop_engine(ap); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1205 | |
| 1206 | /* clear D2H reception area to properly wait for D2H FIS */ |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1207 | ata_tf_init(link->device, &tf); |
Tejun Heo | dfd7a3d | 2007-01-26 15:37:20 +0900 | [diff] [blame] | 1208 | tf.command = 0x80; |
Tejun Heo | 9977126 | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1209 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1210 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1211 | rc = sata_std_hardreset(link, class, deadline); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1212 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1213 | ahci_start_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1214 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1215 | if (rc == 0 && ata_link_online(link)) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1216 | *class = ahci_dev_classify(ap); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1217 | if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1218 | *class = ATA_DEV_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1219 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1220 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1221 | return rc; |
| 1222 | } |
| 1223 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1224 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1225 | unsigned long deadline) |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1226 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1227 | struct ata_port *ap = link->ap; |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1228 | u32 serror; |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1229 | int rc; |
| 1230 | |
| 1231 | DPRINTK("ENTER\n"); |
| 1232 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1233 | ahci_stop_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1234 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1235 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1236 | deadline); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1237 | |
| 1238 | /* vt8251 needs SError cleared for the port to operate */ |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1239 | ahci_scr_read(ap, SCR_ERROR, &serror); |
| 1240 | ahci_scr_write(ap, SCR_ERROR, serror); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1241 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1242 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1243 | |
| 1244 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1245 | |
| 1246 | /* vt8251 doesn't clear BSY on signature FIS reception, |
| 1247 | * request follow-up softreset. |
| 1248 | */ |
| 1249 | return rc ?: -EAGAIN; |
| 1250 | } |
| 1251 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame^] | 1252 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
| 1253 | unsigned long deadline) |
| 1254 | { |
| 1255 | struct ata_port *ap = link->ap; |
| 1256 | struct ahci_port_priv *pp = ap->private_data; |
| 1257 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1258 | struct ata_taskfile tf; |
| 1259 | int rc; |
| 1260 | |
| 1261 | ahci_stop_engine(ap); |
| 1262 | |
| 1263 | /* clear D2H reception area to properly wait for D2H FIS */ |
| 1264 | ata_tf_init(link->device, &tf); |
| 1265 | tf.command = 0x80; |
| 1266 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
| 1267 | |
| 1268 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
| 1269 | deadline); |
| 1270 | |
| 1271 | ahci_start_engine(ap); |
| 1272 | |
| 1273 | if (rc || ata_link_offline(link)) |
| 1274 | return rc; |
| 1275 | |
| 1276 | /* spec mandates ">= 2ms" before checking status */ |
| 1277 | msleep(150); |
| 1278 | |
| 1279 | /* The pseudo configuration device on SIMG4726 attached to |
| 1280 | * ASUS P5W-DH Deluxe doesn't send signature FIS after |
| 1281 | * hardreset if no device is attached to the first downstream |
| 1282 | * port && the pseudo device locks up on SRST w/ PMP==0. To |
| 1283 | * work around this, wait for !BSY only briefly. If BSY isn't |
| 1284 | * cleared, perform CLO and proceed to IDENTIFY (achieved by |
| 1285 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). |
| 1286 | * |
| 1287 | * Wait for two seconds. Devices attached to downstream port |
| 1288 | * which can't process the following IDENTIFY after this will |
| 1289 | * have to be reset again. For most cases, this should |
| 1290 | * suffice while making probing snappish enough. |
| 1291 | */ |
| 1292 | rc = ata_wait_ready(ap, jiffies + 2 * HZ); |
| 1293 | if (rc) |
| 1294 | ahci_kick_engine(ap, 0); |
| 1295 | |
| 1296 | return 0; |
| 1297 | } |
| 1298 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1299 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1300 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1301 | struct ata_port *ap = link->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1302 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1303 | u32 new_tmp, tmp; |
| 1304 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1305 | ata_std_postreset(link, class); |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1306 | |
| 1307 | /* Make sure port's ATAPI bit is set appropriately */ |
| 1308 | new_tmp = tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1309 | if (*class == ATA_DEV_ATAPI) |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1310 | new_tmp |= PORT_CMD_ATAPI; |
| 1311 | else |
| 1312 | new_tmp &= ~PORT_CMD_ATAPI; |
| 1313 | if (new_tmp != tmp) { |
| 1314 | writel(new_tmp, port_mmio + PORT_CMD); |
| 1315 | readl(port_mmio + PORT_CMD); /* flush */ |
| 1316 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1317 | } |
| 1318 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1319 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, |
| 1320 | unsigned long deadline) |
| 1321 | { |
| 1322 | return ahci_do_softreset(link, class, link->pmp, deadline); |
| 1323 | } |
| 1324 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1325 | static u8 ahci_check_status(struct ata_port *ap) |
| 1326 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1327 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1328 | |
| 1329 | return readl(mmio + PORT_TFDATA) & 0xFF; |
| 1330 | } |
| 1331 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1332 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 1333 | { |
| 1334 | struct ahci_port_priv *pp = ap->private_data; |
| 1335 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1336 | |
| 1337 | ata_tf_from_fis(d2h_fis, tf); |
| 1338 | } |
| 1339 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1340 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1341 | { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1342 | struct scatterlist *sg; |
| 1343 | struct ahci_sg *ahci_sg; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1344 | unsigned int n_sg = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1345 | |
| 1346 | VPRINTK("ENTER\n"); |
| 1347 | |
| 1348 | /* |
| 1349 | * Next, the S/G list. |
| 1350 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1351 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1352 | ata_for_each_sg(sg, qc) { |
| 1353 | dma_addr_t addr = sg_dma_address(sg); |
| 1354 | u32 sg_len = sg_dma_len(sg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1355 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1356 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 1357 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 1358 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1359 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1360 | ahci_sg++; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1361 | n_sg++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1362 | } |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1363 | |
| 1364 | return n_sg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1365 | } |
| 1366 | |
| 1367 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
| 1368 | { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1369 | struct ata_port *ap = qc->ap; |
| 1370 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1371 | int is_atapi = is_atapi_taskfile(&qc->tf); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1372 | void *cmd_tbl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1373 | u32 opts; |
| 1374 | const u32 cmd_fis_len = 5; /* five dwords */ |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1375 | unsigned int n_elem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1376 | |
| 1377 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1378 | * Fill in command table information. First, the header, |
| 1379 | * a SATA Register - Host to Device command FIS. |
| 1380 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1381 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
| 1382 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1383 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1384 | if (is_atapi) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1385 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
| 1386 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1387 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1389 | n_elem = 0; |
| 1390 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1391 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1392 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1393 | /* |
| 1394 | * Fill in command slot information. |
| 1395 | */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1396 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1397 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 1398 | opts |= AHCI_CMD_WRITE; |
| 1399 | if (is_atapi) |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 1400 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1401 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1402 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1403 | } |
| 1404 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1405 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1407 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1408 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1409 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
| 1410 | struct ata_link *link = NULL; |
| 1411 | struct ata_queued_cmd *active_qc; |
| 1412 | struct ata_eh_info *active_ehi; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1413 | u32 serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1414 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1415 | /* determine active link */ |
| 1416 | ata_port_for_each_link(link, ap) |
| 1417 | if (ata_link_active(link)) |
| 1418 | break; |
| 1419 | if (!link) |
| 1420 | link = &ap->link; |
| 1421 | |
| 1422 | active_qc = ata_qc_from_tag(ap, link->active_tag); |
| 1423 | active_ehi = &link->eh_info; |
| 1424 | |
| 1425 | /* record irq stat */ |
| 1426 | ata_ehi_clear_desc(host_ehi); |
| 1427 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 1428 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1429 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1430 | ahci_scr_read(ap, SCR_ERROR, &serror); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1431 | ahci_scr_write(ap, SCR_ERROR, serror); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1432 | host_ehi->serror |= serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1433 | |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 1434 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1435 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 1436 | irq_stat &= ~PORT_IRQ_IF_ERR; |
| 1437 | |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 1438 | if (irq_stat & PORT_IRQ_TF_ERR) { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1439 | /* If qc is active, charge it; otherwise, the active |
| 1440 | * link. There's no active qc on NCQ errors. It will |
| 1441 | * be determined by EH by reading log page 10h. |
| 1442 | */ |
| 1443 | if (active_qc) |
| 1444 | active_qc->err_mask |= AC_ERR_DEV; |
| 1445 | else |
| 1446 | active_ehi->err_mask |= AC_ERR_DEV; |
| 1447 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1448 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1449 | host_ehi->serror &= ~SERR_INTERNAL; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1450 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1451 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1452 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
| 1453 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1454 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1455 | active_ehi->err_mask |= AC_ERR_HSM; |
| 1456 | active_ehi->action |= ATA_EH_SOFTRESET; |
| 1457 | ata_ehi_push_desc(active_ehi, |
| 1458 | "unknown FIS %08x %08x %08x %08x" , |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1459 | unk[0], unk[1], unk[2], unk[3]); |
| 1460 | } |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 1461 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1462 | if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) { |
| 1463 | active_ehi->err_mask |= AC_ERR_HSM; |
| 1464 | active_ehi->action |= ATA_EH_SOFTRESET; |
| 1465 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); |
| 1466 | } |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1467 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1468 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { |
| 1469 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
| 1470 | host_ehi->action |= ATA_EH_SOFTRESET; |
| 1471 | ata_ehi_push_desc(host_ehi, "host bus error"); |
| 1472 | } |
| 1473 | |
| 1474 | if (irq_stat & PORT_IRQ_IF_ERR) { |
| 1475 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
| 1476 | host_ehi->action |= ATA_EH_SOFTRESET; |
| 1477 | ata_ehi_push_desc(host_ehi, "interface fatal error"); |
| 1478 | } |
| 1479 | |
| 1480 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
| 1481 | ata_ehi_hotplugged(host_ehi); |
| 1482 | ata_ehi_push_desc(host_ehi, "%s", |
| 1483 | irq_stat & PORT_IRQ_CONNECT ? |
| 1484 | "connection status changed" : "PHY RDY changed"); |
| 1485 | } |
| 1486 | |
| 1487 | /* okay, let's hand over to EH */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1488 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1489 | if (irq_stat & PORT_IRQ_FREEZE) |
| 1490 | ata_port_freeze(ap); |
| 1491 | else |
| 1492 | ata_port_abort(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1493 | } |
| 1494 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1495 | static void ahci_port_intr(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1496 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1497 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1498 | struct ata_eh_info *ehi = &ap->link.eh_info; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1499 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 1500 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 1501 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1502 | u32 status, qc_active; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1503 | int rc, known_irq = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1504 | |
| 1505 | status = readl(port_mmio + PORT_IRQ_STAT); |
| 1506 | writel(status, port_mmio + PORT_IRQ_STAT); |
| 1507 | |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 1508 | /* ignore BAD_PMP while resetting */ |
| 1509 | if (unlikely(resetting)) |
| 1510 | status &= ~PORT_IRQ_BAD_PMP; |
| 1511 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1512 | if (unlikely(status & PORT_IRQ_ERROR)) { |
| 1513 | ahci_error_intr(ap, status); |
| 1514 | return; |
| 1515 | } |
| 1516 | |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 1517 | if (status & PORT_IRQ_SDB_FIS) { |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 1518 | /* If SNotification is available, leave notification |
| 1519 | * handling to sata_async_notification(). If not, |
| 1520 | * emulate it by snooping SDB FIS RX area. |
| 1521 | * |
| 1522 | * Snooping FIS RX area is probably cheaper than |
| 1523 | * poking SNotification but some constrollers which |
| 1524 | * implement SNotification, ICH9 for example, don't |
| 1525 | * store AN SDB FIS into receive area. |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 1526 | */ |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 1527 | if (hpriv->cap & HOST_CAP_SNTF) |
Tejun Heo | 7d77b24 | 2007-09-23 13:14:13 +0900 | [diff] [blame] | 1528 | sata_async_notification(ap); |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 1529 | else { |
| 1530 | /* If the 'N' bit in word 0 of the FIS is set, |
| 1531 | * we just received asynchronous notification. |
| 1532 | * Tell libata about it. |
| 1533 | */ |
| 1534 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
| 1535 | u32 f0 = le32_to_cpu(f[0]); |
| 1536 | |
| 1537 | if (f0 & (1 << 15)) |
| 1538 | sata_async_notification(ap); |
| 1539 | } |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 1540 | } |
| 1541 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1542 | /* pp->active_link is valid iff any command is in flight */ |
| 1543 | if (ap->qc_active && pp->active_link->sactive) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1544 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
| 1545 | else |
| 1546 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); |
| 1547 | |
| 1548 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 1549 | |
| 1550 | /* If resetting, spurious or invalid completions are expected, |
| 1551 | * return unconditionally. |
| 1552 | */ |
| 1553 | if (resetting) |
| 1554 | return; |
| 1555 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1556 | if (rc > 0) |
| 1557 | return; |
| 1558 | if (rc < 0) { |
| 1559 | ehi->err_mask |= AC_ERR_HSM; |
| 1560 | ehi->action |= ATA_EH_SOFTRESET; |
| 1561 | ata_port_freeze(ap); |
| 1562 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1563 | } |
| 1564 | |
Robert P. J. Day | 3a4fa0a | 2007-10-19 23:10:43 +0200 | [diff] [blame] | 1565 | /* hmmm... a spurious interrupt */ |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 1566 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1567 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
| 1568 | * implementation for non-NCQ commands. |
| 1569 | */ |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1570 | if (!ap->link.sactive) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1571 | return; |
| 1572 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1573 | if (status & PORT_IRQ_D2H_REG_FIS) { |
| 1574 | if (!pp->ncq_saw_d2h) |
| 1575 | ata_port_printk(ap, KERN_INFO, |
| 1576 | "D2H reg with I during NCQ, " |
| 1577 | "this message won't be printed again\n"); |
| 1578 | pp->ncq_saw_d2h = 1; |
| 1579 | known_irq = 1; |
| 1580 | } |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 1581 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1582 | if (status & PORT_IRQ_DMAS_FIS) { |
| 1583 | if (!pp->ncq_saw_dmas) |
| 1584 | ata_port_printk(ap, KERN_INFO, |
| 1585 | "DMAS FIS during NCQ, " |
| 1586 | "this message won't be printed again\n"); |
| 1587 | pp->ncq_saw_dmas = 1; |
| 1588 | known_irq = 1; |
| 1589 | } |
| 1590 | |
Tejun Heo | a2bbd0c | 2007-02-21 16:34:25 +0900 | [diff] [blame] | 1591 | if (status & PORT_IRQ_SDB_FIS) { |
Al Viro | 04d4f7a | 2007-02-09 16:39:30 +0000 | [diff] [blame] | 1592 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1593 | |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 1594 | if (le32_to_cpu(f[1])) { |
| 1595 | /* SDB FIS containing spurious completions |
| 1596 | * might be dangerous, whine and fail commands |
| 1597 | * with HSM violation. EH will turn off NCQ |
| 1598 | * after several such failures. |
| 1599 | */ |
| 1600 | ata_ehi_push_desc(ehi, |
| 1601 | "spurious completions during NCQ " |
| 1602 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", |
| 1603 | readl(port_mmio + PORT_CMD_ISSUE), |
| 1604 | readl(port_mmio + PORT_SCR_ACT), |
| 1605 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); |
| 1606 | ehi->err_mask |= AC_ERR_HSM; |
| 1607 | ehi->action |= ATA_EH_SOFTRESET; |
| 1608 | ata_port_freeze(ap); |
| 1609 | } else { |
| 1610 | if (!pp->ncq_saw_sdb) |
| 1611 | ata_port_printk(ap, KERN_INFO, |
| 1612 | "spurious SDB FIS %08x:%08x during NCQ, " |
| 1613 | "this message won't be printed again\n", |
| 1614 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); |
| 1615 | pp->ncq_saw_sdb = 1; |
| 1616 | } |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1617 | known_irq = 1; |
| 1618 | } |
| 1619 | |
| 1620 | if (!known_irq) |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1621 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1622 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1623 | status, ap->link.active_tag, ap->link.sactive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1624 | } |
| 1625 | |
| 1626 | static void ahci_irq_clear(struct ata_port *ap) |
| 1627 | { |
| 1628 | /* TODO */ |
| 1629 | } |
| 1630 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1631 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1632 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1633 | struct ata_host *host = dev_instance; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1634 | struct ahci_host_priv *hpriv; |
| 1635 | unsigned int i, handled = 0; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1636 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1637 | u32 irq_stat, irq_ack = 0; |
| 1638 | |
| 1639 | VPRINTK("ENTER\n"); |
| 1640 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1641 | hpriv = host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1642 | mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1643 | |
| 1644 | /* sigh. 0xffffffff is a valid return from h/w */ |
| 1645 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
| 1646 | irq_stat &= hpriv->port_map; |
| 1647 | if (!irq_stat) |
| 1648 | return IRQ_NONE; |
| 1649 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 1650 | spin_lock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1651 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 1652 | for (i = 0; i < host->n_ports; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1653 | struct ata_port *ap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1654 | |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1655 | if (!(irq_stat & (1 << i))) |
| 1656 | continue; |
| 1657 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1658 | ap = host->ports[i]; |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1659 | if (ap) { |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1660 | ahci_port_intr(ap); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1661 | VPRINTK("port %u\n", i); |
| 1662 | } else { |
| 1663 | VPRINTK("port %u (no irq)\n", i); |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 1664 | if (ata_ratelimit()) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1665 | dev_printk(KERN_WARNING, host->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1666 | "interrupt on disabled port %u\n", i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1667 | } |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1668 | |
| 1669 | irq_ack |= (1 << i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1670 | } |
| 1671 | |
| 1672 | if (irq_ack) { |
| 1673 | writel(irq_ack, mmio + HOST_IRQ_STAT); |
| 1674 | handled = 1; |
| 1675 | } |
| 1676 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1677 | spin_unlock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1678 | |
| 1679 | VPRINTK("EXIT\n"); |
| 1680 | |
| 1681 | return IRQ_RETVAL(handled); |
| 1682 | } |
| 1683 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1684 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1685 | { |
| 1686 | struct ata_port *ap = qc->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1687 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1688 | struct ahci_port_priv *pp = ap->private_data; |
| 1689 | |
| 1690 | /* Keep track of the currently active link. It will be used |
| 1691 | * in completion path to determine whether NCQ phase is in |
| 1692 | * progress. |
| 1693 | */ |
| 1694 | pp->active_link = qc->dev->link; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1695 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1696 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 1697 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
| 1698 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1700 | |
| 1701 | return 0; |
| 1702 | } |
| 1703 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1704 | static void ahci_freeze(struct ata_port *ap) |
| 1705 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1706 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1707 | |
| 1708 | /* turn IRQ off */ |
| 1709 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 1710 | } |
| 1711 | |
| 1712 | static void ahci_thaw(struct ata_port *ap) |
| 1713 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1714 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1715 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1716 | u32 tmp; |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 1717 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1718 | |
| 1719 | /* clear IRQ */ |
| 1720 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1721 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
Tejun Heo | a718728 | 2007-01-27 11:04:26 +0900 | [diff] [blame] | 1722 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1723 | |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1724 | /* turn IRQ back on */ |
| 1725 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1726 | } |
| 1727 | |
| 1728 | static void ahci_error_handler(struct ata_port *ap) |
| 1729 | { |
Tejun Heo | b51e9e5 | 2006-06-29 01:29:30 +0900 | [diff] [blame] | 1730 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1731 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1732 | ahci_stop_engine(ap); |
| 1733 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1734 | } |
| 1735 | |
| 1736 | /* perform recovery */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1737 | sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset, |
| 1738 | ahci_hardreset, ahci_postreset, |
| 1739 | sata_pmp_std_prereset, ahci_pmp_softreset, |
| 1740 | sata_pmp_std_hardreset, sata_pmp_std_postreset); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1741 | } |
| 1742 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1743 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
| 1744 | { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1745 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1746 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1747 | ahci_stop_engine(ap); |
| 1748 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1749 | } |
| 1750 | |
| 1751 | /* perform recovery */ |
| 1752 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, |
| 1753 | ahci_postreset); |
| 1754 | } |
| 1755 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame^] | 1756 | static void ahci_p5wdh_error_handler(struct ata_port *ap) |
| 1757 | { |
| 1758 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1759 | /* restart engine */ |
| 1760 | ahci_stop_engine(ap); |
| 1761 | ahci_start_engine(ap); |
| 1762 | } |
| 1763 | |
| 1764 | /* perform recovery */ |
| 1765 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset, |
| 1766 | ahci_postreset); |
| 1767 | } |
| 1768 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1769 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
| 1770 | { |
| 1771 | struct ata_port *ap = qc->ap; |
| 1772 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1773 | /* make DMA engine forget about the failed command */ |
| 1774 | if (qc->flags & ATA_QCFLAG_FAILED) |
| 1775 | ahci_kick_engine(ap, 1); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1776 | } |
| 1777 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1778 | static void ahci_pmp_attach(struct ata_port *ap) |
| 1779 | { |
| 1780 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1781 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1782 | u32 cmd; |
| 1783 | |
| 1784 | cmd = readl(port_mmio + PORT_CMD); |
| 1785 | cmd |= PORT_CMD_PMP; |
| 1786 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1787 | |
| 1788 | pp->intr_mask |= PORT_IRQ_BAD_PMP; |
| 1789 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1790 | } |
| 1791 | |
| 1792 | static void ahci_pmp_detach(struct ata_port *ap) |
| 1793 | { |
| 1794 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1795 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1796 | u32 cmd; |
| 1797 | |
| 1798 | cmd = readl(port_mmio + PORT_CMD); |
| 1799 | cmd &= ~PORT_CMD_PMP; |
| 1800 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1801 | |
| 1802 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; |
| 1803 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1804 | } |
| 1805 | |
Alexey Dobriyan | 028a259 | 2007-07-17 23:48:48 +0400 | [diff] [blame] | 1806 | static int ahci_port_resume(struct ata_port *ap) |
| 1807 | { |
| 1808 | ahci_power_up(ap); |
| 1809 | ahci_start_port(ap); |
| 1810 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1811 | if (ap->nr_pmp_links) |
| 1812 | ahci_pmp_attach(ap); |
| 1813 | else |
| 1814 | ahci_pmp_detach(ap); |
| 1815 | |
Alexey Dobriyan | 028a259 | 2007-07-17 23:48:48 +0400 | [diff] [blame] | 1816 | return 0; |
| 1817 | } |
| 1818 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1819 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1820 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
| 1821 | { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1822 | const char *emsg = NULL; |
| 1823 | int rc; |
| 1824 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1825 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1826 | if (rc == 0) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1827 | ahci_power_down(ap); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1828 | else { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1829 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1830 | ahci_start_port(ap); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1831 | } |
| 1832 | |
| 1833 | return rc; |
| 1834 | } |
| 1835 | |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1836 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
| 1837 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1838 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1839 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1840 | u32 ctl; |
| 1841 | |
| 1842 | if (mesg.event == PM_EVENT_SUSPEND) { |
| 1843 | /* AHCI spec rev1.1 section 8.3.3: |
| 1844 | * Software must disable interrupts prior to requesting a |
| 1845 | * transition of the HBA to D3 state. |
| 1846 | */ |
| 1847 | ctl = readl(mmio + HOST_CTL); |
| 1848 | ctl &= ~HOST_IRQ_EN; |
| 1849 | writel(ctl, mmio + HOST_CTL); |
| 1850 | readl(mmio + HOST_CTL); /* flush */ |
| 1851 | } |
| 1852 | |
| 1853 | return ata_pci_device_suspend(pdev, mesg); |
| 1854 | } |
| 1855 | |
| 1856 | static int ahci_pci_device_resume(struct pci_dev *pdev) |
| 1857 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1858 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1859 | int rc; |
| 1860 | |
Tejun Heo | 553c4aa | 2006-12-26 19:39:50 +0900 | [diff] [blame] | 1861 | rc = ata_pci_device_do_resume(pdev); |
| 1862 | if (rc) |
| 1863 | return rc; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1864 | |
| 1865 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1866 | rc = ahci_reset_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1867 | if (rc) |
| 1868 | return rc; |
| 1869 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1870 | ahci_init_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1871 | } |
| 1872 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1873 | ata_host_resume(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1874 | |
| 1875 | return 0; |
| 1876 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1877 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1878 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1879 | static int ahci_port_start(struct ata_port *ap) |
| 1880 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1881 | struct device *dev = ap->host->dev; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1882 | struct ahci_port_priv *pp; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1883 | void *mem; |
| 1884 | dma_addr_t mem_dma; |
| 1885 | int rc; |
| 1886 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1887 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1888 | if (!pp) |
| 1889 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1890 | |
| 1891 | rc = ata_pad_alloc(ap, dev); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1892 | if (rc) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1893 | return rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1894 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1895 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
| 1896 | GFP_KERNEL); |
| 1897 | if (!mem) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1898 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1899 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 1900 | |
| 1901 | /* |
| 1902 | * First item in chunk of DMA memory: 32-slot command table, |
| 1903 | * 32 bytes each in size |
| 1904 | */ |
| 1905 | pp->cmd_slot = mem; |
| 1906 | pp->cmd_slot_dma = mem_dma; |
| 1907 | |
| 1908 | mem += AHCI_CMD_SLOT_SZ; |
| 1909 | mem_dma += AHCI_CMD_SLOT_SZ; |
| 1910 | |
| 1911 | /* |
| 1912 | * Second item: Received-FIS area |
| 1913 | */ |
| 1914 | pp->rx_fis = mem; |
| 1915 | pp->rx_fis_dma = mem_dma; |
| 1916 | |
| 1917 | mem += AHCI_RX_FIS_SZ; |
| 1918 | mem_dma += AHCI_RX_FIS_SZ; |
| 1919 | |
| 1920 | /* |
| 1921 | * Third item: data area for storing a single command |
| 1922 | * and its scatter-gather table |
| 1923 | */ |
| 1924 | pp->cmd_tbl = mem; |
| 1925 | pp->cmd_tbl_dma = mem_dma; |
| 1926 | |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 1927 | /* |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 1928 | * Save off initial list of interrupts to be enabled. |
| 1929 | * This could be changed later |
| 1930 | */ |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 1931 | pp->intr_mask = DEF_PORT_IRQ; |
| 1932 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1933 | ap->private_data = pp; |
| 1934 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1935 | /* engage engines, captain */ |
| 1936 | return ahci_port_resume(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1937 | } |
| 1938 | |
| 1939 | static void ahci_port_stop(struct ata_port *ap) |
| 1940 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1941 | const char *emsg = NULL; |
| 1942 | int rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1943 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1944 | /* de-initialize port */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1945 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1946 | if (rc) |
| 1947 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1948 | } |
| 1949 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1950 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1951 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1952 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1953 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1954 | if (using_dac && |
| 1955 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 1956 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 1957 | if (rc) { |
| 1958 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1959 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1960 | dev_printk(KERN_ERR, &pdev->dev, |
| 1961 | "64-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1962 | return rc; |
| 1963 | } |
| 1964 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1965 | } else { |
| 1966 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 1967 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1968 | dev_printk(KERN_ERR, &pdev->dev, |
| 1969 | "32-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1970 | return rc; |
| 1971 | } |
| 1972 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1973 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1974 | dev_printk(KERN_ERR, &pdev->dev, |
| 1975 | "32-bit consistent DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1976 | return rc; |
| 1977 | } |
| 1978 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1979 | return 0; |
| 1980 | } |
| 1981 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1982 | static void ahci_print_info(struct ata_host *host) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1983 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1984 | struct ahci_host_priv *hpriv = host->private_data; |
| 1985 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 1986 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1987 | u32 vers, cap, impl, speed; |
| 1988 | const char *speed_s; |
| 1989 | u16 cc; |
| 1990 | const char *scc_s; |
| 1991 | |
| 1992 | vers = readl(mmio + HOST_VERSION); |
| 1993 | cap = hpriv->cap; |
| 1994 | impl = hpriv->port_map; |
| 1995 | |
| 1996 | speed = (cap >> 20) & 0xf; |
| 1997 | if (speed == 1) |
| 1998 | speed_s = "1.5"; |
| 1999 | else if (speed == 2) |
| 2000 | speed_s = "3"; |
| 2001 | else |
| 2002 | speed_s = "?"; |
| 2003 | |
| 2004 | pci_read_config_word(pdev, 0x0a, &cc); |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2005 | if (cc == PCI_CLASS_STORAGE_IDE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2006 | scc_s = "IDE"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2007 | else if (cc == PCI_CLASS_STORAGE_SATA) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2008 | scc_s = "SATA"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2009 | else if (cc == PCI_CLASS_STORAGE_RAID) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2010 | scc_s = "RAID"; |
| 2011 | else |
| 2012 | scc_s = "unknown"; |
| 2013 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2014 | dev_printk(KERN_INFO, &pdev->dev, |
| 2015 | "AHCI %02x%02x.%02x%02x " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2016 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2017 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2018 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2019 | (vers >> 24) & 0xff, |
| 2020 | (vers >> 16) & 0xff, |
| 2021 | (vers >> 8) & 0xff, |
| 2022 | vers & 0xff, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2023 | |
| 2024 | ((cap >> 8) & 0x1f) + 1, |
| 2025 | (cap & 0x1f) + 1, |
| 2026 | speed_s, |
| 2027 | impl, |
| 2028 | scc_s); |
| 2029 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2030 | dev_printk(KERN_INFO, &pdev->dev, |
| 2031 | "flags: " |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2032 | "%s%s%s%s%s%s%s" |
| 2033 | "%s%s%s%s%s%s%s\n" |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2034 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2035 | |
| 2036 | cap & (1 << 31) ? "64bit " : "", |
| 2037 | cap & (1 << 30) ? "ncq " : "", |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2038 | cap & (1 << 29) ? "sntf " : "", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2039 | cap & (1 << 28) ? "ilck " : "", |
| 2040 | cap & (1 << 27) ? "stag " : "", |
| 2041 | cap & (1 << 26) ? "pm " : "", |
| 2042 | cap & (1 << 25) ? "led " : "", |
| 2043 | |
| 2044 | cap & (1 << 24) ? "clo " : "", |
| 2045 | cap & (1 << 19) ? "nz " : "", |
| 2046 | cap & (1 << 18) ? "only " : "", |
| 2047 | cap & (1 << 17) ? "pmp " : "", |
| 2048 | cap & (1 << 15) ? "pio " : "", |
| 2049 | cap & (1 << 14) ? "slum " : "", |
| 2050 | cap & (1 << 13) ? "part " : "" |
| 2051 | ); |
| 2052 | } |
| 2053 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame^] | 2054 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
| 2055 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't |
| 2056 | * support PMP and the 4726 either directly exports the device |
| 2057 | * attached to the first downstream port or acts as a hardware storage |
| 2058 | * controller and emulate a single ATA device (can be RAID 0/1 or some |
| 2059 | * other configuration). |
| 2060 | * |
| 2061 | * When there's no device attached to the first downstream port of the |
| 2062 | * 4726, "Config Disk" appears, which is a pseudo ATA device to |
| 2063 | * configure the 4726. However, ATA emulation of the device is very |
| 2064 | * lame. It doesn't send signature D2H Reg FIS after the initial |
| 2065 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. |
| 2066 | * |
| 2067 | * The following function works around the problem by always using |
| 2068 | * hardreset on the port and not depending on receiving signature FIS |
| 2069 | * afterward. If signature FIS isn't received soon, ATA class is |
| 2070 | * assumed without follow-up softreset. |
| 2071 | */ |
| 2072 | static void ahci_p5wdh_workaround(struct ata_host *host) |
| 2073 | { |
| 2074 | static struct dmi_system_id sysids[] = { |
| 2075 | { |
| 2076 | .ident = "P5W DH Deluxe", |
| 2077 | .matches = { |
| 2078 | DMI_MATCH(DMI_SYS_VENDOR, |
| 2079 | "ASUSTEK COMPUTER INC"), |
| 2080 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), |
| 2081 | }, |
| 2082 | }, |
| 2083 | { } |
| 2084 | }; |
| 2085 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2086 | |
| 2087 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && |
| 2088 | dmi_check_system(sysids)) { |
| 2089 | struct ata_port *ap = host->ports[1]; |
| 2090 | |
| 2091 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " |
| 2092 | "Deluxe on-board SIMG4726 workaround\n"); |
| 2093 | |
| 2094 | ap->ops = &ahci_p5wdh_ops; |
| 2095 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; |
| 2096 | } |
| 2097 | } |
| 2098 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2099 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2100 | { |
| 2101 | static int printed_version; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2102 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
| 2103 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2104 | struct device *dev = &pdev->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2105 | struct ahci_host_priv *hpriv; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2106 | struct ata_host *host; |
| 2107 | int i, rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2108 | |
| 2109 | VPRINTK("ENTER\n"); |
| 2110 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2111 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
| 2112 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2113 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2114 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2115 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2116 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2117 | rc = pcim_enable_device(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2118 | if (rc) |
| 2119 | return rc; |
| 2120 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2121 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
| 2122 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2123 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2124 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2125 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2126 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2127 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
| 2128 | if (!hpriv) |
| 2129 | return -ENOMEM; |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2130 | hpriv->flags |= (unsigned long)pi.private_data; |
| 2131 | |
| 2132 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) |
| 2133 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2134 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2135 | /* save initial config */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2136 | ahci_save_initial_config(pdev, hpriv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2137 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2138 | /* prepare host */ |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2139 | if (hpriv->cap & HOST_CAP_NCQ) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2140 | pi.flags |= ATA_FLAG_NCQ; |
| 2141 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2142 | if (hpriv->cap & HOST_CAP_PMP) |
| 2143 | pi.flags |= ATA_FLAG_PMP; |
| 2144 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2145 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
| 2146 | if (!host) |
| 2147 | return -ENOMEM; |
| 2148 | host->iomap = pcim_iomap_table(pdev); |
| 2149 | host->private_data = hpriv; |
| 2150 | |
| 2151 | for (i = 0; i < host->n_ports; i++) { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 2152 | struct ata_port *ap = host->ports[i]; |
| 2153 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2154 | |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 2155 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
| 2156 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, |
| 2157 | 0x100 + ap->port_no * 0x80, "port"); |
| 2158 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 2159 | /* standard SATA port setup */ |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2160 | if (hpriv->port_map & (1 << i)) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2161 | ap->ioaddr.cmd_addr = port_mmio; |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 2162 | |
| 2163 | /* disabled/not-implemented port */ |
| 2164 | else |
| 2165 | ap->ops = &ata_dummy_port_ops; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2166 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2167 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame^] | 2168 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
| 2169 | ahci_p5wdh_workaround(host); |
| 2170 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2171 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2172 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2173 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2174 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2175 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2176 | rc = ahci_reset_controller(host); |
| 2177 | if (rc) |
| 2178 | return rc; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2179 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2180 | ahci_init_controller(host); |
| 2181 | ahci_print_info(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2182 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2183 | pci_set_master(pdev); |
| 2184 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, |
| 2185 | &ahci_sht); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 2186 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2187 | |
| 2188 | static int __init ahci_init(void) |
| 2189 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 2190 | return pci_register_driver(&ahci_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2191 | } |
| 2192 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2193 | static void __exit ahci_exit(void) |
| 2194 | { |
| 2195 | pci_unregister_driver(&ahci_pci_driver); |
| 2196 | } |
| 2197 | |
| 2198 | |
| 2199 | MODULE_AUTHOR("Jeff Garzik"); |
| 2200 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); |
| 2201 | MODULE_LICENSE("GPL"); |
| 2202 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
Jeff Garzik | 6885433 | 2005-08-23 02:53:51 -0400 | [diff] [blame] | 2203 | MODULE_VERSION(DRV_VERSION); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2204 | |
| 2205 | module_init(ahci_init); |
| 2206 | module_exit(ahci_exit); |