blob: d36c11b73a35ca656ab04e9c5ef0492f96950b32 [file] [log] [blame]
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001/*
2 * Copyright (C) 2009 Texas Instruments.
Brian Niebuhr43abb112010-10-06 18:34:47 +05303 * Copyright (C) 2010 EF Johnson Technologies
Sandeep Paulraj358934a2009-12-16 22:02:18 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Sandeep Paulraj358934a2009-12-16 22:02:18 +000014 */
15
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/module.h>
20#include <linux/delay.h>
21#include <linux/platform_device.h>
22#include <linux/err.h>
23#include <linux/clk.h>
Matt Porter048177c2012-08-22 21:09:36 -040024#include <linux/dmaengine.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000025#include <linux/dma-mapping.h>
Murali Karicheriaae71472012-12-11 16:20:39 -050026#include <linux/of.h>
27#include <linux/of_device.h>
Murali Karicheria88e34e2014-08-01 19:40:32 +030028#include <linux/of_gpio.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000029#include <linux/spi/spi.h>
30#include <linux/spi/spi_bitbang.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000032
Arnd Bergmannec2a0832012-08-24 15:11:34 +020033#include <linux/platform_data/spi-davinci.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000034
Sandeep Paulraj358934a2009-12-16 22:02:18 +000035#define CS_DEFAULT 0xFF
36
Sandeep Paulraj358934a2009-12-16 22:02:18 +000037#define SPIFMT_PHASE_MASK BIT(16)
38#define SPIFMT_POLARITY_MASK BIT(17)
39#define SPIFMT_DISTIMER_MASK BIT(18)
40#define SPIFMT_SHIFTDIR_MASK BIT(20)
41#define SPIFMT_WAITENA_MASK BIT(21)
42#define SPIFMT_PARITYENA_MASK BIT(22)
43#define SPIFMT_ODD_PARITY_MASK BIT(23)
44#define SPIFMT_WDELAY_MASK 0x3f000000u
45#define SPIFMT_WDELAY_SHIFT 24
Brian Niebuhr7fe00922010-08-13 13:27:23 +053046#define SPIFMT_PRESCALE_SHIFT 8
Sandeep Paulraj358934a2009-12-16 22:02:18 +000047
Sandeep Paulraj358934a2009-12-16 22:02:18 +000048/* SPIPC0 */
49#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
50#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
51#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
52#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000053
54#define SPIINT_MASKALL 0x0101035F
Brian Niebuhre0d205e2010-09-02 16:52:06 +053055#define SPIINT_MASKINT 0x0000015F
56#define SPI_INTLVL_1 0x000001FF
57#define SPI_INTLVL_0 0x00000000
Sandeep Paulraj358934a2009-12-16 22:02:18 +000058
Brian Niebuhrcfbc5d12010-08-12 12:27:33 +053059/* SPIDAT1 (upper 16 bit defines) */
60#define SPIDAT1_CSHOLD_MASK BIT(12)
Murali Karicheri365a7bb2014-09-16 14:25:05 +030061#define SPIDAT1_WDEL BIT(10)
Brian Niebuhrcfbc5d12010-08-12 12:27:33 +053062
63/* SPIGCR1 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000064#define SPIGCR1_CLKMOD_MASK BIT(1)
65#define SPIGCR1_MASTER_MASK BIT(0)
Brian Niebuhr3f27b572010-10-06 18:25:43 +053066#define SPIGCR1_POWERDOWN_MASK BIT(8)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000067#define SPIGCR1_LOOPBACK_MASK BIT(16)
Sekhar Nori8e206f12010-08-20 16:20:49 +053068#define SPIGCR1_SPIENA_MASK BIT(24)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000069
70/* SPIBUF */
71#define SPIBUF_TXFULL_MASK BIT(29)
72#define SPIBUF_RXEMPTY_MASK BIT(31)
73
Brian Niebuhr7abbf232010-08-19 15:07:38 +053074/* SPIDELAY */
75#define SPIDELAY_C2TDELAY_SHIFT 24
76#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
77#define SPIDELAY_T2CDELAY_SHIFT 16
78#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
79#define SPIDELAY_T2EDELAY_SHIFT 8
80#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
81#define SPIDELAY_C2EDELAY_SHIFT 0
82#define SPIDELAY_C2EDELAY_MASK 0xFF
83
Sandeep Paulraj358934a2009-12-16 22:02:18 +000084/* Error Masks */
85#define SPIFLG_DLEN_ERR_MASK BIT(0)
86#define SPIFLG_TIMEOUT_MASK BIT(1)
87#define SPIFLG_PARERR_MASK BIT(2)
88#define SPIFLG_DESYNC_MASK BIT(3)
89#define SPIFLG_BITERR_MASK BIT(4)
90#define SPIFLG_OVRRUN_MASK BIT(6)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000091#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
Brian Niebuhr839c9962010-08-23 16:39:19 +053092#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
93 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
94 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
95 | SPIFLG_OVRRUN_MASK)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000096
Sandeep Paulraj358934a2009-12-16 22:02:18 +000097#define SPIINT_DMA_REQ_EN BIT(16)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000098
Sandeep Paulraj358934a2009-12-16 22:02:18 +000099/* SPI Controller registers */
100#define SPIGCR0 0x00
101#define SPIGCR1 0x04
102#define SPIINT 0x08
103#define SPILVL 0x0c
104#define SPIFLG 0x10
105#define SPIPC0 0x14
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000106#define SPIDAT1 0x3c
107#define SPIBUF 0x40
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000108#define SPIDELAY 0x48
109#define SPIDEF 0x4c
110#define SPIFMT0 0x50
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000111
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000112/* SPI Controller driver's private data. */
113struct davinci_spi {
114 struct spi_bitbang bitbang;
115 struct clk *clk;
116
117 u8 version;
118 resource_size_t pbase;
119 void __iomem *base;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530120 u32 irq;
121 struct completion done;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000122
123 const void *tx;
124 void *rx;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530125 int rcount;
126 int wcount;
Matt Porter048177c2012-08-22 21:09:36 -0400127
128 struct dma_chan *dma_rx;
129 struct dma_chan *dma_tx;
Matt Porter048177c2012-08-22 21:09:36 -0400130
Murali Karicheriaae71472012-12-11 16:20:39 -0500131 struct davinci_spi_platform_data pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000132
133 void (*get_rx)(u32 rx_data, struct davinci_spi *);
134 u32 (*get_tx)(struct davinci_spi *);
135
Murali Karicheri7480e752014-07-31 20:33:14 +0300136 u8 *bytes_per_word;
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500137
138 u8 prescaler_limit;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000139};
140
Brian Niebuhr53a31b02010-08-16 15:05:51 +0530141static struct davinci_spi_config davinci_spi_default_cfg;
142
Sekhar Nori212d4b62010-10-11 10:41:39 +0530143static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000144{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530145 if (dspi->rx) {
146 u8 *rx = dspi->rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530147 *rx++ = (u8)data;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530148 dspi->rx = rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530149 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000150}
151
Sekhar Nori212d4b62010-10-11 10:41:39 +0530152static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000153{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530154 if (dspi->rx) {
155 u16 *rx = dspi->rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530156 *rx++ = (u16)data;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530157 dspi->rx = rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530158 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000159}
160
Sekhar Nori212d4b62010-10-11 10:41:39 +0530161static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000162{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530163 u32 data = 0;
Jingoo Han859c3372014-09-02 11:48:00 +0900164
Sekhar Nori212d4b62010-10-11 10:41:39 +0530165 if (dspi->tx) {
166 const u8 *tx = dspi->tx;
Jingoo Han859c3372014-09-02 11:48:00 +0900167
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530168 data = *tx++;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530169 dspi->tx = tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530170 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000171 return data;
172}
173
Sekhar Nori212d4b62010-10-11 10:41:39 +0530174static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000175{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530176 u32 data = 0;
Jingoo Han859c3372014-09-02 11:48:00 +0900177
Sekhar Nori212d4b62010-10-11 10:41:39 +0530178 if (dspi->tx) {
179 const u16 *tx = dspi->tx;
Jingoo Han859c3372014-09-02 11:48:00 +0900180
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530181 data = *tx++;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530182 dspi->tx = tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530183 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000184 return data;
185}
186
187static inline void set_io_bits(void __iomem *addr, u32 bits)
188{
189 u32 v = ioread32(addr);
190
191 v |= bits;
192 iowrite32(v, addr);
193}
194
195static inline void clear_io_bits(void __iomem *addr, u32 bits)
196{
197 u32 v = ioread32(addr);
198
199 v &= ~bits;
200 iowrite32(v, addr);
201}
202
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000203/*
204 * Interface to control the chip select signal
205 */
206static void davinci_spi_chipselect(struct spi_device *spi, int value)
207{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530208 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000209 struct davinci_spi_platform_data *pdata;
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300210 struct davinci_spi_config *spicfg = spi->controller_data;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530211 u8 chip_sel = spi->chip_select;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530212 u16 spidat1 = CS_DEFAULT;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000213
Sekhar Nori212d4b62010-10-11 10:41:39 +0530214 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500215 pdata = &dspi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000216
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300217 /* program delay transfers if tx_delay is non zero */
218 if (spicfg->wdelay)
219 spidat1 |= SPIDAT1_WDEL;
220
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000221 /*
222 * Board specific chip select logic decides the polarity and cs
223 * line for the controller
224 */
Luis de Bethencourt8cae0422015-10-16 16:22:07 +0100225 if (spi->cs_gpio >= 0) {
Brian Niebuhr23853972010-08-13 10:57:44 +0530226 if (value == BITBANG_CS_ACTIVE)
Luis de Bethencourt8cae0422015-10-16 16:22:07 +0100227 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH);
Brian Niebuhr23853972010-08-13 10:57:44 +0530228 else
Luis de Bethencourt8cae0422015-10-16 16:22:07 +0100229 gpio_set_value(spi->cs_gpio,
230 !(spi->mode & SPI_CS_HIGH));
Brian Niebuhr23853972010-08-13 10:57:44 +0530231 } else {
232 if (value == BITBANG_CS_ACTIVE) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530233 spidat1 |= SPIDAT1_CSHOLD_MASK;
234 spidat1 &= ~(0x1 << chip_sel);
Brian Niebuhr23853972010-08-13 10:57:44 +0530235 }
Brian Niebuhr23853972010-08-13 10:57:44 +0530236 }
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300237
238 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000239}
240
241/**
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530242 * davinci_spi_get_prescale - Calculates the correct prescale value
243 * @maxspeed_hz: the maximum rate the SPI clock can run at
244 *
245 * This function calculates the prescale value that generates a clock rate
246 * less than or equal to the specified maximum.
247 *
Franklin S Cooper Jrbba732d2015-07-22 07:32:21 -0500248 * Returns: calculated prescale value for easy programming into SPI registers
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530249 * or negative error number if valid prescalar cannot be updated.
250 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530251static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530252 u32 max_speed_hz)
253{
254 int ret;
255
Franklin S Cooper Jrbba732d2015-07-22 07:32:21 -0500256 /* Subtract 1 to match what will be programmed into SPI register. */
257 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530258
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500259 if (ret < dspi->prescaler_limit || ret > 255)
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530260 return -EINVAL;
261
Franklin S Cooper Jrbba732d2015-07-22 07:32:21 -0500262 return ret;
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530263}
264
265/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000266 * davinci_spi_setup_transfer - This functions will determine transfer method
267 * @spi: spi device on which data transfer to be done
268 * @t: spi transfer in which transfer info is filled
269 *
270 * This function determines data transfer method (8/16/32 bit transfer).
271 * It will also set the SPI Clock Control register according to
272 * SPI slave device freq.
273 */
274static int davinci_spi_setup_transfer(struct spi_device *spi,
275 struct spi_transfer *t)
276{
277
Sekhar Nori212d4b62010-10-11 10:41:39 +0530278 struct davinci_spi *dspi;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530279 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000280 u8 bits_per_word = 0;
Sachin Kamat32ea3942013-09-11 16:05:04 +0530281 u32 hz = 0, spifmt = 0;
282 int prescale;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000283
Sekhar Nori212d4b62010-10-11 10:41:39 +0530284 dspi = spi_master_get_devdata(spi->master);
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300285 spicfg = spi->controller_data;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530286 if (!spicfg)
287 spicfg = &davinci_spi_default_cfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000288
289 if (t) {
290 bits_per_word = t->bits_per_word;
291 hz = t->speed_hz;
292 }
293
294 /* if bits_per_word is not set then set it default */
295 if (!bits_per_word)
296 bits_per_word = spi->bits_per_word;
297
298 /*
299 * Assign function pointer to appropriate transfer method
300 * 8bit, 16bit or 32bit transfer
301 */
Stephen Warren24778be2013-05-21 20:36:35 -0600302 if (bits_per_word <= 8) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530303 dspi->get_rx = davinci_spi_rx_buf_u8;
304 dspi->get_tx = davinci_spi_tx_buf_u8;
305 dspi->bytes_per_word[spi->chip_select] = 1;
Stephen Warren24778be2013-05-21 20:36:35 -0600306 } else {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530307 dspi->get_rx = davinci_spi_rx_buf_u16;
308 dspi->get_tx = davinci_spi_tx_buf_u16;
309 dspi->bytes_per_word[spi->chip_select] = 2;
Stephen Warren24778be2013-05-21 20:36:35 -0600310 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000311
312 if (!hz)
313 hz = spi->max_speed_hz;
314
Brian Niebuhr25f33512010-08-19 12:15:22 +0530315 /* Set up SPIFMTn register, unique to this chipselect. */
316
Sekhar Nori212d4b62010-10-11 10:41:39 +0530317 prescale = davinci_spi_get_prescale(dspi, hz);
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530318 if (prescale < 0)
319 return prescale;
320
Brian Niebuhr25f33512010-08-19 12:15:22 +0530321 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000322
Brian Niebuhr25f33512010-08-19 12:15:22 +0530323 if (spi->mode & SPI_LSB_FIRST)
324 spifmt |= SPIFMT_SHIFTDIR_MASK;
325
326 if (spi->mode & SPI_CPOL)
327 spifmt |= SPIFMT_POLARITY_MASK;
328
329 if (!(spi->mode & SPI_CPHA))
330 spifmt |= SPIFMT_PHASE_MASK;
331
332 /*
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300333 * Assume wdelay is used only on SPI peripherals that has this field
334 * in SPIFMTn register and when it's configured from board file or DT.
335 */
336 if (spicfg->wdelay)
337 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
338 & SPIFMT_WDELAY_MASK);
339
340 /*
Brian Niebuhr25f33512010-08-19 12:15:22 +0530341 * Version 1 hardware supports two basic SPI modes:
342 * - Standard SPI mode uses 4 pins, with chipselect
343 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
344 * (distinct from SPI_3WIRE, with just one data wire;
345 * or similar variants without MOSI or without MISO)
346 *
347 * Version 2 hardware supports an optional handshaking signal,
348 * so it can support two more modes:
349 * - 5 pin SPI variant is standard SPI plus SPI_READY
350 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
351 */
352
Sekhar Nori212d4b62010-10-11 10:41:39 +0530353 if (dspi->version == SPI_VERSION_2) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530354
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530355 u32 delay = 0;
356
Brian Niebuhr25f33512010-08-19 12:15:22 +0530357 if (spicfg->odd_parity)
358 spifmt |= SPIFMT_ODD_PARITY_MASK;
359
360 if (spicfg->parity_enable)
361 spifmt |= SPIFMT_PARITYENA_MASK;
362
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530363 if (spicfg->timer_disable) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530364 spifmt |= SPIFMT_DISTIMER_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530365 } else {
366 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
367 & SPIDELAY_C2TDELAY_MASK;
368 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
369 & SPIDELAY_T2CDELAY_MASK;
370 }
Brian Niebuhr25f33512010-08-19 12:15:22 +0530371
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530372 if (spi->mode & SPI_READY) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530373 spifmt |= SPIFMT_WAITENA_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530374 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
375 & SPIDELAY_T2EDELAY_MASK;
376 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
377 & SPIDELAY_C2EDELAY_MASK;
378 }
379
Sekhar Nori212d4b62010-10-11 10:41:39 +0530380 iowrite32(delay, dspi->base + SPIDELAY);
Brian Niebuhr25f33512010-08-19 12:15:22 +0530381 }
382
Sekhar Nori212d4b62010-10-11 10:41:39 +0530383 iowrite32(spifmt, dspi->base + SPIFMT0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000384
385 return 0;
386}
387
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300388static int davinci_spi_of_setup(struct spi_device *spi)
389{
390 struct davinci_spi_config *spicfg = spi->controller_data;
391 struct device_node *np = spi->dev.of_node;
392 u32 prop;
393
394 if (spicfg == NULL && np) {
395 spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
396 if (!spicfg)
397 return -ENOMEM;
398 *spicfg = davinci_spi_default_cfg;
399 /* override with dt configured values */
400 if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
401 spicfg->wdelay = (u8)prop;
402 spi->controller_data = spicfg;
403 }
404
405 return 0;
406}
407
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000408/**
409 * davinci_spi_setup - This functions will set default transfer method
410 * @spi: spi device on which data transfer to be done
411 *
412 * This functions sets the default transfer method.
413 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000414static int davinci_spi_setup(struct spi_device *spi)
415{
Brian Niebuhrb23a5d42010-09-24 18:53:32 +0530416 int retval = 0;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530417 struct davinci_spi *dspi;
Brian Niebuhrbe884712010-09-03 12:15:28 +0530418 struct davinci_spi_platform_data *pdata;
Murali Karicheria88e34e2014-08-01 19:40:32 +0300419 struct spi_master *master = spi->master;
420 struct device_node *np = spi->dev.of_node;
421 bool internal_cs = true;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000422
Sekhar Nori212d4b62010-10-11 10:41:39 +0530423 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500424 pdata = &dspi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000425
Brian Niebuhrbe884712010-09-03 12:15:28 +0530426 if (!(spi->mode & SPI_NO_CS)) {
Murali Karicheria88e34e2014-08-01 19:40:32 +0300427 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
Grygorii Strashko8936dec2014-09-12 17:54:00 +0300428 retval = gpio_direction_output(
429 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
Murali Karicheria88e34e2014-08-01 19:40:32 +0300430 internal_cs = false;
431 } else if (pdata->chip_sel &&
432 spi->chip_select < pdata->num_chipselect &&
433 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300434 spi->cs_gpio = pdata->chip_sel[spi->chip_select];
Grygorii Strashko8936dec2014-09-12 17:54:00 +0300435 retval = gpio_direction_output(
436 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
Murali Karicheria88e34e2014-08-01 19:40:32 +0300437 internal_cs = false;
438 }
Brian Niebuhrbe884712010-09-03 12:15:28 +0530439
Grygorii Strashko3f2dad92014-08-21 18:25:05 +0300440 if (retval) {
441 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
442 spi->cs_gpio, retval);
443 return retval;
444 }
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300445
Grygorii Strashko3f2dad92014-08-21 18:25:05 +0300446 if (internal_cs)
447 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
448 }
Murali Karicheria88e34e2014-08-01 19:40:32 +0300449
Brian Niebuhrbe884712010-09-03 12:15:28 +0530450 if (spi->mode & SPI_READY)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530451 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530452
453 if (spi->mode & SPI_LOOP)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530454 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530455 else
Sekhar Nori212d4b62010-10-11 10:41:39 +0530456 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530457
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300458 return davinci_spi_of_setup(spi);
459}
460
461static void davinci_spi_cleanup(struct spi_device *spi)
462{
463 struct davinci_spi_config *spicfg = spi->controller_data;
464
465 spi->controller_data = NULL;
466 if (spi->dev.of_node)
467 kfree(spicfg);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000468}
469
Sekhar Nori212d4b62010-10-11 10:41:39 +0530470static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000471{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530472 struct device *sdev = dspi->bitbang.master->dev.parent;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000473
474 if (int_status & SPIFLG_TIMEOUT_MASK) {
Sekhar Nori21c015b2015-12-10 21:59:05 +0530475 dev_err(sdev, "SPI Time-out Error\n");
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000476 return -ETIMEDOUT;
477 }
478 if (int_status & SPIFLG_DESYNC_MASK) {
Sekhar Nori21c015b2015-12-10 21:59:05 +0530479 dev_err(sdev, "SPI Desynchronization Error\n");
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000480 return -EIO;
481 }
482 if (int_status & SPIFLG_BITERR_MASK) {
Sekhar Nori21c015b2015-12-10 21:59:05 +0530483 dev_err(sdev, "SPI Bit error\n");
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000484 return -EIO;
485 }
486
Sekhar Nori212d4b62010-10-11 10:41:39 +0530487 if (dspi->version == SPI_VERSION_2) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000488 if (int_status & SPIFLG_DLEN_ERR_MASK) {
Sekhar Nori21c015b2015-12-10 21:59:05 +0530489 dev_err(sdev, "SPI Data Length Error\n");
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000490 return -EIO;
491 }
492 if (int_status & SPIFLG_PARERR_MASK) {
Sekhar Nori21c015b2015-12-10 21:59:05 +0530493 dev_err(sdev, "SPI Parity Error\n");
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000494 return -EIO;
495 }
496 if (int_status & SPIFLG_OVRRUN_MASK) {
Sekhar Nori21c015b2015-12-10 21:59:05 +0530497 dev_err(sdev, "SPI Data Overrun error\n");
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000498 return -EIO;
499 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000500 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
Sekhar Nori21c015b2015-12-10 21:59:05 +0530501 dev_err(sdev, "SPI Buffer Init Active\n");
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000502 return -EBUSY;
503 }
504 }
505
506 return 0;
507}
508
509/**
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530510 * davinci_spi_process_events - check for and handle any SPI controller events
Sekhar Nori212d4b62010-10-11 10:41:39 +0530511 * @dspi: the controller data
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530512 *
513 * This function will check the SPIFLG register and handle any events that are
514 * detected there
515 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530516static int davinci_spi_process_events(struct davinci_spi *dspi)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530517{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530518 u32 buf, status, errors = 0, spidat1;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530519
Sekhar Nori212d4b62010-10-11 10:41:39 +0530520 buf = ioread32(dspi->base + SPIBUF);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530521
Sekhar Nori212d4b62010-10-11 10:41:39 +0530522 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
523 dspi->get_rx(buf & 0xFFFF, dspi);
524 dspi->rcount--;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530525 }
526
Sekhar Nori212d4b62010-10-11 10:41:39 +0530527 status = ioread32(dspi->base + SPIFLG);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530528
529 if (unlikely(status & SPIFLG_ERROR_MASK)) {
530 errors = status & SPIFLG_ERROR_MASK;
531 goto out;
532 }
533
Sekhar Nori212d4b62010-10-11 10:41:39 +0530534 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
535 spidat1 = ioread32(dspi->base + SPIDAT1);
536 dspi->wcount--;
537 spidat1 &= ~0xFFFF;
538 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
539 iowrite32(spidat1, dspi->base + SPIDAT1);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530540 }
541
542out:
543 return errors;
544}
545
Matt Porter048177c2012-08-22 21:09:36 -0400546static void davinci_spi_dma_rx_callback(void *data)
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530547{
Matt Porter048177c2012-08-22 21:09:36 -0400548 struct davinci_spi *dspi = (struct davinci_spi *)data;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530549
Matt Porter048177c2012-08-22 21:09:36 -0400550 dspi->rcount = 0;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530551
Matt Porter048177c2012-08-22 21:09:36 -0400552 if (!dspi->wcount && !dspi->rcount)
553 complete(&dspi->done);
554}
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530555
Matt Porter048177c2012-08-22 21:09:36 -0400556static void davinci_spi_dma_tx_callback(void *data)
557{
558 struct davinci_spi *dspi = (struct davinci_spi *)data;
559
560 dspi->wcount = 0;
561
562 if (!dspi->wcount && !dspi->rcount)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530563 complete(&dspi->done);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530564}
565
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530566/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000567 * davinci_spi_bufs - functions which will handle transfer data
568 * @spi: spi device on which data transfer to be done
569 * @t: spi transfer in which transfer info is filled
570 *
571 * This function will put data to be transferred into data register
572 * of SPI controller and then wait until the completion will be marked
573 * by the IRQ Handler.
574 */
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530575static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000576{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530577 struct davinci_spi *dspi;
Matt Porter048177c2012-08-22 21:09:36 -0400578 int data_type, ret = -ENOMEM;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530579 u32 tx_data, spidat1;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530580 u32 errors = 0;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530581 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000582 struct davinci_spi_platform_data *pdata;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530583 unsigned uninitialized_var(rx_buf_count);
Matt Porter048177c2012-08-22 21:09:36 -0400584 void *dummy_buf = NULL;
585 struct scatterlist sg_rx, sg_tx;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000586
Sekhar Nori212d4b62010-10-11 10:41:39 +0530587 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500588 pdata = &dspi->pdata;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530589 spicfg = (struct davinci_spi_config *)spi->controller_data;
590 if (!spicfg)
591 spicfg = &davinci_spi_default_cfg;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530592
593 /* convert len to words based on bits_per_word */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530594 data_type = dspi->bytes_per_word[spi->chip_select];
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000595
Sekhar Nori212d4b62010-10-11 10:41:39 +0530596 dspi->tx = t->tx_buf;
597 dspi->rx = t->rx_buf;
598 dspi->wcount = t->len / data_type;
599 dspi->rcount = dspi->wcount;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530600
Sekhar Nori212d4b62010-10-11 10:41:39 +0530601 spidat1 = ioread32(dspi->base + SPIDAT1);
Brian Niebuhr839c9962010-08-23 16:39:19 +0530602
Sekhar Nori212d4b62010-10-11 10:41:39 +0530603 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
604 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000605
Wolfram Sang16735d02013-11-14 14:32:02 -0800606 reinit_completion(&dspi->done);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530607
608 if (spicfg->io_type == SPI_IO_TYPE_INTR)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530609 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530610
611 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
612 /* start the transfer */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530613 dspi->wcount--;
614 tx_data = dspi->get_tx(dspi);
615 spidat1 &= 0xFFFF0000;
616 spidat1 |= tx_data & 0xFFFF;
617 iowrite32(spidat1, dspi->base + SPIDAT1);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530618 } else {
Matt Porter048177c2012-08-22 21:09:36 -0400619 struct dma_slave_config dma_rx_conf = {
620 .direction = DMA_DEV_TO_MEM,
621 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
622 .src_addr_width = data_type,
623 .src_maxburst = 1,
624 };
625 struct dma_slave_config dma_tx_conf = {
626 .direction = DMA_MEM_TO_DEV,
627 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
628 .dst_addr_width = data_type,
629 .dst_maxburst = 1,
630 };
631 struct dma_async_tx_descriptor *rxdesc;
632 struct dma_async_tx_descriptor *txdesc;
633 void *buf;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530634
Matt Porter048177c2012-08-22 21:09:36 -0400635 dummy_buf = kzalloc(t->len, GFP_KERNEL);
636 if (!dummy_buf)
637 goto err_alloc_dummy_buf;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530638
Matt Porter048177c2012-08-22 21:09:36 -0400639 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
640 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530641
Matt Porter048177c2012-08-22 21:09:36 -0400642 sg_init_table(&sg_rx, 1);
643 if (!t->rx_buf)
644 buf = dummy_buf;
Michael Williamsonb1178b22011-03-14 11:49:02 -0400645 else
Matt Porter048177c2012-08-22 21:09:36 -0400646 buf = t->rx_buf;
647 t->rx_dma = dma_map_single(&spi->dev, buf,
648 t->len, DMA_FROM_DEVICE);
649 if (!t->rx_dma) {
650 ret = -EFAULT;
651 goto err_rx_map;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530652 }
Matt Porter048177c2012-08-22 21:09:36 -0400653 sg_dma_address(&sg_rx) = t->rx_dma;
654 sg_dma_len(&sg_rx) = t->len;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530655
Matt Porter048177c2012-08-22 21:09:36 -0400656 sg_init_table(&sg_tx, 1);
657 if (!t->tx_buf)
658 buf = dummy_buf;
659 else
660 buf = (void *)t->tx_buf;
661 t->tx_dma = dma_map_single(&spi->dev, buf,
Christian Eggers89c66ee2013-07-29 20:54:09 +0200662 t->len, DMA_TO_DEVICE);
Matt Porter048177c2012-08-22 21:09:36 -0400663 if (!t->tx_dma) {
664 ret = -EFAULT;
665 goto err_tx_map;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530666 }
Matt Porter048177c2012-08-22 21:09:36 -0400667 sg_dma_address(&sg_tx) = t->tx_dma;
668 sg_dma_len(&sg_tx) = t->len;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530669
Matt Porter048177c2012-08-22 21:09:36 -0400670 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
671 &sg_rx, 1, DMA_DEV_TO_MEM,
672 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
673 if (!rxdesc)
674 goto err_desc;
675
676 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
677 &sg_tx, 1, DMA_MEM_TO_DEV,
678 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
679 if (!txdesc)
680 goto err_desc;
681
682 rxdesc->callback = davinci_spi_dma_rx_callback;
683 rxdesc->callback_param = (void *)dspi;
684 txdesc->callback = davinci_spi_dma_tx_callback;
685 txdesc->callback_param = (void *)dspi;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530686
687 if (pdata->cshold_bug)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530688 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530689
Matt Porter048177c2012-08-22 21:09:36 -0400690 dmaengine_submit(rxdesc);
691 dmaengine_submit(txdesc);
692
693 dma_async_issue_pending(dspi->dma_rx);
694 dma_async_issue_pending(dspi->dma_tx);
695
Sekhar Nori212d4b62010-10-11 10:41:39 +0530696 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530697 }
Brian Niebuhrcf90fe72010-08-20 17:02:49 +0530698
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530699 /* Wait for the transfer to complete */
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530700 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
Sekhar Nori7f3ac712015-12-10 21:59:04 +0530701 if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
702 errors = SPIFLG_TIMEOUT_MASK;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530703 } else {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530704 while (dspi->rcount > 0 || dspi->wcount > 0) {
705 errors = davinci_spi_process_events(dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530706 if (errors)
707 break;
708 cpu_relax();
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000709 }
710 }
711
Sekhar Nori212d4b62010-10-11 10:41:39 +0530712 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530713 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530714 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
Matt Porter048177c2012-08-22 21:09:36 -0400715
716 dma_unmap_single(&spi->dev, t->rx_dma,
717 t->len, DMA_FROM_DEVICE);
718 dma_unmap_single(&spi->dev, t->tx_dma,
719 t->len, DMA_TO_DEVICE);
720 kfree(dummy_buf);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530721 }
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530722
Sekhar Nori212d4b62010-10-11 10:41:39 +0530723 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
724 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
Brian Niebuhr3f27b572010-10-06 18:25:43 +0530725
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000726 /*
727 * Check for bit error, desync error,parity error,timeout error and
728 * receive overflow errors
729 */
Brian Niebuhr839c9962010-08-23 16:39:19 +0530730 if (errors) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530731 ret = davinci_spi_check_error(dspi, errors);
Brian Niebuhr839c9962010-08-23 16:39:19 +0530732 WARN(!ret, "%s: error reported but no error found!\n",
733 dev_name(&spi->dev));
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000734 return ret;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530735 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000736
Sekhar Nori212d4b62010-10-11 10:41:39 +0530737 if (dspi->rcount != 0 || dspi->wcount != 0) {
Matt Porter048177c2012-08-22 21:09:36 -0400738 dev_err(&spi->dev, "SPI data transfer error\n");
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530739 return -EIO;
740 }
741
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000742 return t->len;
Matt Porter048177c2012-08-22 21:09:36 -0400743
744err_desc:
745 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
746err_tx_map:
747 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
748err_rx_map:
749 kfree(dummy_buf);
750err_alloc_dummy_buf:
751 return ret;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000752}
753
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530754/**
Murali Karicheri32310aa2012-12-21 15:13:26 -0500755 * dummy_thread_fn - dummy thread function
756 * @irq: IRQ number for this SPI Master
757 * @context_data: structure for SPI Master controller davinci_spi
758 *
759 * This is to satisfy the request_threaded_irq() API so that the irq
760 * handler is called in interrupt context.
761 */
762static irqreturn_t dummy_thread_fn(s32 irq, void *data)
763{
764 return IRQ_HANDLED;
765}
766
767/**
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530768 * davinci_spi_irq - Interrupt handler for SPI Master Controller
769 * @irq: IRQ number for this SPI Master
770 * @context_data: structure for SPI Master controller davinci_spi
771 *
772 * ISR will determine that interrupt arrives either for READ or WRITE command.
773 * According to command it will do the appropriate action. It will check
774 * transfer length and if it is not zero then dispatch transfer command again.
775 * If transfer length is zero then it will indicate the COMPLETION so that
776 * davinci_spi_bufs function can go ahead.
777 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530778static irqreturn_t davinci_spi_irq(s32 irq, void *data)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530779{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530780 struct davinci_spi *dspi = data;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530781 int status;
782
Sekhar Nori212d4b62010-10-11 10:41:39 +0530783 status = davinci_spi_process_events(dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530784 if (unlikely(status != 0))
Sekhar Nori212d4b62010-10-11 10:41:39 +0530785 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530786
Sekhar Nori212d4b62010-10-11 10:41:39 +0530787 if ((!dspi->rcount && !dspi->wcount) || status)
788 complete(&dspi->done);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530789
790 return IRQ_HANDLED;
791}
792
Sekhar Nori212d4b62010-10-11 10:41:39 +0530793static int davinci_spi_request_dma(struct davinci_spi *dspi)
Sekhar Nori903ca252010-10-01 14:51:40 +0530794{
Matt Porter048177c2012-08-22 21:09:36 -0400795 struct device *sdev = dspi->bitbang.master->dev.parent;
Sekhar Nori903ca252010-10-01 14:51:40 +0530796
Peter Ujfalusife5fd252016-04-29 16:10:22 +0300797 dspi->dma_rx = dma_request_chan(sdev, "rx");
798 if (IS_ERR(dspi->dma_rx))
799 return PTR_ERR(dspi->dma_rx);
Matt Porter048177c2012-08-22 21:09:36 -0400800
Peter Ujfalusife5fd252016-04-29 16:10:22 +0300801 dspi->dma_tx = dma_request_chan(sdev, "tx");
802 if (IS_ERR(dspi->dma_tx)) {
803 dma_release_channel(dspi->dma_rx);
804 return PTR_ERR(dspi->dma_tx);
Sekhar Nori903ca252010-10-01 14:51:40 +0530805 }
806
807 return 0;
808}
809
Murali Karicheriaae71472012-12-11 16:20:39 -0500810#if defined(CONFIG_OF)
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500811
812/* OF SPI data structure */
813struct davinci_spi_of_data {
814 u8 version;
815 u8 prescaler_limit;
816};
817
818static const struct davinci_spi_of_data dm6441_spi_data = {
819 .version = SPI_VERSION_1,
820 .prescaler_limit = 2,
821};
822
823static const struct davinci_spi_of_data da830_spi_data = {
824 .version = SPI_VERSION_2,
825 .prescaler_limit = 2,
826};
827
828static const struct davinci_spi_of_data keystone_spi_data = {
829 .version = SPI_VERSION_1,
830 .prescaler_limit = 0,
831};
832
Murali Karicheriaae71472012-12-11 16:20:39 -0500833static const struct of_device_id davinci_spi_of_match[] = {
834 {
Manjunathappa, Prakash804413f2013-04-03 19:39:06 +0530835 .compatible = "ti,dm6441-spi",
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500836 .data = &dm6441_spi_data,
Murali Karicheriaae71472012-12-11 16:20:39 -0500837 },
838 {
Manjunathappa, Prakash804413f2013-04-03 19:39:06 +0530839 .compatible = "ti,da830-spi",
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500840 .data = &da830_spi_data,
841 },
842 {
843 .compatible = "ti,keystone-spi",
844 .data = &keystone_spi_data,
Murali Karicheriaae71472012-12-11 16:20:39 -0500845 },
846 { },
847};
Manjunathappa, Prakash0d2d0cc2013-02-25 16:14:07 +0530848MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
Murali Karicheriaae71472012-12-11 16:20:39 -0500849
850/**
851 * spi_davinci_get_pdata - Get platform data from DTS binding
852 * @pdev: ptr to platform data
853 * @dspi: ptr to driver data
854 *
855 * Parses and populates pdata in dspi from device tree bindings.
856 *
857 * NOTE: Not all platform data params are supported currently.
858 */
859static int spi_davinci_get_pdata(struct platform_device *pdev,
860 struct davinci_spi *dspi)
861{
862 struct device_node *node = pdev->dev.of_node;
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500863 struct davinci_spi_of_data *spi_data;
Murali Karicheriaae71472012-12-11 16:20:39 -0500864 struct davinci_spi_platform_data *pdata;
865 unsigned int num_cs, intr_line = 0;
866 const struct of_device_id *match;
867
868 pdata = &dspi->pdata;
869
Axel Linb53b34f2014-02-06 11:45:08 +0800870 match = of_match_device(davinci_spi_of_match, &pdev->dev);
Murali Karicheriaae71472012-12-11 16:20:39 -0500871 if (!match)
872 return -ENODEV;
873
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500874 spi_data = (struct davinci_spi_of_data *)match->data;
Murali Karicheriaae71472012-12-11 16:20:39 -0500875
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500876 pdata->version = spi_data->version;
877 pdata->prescaler_limit = spi_data->prescaler_limit;
Murali Karicheriaae71472012-12-11 16:20:39 -0500878 /*
879 * default num_cs is 1 and all chipsel are internal to the chip
Murali Karicheria88e34e2014-08-01 19:40:32 +0300880 * indicated by chip_sel being NULL or cs_gpios being NULL or
881 * set to -ENOENT. num-cs includes internal as well as gpios.
Murali Karicheriaae71472012-12-11 16:20:39 -0500882 * indicated by chip_sel being NULL. GPIO based CS is not
883 * supported yet in DT bindings.
884 */
885 num_cs = 1;
886 of_property_read_u32(node, "num-cs", &num_cs);
887 pdata->num_chipselect = num_cs;
888 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
889 pdata->intr_line = intr_line;
890 return 0;
891}
892#else
Murali Karicheriaae71472012-12-11 16:20:39 -0500893static struct davinci_spi_platform_data
894 *spi_davinci_get_pdata(struct platform_device *pdev,
895 struct davinci_spi *dspi)
896{
897 return -ENODEV;
898}
899#endif
900
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000901/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000902 * davinci_spi_probe - probe function for SPI Master Controller
903 * @pdev: platform_device structure which contains plateform specific data
Brian Niebuhr035540f2010-10-06 18:32:40 +0530904 *
905 * According to Linux Device Model this function will be invoked by Linux
906 * with platform_device struct which contains the device specific info.
907 * This function will map the SPI controller's memory, register IRQ,
908 * Reset SPI controller and setting its registers to default value.
909 * It will invoke spi_bitbang_start to create work queue so that client driver
910 * can register transfer method to work queue.
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000911 */
Grant Likelyfd4a3192012-12-07 16:57:14 +0000912static int davinci_spi_probe(struct platform_device *pdev)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000913{
914 struct spi_master *master;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530915 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000916 struct davinci_spi_platform_data *pdata;
Jingoo Han5b3bb592013-12-09 19:12:03 +0900917 struct resource *r;
Grygorii Strashkoc0600142014-08-01 19:40:33 +0300918 int ret = 0;
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530919 u32 spipc0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000920
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000921 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
922 if (master == NULL) {
923 ret = -ENOMEM;
924 goto err;
925 }
926
Jingoo Han24b5a822013-05-23 19:20:40 +0900927 platform_set_drvdata(pdev, master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000928
Sekhar Nori212d4b62010-10-11 10:41:39 +0530929 dspi = spi_master_get_devdata(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000930
Jingoo Han8074cf02013-07-30 16:58:59 +0900931 if (dev_get_platdata(&pdev->dev)) {
932 pdata = dev_get_platdata(&pdev->dev);
Murali Karicheriaae71472012-12-11 16:20:39 -0500933 dspi->pdata = *pdata;
934 } else {
935 /* update dspi pdata with that from the DT */
936 ret = spi_davinci_get_pdata(pdev, dspi);
937 if (ret < 0)
938 goto free_master;
939 }
940
941 /* pdata in dspi is now updated and point pdata to that */
942 pdata = &dspi->pdata;
943
Murali Karicheri7480e752014-07-31 20:33:14 +0300944 dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
945 sizeof(*dspi->bytes_per_word) *
946 pdata->num_chipselect, GFP_KERNEL);
947 if (dspi->bytes_per_word == NULL) {
948 ret = -ENOMEM;
949 goto free_master;
950 }
951
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000952 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
953 if (r == NULL) {
954 ret = -ENOENT;
955 goto free_master;
956 }
957
Sekhar Nori212d4b62010-10-11 10:41:39 +0530958 dspi->pbase = r->start;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000959
Jingoo Han5b3bb592013-12-09 19:12:03 +0900960 dspi->base = devm_ioremap_resource(&pdev->dev, r);
961 if (IS_ERR(dspi->base)) {
962 ret = PTR_ERR(dspi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000963 goto free_master;
964 }
965
Andrzej Hajda8494cde2015-09-24 16:00:10 +0200966 ret = platform_get_irq(pdev, 0);
967 if (ret == 0)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530968 ret = -EINVAL;
Andrzej Hajda8494cde2015-09-24 16:00:10 +0200969 if (ret < 0)
Jingoo Han5b3bb592013-12-09 19:12:03 +0900970 goto free_master;
Andrzej Hajda8494cde2015-09-24 16:00:10 +0200971 dspi->irq = ret;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530972
Jingoo Han5b3bb592013-12-09 19:12:03 +0900973 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
974 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530975 if (ret)
Jingoo Han5b3bb592013-12-09 19:12:03 +0900976 goto free_master;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530977
Axel Lin94c69f72013-09-10 15:43:41 +0800978 dspi->bitbang.master = master;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000979
Jingoo Han5b3bb592013-12-09 19:12:03 +0900980 dspi->clk = devm_clk_get(&pdev->dev, NULL);
Sekhar Nori212d4b62010-10-11 10:41:39 +0530981 if (IS_ERR(dspi->clk)) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000982 ret = -ENODEV;
Jingoo Han5b3bb592013-12-09 19:12:03 +0900983 goto free_master;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000984 }
Murali Karicheriaae71472012-12-11 16:20:39 -0500985 clk_prepare_enable(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000986
Murali Karicheriaae71472012-12-11 16:20:39 -0500987 master->dev.of_node = pdev->dev.of_node;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000988 master->bus_num = pdev->id;
989 master->num_chipselect = pdata->num_chipselect;
Stephen Warren24778be2013-05-21 20:36:35 -0600990 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000991 master->setup = davinci_spi_setup;
Murali Karicheri365a7bb2014-09-16 14:25:05 +0300992 master->cleanup = davinci_spi_cleanup;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000993
Sekhar Nori212d4b62010-10-11 10:41:39 +0530994 dspi->bitbang.chipselect = davinci_spi_chipselect;
995 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
Franklin S Cooper Jrfa466c92015-07-22 07:32:22 -0500996 dspi->prescaler_limit = pdata->prescaler_limit;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530997 dspi->version = pdata->version;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000998
Sekhar Nori212d4b62010-10-11 10:41:39 +0530999 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1000 if (dspi->version == SPI_VERSION_2)
1001 dspi->bitbang.flags |= SPI_READY;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001002
Grygorii Strashko8936dec2014-09-12 17:54:00 +03001003 if (pdev->dev.of_node) {
1004 int i;
1005
1006 for (i = 0; i < pdata->num_chipselect; i++) {
1007 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1008 "cs-gpios", i);
1009
1010 if (cs_gpio == -EPROBE_DEFER) {
1011 ret = cs_gpio;
1012 goto free_clk;
1013 }
1014
1015 if (gpio_is_valid(cs_gpio)) {
1016 ret = devm_gpio_request(&pdev->dev, cs_gpio,
1017 dev_name(&pdev->dev));
1018 if (ret)
1019 goto free_clk;
1020 }
1021 }
1022 }
1023
Sekhar Nori212d4b62010-10-11 10:41:39 +05301024 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
Brian Niebuhr96fd8812010-09-27 22:23:23 +05301025
Peter Ujfalusife5fd252016-04-29 16:10:22 +03001026 ret = davinci_spi_request_dma(dspi);
1027 if (ret == -EPROBE_DEFER) {
1028 goto free_clk;
1029 } else if (ret) {
1030 dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret);
1031 dspi->dma_rx = NULL;
1032 dspi->dma_tx = NULL;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001033 }
1034
Sekhar Nori212d4b62010-10-11 10:41:39 +05301035 dspi->get_rx = davinci_spi_rx_buf_u8;
1036 dspi->get_tx = davinci_spi_tx_buf_u8;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001037
Sekhar Nori212d4b62010-10-11 10:41:39 +05301038 init_completion(&dspi->done);
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301039
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001040 /* Reset In/OUT SPI module */
Sekhar Nori212d4b62010-10-11 10:41:39 +05301041 iowrite32(0, dspi->base + SPIGCR0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001042 udelay(100);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301043 iowrite32(1, dspi->base + SPIGCR0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001044
Brian Niebuhrbe884712010-09-03 12:15:28 +05301045 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +05301046 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
Sekhar Nori212d4b62010-10-11 10:41:39 +05301047 iowrite32(spipc0, dspi->base + SPIPC0);
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +05301048
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301049 if (pdata->intr_line)
Sekhar Nori212d4b62010-10-11 10:41:39 +05301050 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301051 else
Sekhar Nori212d4b62010-10-11 10:41:39 +05301052 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301053
Sekhar Nori212d4b62010-10-11 10:41:39 +05301054 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
Brian Niebuhr843a7132010-08-12 12:49:05 +05301055
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001056 /* master mode default */
Sekhar Nori212d4b62010-10-11 10:41:39 +05301057 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1058 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1059 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001060
Sekhar Nori212d4b62010-10-11 10:41:39 +05301061 ret = spi_bitbang_start(&dspi->bitbang);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001062 if (ret)
Sekhar Nori903ca252010-10-01 14:51:40 +05301063 goto free_dma;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001064
Sekhar Nori212d4b62010-10-11 10:41:39 +05301065 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001066
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001067 return ret;
1068
Sekhar Nori903ca252010-10-01 14:51:40 +05301069free_dma:
Peter Ujfalusife5fd252016-04-29 16:10:22 +03001070 if (dspi->dma_rx) {
1071 dma_release_channel(dspi->dma_rx);
1072 dma_release_channel(dspi->dma_tx);
1073 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001074free_clk:
Murali Karicheriaae71472012-12-11 16:20:39 -05001075 clk_disable_unprepare(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001076free_master:
Axel Lin94c69f72013-09-10 15:43:41 +08001077 spi_master_put(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001078err:
1079 return ret;
1080}
1081
1082/**
1083 * davinci_spi_remove - remove function for SPI Master Controller
1084 * @pdev: platform_device structure which contains plateform specific data
1085 *
1086 * This function will do the reverse action of davinci_spi_probe function
1087 * It will free the IRQ and SPI controller's memory region.
1088 * It will also call spi_bitbang_stop to destroy the work queue which was
1089 * created by spi_bitbang_start.
1090 */
Grant Likelyfd4a3192012-12-07 16:57:14 +00001091static int davinci_spi_remove(struct platform_device *pdev)
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001092{
Sekhar Nori212d4b62010-10-11 10:41:39 +05301093 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001094 struct spi_master *master;
1095
Jingoo Han24b5a822013-05-23 19:20:40 +09001096 master = platform_get_drvdata(pdev);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301097 dspi = spi_master_get_devdata(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001098
Sekhar Nori212d4b62010-10-11 10:41:39 +05301099 spi_bitbang_stop(&dspi->bitbang);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001100
Murali Karicheriaae71472012-12-11 16:20:39 -05001101 clk_disable_unprepare(dspi->clk);
Axel Lin94c69f72013-09-10 15:43:41 +08001102 spi_master_put(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001103
Peter Ujfalusife5fd252016-04-29 16:10:22 +03001104 if (dspi->dma_rx) {
1105 dma_release_channel(dspi->dma_rx);
1106 dma_release_channel(dspi->dma_tx);
1107 }
1108
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001109 return 0;
1110}
1111
1112static struct platform_driver davinci_spi_driver = {
Brian Niebuhrd8c174c2010-10-06 18:47:16 +05301113 .driver = {
1114 .name = "spi_davinci",
Axel Linb53b34f2014-02-06 11:45:08 +08001115 .of_match_table = of_match_ptr(davinci_spi_of_match),
Brian Niebuhrd8c174c2010-10-06 18:47:16 +05301116 },
Grant Likely940ab882011-10-05 11:29:49 -06001117 .probe = davinci_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001118 .remove = davinci_spi_remove,
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001119};
Grant Likely940ab882011-10-05 11:29:49 -06001120module_platform_driver(davinci_spi_driver);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001121
1122MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1123MODULE_LICENSE("GPL");