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Feng Tange24c7452009-12-14 14:20:22 -08001/*
Grant Likelyca632f52011-06-06 01:16:30 -06002 * Designware SPI core controller driver (refer pxa2xx_spi.c)
Feng Tange24c7452009-12-14 14:20:22 -08003 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
Feng Tange24c7452009-12-14 14:20:22 -080014 */
15
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040018#include <linux/module.h>
Feng Tange24c7452009-12-14 14:20:22 -080019#include <linux/highmem.h>
20#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Feng Tange24c7452009-12-14 14:20:22 -080022#include <linux/spi/spi.h>
Baruch Siachd9c73bb2014-01-31 12:07:47 +020023#include <linux/gpio.h>
Feng Tange24c7452009-12-14 14:20:22 -080024
Grant Likelyca632f52011-06-06 01:16:30 -060025#include "spi-dw.h"
Grant Likely568a60e2011-02-28 12:47:12 -070026
Feng Tange24c7452009-12-14 14:20:22 -080027#ifdef CONFIG_DEBUG_FS
28#include <linux/debugfs.h>
29#endif
30
Feng Tange24c7452009-12-14 14:20:22 -080031/* Slave spi_dev related */
32struct chip_data {
Feng Tange24c7452009-12-14 14:20:22 -080033 u8 cs; /* chip select pin */
Feng Tange24c7452009-12-14 14:20:22 -080034 u8 tmode; /* TR/TO/RO/EEPROM */
35 u8 type; /* SPI/SSP/MicroWire */
36
37 u8 poll_mode; /* 1 means use poll mode */
38
Feng Tange24c7452009-12-14 14:20:22 -080039 u8 enable_dma;
Feng Tange24c7452009-12-14 14:20:22 -080040 u16 clk_div; /* baud rate divider */
41 u32 speed_hz; /* baud rate */
Feng Tange24c7452009-12-14 14:20:22 -080042 void (*cs_control)(u32 command);
43};
44
45#ifdef CONFIG_DEBUG_FS
Feng Tange24c7452009-12-14 14:20:22 -080046#define SPI_REGS_BUFSIZE 1024
Andy Shevchenko53288fe2014-09-12 15:11:56 +030047static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
48 size_t count, loff_t *ppos)
Feng Tange24c7452009-12-14 14:20:22 -080049{
Andy Shevchenko53288fe2014-09-12 15:11:56 +030050 struct dw_spi *dws = file->private_data;
Feng Tange24c7452009-12-14 14:20:22 -080051 char *buf;
52 u32 len = 0;
53 ssize_t ret;
54
Feng Tange24c7452009-12-14 14:20:22 -080055 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
56 if (!buf)
57 return 0;
58
59 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
Andy Shevchenko53288fe2014-09-12 15:11:56 +030060 "%s registers:\n", dev_name(&dws->master->dev));
Feng Tange24c7452009-12-14 14:20:22 -080061 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
62 "=================================\n");
63 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070064 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
Feng Tange24c7452009-12-14 14:20:22 -080065 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070066 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
Feng Tange24c7452009-12-14 14:20:22 -080067 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070068 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
Feng Tange24c7452009-12-14 14:20:22 -080069 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070070 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
Feng Tange24c7452009-12-14 14:20:22 -080071 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070072 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
Feng Tange24c7452009-12-14 14:20:22 -080073 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070074 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080075 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070076 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080077 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070078 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080079 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070080 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080081 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070082 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
Feng Tange24c7452009-12-14 14:20:22 -080083 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070084 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
Feng Tange24c7452009-12-14 14:20:22 -080085 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070086 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
Feng Tange24c7452009-12-14 14:20:22 -080087 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070088 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
Feng Tange24c7452009-12-14 14:20:22 -080089 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070090 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
Feng Tange24c7452009-12-14 14:20:22 -080091 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070092 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
Feng Tange24c7452009-12-14 14:20:22 -080093 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "=================================\n");
95
Andy Shevchenko53288fe2014-09-12 15:11:56 +030096 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
Feng Tange24c7452009-12-14 14:20:22 -080097 kfree(buf);
98 return ret;
99}
100
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300101static const struct file_operations dw_spi_regs_ops = {
Feng Tange24c7452009-12-14 14:20:22 -0800102 .owner = THIS_MODULE,
Stephen Boyd234e3402012-04-05 14:25:11 -0700103 .open = simple_open,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300104 .read = dw_spi_show_regs,
Arnd Bergmann6038f372010-08-15 18:52:59 +0200105 .llseek = default_llseek,
Feng Tange24c7452009-12-14 14:20:22 -0800106};
107
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300108static int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800109{
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300110 dws->debugfs = debugfs_create_dir("dw_spi", NULL);
Feng Tange24c7452009-12-14 14:20:22 -0800111 if (!dws->debugfs)
112 return -ENOMEM;
113
114 debugfs_create_file("registers", S_IFREG | S_IRUGO,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300115 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
Feng Tange24c7452009-12-14 14:20:22 -0800116 return 0;
117}
118
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300119static void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800120{
Jingoo Hanfadcace2014-09-02 11:49:24 +0900121 debugfs_remove_recursive(dws->debugfs);
Feng Tange24c7452009-12-14 14:20:22 -0800122}
123
124#else
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300125static inline int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800126{
George Shore20a588f2010-01-21 11:40:49 +0000127 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800128}
129
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300130static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800131{
132}
133#endif /* CONFIG_DEBUG_FS */
134
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200135static void dw_spi_set_cs(struct spi_device *spi, bool enable)
136{
137 struct dw_spi *dws = spi_master_get_devdata(spi->master);
138 struct chip_data *chip = spi_get_ctldata(spi);
139
140 /* Chip select logic is inverted from spi_set_cs() */
Andy Shevchenko207cda92015-03-25 20:26:26 +0200141 if (chip && chip->cs_control)
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200142 chip->cs_control(!enable);
143
144 if (!enable)
145 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
146}
147
Alek Du2ff271b2011-03-30 23:09:54 +0800148/* Return the max entries we can fill into tx fifo */
149static inline u32 tx_max(struct dw_spi *dws)
150{
151 u32 tx_left, tx_room, rxtx_gap;
152
153 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
Thor Thayerdd114442015-03-12 14:19:31 -0500154 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
Alek Du2ff271b2011-03-30 23:09:54 +0800155
156 /*
157 * Another concern is about the tx/rx mismatch, we
158 * though to use (dws->fifo_len - rxflr - txflr) as
159 * one maximum value for tx, but it doesn't cover the
160 * data which is out of tx/rx fifo and inside the
161 * shift registers. So a control from sw point of
162 * view is taken.
163 */
164 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
165 / dws->n_bytes;
166
167 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
168}
169
170/* Return the max entries we should read out of rx fifo */
171static inline u32 rx_max(struct dw_spi *dws)
172{
173 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
174
Thor Thayerdd114442015-03-12 14:19:31 -0500175 return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
Alek Du2ff271b2011-03-30 23:09:54 +0800176}
177
Alek Du3b8a4dd2011-03-30 23:09:55 +0800178static void dw_writer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800179{
Alek Du2ff271b2011-03-30 23:09:54 +0800180 u32 max = tx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800181 u16 txw = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800182
Alek Du2ff271b2011-03-30 23:09:54 +0800183 while (max--) {
184 /* Set the tx word if the transfer's original "tx" is not null */
185 if (dws->tx_end - dws->len) {
186 if (dws->n_bytes == 1)
187 txw = *(u8 *)(dws->tx);
188 else
189 txw = *(u16 *)(dws->tx);
190 }
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200191 dw_write_io_reg(dws, DW_SPI_DR, txw);
Alek Du2ff271b2011-03-30 23:09:54 +0800192 dws->tx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800193 }
Feng Tange24c7452009-12-14 14:20:22 -0800194}
195
Alek Du3b8a4dd2011-03-30 23:09:55 +0800196static void dw_reader(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800197{
Alek Du2ff271b2011-03-30 23:09:54 +0800198 u32 max = rx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800199 u16 rxw;
Feng Tange24c7452009-12-14 14:20:22 -0800200
Alek Du2ff271b2011-03-30 23:09:54 +0800201 while (max--) {
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200202 rxw = dw_read_io_reg(dws, DW_SPI_DR);
Feng Tangde6efe02011-03-30 23:09:52 +0800203 /* Care rx only if the transfer's original "rx" is not null */
204 if (dws->rx_end - dws->len) {
205 if (dws->n_bytes == 1)
206 *(u8 *)(dws->rx) = rxw;
207 else
208 *(u16 *)(dws->rx) = rxw;
209 }
210 dws->rx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800211 }
Feng Tange24c7452009-12-14 14:20:22 -0800212}
213
Feng Tange24c7452009-12-14 14:20:22 -0800214static void int_error_stop(struct dw_spi *dws, const char *msg)
215{
Andy Shevchenko45746e82015-03-02 14:58:55 +0200216 spi_reset_chip(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800217
218 dev_err(&dws->master->dev, "%s\n", msg);
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200219 dws->master->cur_msg->status = -EIO;
220 spi_finalize_current_transfer(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800221}
222
Feng Tange24c7452009-12-14 14:20:22 -0800223static irqreturn_t interrupt_transfer(struct dw_spi *dws)
224{
Thor Thayerdd114442015-03-12 14:19:31 -0500225 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
Feng Tange24c7452009-12-14 14:20:22 -0800226
Feng Tange24c7452009-12-14 14:20:22 -0800227 /* Error handling */
228 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
Thor Thayerdd114442015-03-12 14:19:31 -0500229 dw_readl(dws, DW_SPI_ICR);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800230 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
Feng Tange24c7452009-12-14 14:20:22 -0800231 return IRQ_HANDLED;
232 }
233
Alek Du3b8a4dd2011-03-30 23:09:55 +0800234 dw_reader(dws);
235 if (dws->rx_end == dws->rx) {
236 spi_mask_intr(dws, SPI_INT_TXEI);
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200237 spi_finalize_current_transfer(dws->master);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800238 return IRQ_HANDLED;
239 }
Feng Tang552e4502010-01-20 13:49:45 -0700240 if (irq_status & SPI_INT_TXEI) {
241 spi_mask_intr(dws, SPI_INT_TXEI);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800242 dw_writer(dws);
243 /* Enable TX irq always, it will be disabled when RX finished */
244 spi_umask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800245 }
Feng Tang552e4502010-01-20 13:49:45 -0700246
Feng Tange24c7452009-12-14 14:20:22 -0800247 return IRQ_HANDLED;
248}
249
250static irqreturn_t dw_spi_irq(int irq, void *dev_id)
251{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200252 struct spi_master *master = dev_id;
253 struct dw_spi *dws = spi_master_get_devdata(master);
Thor Thayerdd114442015-03-12 14:19:31 -0500254 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
Yong Wangcbcc0622010-09-07 15:27:27 +0800255
Yong Wangcbcc0622010-09-07 15:27:27 +0800256 if (!irq_status)
257 return IRQ_NONE;
Feng Tange24c7452009-12-14 14:20:22 -0800258
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200259 if (!master->cur_msg) {
Feng Tange24c7452009-12-14 14:20:22 -0800260 spi_mask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800261 return IRQ_HANDLED;
262 }
263
264 return dws->transfer_handler(dws);
265}
266
267/* Must be called inside pump_transfers() */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200268static int poll_transfer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800269{
Alek Du2ff271b2011-03-30 23:09:54 +0800270 do {
271 dw_writer(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800272 dw_reader(dws);
Alek Du2ff271b2011-03-30 23:09:54 +0800273 cpu_relax();
274 } while (dws->rx_end > dws->rx);
Feng Tange24c7452009-12-14 14:20:22 -0800275
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200276 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800277}
278
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200279static int dw_spi_transfer_one(struct spi_master *master,
280 struct spi_device *spi, struct spi_transfer *transfer)
Feng Tange24c7452009-12-14 14:20:22 -0800281{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200282 struct dw_spi *dws = spi_master_get_devdata(master);
283 struct chip_data *chip = spi_get_ctldata(spi);
Feng Tange24c7452009-12-14 14:20:22 -0800284 u8 imask = 0;
Andy Shevchenkoea113702015-02-24 13:32:11 +0200285 u16 txlevel = 0;
Andy Shevchenkode6feda2015-10-14 23:12:21 +0300286 u16 clk_div;
Andy Shevchenko4adb1f82015-10-14 23:12:18 +0300287 u32 cr0;
Andy Shevchenko9f145382015-03-09 16:48:46 +0200288 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800289
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200290 dws->dma_mapped = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800291
Feng Tange24c7452009-12-14 14:20:22 -0800292 dws->tx = (void *)transfer->tx_buf;
293 dws->tx_end = dws->tx + transfer->len;
294 dws->rx = transfer->rx_buf;
295 dws->rx_end = dws->rx + transfer->len;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200296 dws->len = transfer->len;
Feng Tange24c7452009-12-14 14:20:22 -0800297
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200298 spi_enable_chip(dws, 0);
299
Feng Tange24c7452009-12-14 14:20:22 -0800300 /* Handle per transfer options for bpw and speed */
Andy Shevchenkode6feda2015-10-14 23:12:21 +0300301 if (transfer->speed_hz != chip->speed_hz) {
Jarkko Nikula0ed36992015-09-15 16:26:23 +0300302 /* clk_div doesn't support odd number */
Andy Shevchenkode6feda2015-10-14 23:12:21 +0300303 clk_div = (dws->max_freq / transfer->speed_hz + 1) & 0xfffe;
Feng Tange24c7452009-12-14 14:20:22 -0800304
Andy Shevchenkode6feda2015-10-14 23:12:21 +0300305 chip->speed_hz = transfer->speed_hz;
Jarkko Nikula0ed36992015-09-15 16:26:23 +0300306 chip->clk_div = clk_div;
Feng Tange24c7452009-12-14 14:20:22 -0800307
Jarkko Nikula0ed36992015-09-15 16:26:23 +0300308 spi_set_clk(dws, chip->clk_div);
Feng Tange24c7452009-12-14 14:20:22 -0800309 }
Jarkko Nikula0ed36992015-09-15 16:26:23 +0300310 if (transfer->bits_per_word == 8) {
311 dws->n_bytes = 1;
312 dws->dma_width = 1;
313 } else if (transfer->bits_per_word == 16) {
314 dws->n_bytes = 2;
315 dws->dma_width = 2;
Andy Shevchenko863cb2f2015-10-14 23:12:20 +0300316 } else {
317 return -EINVAL;
Feng Tange24c7452009-12-14 14:20:22 -0800318 }
Andy Shevchenko4adb1f82015-10-14 23:12:18 +0300319 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
Jarkko Nikula0ed36992015-09-15 16:26:23 +0300320 cr0 = (transfer->bits_per_word - 1)
321 | (chip->type << SPI_FRF_OFFSET)
322 | (spi->mode << SPI_MODE_OFFSET)
323 | (chip->tmode << SPI_TMOD_OFFSET);
Feng Tange24c7452009-12-14 14:20:22 -0800324
George Shore052dc7c2010-01-21 11:40:52 +0000325 /*
326 * Adjust transfer mode if necessary. Requires platform dependent
327 * chipselect mechanism.
328 */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200329 if (chip->cs_control) {
George Shore052dc7c2010-01-21 11:40:52 +0000330 if (dws->rx && dws->tx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800331 chip->tmode = SPI_TMOD_TR;
George Shore052dc7c2010-01-21 11:40:52 +0000332 else if (dws->rx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800333 chip->tmode = SPI_TMOD_RO;
George Shore052dc7c2010-01-21 11:40:52 +0000334 else
Feng Tange3e55ff2010-09-07 15:52:06 +0800335 chip->tmode = SPI_TMOD_TO;
George Shore052dc7c2010-01-21 11:40:52 +0000336
Feng Tange3e55ff2010-09-07 15:52:06 +0800337 cr0 &= ~SPI_TMOD_MASK;
George Shore052dc7c2010-01-21 11:40:52 +0000338 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
339 }
340
Thor Thayerdd114442015-03-12 14:19:31 -0500341 dw_writel(dws, DW_SPI_CTRL0, cr0);
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200342
Feng Tange24c7452009-12-14 14:20:22 -0800343 /* Check if current transfer is a DMA transaction */
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200344 if (master->can_dma && master->can_dma(master, spi, transfer))
345 dws->dma_mapped = master->cur_msg_mapped;
Feng Tange24c7452009-12-14 14:20:22 -0800346
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200347 /* For poll mode just disable all interrupts */
348 spi_mask_intr(dws, 0xff);
349
Feng Tang552e4502010-01-20 13:49:45 -0700350 /*
351 * Interrupt mode
352 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
353 */
Andy Shevchenko9f145382015-03-09 16:48:46 +0200354 if (dws->dma_mapped) {
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200355 ret = dws->dma_ops->dma_setup(dws, transfer);
Andy Shevchenko9f145382015-03-09 16:48:46 +0200356 if (ret < 0) {
357 spi_enable_chip(dws, 1);
358 return ret;
359 }
360 } else if (!chip->poll_mode) {
Andy Shevchenkoea113702015-02-24 13:32:11 +0200361 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
Thor Thayerdd114442015-03-12 14:19:31 -0500362 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
Feng Tang552e4502010-01-20 13:49:45 -0700363
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200364 /* Set the interrupt mask */
Jingoo Hanfadcace2014-09-02 11:49:24 +0900365 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
366 SPI_INT_RXUI | SPI_INT_RXOI;
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200367 spi_umask_intr(dws, imask);
368
Feng Tange24c7452009-12-14 14:20:22 -0800369 dws->transfer_handler = interrupt_transfer;
370 }
371
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200372 spi_enable_chip(dws, 1);
Feng Tange24c7452009-12-14 14:20:22 -0800373
Andy Shevchenko9f145382015-03-09 16:48:46 +0200374 if (dws->dma_mapped) {
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200375 ret = dws->dma_ops->dma_transfer(dws, transfer);
Andy Shevchenko9f145382015-03-09 16:48:46 +0200376 if (ret < 0)
377 return ret;
378 }
Feng Tange24c7452009-12-14 14:20:22 -0800379
380 if (chip->poll_mode)
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200381 return poll_transfer(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800382
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200383 return 1;
Feng Tange24c7452009-12-14 14:20:22 -0800384}
385
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200386static void dw_spi_handle_err(struct spi_master *master,
Baruch Siachec37e8e2014-01-31 12:07:44 +0200387 struct spi_message *msg)
Feng Tange24c7452009-12-14 14:20:22 -0800388{
Baruch Siachec37e8e2014-01-31 12:07:44 +0200389 struct dw_spi *dws = spi_master_get_devdata(master);
Feng Tange24c7452009-12-14 14:20:22 -0800390
Andy Shevchenko4d5ac1e2015-03-09 16:48:48 +0200391 if (dws->dma_mapped)
392 dws->dma_ops->dma_stop(dws);
393
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200394 spi_reset_chip(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800395}
396
397/* This may be called twice for each spi dev */
398static int dw_spi_setup(struct spi_device *spi)
399{
400 struct dw_spi_chip *chip_info = NULL;
401 struct chip_data *chip;
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200402 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800403
Feng Tange24c7452009-12-14 14:20:22 -0800404 /* Only alloc on first setup */
405 chip = spi_get_ctldata(spi);
406 if (!chip) {
Axel Lina97c8832014-08-31 12:47:06 +0800407 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
Feng Tange24c7452009-12-14 14:20:22 -0800408 if (!chip)
409 return -ENOMEM;
Baruch Siach43f627a2013-12-30 20:30:46 +0200410 spi_set_ctldata(spi, chip);
Feng Tange24c7452009-12-14 14:20:22 -0800411 }
412
413 /*
414 * Protocol drivers may change the chip settings, so...
415 * if chip_info exists, use it
416 */
417 chip_info = spi->controller_data;
418
419 /* chip_info doesn't always exist */
420 if (chip_info) {
421 if (chip_info->cs_control)
422 chip->cs_control = chip_info->cs_control;
423
424 chip->poll_mode = chip_info->poll_mode;
425 chip->type = chip_info->type;
Feng Tange24c7452009-12-14 14:20:22 -0800426 }
427
Jisheng Zhang60968282015-12-23 19:05:39 +0800428 chip->tmode = SPI_TMOD_TR;
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300429
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200430 if (gpio_is_valid(spi->cs_gpio)) {
431 ret = gpio_direction_output(spi->cs_gpio,
432 !(spi->mode & SPI_CS_HIGH));
433 if (ret)
434 return ret;
435 }
436
Feng Tange24c7452009-12-14 14:20:22 -0800437 return 0;
438}
439
Axel Lina97c8832014-08-31 12:47:06 +0800440static void dw_spi_cleanup(struct spi_device *spi)
441{
442 struct chip_data *chip = spi_get_ctldata(spi);
443
444 kfree(chip);
445 spi_set_ctldata(spi, NULL);
446}
447
Feng Tange24c7452009-12-14 14:20:22 -0800448/* Restart the controller, disable all interrupts, clean rx fifo */
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200449static void spi_hw_init(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800450{
Andy Shevchenko45746e82015-03-02 14:58:55 +0200451 spi_reset_chip(dws);
Feng Tangc587b6f2010-01-21 10:41:10 +0800452
453 /*
454 * Try to detect the FIFO depth if not set by interface driver,
455 * the depth could be from 2 to 256 from HW spec
456 */
457 if (!dws->fifo_len) {
458 u32 fifo;
Jingoo Hanfadcace2014-09-02 11:49:24 +0900459
Andy Shevchenko9d239d32015-02-25 11:39:36 +0200460 for (fifo = 1; fifo < 256; fifo++) {
Thor Thayerdd114442015-03-12 14:19:31 -0500461 dw_writel(dws, DW_SPI_TXFLTR, fifo);
462 if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
Feng Tangc587b6f2010-01-21 10:41:10 +0800463 break;
464 }
Thor Thayerdd114442015-03-12 14:19:31 -0500465 dw_writel(dws, DW_SPI_TXFLTR, 0);
Feng Tangc587b6f2010-01-21 10:41:10 +0800466
Andy Shevchenko9d239d32015-02-25 11:39:36 +0200467 dws->fifo_len = (fifo == 1) ? 0 : fifo;
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200468 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
Feng Tangc587b6f2010-01-21 10:41:10 +0800469 }
Feng Tange24c7452009-12-14 14:20:22 -0800470}
471
Baruch Siach04f421e2013-12-30 20:30:44 +0200472int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800473{
474 struct spi_master *master;
475 int ret;
476
477 BUG_ON(dws == NULL);
478
Baruch Siach04f421e2013-12-30 20:30:44 +0200479 master = spi_alloc_master(dev, 0);
480 if (!master)
481 return -ENOMEM;
Feng Tange24c7452009-12-14 14:20:22 -0800482
483 dws->master = master;
484 dws->type = SSI_MOTO_SPI;
Feng Tange24c7452009-12-14 14:20:22 -0800485 dws->dma_inited = 0;
Andy Shevchenkod7ef54c2015-10-27 17:48:16 +0200486 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
Andy Shevchenkoc3c6e232014-09-18 20:08:57 +0300487 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
Feng Tange24c7452009-12-14 14:20:22 -0800488
Andy Shevchenko02f20382015-10-20 12:11:40 +0300489 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dws->name, master);
Feng Tange24c7452009-12-14 14:20:22 -0800490 if (ret < 0) {
Andy Shevchenko5f0966e2015-10-14 23:12:17 +0300491 dev_err(dev, "can not get IRQ\n");
Feng Tange24c7452009-12-14 14:20:22 -0800492 goto err_free_master;
493 }
494
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300495 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
Stephen Warren24778be2013-05-21 20:36:35 -0600496 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Feng Tange24c7452009-12-14 14:20:22 -0800497 master->bus_num = dws->bus_num;
498 master->num_chipselect = dws->num_cs;
Feng Tange24c7452009-12-14 14:20:22 -0800499 master->setup = dw_spi_setup;
Axel Lina97c8832014-08-31 12:47:06 +0800500 master->cleanup = dw_spi_cleanup;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200501 master->set_cs = dw_spi_set_cs;
502 master->transfer_one = dw_spi_transfer_one;
503 master->handle_err = dw_spi_handle_err;
Axel Lin765ee702014-02-20 21:37:56 +0800504 master->max_speed_hz = dws->max_freq;
Thor Thayer9c6de472014-10-08 13:51:34 -0500505 master->dev.of_node = dev->of_node;
Feng Tange24c7452009-12-14 14:20:22 -0800506
Feng Tange24c7452009-12-14 14:20:22 -0800507 /* Basic HW init */
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200508 spi_hw_init(dev, dws);
Feng Tange24c7452009-12-14 14:20:22 -0800509
Feng Tang7063c0d2010-12-24 13:59:11 +0800510 if (dws->dma_ops && dws->dma_ops->dma_init) {
511 ret = dws->dma_ops->dma_init(dws);
512 if (ret) {
Andy Shevchenko3dbb3b92015-01-07 16:56:54 +0200513 dev_warn(dev, "DMA init failed\n");
Feng Tang7063c0d2010-12-24 13:59:11 +0800514 dws->dma_inited = 0;
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200515 } else {
516 master->can_dma = dws->dma_ops->can_dma;
Feng Tang7063c0d2010-12-24 13:59:11 +0800517 }
518 }
519
Feng Tange24c7452009-12-14 14:20:22 -0800520 spi_master_set_devdata(master, dws);
Baruch Siach04f421e2013-12-30 20:30:44 +0200521 ret = devm_spi_register_master(dev, master);
Feng Tange24c7452009-12-14 14:20:22 -0800522 if (ret) {
523 dev_err(&master->dev, "problem registering spi master\n");
Baruch Siachec37e8e2014-01-31 12:07:44 +0200524 goto err_dma_exit;
Feng Tange24c7452009-12-14 14:20:22 -0800525 }
526
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300527 dw_spi_debugfs_init(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800528 return 0;
529
Baruch Siachec37e8e2014-01-31 12:07:44 +0200530err_dma_exit:
Feng Tang7063c0d2010-12-24 13:59:11 +0800531 if (dws->dma_ops && dws->dma_ops->dma_exit)
532 dws->dma_ops->dma_exit(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800533 spi_enable_chip(dws, 0);
Andy Shevchenko02f20382015-10-20 12:11:40 +0300534 free_irq(dws->irq, master);
Feng Tange24c7452009-12-14 14:20:22 -0800535err_free_master:
536 spi_master_put(master);
Feng Tange24c7452009-12-14 14:20:22 -0800537 return ret;
538}
Feng Tang79290a22010-12-24 13:59:10 +0800539EXPORT_SYMBOL_GPL(dw_spi_add_host);
Feng Tange24c7452009-12-14 14:20:22 -0800540
Grant Likelyfd4a3192012-12-07 16:57:14 +0000541void dw_spi_remove_host(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800542{
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300543 dw_spi_debugfs_remove(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800544
Feng Tang7063c0d2010-12-24 13:59:11 +0800545 if (dws->dma_ops && dws->dma_ops->dma_exit)
546 dws->dma_ops->dma_exit(dws);
Andy Shevchenko1cc3f142015-10-14 23:12:23 +0300547
548 spi_shutdown_chip(dws);
Andy Shevchenko02f20382015-10-20 12:11:40 +0300549
550 free_irq(dws->irq, dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800551}
Feng Tang79290a22010-12-24 13:59:10 +0800552EXPORT_SYMBOL_GPL(dw_spi_remove_host);
Feng Tange24c7452009-12-14 14:20:22 -0800553
554int dw_spi_suspend_host(struct dw_spi *dws)
555{
Andy Shevchenko1cc3f142015-10-14 23:12:23 +0300556 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800557
Baruch Siachec37e8e2014-01-31 12:07:44 +0200558 ret = spi_master_suspend(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800559 if (ret)
560 return ret;
Andy Shevchenko1cc3f142015-10-14 23:12:23 +0300561
562 spi_shutdown_chip(dws);
563 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800564}
Feng Tang79290a22010-12-24 13:59:10 +0800565EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
Feng Tange24c7452009-12-14 14:20:22 -0800566
567int dw_spi_resume_host(struct dw_spi *dws)
568{
569 int ret;
570
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200571 spi_hw_init(&dws->master->dev, dws);
Baruch Siachec37e8e2014-01-31 12:07:44 +0200572 ret = spi_master_resume(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800573 if (ret)
574 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
575 return ret;
576}
Feng Tang79290a22010-12-24 13:59:10 +0800577EXPORT_SYMBOL_GPL(dw_spi_resume_host);
Feng Tange24c7452009-12-14 14:20:22 -0800578
579MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
580MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
581MODULE_LICENSE("GPL v2");