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Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03001/* Intel i7 core/Nehalem Memory Controller kernel module
2 *
David Sterbae7bf0682010-12-27 16:51:15 +01003 * This driver supports the memory controllers found on the Intel
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03004 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
6 * and Westmere-EP.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03007 *
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
10 *
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -030011 * Copyright (c) 2009-2010 by:
Mauro Carvalho Chehab37e59f82014-02-07 08:03:07 -020012 * Mauro Carvalho Chehab
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030013 *
14 * Red Hat Inc. http://www.redhat.com
15 *
16 * Forked and adapted from the i5400_edac driver
17 *
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
24 * also available at:
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
26 */
27
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030028#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/pci_ids.h>
32#include <linux/slab.h>
Randy Dunlap3b918c12009-11-08 01:36:40 -020033#include <linux/delay.h>
Nils Carlson535e9c72011-08-08 06:21:26 -030034#include <linux/dmi.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030035#include <linux/edac.h>
36#include <linux/mmzone.h>
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030037#include <linux/smp.h>
Borislav Petkov4140c542011-07-18 11:24:46 -030038#include <asm/mce.h>
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -030039#include <asm/processor.h>
Sedat Dilek4fad8092011-09-21 23:44:52 -030040#include <asm/div64.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030041
42#include "edac_core.h"
43
Mauro Carvalho Chehab18c29002010-08-10 18:33:27 -030044/* Static vars */
45static LIST_HEAD(i7core_edac_list);
46static DEFINE_MUTEX(i7core_edac_lock);
47static int probed;
48
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -030049static int use_pci_fixup;
50module_param(use_pci_fixup, int, 0444);
51MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030052/*
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030053 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
54 * registers start at bus 255, and are not reported by BIOS.
55 * We currently find devices with only 2 sockets. In order to support more QPI
56 * Quick Path Interconnect, just increment this number.
57 */
58#define MAX_SOCKET_BUSES 2
59
60
61/*
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030062 * Alter this version for the module when modifications are made
63 */
Michal Marek152ba392011-04-01 12:41:20 +020064#define I7CORE_REVISION " Ver: 1.0.0"
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030065#define EDAC_MOD_STR "i7core_edac"
66
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030067/*
68 * Debug macros
69 */
70#define i7core_printk(level, fmt, arg...) \
71 edac_printk(level, "i7core", fmt, ##arg)
72
73#define i7core_mc_printk(mci, level, fmt, arg...) \
74 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
75
76/*
77 * i7core Memory Controller Registers
78 */
79
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030080 /* OFFSETS for Device 0 Function 0 */
81
82#define MC_CFG_CONTROL 0x90
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -030083 #define MC_CFG_UNLOCK 0x02
84 #define MC_CFG_LOCK 0x00
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030085
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030086 /* OFFSETS for Device 3 Function 0 */
87
88#define MC_CONTROL 0x48
89#define MC_STATUS 0x4c
90#define MC_MAX_DOD 0x64
91
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -030092/*
David Mackey15ed1032012-04-17 11:30:52 -070093 * OFFSETS for Device 3 Function 4, as indicated on Xeon 5500 datasheet:
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -030094 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
95 */
96
97#define MC_TEST_ERR_RCV1 0x60
98 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
99
100#define MC_TEST_ERR_RCV0 0x64
101 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
102 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
103
David Mackey15ed1032012-04-17 11:30:52 -0700104/* OFFSETS for Device 3 Function 2, as indicated on Xeon 5500 datasheet */
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300105#define MC_SSRCONTROL 0x48
106 #define SSR_MODE_DISABLE 0x00
107 #define SSR_MODE_ENABLE 0x01
108 #define SSR_MODE_MASK 0x03
109
110#define MC_SCRUB_CONTROL 0x4c
111 #define STARTSCRUB (1 << 24)
Nils Carlson535e9c72011-08-08 06:21:26 -0300112 #define SCRUBINTERVAL_MASK 0xffffff
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300113
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300114#define MC_COR_ECC_CNT_0 0x80
115#define MC_COR_ECC_CNT_1 0x84
116#define MC_COR_ECC_CNT_2 0x88
117#define MC_COR_ECC_CNT_3 0x8c
118#define MC_COR_ECC_CNT_4 0x90
119#define MC_COR_ECC_CNT_5 0x94
120
121#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
122#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
123
124
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300125 /* OFFSETS for Devices 4,5 and 6 Function 0 */
126
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300127#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
128 #define THREE_DIMMS_PRESENT (1 << 24)
129 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
130 #define QUAD_RANK_PRESENT (1 << 22)
131 #define REGISTERED_DIMM (1 << 15)
132
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300133#define MC_CHANNEL_MAPPER 0x60
134 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
135 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
136
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300137#define MC_CHANNEL_RANK_PRESENT 0x7c
138 #define RANK_PRESENT_MASK 0xffff
139
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300140#define MC_CHANNEL_ADDR_MATCH 0xf0
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300141#define MC_CHANNEL_ERROR_MASK 0xf8
142#define MC_CHANNEL_ERROR_INJECT 0xfc
143 #define INJECT_ADDR_PARITY 0x10
144 #define INJECT_ECC 0x08
145 #define MASK_CACHELINE 0x06
146 #define MASK_FULL_CACHELINE 0x06
147 #define MASK_MSB32_CACHELINE 0x04
148 #define MASK_LSB32_CACHELINE 0x02
149 #define NO_MASK_CACHELINE 0x00
150 #define REPEAT_EN 0x01
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300151
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300152 /* OFFSETS for Devices 4,5 and 6 Function 1 */
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300153
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300154#define MC_DOD_CH_DIMM0 0x48
155#define MC_DOD_CH_DIMM1 0x4c
156#define MC_DOD_CH_DIMM2 0x50
157 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
158 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
159 #define DIMM_PRESENT_MASK (1 << 9)
160 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300161 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
162 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
163 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
164 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300165 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300166 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300167 #define MC_DOD_NUMCOL_MASK 3
168 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300169
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300170#define MC_RANK_PRESENT 0x7c
171
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300172#define MC_SAG_CH_0 0x80
173#define MC_SAG_CH_1 0x84
174#define MC_SAG_CH_2 0x88
175#define MC_SAG_CH_3 0x8c
176#define MC_SAG_CH_4 0x90
177#define MC_SAG_CH_5 0x94
178#define MC_SAG_CH_6 0x98
179#define MC_SAG_CH_7 0x9c
180
181#define MC_RIR_LIMIT_CH_0 0x40
182#define MC_RIR_LIMIT_CH_1 0x44
183#define MC_RIR_LIMIT_CH_2 0x48
184#define MC_RIR_LIMIT_CH_3 0x4C
185#define MC_RIR_LIMIT_CH_4 0x50
186#define MC_RIR_LIMIT_CH_5 0x54
187#define MC_RIR_LIMIT_CH_6 0x58
188#define MC_RIR_LIMIT_CH_7 0x5C
189#define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
190
191#define MC_RIR_WAY_CH 0x80
192 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
193 #define MC_RIR_WAY_RANK_MASK 0x7
194
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300195/*
196 * i7core structs
197 */
198
199#define NUM_CHANS 3
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300200#define MAX_DIMMS 3 /* Max DIMMS per channel */
201#define MAX_MCR_FUNC 4
202#define MAX_CHAN_FUNC 3
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300203
204struct i7core_info {
205 u32 mc_control;
206 u32 mc_status;
207 u32 max_dod;
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300208 u32 ch_map;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300209};
210
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300211
212struct i7core_inject {
213 int enable;
214
215 u32 section;
216 u32 type;
217 u32 eccmask;
218
219 /* Error address mask */
220 int channel, dimm, rank, bank, page, col;
221};
222
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300223struct i7core_channel {
Mauro Carvalho Chehab0bf09e82012-04-26 11:47:29 -0300224 bool is_3dimms_present;
225 bool is_single_4rank;
226 bool has_4rank;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300227 u32 dimms;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300228};
229
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300230struct pci_id_descr {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300231 int dev;
232 int func;
233 int dev_id;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300234 int optional;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300235};
236
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300237struct pci_id_table {
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300238 const struct pci_id_descr *descr;
239 int n_devs;
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300240};
241
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300242struct i7core_dev {
243 struct list_head list;
244 u8 socket;
245 struct pci_dev **pdev;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300246 int n_devs;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300247 struct mem_ctl_info *mci;
248};
249
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300250struct i7core_pvt {
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -0300251 struct device *addrmatch_dev, *chancounts_dev;
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300252
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300253 struct pci_dev *pci_noncore;
254 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
255 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
256
257 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300258
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300259 struct i7core_info info;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300260 struct i7core_inject inject;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300261 struct i7core_channel channel[NUM_CHANS];
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300262
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300263 int ce_count_available;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300264
265 /* ECC corrected errors counts per udimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300266 unsigned long udimm_ce_count[MAX_DIMMS];
267 int udimm_last_ce_count[MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300268 /* ECC corrected errors counts per rdimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300269 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
270 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300271
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -0300272 bool is_registered, enable_scrub;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300273
Nils Carlson535e9c72011-08-08 06:21:26 -0300274 /* DCLK Frequency used for computing scrub rate */
275 int dclk_freq;
276
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300277 /* Struct to control EDAC polling */
278 struct edac_pci_ctl_info *i7core_pci;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300279};
280
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300281#define PCI_DESCR(device, function, device_id) \
282 .dev = (device), \
283 .func = (function), \
284 .dev_id = (device_id)
285
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300286static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300287 /* Memory controller */
288 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
289 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300290 /* Exists only for RDIMM */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300291 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300292 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
293
294 /* Channel 0 */
295 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
296 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
297 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
298 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
299
300 /* Channel 1 */
301 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
302 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
303 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
304 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
305
306 /* Channel 2 */
307 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
308 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
309 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
310 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300311
312 /* Generic Non-core registers */
313 /*
314 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
315 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
316 * the probing code needs to test for the other address in case of
317 * failure of this one
318 */
319 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
320
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300321};
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300322
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300323static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300324 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
325 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
326 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
327
328 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
329 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
330 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
331 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
332
Mauro Carvalho Chehab508fa172009-10-14 13:44:37 -0300333 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
334 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
335 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
336 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300337
338 /*
339 * This is the PCI device has an alternate address on some
340 * processors like Core i7 860
341 */
342 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300343};
344
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300345static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300346 /* Memory controller */
347 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
348 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
349 /* Exists only for RDIMM */
350 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
351 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
352
353 /* Channel 0 */
354 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
355 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
356 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
357 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
358
359 /* Channel 1 */
360 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
361 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
362 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
363 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
364
365 /* Channel 2 */
366 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
367 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
368 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
369 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300370
371 /* Generic Non-core registers */
372 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
373
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300374};
375
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300376#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
377static const struct pci_id_table pci_dev_table[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300378 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
379 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
380 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -0200381 {0,} /* 0 terminated list. */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300382};
383
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300384/*
385 * pci_device_id table for which devices we are looking for
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300386 */
Jingoo Hanba935f42013-12-06 10:23:08 +0100387static const struct pci_device_id i7core_pci_tbl[] = {
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -0300388 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
Mauro Carvalho Chehabf05da2f2009-10-14 13:31:06 -0300389 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300390 {0,} /* 0 terminated list. */
391};
392
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300393/****************************************************************************
David Mackey15ed1032012-04-17 11:30:52 -0700394 Ancillary status routines
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300395 ****************************************************************************/
396
397 /* MC_CONTROL bits */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300398#define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
399#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300400
401 /* MC_STATUS bits */
Keith Mannthey61053fd2009-09-02 23:46:59 -0300402#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300403#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300404
405 /* MC_MAX_DOD read functions */
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300406static inline int numdimms(u32 dimms)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300407{
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300408 return (dimms & 0x3) + 1;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300409}
410
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300411static inline int numrank(u32 rank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300412{
Niklas Söderlundc31d34f2012-01-29 23:04:32 +0100413 static const int ranks[] = { 1, 2, 4, -EINVAL };
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300414
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300415 return ranks[rank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300416}
417
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300418static inline int numbank(u32 bank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300419{
Niklas Söderlundc31d34f2012-01-29 23:04:32 +0100420 static const int banks[] = { 4, 8, 16, -EINVAL };
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300421
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300422 return banks[bank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300423}
424
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300425static inline int numrow(u32 row)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300426{
Niklas Söderlundc31d34f2012-01-29 23:04:32 +0100427 static const int rows[] = {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300428 1 << 12, 1 << 13, 1 << 14, 1 << 15,
429 1 << 16, -EINVAL, -EINVAL, -EINVAL,
430 };
431
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300432 return rows[row & 0x7];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300433}
434
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300435static inline int numcol(u32 col)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300436{
Niklas Söderlundc31d34f2012-01-29 23:04:32 +0100437 static const int cols[] = {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300438 1 << 10, 1 << 11, 1 << 12, -EINVAL,
439 };
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300440 return cols[col & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300441}
442
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300443static struct i7core_dev *get_i7core_dev(u8 socket)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300444{
445 struct i7core_dev *i7core_dev;
446
447 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
448 if (i7core_dev->socket == socket)
449 return i7core_dev;
450 }
451
452 return NULL;
453}
454
Hidetoshi Seto848b2f72010-08-20 04:24:44 -0300455static struct i7core_dev *alloc_i7core_dev(u8 socket,
456 const struct pci_id_table *table)
457{
458 struct i7core_dev *i7core_dev;
459
460 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
461 if (!i7core_dev)
462 return NULL;
463
464 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
465 GFP_KERNEL);
466 if (!i7core_dev->pdev) {
467 kfree(i7core_dev);
468 return NULL;
469 }
470
471 i7core_dev->socket = socket;
472 i7core_dev->n_devs = table->n_devs;
473 list_add_tail(&i7core_dev->list, &i7core_edac_list);
474
475 return i7core_dev;
476}
477
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -0300478static void free_i7core_dev(struct i7core_dev *i7core_dev)
479{
480 list_del(&i7core_dev->list);
481 kfree(i7core_dev->pdev);
482 kfree(i7core_dev);
483}
484
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300485/****************************************************************************
486 Memory check routines
487 ****************************************************************************/
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300488
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300489static int get_dimm_config(struct mem_ctl_info *mci)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300490{
491 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300492 struct pci_dev *pdev;
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300493 int i, j;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300494 enum edac_type mode;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300495 enum mem_type mtype;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300496 struct dimm_info *dimm;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300497
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300498 /* Get data from the MC register, function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300499 pdev = pvt->pci_mcr[0];
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300500 if (!pdev)
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300501 return -ENODEV;
502
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300503 /* Device 3 function 0 reads */
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300504 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
505 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
506 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
507 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300508
Joe Perches956b9ba2012-04-29 17:08:39 -0300509 edac_dbg(0, "QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
510 pvt->i7core_dev->socket, pvt->info.mc_control,
511 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300512
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300513 if (ECC_ENABLED(pvt)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300514 edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300515 if (ECCx8(pvt))
516 mode = EDAC_S8ECD8ED;
517 else
518 mode = EDAC_S4ECD4ED;
519 } else {
Joe Perches956b9ba2012-04-29 17:08:39 -0300520 edac_dbg(0, "ECC disabled\n");
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300521 mode = EDAC_NONE;
522 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300523
524 /* FIXME: need to handle the error codes */
Joe Perches956b9ba2012-04-29 17:08:39 -0300525 edac_dbg(0, "DOD Max limits: DIMMS: %d, %d-ranked, %d-banked x%x x 0x%x\n",
526 numdimms(pvt->info.max_dod),
527 numrank(pvt->info.max_dod >> 2),
528 numbank(pvt->info.max_dod >> 4),
529 numrow(pvt->info.max_dod >> 6),
530 numcol(pvt->info.max_dod >> 9));
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300531
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300532 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300533 u32 data, dimm_dod[3], value[8];
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300534
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300535 if (!pvt->pci_ch[i][0])
536 continue;
537
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300538 if (!CH_ACTIVE(pvt, i)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300539 edac_dbg(0, "Channel %i is not active\n", i);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300540 continue;
541 }
542 if (CH_DISABLED(pvt, i)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300543 edac_dbg(0, "Channel %i is disabled\n", i);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300544 continue;
545 }
546
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300547 /* Devices 4-6 function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300548 pci_read_config_dword(pvt->pci_ch[i][0],
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300549 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
550
Mauro Carvalho Chehab0bf09e82012-04-26 11:47:29 -0300551
552 if (data & THREE_DIMMS_PRESENT)
553 pvt->channel[i].is_3dimms_present = true;
554
555 if (data & SINGLE_QUAD_RANK_PRESENT)
556 pvt->channel[i].is_single_4rank = true;
557
558 if (data & QUAD_RANK_PRESENT)
559 pvt->channel[i].has_4rank = true;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300560
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300561 if (data & REGISTERED_DIMM)
562 mtype = MEM_RDDR3;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300563 else
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300564 mtype = MEM_DDR3;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300565
566 /* Devices 4-6 function 1 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300567 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300568 MC_DOD_CH_DIMM0, &dimm_dod[0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300569 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300570 MC_DOD_CH_DIMM1, &dimm_dod[1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300571 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300572 MC_DOD_CH_DIMM2, &dimm_dod[2]);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300573
Joe Perches956b9ba2012-04-29 17:08:39 -0300574 edac_dbg(0, "Ch%d phy rd%d, wr%d (0x%08x): %s%s%s%cDIMMs\n",
575 i,
576 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
577 data,
578 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
579 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
580 pvt->channel[i].has_4rank ? "HAS_4R " : "",
581 (data & REGISTERED_DIMM) ? 'R' : 'U');
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300582
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300583 for (j = 0; j < 3; j++) {
584 u32 banks, ranks, rows, cols;
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300585 u32 size, npages;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300586
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300587 if (!DIMM_PRESENT(dimm_dod[j]))
588 continue;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300589
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -0300590 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
591 i, j, 0);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300592 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
593 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
594 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
595 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300596
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300597 /* DDR3 has 8 I/O banks */
598 size = (rows * cols * banks * ranks) >> (20 - 3);
599
Joe Perches956b9ba2012-04-29 17:08:39 -0300600 edac_dbg(0, "\tdimm %d %d Mb offset: %x, bank: %d, rank: %d, row: %#x, col: %#x\n",
601 j, size,
602 RANKOFFSET(dimm_dod[j]),
603 banks, ranks, rows, cols);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300604
Mauro Carvalho Chehabe9144602010-08-10 20:26:35 -0300605 npages = MiB_TO_PAGES(size);
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300606
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300607 dimm->nr_pages = npages;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300608
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300609 switch (banks) {
610 case 4:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300611 dimm->dtype = DEV_X4;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300612 break;
613 case 8:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300614 dimm->dtype = DEV_X8;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300615 break;
616 case 16:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300617 dimm->dtype = DEV_X16;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300618 break;
619 default:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300620 dimm->dtype = DEV_UNKNOWN;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300621 }
622
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300623 snprintf(dimm->label, sizeof(dimm->label),
624 "CPU#%uChannel#%u_DIMM#%u",
625 pvt->i7core_dev->socket, i, j);
626 dimm->grain = 8;
627 dimm->edac_mode = mode;
628 dimm->mtype = mtype;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300629 }
630
631 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
632 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
633 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
634 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
635 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
636 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
637 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
638 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
Joe Perches956b9ba2012-04-29 17:08:39 -0300639 edac_dbg(1, "\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300640 for (j = 0; j < 8; j++)
Joe Perches956b9ba2012-04-29 17:08:39 -0300641 edac_dbg(1, "\t\t%#x\t%#x\t%#x\n",
642 (value[j] >> 27) & 0x1,
643 (value[j] >> 24) & 0x7,
644 (value[j] & ((1 << 24) - 1)));
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300645 }
646
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300647 return 0;
648}
649
650/****************************************************************************
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300651 Error insertion routines
652 ****************************************************************************/
653
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300654#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
655
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300656/* The i7core has independent error injection features per channel.
657 However, to have a simpler code, we don't allow enabling error injection
658 on more than one channel.
659 Also, since a change at an inject parameter will be applied only at enable,
660 we're disabling error injection on all write calls to the sysfs nodes that
661 controls the error code injection.
662 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300663static int disable_inject(const struct mem_ctl_info *mci)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300664{
665 struct i7core_pvt *pvt = mci->pvt_info;
666
667 pvt->inject.enable = 0;
668
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300669 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300670 return -ENODEV;
671
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300672 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300673 MC_CHANNEL_ERROR_INJECT, 0);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300674
675 return 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300676}
677
678/*
679 * i7core inject inject.section
680 *
681 * accept and store error injection inject.section value
682 * bit 0 - refers to the lower 32-byte half cacheline
683 * bit 1 - refers to the upper 32-byte half cacheline
684 */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300685static ssize_t i7core_inject_section_store(struct device *dev,
686 struct device_attribute *mattr,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300687 const char *data, size_t count)
688{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300689 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300690 struct i7core_pvt *pvt = mci->pvt_info;
691 unsigned long value;
692 int rc;
693
694 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300695 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300696
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900697 rc = kstrtoul(data, 10, &value);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300698 if ((rc < 0) || (value > 3))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300699 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300700
701 pvt->inject.section = (u32) value;
702 return count;
703}
704
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300705static ssize_t i7core_inject_section_show(struct device *dev,
706 struct device_attribute *mattr,
707 char *data)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300708{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300709 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300710 struct i7core_pvt *pvt = mci->pvt_info;
711 return sprintf(data, "0x%08x\n", pvt->inject.section);
712}
713
714/*
715 * i7core inject.type
716 *
717 * accept and store error injection inject.section value
718 * bit 0 - repeat enable - Enable error repetition
719 * bit 1 - inject ECC error
720 * bit 2 - inject parity error
721 */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300722static ssize_t i7core_inject_type_store(struct device *dev,
723 struct device_attribute *mattr,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300724 const char *data, size_t count)
725{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300726 struct mem_ctl_info *mci = to_mci(dev);
727struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300728 unsigned long value;
729 int rc;
730
731 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300732 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300733
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900734 rc = kstrtoul(data, 10, &value);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300735 if ((rc < 0) || (value > 7))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300736 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300737
738 pvt->inject.type = (u32) value;
739 return count;
740}
741
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300742static ssize_t i7core_inject_type_show(struct device *dev,
743 struct device_attribute *mattr,
744 char *data)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300745{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300746 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300747 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300748
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300749 return sprintf(data, "0x%08x\n", pvt->inject.type);
750}
751
752/*
753 * i7core_inject_inject.eccmask_store
754 *
755 * The type of error (UE/CE) will depend on the inject.eccmask value:
756 * Any bits set to a 1 will flip the corresponding ECC bit
757 * Correctable errors can be injected by flipping 1 bit or the bits within
758 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
759 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
760 * uncorrectable error to be injected.
761 */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300762static ssize_t i7core_inject_eccmask_store(struct device *dev,
763 struct device_attribute *mattr,
764 const char *data, size_t count)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300765{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300766 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300767 struct i7core_pvt *pvt = mci->pvt_info;
768 unsigned long value;
769 int rc;
770
771 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300772 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300773
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900774 rc = kstrtoul(data, 10, &value);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300775 if (rc < 0)
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300776 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300777
778 pvt->inject.eccmask = (u32) value;
779 return count;
780}
781
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300782static ssize_t i7core_inject_eccmask_show(struct device *dev,
783 struct device_attribute *mattr,
784 char *data)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300785{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300786 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300787 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300788
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300789 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
790}
791
792/*
793 * i7core_addrmatch
794 *
795 * The type of error (UE/CE) will depend on the inject.eccmask value:
796 * Any bits set to a 1 will flip the corresponding ECC bit
797 * Correctable errors can be injected by flipping 1 bit or the bits within
798 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
799 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
800 * uncorrectable error to be injected.
801 */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300802
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300803#define DECLARE_ADDR_MATCH(param, limit) \
804static ssize_t i7core_inject_store_##param( \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300805 struct device *dev, \
806 struct device_attribute *mattr, \
807 const char *data, size_t count) \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300808{ \
Prarit Bhargava42709ef2012-10-16 09:02:27 -0400809 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300810 struct i7core_pvt *pvt; \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300811 long value; \
812 int rc; \
813 \
Joe Perches956b9ba2012-04-29 17:08:39 -0300814 edac_dbg(1, "\n"); \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300815 pvt = mci->pvt_info; \
816 \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300817 if (pvt->inject.enable) \
818 disable_inject(mci); \
819 \
Mauro Carvalho Chehab4f87fad2009-10-04 11:54:56 -0300820 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300821 value = -1; \
822 else { \
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900823 rc = kstrtoul(data, 10, &value); \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300824 if ((rc < 0) || (value >= limit)) \
825 return -EIO; \
826 } \
827 \
828 pvt->inject.param = value; \
829 \
830 return count; \
831} \
832 \
833static ssize_t i7core_inject_show_##param( \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300834 struct device *dev, \
835 struct device_attribute *mattr, \
836 char *data) \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300837{ \
Prarit Bhargava42709ef2012-10-16 09:02:27 -0400838 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300839 struct i7core_pvt *pvt; \
840 \
841 pvt = mci->pvt_info; \
Joe Perches956b9ba2012-04-29 17:08:39 -0300842 edac_dbg(1, "pvt=%p\n", pvt); \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300843 if (pvt->inject.param < 0) \
844 return sprintf(data, "any\n"); \
845 else \
846 return sprintf(data, "%d\n", pvt->inject.param);\
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300847}
848
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300849#define ATTR_ADDR_MATCH(param) \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300850 static DEVICE_ATTR(param, S_IRUGO | S_IWUSR, \
851 i7core_inject_show_##param, \
852 i7core_inject_store_##param)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300853
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300854DECLARE_ADDR_MATCH(channel, 3);
855DECLARE_ADDR_MATCH(dimm, 3);
856DECLARE_ADDR_MATCH(rank, 4);
857DECLARE_ADDR_MATCH(bank, 32);
858DECLARE_ADDR_MATCH(page, 0x10000);
859DECLARE_ADDR_MATCH(col, 0x4000);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300860
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300861ATTR_ADDR_MATCH(channel);
862ATTR_ADDR_MATCH(dimm);
863ATTR_ADDR_MATCH(rank);
864ATTR_ADDR_MATCH(bank);
865ATTR_ADDR_MATCH(page);
866ATTR_ADDR_MATCH(col);
867
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300868static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300869{
870 u32 read;
871 int count;
872
Joe Perches956b9ba2012-04-29 17:08:39 -0300873 edac_dbg(0, "setting pci %02x:%02x.%x reg=%02x value=%08x\n",
874 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
875 where, val);
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300876
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300877 for (count = 0; count < 10; count++) {
878 if (count)
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300879 msleep(100);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300880 pci_write_config_dword(dev, where, val);
881 pci_read_config_dword(dev, where, &read);
882
883 if (read == val)
884 return 0;
885 }
886
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300887 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
888 "write=%08x. Read=%08x\n",
889 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
890 where, val, read);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300891
892 return -EINVAL;
893}
894
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300895/*
896 * This routine prepares the Memory Controller for error injection.
897 * The error will be injected when some process tries to write to the
898 * memory that matches the given criteria.
899 * The criteria can be set in terms of a mask where dimm, rank, bank, page
900 * and col can be specified.
901 * A -1 value for any of the mask items will make the MCU to ignore
902 * that matching criteria for error injection.
903 *
904 * It should be noticed that the error will only happen after a write operation
905 * on a memory that matches the condition. if REPEAT_EN is not enabled at
906 * inject mask, then it will produce just one error. Otherwise, it will repeat
907 * until the injectmask would be cleaned.
908 *
909 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
910 * is reliable enough to check if the MC is using the
911 * three channels. However, this is not clear at the datasheet.
912 */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300913static ssize_t i7core_inject_enable_store(struct device *dev,
914 struct device_attribute *mattr,
915 const char *data, size_t count)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300916{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300917 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300918 struct i7core_pvt *pvt = mci->pvt_info;
919 u32 injectmask;
920 u64 mask = 0;
921 int rc;
922 long enable;
923
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300924 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300925 return 0;
926
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900927 rc = kstrtoul(data, 10, &enable);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300928 if ((rc < 0))
929 return 0;
930
931 if (enable) {
932 pvt->inject.enable = 1;
933 } else {
934 disable_inject(mci);
935 return count;
936 }
937
938 /* Sets pvt->inject.dimm mask */
939 if (pvt->inject.dimm < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200940 mask |= 1LL << 41;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300941 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300942 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -0200943 mask |= (pvt->inject.dimm & 0x3LL) << 35;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300944 else
Alan Cox486dd092009-11-08 01:34:27 -0200945 mask |= (pvt->inject.dimm & 0x1LL) << 36;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300946 }
947
948 /* Sets pvt->inject.rank mask */
949 if (pvt->inject.rank < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200950 mask |= 1LL << 40;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300951 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300952 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -0200953 mask |= (pvt->inject.rank & 0x1LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300954 else
Alan Cox486dd092009-11-08 01:34:27 -0200955 mask |= (pvt->inject.rank & 0x3LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300956 }
957
958 /* Sets pvt->inject.bank mask */
959 if (pvt->inject.bank < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200960 mask |= 1LL << 39;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300961 else
Alan Cox486dd092009-11-08 01:34:27 -0200962 mask |= (pvt->inject.bank & 0x15LL) << 30;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300963
964 /* Sets pvt->inject.page mask */
965 if (pvt->inject.page < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200966 mask |= 1LL << 38;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300967 else
Alan Cox486dd092009-11-08 01:34:27 -0200968 mask |= (pvt->inject.page & 0xffff) << 14;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300969
970 /* Sets pvt->inject.column mask */
971 if (pvt->inject.col < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200972 mask |= 1LL << 37;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300973 else
Alan Cox486dd092009-11-08 01:34:27 -0200974 mask |= (pvt->inject.col & 0x3fff);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300975
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300976 /*
977 * bit 0: REPEAT_EN
978 * bits 1-2: MASK_HALF_CACHELINE
979 * bit 3: INJECT_ECC
980 * bit 4: INJECT_ADDR_PARITY
981 */
982
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -0300983 injectmask = (pvt->inject.type & 1) |
984 (pvt->inject.section & 0x3) << 1 |
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300985 (pvt->inject.type & 0x6) << (3 - 1);
986
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300987 /* Unlock writes to registers - this register is write only */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300988 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300989 MC_CFG_CONTROL, 0x2);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300990
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300991 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300992 MC_CHANNEL_ADDR_MATCH, mask);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300993 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300994 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
995
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300996 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300997 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
998
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300999 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001000 MC_CHANNEL_ERROR_INJECT, injectmask);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001001
1002 /*
1003 * This is something undocumented, based on my tests
1004 * Without writing 8 to this register, errors aren't injected. Not sure
1005 * why.
1006 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001007 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001008 MC_CFG_CONTROL, 8);
1009
Joe Perches956b9ba2012-04-29 17:08:39 -03001010 edac_dbg(0, "Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",
1011 mask, pvt->inject.eccmask, injectmask);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001012
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001013
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001014 return count;
1015}
1016
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001017static ssize_t i7core_inject_enable_show(struct device *dev,
1018 struct device_attribute *mattr,
1019 char *data)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001020{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001021 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001022 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001023 u32 injectmask;
1024
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -03001025 if (!pvt->pci_ch[pvt->inject.channel][0])
1026 return 0;
1027
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001028 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001029 MC_CHANNEL_ERROR_INJECT, &injectmask);
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001030
Joe Perches956b9ba2012-04-29 17:08:39 -03001031 edac_dbg(0, "Inject error read: 0x%018x\n", injectmask);
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001032
1033 if (injectmask & 0x0c)
1034 pvt->inject.enable = 1;
1035
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001036 return sprintf(data, "%d\n", pvt->inject.enable);
1037}
1038
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001039#define DECLARE_COUNTER(param) \
1040static ssize_t i7core_show_counter_##param( \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001041 struct device *dev, \
1042 struct device_attribute *mattr, \
1043 char *data) \
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001044{ \
Prarit Bhargava42709ef2012-10-16 09:02:27 -04001045 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001046 struct i7core_pvt *pvt = mci->pvt_info; \
1047 \
Joe Perches956b9ba2012-04-29 17:08:39 -03001048 edac_dbg(1, "\n"); \
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001049 if (!pvt->ce_count_available || (pvt->is_registered)) \
1050 return sprintf(data, "data unavailable\n"); \
1051 return sprintf(data, "%lu\n", \
1052 pvt->udimm_ce_count[param]); \
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001053}
1054
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001055#define ATTR_COUNTER(param) \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001056 static DEVICE_ATTR(udimm##param, S_IRUGO | S_IWUSR, \
1057 i7core_show_counter_##param, \
1058 NULL)
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001059
1060DECLARE_COUNTER(0);
1061DECLARE_COUNTER(1);
1062DECLARE_COUNTER(2);
1063
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001064ATTR_COUNTER(0);
1065ATTR_COUNTER(1);
1066ATTR_COUNTER(2);
1067
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001068/*
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001069 * inject_addrmatch device sysfs struct
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001070 */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001071
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001072static struct attribute *i7core_addrmatch_attrs[] = {
1073 &dev_attr_channel.attr,
1074 &dev_attr_dimm.attr,
1075 &dev_attr_rank.attr,
1076 &dev_attr_bank.attr,
1077 &dev_attr_page.attr,
1078 &dev_attr_col.attr,
1079 NULL
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001080};
1081
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001082static struct attribute_group addrmatch_grp = {
1083 .attrs = i7core_addrmatch_attrs,
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001084};
1085
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001086static const struct attribute_group *addrmatch_groups[] = {
1087 &addrmatch_grp,
1088 NULL
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001089};
1090
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001091static void addrmatch_release(struct device *device)
1092{
Joe Perches956b9ba2012-04-29 17:08:39 -03001093 edac_dbg(1, "Releasing device %s\n", dev_name(device));
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001094 kfree(device);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001095}
1096
1097static struct device_type addrmatch_type = {
1098 .groups = addrmatch_groups,
1099 .release = addrmatch_release,
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001100};
1101
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001102/*
1103 * all_channel_counts sysfs struct
1104 */
1105
1106static struct attribute *i7core_udimm_counters_attrs[] = {
1107 &dev_attr_udimm0.attr,
1108 &dev_attr_udimm1.attr,
1109 &dev_attr_udimm2.attr,
1110 NULL
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001111};
1112
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001113static struct attribute_group all_channel_counts_grp = {
1114 .attrs = i7core_udimm_counters_attrs,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001115};
1116
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001117static const struct attribute_group *all_channel_counts_groups[] = {
1118 &all_channel_counts_grp,
1119 NULL
1120};
1121
1122static void all_channel_counts_release(struct device *device)
1123{
Joe Perches956b9ba2012-04-29 17:08:39 -03001124 edac_dbg(1, "Releasing device %s\n", dev_name(device));
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001125 kfree(device);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001126}
1127
1128static struct device_type all_channel_counts_type = {
1129 .groups = all_channel_counts_groups,
1130 .release = all_channel_counts_release,
1131};
1132
1133/*
1134 * inject sysfs attributes
1135 */
1136
1137static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
1138 i7core_inject_section_show, i7core_inject_section_store);
1139
1140static DEVICE_ATTR(inject_type, S_IRUGO | S_IWUSR,
1141 i7core_inject_type_show, i7core_inject_type_store);
1142
1143
1144static DEVICE_ATTR(inject_eccmask, S_IRUGO | S_IWUSR,
1145 i7core_inject_eccmask_show, i7core_inject_eccmask_store);
1146
1147static DEVICE_ATTR(inject_enable, S_IRUGO | S_IWUSR,
1148 i7core_inject_enable_show, i7core_inject_enable_store);
1149
Takashi Iwai2eace182015-02-04 11:48:55 +01001150static struct attribute *i7core_dev_attrs[] = {
1151 &dev_attr_inject_section.attr,
1152 &dev_attr_inject_type.attr,
1153 &dev_attr_inject_eccmask.attr,
1154 &dev_attr_inject_enable.attr,
1155 NULL
1156};
1157
1158ATTRIBUTE_GROUPS(i7core_dev);
1159
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001160static int i7core_create_sysfs_devices(struct mem_ctl_info *mci)
1161{
1162 struct i7core_pvt *pvt = mci->pvt_info;
1163 int rc;
1164
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001165 pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL);
1166 if (!pvt->addrmatch_dev)
Takashi Iwaie97d7e32015-02-04 11:48:54 +01001167 return -ENOMEM;
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001168
1169 pvt->addrmatch_dev->type = &addrmatch_type;
1170 pvt->addrmatch_dev->bus = mci->dev.bus;
1171 device_initialize(pvt->addrmatch_dev);
1172 pvt->addrmatch_dev->parent = &mci->dev;
1173 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch");
1174 dev_set_drvdata(pvt->addrmatch_dev, mci);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001175
Joe Perches956b9ba2012-04-29 17:08:39 -03001176 edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev));
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001177
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001178 rc = device_add(pvt->addrmatch_dev);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001179 if (rc < 0)
1180 return rc;
1181
1182 if (!pvt->is_registered) {
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001183 pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev),
1184 GFP_KERNEL);
1185 if (!pvt->chancounts_dev) {
1186 put_device(pvt->addrmatch_dev);
1187 device_del(pvt->addrmatch_dev);
Takashi Iwaie97d7e32015-02-04 11:48:54 +01001188 return -ENOMEM;
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001189 }
1190
1191 pvt->chancounts_dev->type = &all_channel_counts_type;
1192 pvt->chancounts_dev->bus = mci->dev.bus;
1193 device_initialize(pvt->chancounts_dev);
1194 pvt->chancounts_dev->parent = &mci->dev;
1195 dev_set_name(pvt->chancounts_dev, "all_channel_counts");
1196 dev_set_drvdata(pvt->chancounts_dev, mci);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001197
Joe Perches956b9ba2012-04-29 17:08:39 -03001198 edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev));
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001199
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001200 rc = device_add(pvt->chancounts_dev);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001201 if (rc < 0)
1202 return rc;
1203 }
1204 return 0;
1205}
1206
1207static void i7core_delete_sysfs_devices(struct mem_ctl_info *mci)
1208{
1209 struct i7core_pvt *pvt = mci->pvt_info;
1210
Joe Perches956b9ba2012-04-29 17:08:39 -03001211 edac_dbg(1, "\n");
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001212
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001213 if (!pvt->is_registered) {
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001214 put_device(pvt->chancounts_dev);
1215 device_del(pvt->chancounts_dev);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001216 }
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001217 put_device(pvt->addrmatch_dev);
1218 device_del(pvt->addrmatch_dev);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001219}
1220
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001221/****************************************************************************
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001222 Device initialization routines: put/get, init/exit
1223 ****************************************************************************/
1224
1225/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001226 * i7core_put_all_devices 'put' all the devices that we have
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001227 * reserved via 'get'
1228 */
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001229static void i7core_put_devices(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001230{
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001231 int i;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001232
Joe Perches956b9ba2012-04-29 17:08:39 -03001233 edac_dbg(0, "\n");
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001234 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001235 struct pci_dev *pdev = i7core_dev->pdev[i];
1236 if (!pdev)
1237 continue;
Joe Perches956b9ba2012-04-29 17:08:39 -03001238 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1239 pdev->bus->number,
1240 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001241 pci_dev_put(pdev);
1242 }
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001243}
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001244
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001245static void i7core_put_all_devices(void)
1246{
Mauro Carvalho Chehab42538682009-09-24 09:59:13 -03001247 struct i7core_dev *i7core_dev, *tmp;
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001248
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001249 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001250 i7core_put_devices(i7core_dev);
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -03001251 free_i7core_dev(i7core_dev);
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001252 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001253}
1254
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001255static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
Keith Manntheybc2d7242009-09-03 00:05:05 -03001256{
1257 struct pci_dev *pdev = NULL;
1258 int i;
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03001259
Keith Manntheybc2d7242009-09-03 00:05:05 -03001260 /*
David Sterbae7bf0682010-12-27 16:51:15 +01001261 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
Keith Manntheybc2d7242009-09-03 00:05:05 -03001262 * aren't announced by acpi. So, we need to use a legacy scan probing
1263 * to detect them
1264 */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001265 while (table && table->descr) {
1266 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1267 if (unlikely(!pdev)) {
1268 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1269 pcibios_scan_specific_bus(255-i);
1270 }
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001271 pci_dev_put(pdev);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001272 table++;
Keith Manntheybc2d7242009-09-03 00:05:05 -03001273 }
1274}
1275
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001276static unsigned i7core_pci_lastbus(void)
1277{
1278 int last_bus = 0, bus;
1279 struct pci_bus *b = NULL;
1280
1281 while ((b = pci_find_next_bus(b)) != NULL) {
1282 bus = b->number;
Joe Perches956b9ba2012-04-29 17:08:39 -03001283 edac_dbg(0, "Found bus %d\n", bus);
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001284 if (bus > last_bus)
1285 last_bus = bus;
1286 }
1287
Joe Perches956b9ba2012-04-29 17:08:39 -03001288 edac_dbg(0, "Last bus %d\n", last_bus);
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001289
1290 return last_bus;
1291}
1292
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001293/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001294 * i7core_get_all_devices Find and perform 'get' operation on the MCH's
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001295 * device/functions we want to reference for this driver
1296 *
1297 * Need to 'get' device 16 func 1 and func 2
1298 */
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001299static int i7core_get_onedevice(struct pci_dev **prev,
1300 const struct pci_id_table *table,
1301 const unsigned devno,
1302 const unsigned last_bus)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001303{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001304 struct i7core_dev *i7core_dev;
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001305 const struct pci_id_descr *dev_descr = &table->descr[devno];
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001306
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001307 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03001308 u8 bus = 0;
1309 u8 socket = 0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001310
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001311 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001312 dev_descr->dev_id, *prev);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001313
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001314 /*
David Mackey15ed1032012-04-17 11:30:52 -07001315 * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001316 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1317 * to probe for the alternate address in case of failure
1318 */
Jean Delvarec0f5eee2014-02-24 09:39:27 +01001319 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) {
1320 pci_dev_get(*prev); /* pci_get_device will put it */
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001321 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1322 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
Jean Delvarec0f5eee2014-02-24 09:39:27 +01001323 }
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001324
Jean Delvarec0f5eee2014-02-24 09:39:27 +01001325 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE &&
1326 !pdev) {
1327 pci_dev_get(*prev); /* pci_get_device will put it */
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001328 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1329 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1330 *prev);
Jean Delvarec0f5eee2014-02-24 09:39:27 +01001331 }
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001332
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001333 if (!pdev) {
1334 if (*prev) {
1335 *prev = pdev;
1336 return 0;
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -03001337 }
1338
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001339 if (dev_descr->optional)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001340 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001341
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001342 if (devno == 0)
1343 return -ENODEV;
1344
Daniel J Bluemanab089372010-07-23 23:16:52 +01001345 i7core_printk(KERN_INFO,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001346 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001347 dev_descr->dev, dev_descr->func,
1348 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001349
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001350 /* End of list, leave */
1351 return -ENODEV;
1352 }
1353 bus = pdev->bus->number;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001354
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001355 socket = last_bus - bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001356
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001357 i7core_dev = get_i7core_dev(socket);
1358 if (!i7core_dev) {
Hidetoshi Seto848b2f72010-08-20 04:24:44 -03001359 i7core_dev = alloc_i7core_dev(socket, table);
Hidetoshi Seto28966372010-08-20 04:28:51 -03001360 if (!i7core_dev) {
1361 pci_dev_put(pdev);
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001362 return -ENOMEM;
Hidetoshi Seto28966372010-08-20 04:28:51 -03001363 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001364 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001365
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001366 if (i7core_dev->pdev[devno]) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001367 i7core_printk(KERN_ERR,
1368 "Duplicated device for "
1369 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001370 bus, dev_descr->dev, dev_descr->func,
1371 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001372 pci_dev_put(pdev);
1373 return -ENODEV;
1374 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001375
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001376 i7core_dev->pdev[devno] = pdev;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001377
1378 /* Sanity check */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001379 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1380 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001381 i7core_printk(KERN_ERR,
1382 "Device PCI ID %04x:%04x "
1383 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001384 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001385 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001386 bus, dev_descr->dev, dev_descr->func);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001387 return -ENODEV;
1388 }
1389
1390 /* Be sure that the device is enabled */
1391 if (unlikely(pci_enable_device(pdev) < 0)) {
1392 i7core_printk(KERN_ERR,
1393 "Couldn't enable "
1394 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001395 bus, dev_descr->dev, dev_descr->func,
1396 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001397 return -ENODEV;
1398 }
1399
Joe Perches956b9ba2012-04-29 17:08:39 -03001400 edac_dbg(0, "Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1401 socket, bus, dev_descr->dev,
1402 dev_descr->func,
1403 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001404
Mauro Carvalho Chehaba3e15412010-08-21 08:52:41 -03001405 /*
1406 * As stated on drivers/pci/search.c, the reference count for
1407 * @from is always decremented if it is not %NULL. So, as we need
1408 * to get all devices up to null, we need to do a get for the device
1409 */
1410 pci_dev_get(pdev);
1411
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001412 *prev = pdev;
1413
1414 return 0;
1415}
1416
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001417static int i7core_get_all_devices(void)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001418{
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001419 int i, rc, last_bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001420 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001421 const struct pci_id_table *table = pci_dev_table;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001422
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001423 last_bus = i7core_pci_lastbus();
1424
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001425 while (table && table->descr) {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001426 for (i = 0; i < table->n_devs; i++) {
1427 pdev = NULL;
1428 do {
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001429 rc = i7core_get_onedevice(&pdev, table, i,
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001430 last_bus);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001431 if (rc < 0) {
1432 if (i == 0) {
1433 i = table->n_devs;
1434 break;
1435 }
1436 i7core_put_all_devices();
1437 return -ENODEV;
1438 }
1439 } while (pdev);
1440 }
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001441 table++;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001442 }
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001443
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001444 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001445}
1446
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001447static int mci_bind_devs(struct mem_ctl_info *mci,
1448 struct i7core_dev *i7core_dev)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001449{
1450 struct i7core_pvt *pvt = mci->pvt_info;
1451 struct pci_dev *pdev;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001452 int i, func, slot;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001453 char *family;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001454
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001455 pvt->is_registered = false;
1456 pvt->enable_scrub = false;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001457 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001458 pdev = i7core_dev->pdev[i];
1459 if (!pdev)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001460 continue;
1461
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001462 func = PCI_FUNC(pdev->devfn);
1463 slot = PCI_SLOT(pdev->devfn);
1464 if (slot == 3) {
1465 if (unlikely(func > MAX_MCR_FUNC))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001466 goto error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001467 pvt->pci_mcr[func] = pdev;
1468 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1469 if (unlikely(func > MAX_CHAN_FUNC))
1470 goto error;
1471 pvt->pci_ch[slot - 4][func] = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001472 } else if (!slot && !func) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001473 pvt->pci_noncore = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001474
1475 /* Detect the processor family */
1476 switch (pdev->device) {
1477 case PCI_DEVICE_ID_INTEL_I7_NONCORE:
1478 family = "Xeon 35xx/ i7core";
1479 pvt->enable_scrub = false;
1480 break;
1481 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
1482 family = "i7-800/i5-700";
1483 pvt->enable_scrub = false;
1484 break;
1485 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
1486 family = "Xeon 34xx";
1487 pvt->enable_scrub = false;
1488 break;
1489 case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
1490 family = "Xeon 55xx";
1491 pvt->enable_scrub = true;
1492 break;
1493 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
1494 family = "Xeon 56xx / i7-900";
1495 pvt->enable_scrub = true;
1496 break;
1497 default:
1498 family = "unknown";
1499 pvt->enable_scrub = false;
1500 }
Joe Perches956b9ba2012-04-29 17:08:39 -03001501 edac_dbg(0, "Detected a processor type %s\n", family);
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001502 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001503 goto error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001504
Joe Perches956b9ba2012-04-29 17:08:39 -03001505 edac_dbg(0, "Associated fn %d.%d, dev = %p, socket %d\n",
1506 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1507 pdev, i7core_dev->socket);
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -03001508
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001509 if (PCI_SLOT(pdev->devfn) == 3 &&
1510 PCI_FUNC(pdev->devfn) == 2)
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001511 pvt->is_registered = true;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001512 }
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -03001513
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001514 return 0;
1515
1516error:
1517 i7core_printk(KERN_ERR, "Device %d, function %d "
1518 "is out of the expected range\n",
1519 slot, func);
1520 return -EINVAL;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001521}
1522
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001523/****************************************************************************
1524 Error check routines
1525 ****************************************************************************/
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001526
1527static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001528 const int chan,
1529 const int new0,
1530 const int new1,
1531 const int new2)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001532{
1533 struct i7core_pvt *pvt = mci->pvt_info;
1534 int add0 = 0, add1 = 0, add2 = 0;
1535 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001536 if (pvt->ce_count_available) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001537 /* Updates CE counters */
1538
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001539 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1540 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1541 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001542
1543 if (add2 < 0)
1544 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001545 pvt->rdimm_ce_count[chan][2] += add2;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001546
1547 if (add1 < 0)
1548 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001549 pvt->rdimm_ce_count[chan][1] += add1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001550
1551 if (add0 < 0)
1552 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001553 pvt->rdimm_ce_count[chan][0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001554 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001555 pvt->ce_count_available = 1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001556
1557 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001558 pvt->rdimm_last_ce_count[chan][2] = new2;
1559 pvt->rdimm_last_ce_count[chan][1] = new1;
1560 pvt->rdimm_last_ce_count[chan][0] = new0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001561
1562 /*updated the edac core */
1563 if (add0 != 0)
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001564 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add0,
1565 0, 0, 0,
1566 chan, 0, -1, "error", "");
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001567 if (add1 != 0)
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001568 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add1,
1569 0, 0, 0,
1570 chan, 1, -1, "error", "");
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001571 if (add2 != 0)
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001572 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add2,
1573 0, 0, 0,
1574 chan, 2, -1, "error", "");
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001575}
1576
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001577static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001578{
1579 struct i7core_pvt *pvt = mci->pvt_info;
1580 u32 rcv[3][2];
1581 int i, new0, new1, new2;
1582
1583 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001584 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001585 &rcv[0][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001586 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001587 &rcv[0][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001588 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001589 &rcv[1][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001590 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001591 &rcv[1][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001592 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001593 &rcv[2][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001594 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001595 &rcv[2][1]);
1596 for (i = 0 ; i < 3; i++) {
Joe Perches956b9ba2012-04-29 17:08:39 -03001597 edac_dbg(3, "MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1598 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001599 /*if the channel has 3 dimms*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001600 if (pvt->channel[i].dimms > 2) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001601 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1602 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1603 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1604 } else {
1605 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1606 DIMM_BOT_COR_ERR(rcv[i][0]);
1607 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1608 DIMM_BOT_COR_ERR(rcv[i][1]);
1609 new2 = 0;
1610 }
1611
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001612 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001613 }
1614}
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001615
1616/* This function is based on the device 3 function 4 registers as described on:
1617 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1618 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1619 * also available at:
1620 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1621 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001622static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001623{
1624 struct i7core_pvt *pvt = mci->pvt_info;
1625 u32 rcv1, rcv0;
1626 int new0, new1, new2;
1627
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001628 if (!pvt->pci_mcr[4]) {
Joe Perches956b9ba2012-04-29 17:08:39 -03001629 edac_dbg(0, "MCR registers not found\n");
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001630 return;
1631 }
1632
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001633 /* Corrected test errors */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001634 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1635 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001636
1637 /* Store the new values */
1638 new2 = DIMM2_COR_ERR(rcv1);
1639 new1 = DIMM1_COR_ERR(rcv0);
1640 new0 = DIMM0_COR_ERR(rcv0);
1641
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001642 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001643 if (pvt->ce_count_available) {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001644 /* Updates CE counters */
1645 int add0, add1, add2;
1646
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001647 add2 = new2 - pvt->udimm_last_ce_count[2];
1648 add1 = new1 - pvt->udimm_last_ce_count[1];
1649 add0 = new0 - pvt->udimm_last_ce_count[0];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001650
1651 if (add2 < 0)
1652 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001653 pvt->udimm_ce_count[2] += add2;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001654
1655 if (add1 < 0)
1656 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001657 pvt->udimm_ce_count[1] += add1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001658
1659 if (add0 < 0)
1660 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001661 pvt->udimm_ce_count[0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001662
1663 if (add0 | add1 | add2)
1664 i7core_printk(KERN_ERR, "New Corrected error(s): "
1665 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1666 add0, add1, add2);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001667 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001668 pvt->ce_count_available = 1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001669
1670 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001671 pvt->udimm_last_ce_count[2] = new2;
1672 pvt->udimm_last_ce_count[1] = new1;
1673 pvt->udimm_last_ce_count[0] = new0;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001674}
1675
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001676/*
1677 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1678 * Architectures Software Developer’s Manual Volume 3B.
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001679 * Nehalem are defined as family 0x06, model 0x1a
1680 *
1681 * The MCA registers used here are the following ones:
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001682 * struct mce field MCA Register
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001683 * m->status MSR_IA32_MC8_STATUS
1684 * m->addr MSR_IA32_MC8_ADDR
1685 * m->misc MSR_IA32_MC8_MISC
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001686 * In the case of Nehalem, the error information is masked at .status and .misc
1687 * fields
1688 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001689static void i7core_mce_output_error(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001690 const struct mce *m)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001691{
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001692 struct i7core_pvt *pvt = mci->pvt_info;
Jean Delvaref1189202014-02-24 17:13:58 +01001693 char *optype, *err;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001694 enum hw_event_mc_err_type tp_event;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001695 unsigned long error = m->status & 0x1ff0000l;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001696 bool uncorrected_error = m->mcgstatus & 1ll << 61;
1697 bool ripv = m->mcgstatus & 1;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001698 u32 optypenum = (m->status >> 4) & 0x07;
Mathias Krause8cf2d232011-08-18 09:17:00 +02001699 u32 core_err_cnt = (m->status >> 38) & 0x7fff;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001700 u32 dimm = (m->misc >> 16) & 0x3;
1701 u32 channel = (m->misc >> 18) & 0x3;
1702 u32 syndrome = m->misc >> 32;
1703 u32 errnum = find_first_bit(&error, 32);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001704
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001705 if (uncorrected_error) {
Jean Delvaref1189202014-02-24 17:13:58 +01001706 if (ripv)
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001707 tp_event = HW_EVENT_ERR_FATAL;
Jean Delvaref1189202014-02-24 17:13:58 +01001708 else
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001709 tp_event = HW_EVENT_ERR_UNCORRECTED;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001710 } else {
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001711 tp_event = HW_EVENT_ERR_CORRECTED;
1712 }
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001713
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001714 switch (optypenum) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001715 case 0:
1716 optype = "generic undef request";
1717 break;
1718 case 1:
1719 optype = "read error";
1720 break;
1721 case 2:
1722 optype = "write error";
1723 break;
1724 case 3:
1725 optype = "addr/cmd error";
1726 break;
1727 case 4:
1728 optype = "scrubbing error";
1729 break;
1730 default:
1731 optype = "reserved";
1732 break;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001733 }
1734
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001735 switch (errnum) {
1736 case 16:
1737 err = "read ECC error";
1738 break;
1739 case 17:
1740 err = "RAS ECC error";
1741 break;
1742 case 18:
1743 err = "write parity error";
1744 break;
1745 case 19:
1746 err = "redundacy loss";
1747 break;
1748 case 20:
1749 err = "reserved";
1750 break;
1751 case 21:
1752 err = "memory range error";
1753 break;
1754 case 22:
1755 err = "RTID out of range";
1756 break;
1757 case 23:
1758 err = "address parity error";
1759 break;
1760 case 24:
1761 err = "byte enable parity error";
1762 break;
1763 default:
1764 err = "unknown";
1765 }
1766
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001767 /*
1768 * Call the helper to output message
1769 * FIXME: what to do if core_err_cnt > 1? Currently, it generates
1770 * only one event
1771 */
1772 if (uncorrected_error || !pvt->is_registered)
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001773 edac_mc_handle_error(tp_event, mci, core_err_cnt,
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001774 m->addr >> PAGE_SHIFT,
1775 m->addr & ~PAGE_MASK,
1776 syndrome,
1777 channel, dimm, -1,
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001778 err, optype);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001779}
1780
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001781/*
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001782 * i7core_check_error Retrieve and process errors reported by the
1783 * hardware. Called by the Core module.
1784 */
Tony Luck53595342016-04-28 07:52:11 -07001785static void i7core_check_error(struct mem_ctl_info *mci, struct mce *m)
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001786{
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001787 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001788
Tony Luck53595342016-04-28 07:52:11 -07001789 i7core_mce_output_error(mci, m);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001790
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001791 /*
1792 * Now, let's increment CE error counts
1793 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001794 if (!pvt->is_registered)
1795 i7core_udimm_check_mc_ecc_err(mci);
1796 else
1797 i7core_rdimm_check_mc_ecc_err(mci);
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001798}
1799
1800/*
Tony Luck53595342016-04-28 07:52:11 -07001801 * Check that logging is enabled and that this is the right type
1802 * of error for us to handle.
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001803 */
Borislav Petkov4140c542011-07-18 11:24:46 -03001804static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
1805 void *data)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001806{
Borislav Petkov4140c542011-07-18 11:24:46 -03001807 struct mce *mce = (struct mce *)data;
1808 struct i7core_dev *i7_dev;
1809 struct mem_ctl_info *mci;
1810 struct i7core_pvt *pvt;
1811
1812 i7_dev = get_i7core_dev(mce->socketid);
1813 if (!i7_dev)
Tony Luckc4fc1952016-04-29 15:42:25 +02001814 return NOTIFY_DONE;
Borislav Petkov4140c542011-07-18 11:24:46 -03001815
1816 mci = i7_dev->mci;
1817 pvt = mci->pvt_info;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001818
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001819 /*
1820 * Just let mcelog handle it if the error is
1821 * outside the memory controller
1822 */
1823 if (((mce->status & 0xffff) >> 7) != 1)
Borislav Petkov4140c542011-07-18 11:24:46 -03001824 return NOTIFY_DONE;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001825
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001826 /* Bank 8 registers are the only ones that we know how to handle */
1827 if (mce->bank != 8)
Borislav Petkov4140c542011-07-18 11:24:46 -03001828 return NOTIFY_DONE;
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001829
Tony Luck53595342016-04-28 07:52:11 -07001830 i7core_check_error(mci, mce);
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001831
David Sterbae7bf0682010-12-27 16:51:15 +01001832 /* Advise mcelog that the errors were handled */
Borislav Petkov4140c542011-07-18 11:24:46 -03001833 return NOTIFY_STOP;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001834}
1835
Borislav Petkov4140c542011-07-18 11:24:46 -03001836static struct notifier_block i7_mce_dec = {
1837 .notifier_call = i7core_mce_check_error,
1838};
1839
Nils Carlson535e9c72011-08-08 06:21:26 -03001840struct memdev_dmi_entry {
1841 u8 type;
1842 u8 length;
1843 u16 handle;
1844 u16 phys_mem_array_handle;
1845 u16 mem_err_info_handle;
1846 u16 total_width;
1847 u16 data_width;
1848 u16 size;
1849 u8 form;
1850 u8 device_set;
1851 u8 device_locator;
1852 u8 bank_locator;
1853 u8 memory_type;
1854 u16 type_detail;
1855 u16 speed;
1856 u8 manufacturer;
1857 u8 serial_number;
1858 u8 asset_tag;
1859 u8 part_number;
1860 u8 attributes;
1861 u32 extended_size;
1862 u16 conf_mem_clk_speed;
1863} __attribute__((__packed__));
1864
1865
1866/*
1867 * Decode the DRAM Clock Frequency, be paranoid, make sure that all
1868 * memory devices show the same speed, and if they don't then consider
1869 * all speeds to be invalid.
1870 */
1871static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
1872{
1873 int *dclk_freq = _dclk_freq;
1874 u16 dmi_mem_clk_speed;
1875
1876 if (*dclk_freq == -1)
1877 return;
1878
1879 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
1880 struct memdev_dmi_entry *memdev_dmi_entry =
1881 (struct memdev_dmi_entry *)dh;
1882 unsigned long conf_mem_clk_speed_offset =
1883 (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
1884 (unsigned long)&memdev_dmi_entry->type;
1885 unsigned long speed_offset =
1886 (unsigned long)&memdev_dmi_entry->speed -
1887 (unsigned long)&memdev_dmi_entry->type;
1888
1889 /* Check that a DIMM is present */
1890 if (memdev_dmi_entry->size == 0)
1891 return;
1892
1893 /*
1894 * Pick the configured speed if it's available, otherwise
1895 * pick the DIMM speed, or we don't have a speed.
1896 */
1897 if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
1898 dmi_mem_clk_speed =
1899 memdev_dmi_entry->conf_mem_clk_speed;
1900 } else if (memdev_dmi_entry->length > speed_offset) {
1901 dmi_mem_clk_speed = memdev_dmi_entry->speed;
1902 } else {
1903 *dclk_freq = -1;
1904 return;
1905 }
1906
1907 if (*dclk_freq == 0) {
1908 /* First pass, speed was 0 */
1909 if (dmi_mem_clk_speed > 0) {
1910 /* Set speed if a valid speed is read */
1911 *dclk_freq = dmi_mem_clk_speed;
1912 } else {
1913 /* Otherwise we don't have a valid speed */
1914 *dclk_freq = -1;
1915 }
1916 } else if (*dclk_freq > 0 &&
1917 *dclk_freq != dmi_mem_clk_speed) {
1918 /*
1919 * If we have a speed, check that all DIMMS are the same
1920 * speed, otherwise set the speed as invalid.
1921 */
1922 *dclk_freq = -1;
1923 }
1924 }
1925}
1926
1927/*
1928 * The default DCLK frequency is used as a fallback if we
1929 * fail to find anything reliable in the DMI. The value
1930 * is taken straight from the datasheet.
1931 */
1932#define DEFAULT_DCLK_FREQ 800
1933
1934static int get_dclk_freq(void)
1935{
1936 int dclk_freq = 0;
1937
1938 dmi_walk(decode_dclk, (void *)&dclk_freq);
1939
1940 if (dclk_freq < 1)
1941 return DEFAULT_DCLK_FREQ;
1942
1943 return dclk_freq;
1944}
1945
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001946/*
1947 * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
1948 * to hardware according to SCRUBINTERVAL formula
1949 * found in datasheet.
1950 */
1951static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
1952{
1953 struct i7core_pvt *pvt = mci->pvt_info;
1954 struct pci_dev *pdev;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001955 u32 dw_scrub;
1956 u32 dw_ssr;
1957
1958 /* Get data from the MC register, function 2 */
1959 pdev = pvt->pci_mcr[2];
1960 if (!pdev)
1961 return -ENODEV;
1962
1963 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);
1964
1965 if (new_bw == 0) {
1966 /* Prepare to disable petrol scrub */
1967 dw_scrub &= ~STARTSCRUB;
1968 /* Stop the patrol scrub engine */
Nils Carlson535e9c72011-08-08 06:21:26 -03001969 write_and_test(pdev, MC_SCRUB_CONTROL,
1970 dw_scrub & ~SCRUBINTERVAL_MASK);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001971
1972 /* Get current status of scrub rate and set bit to disable */
1973 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
1974 dw_ssr &= ~SSR_MODE_MASK;
1975 dw_ssr |= SSR_MODE_DISABLE;
1976 } else {
Nils Carlson535e9c72011-08-08 06:21:26 -03001977 const int cache_line_size = 64;
1978 const u32 freq_dclk_mhz = pvt->dclk_freq;
1979 unsigned long long scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001980 /*
1981 * Translate the desired scrub rate to a register value and
Nils Carlson535e9c72011-08-08 06:21:26 -03001982 * program the corresponding register value.
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001983 */
Nils Carlson535e9c72011-08-08 06:21:26 -03001984 scrub_interval = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03001985 cache_line_size * 1000000;
1986 do_div(scrub_interval, new_bw);
Nils Carlson535e9c72011-08-08 06:21:26 -03001987
1988 if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
1989 return -EINVAL;
1990
1991 dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001992
1993 /* Start the patrol scrub engine */
1994 pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
1995 STARTSCRUB | dw_scrub);
1996
1997 /* Get current status of scrub rate and set bit to enable */
1998 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
1999 dw_ssr &= ~SSR_MODE_MASK;
2000 dw_ssr |= SSR_MODE_ENABLE;
2001 }
2002 /* Disable or enable scrubbing */
2003 pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);
2004
2005 return new_bw;
2006}
2007
2008/*
2009 * get_sdram_scrub_rate This routine convert current scrub rate value
David Mackey15ed1032012-04-17 11:30:52 -07002010 * into byte/sec bandwidth according to
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002011 * SCRUBINTERVAL formula found in datasheet.
2012 */
2013static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
2014{
2015 struct i7core_pvt *pvt = mci->pvt_info;
2016 struct pci_dev *pdev;
2017 const u32 cache_line_size = 64;
Nils Carlson535e9c72011-08-08 06:21:26 -03002018 const u32 freq_dclk_mhz = pvt->dclk_freq;
2019 unsigned long long scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002020 u32 scrubval;
2021
2022 /* Get data from the MC register, function 2 */
2023 pdev = pvt->pci_mcr[2];
2024 if (!pdev)
2025 return -ENODEV;
2026
2027 /* Get current scrub control data */
2028 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
2029
2030 /* Mask highest 8-bits to 0 */
Nils Carlson535e9c72011-08-08 06:21:26 -03002031 scrubval &= SCRUBINTERVAL_MASK;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002032 if (!scrubval)
2033 return 0;
2034
2035 /* Calculate scrub rate value into byte/sec bandwidth */
Nils Carlson535e9c72011-08-08 06:21:26 -03002036 scrub_rate = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03002037 1000000 * cache_line_size;
2038 do_div(scrub_rate, scrubval);
Nils Carlson535e9c72011-08-08 06:21:26 -03002039 return (int)scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002040}
2041
2042static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
2043{
2044 struct i7core_pvt *pvt = mci->pvt_info;
2045 u32 pci_lock;
2046
2047 /* Unlock writes to pci registers */
2048 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2049 pci_lock &= ~0x3;
2050 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2051 pci_lock | MC_CFG_UNLOCK);
2052
2053 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
2054 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
2055}
2056
2057static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
2058{
2059 struct i7core_pvt *pvt = mci->pvt_info;
2060 u32 pci_lock;
2061
2062 /* Lock writes to pci registers */
2063 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2064 pci_lock &= ~0x3;
2065 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2066 pci_lock | MC_CFG_LOCK);
2067}
2068
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002069static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
2070{
2071 pvt->i7core_pci = edac_pci_create_generic_ctl(
2072 &pvt->i7core_dev->pdev[0]->dev,
2073 EDAC_MOD_STR);
2074 if (unlikely(!pvt->i7core_pci))
Mauro Carvalho Chehabf9902f22010-08-21 09:42:05 -03002075 i7core_printk(KERN_WARNING,
2076 "Unable to setup PCI error report via EDAC\n");
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002077}
2078
2079static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
2080{
2081 if (likely(pvt->i7core_pci))
2082 edac_pci_release_generic_ctl(pvt->i7core_pci);
2083 else
2084 i7core_printk(KERN_ERR,
2085 "Couldn't find mem_ctl_info for socket %d\n",
2086 pvt->i7core_dev->socket);
2087 pvt->i7core_pci = NULL;
2088}
2089
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002090static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2091{
2092 struct mem_ctl_info *mci = i7core_dev->mci;
2093 struct i7core_pvt *pvt;
2094
2095 if (unlikely(!mci || !mci->pvt_info)) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002096 edac_dbg(0, "MC: dev = %p\n", &i7core_dev->pdev[0]->dev);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002097
2098 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
2099 return;
2100 }
2101
2102 pvt = mci->pvt_info;
2103
Joe Perches956b9ba2012-04-29 17:08:39 -03002104 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002105
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002106 /* Disable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002107 if (pvt->enable_scrub)
2108 disable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002109
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002110 /* Disable EDAC polling */
2111 i7core_pci_ctl_release(pvt);
2112
2113 /* Remove MC sysfs nodes */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03002114 i7core_delete_sysfs_devices(mci);
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -03002115 edac_mc_del_mc(mci->pdev);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002116
Joe Perches956b9ba2012-04-29 17:08:39 -03002117 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002118 kfree(mci->ctl_name);
2119 edac_mc_free(mci);
2120 i7core_dev->mci = NULL;
2121}
2122
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002123static int i7core_register_mci(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002124{
2125 struct mem_ctl_info *mci;
2126 struct i7core_pvt *pvt;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03002127 int rc;
2128 struct edac_mc_layer layers[2];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002129
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002130 /* allocate a new MC control structure */
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03002131
2132 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2133 layers[0].size = NUM_CHANS;
2134 layers[0].is_virt_csrow = false;
2135 layers[1].type = EDAC_MC_LAYER_SLOT;
2136 layers[1].size = MAX_DIMMS;
2137 layers[1].is_virt_csrow = true;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -03002138 mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03002139 sizeof(*pvt));
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002140 if (unlikely(!mci))
2141 return -ENOMEM;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002142
Joe Perches956b9ba2012-04-29 17:08:39 -03002143 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002144
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002145 pvt = mci->pvt_info;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002146 memset(pvt, 0, sizeof(*pvt));
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03002147
Mauro Carvalho Chehab6d37d242010-08-20 12:48:26 -03002148 /* Associates i7core_dev and mci for future usage */
2149 pvt->i7core_dev = i7core_dev;
2150 i7core_dev->mci = mci;
2151
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002152 /*
2153 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
2154 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
2155 * memory channels
2156 */
2157 mci->mtype_cap = MEM_FLAG_DDR3;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002158 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2159 mci->edac_cap = EDAC_FLAG_NONE;
2160 mci->mod_name = "i7core_edac.c";
2161 mci->mod_ver = I7CORE_REVISION;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002162 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
2163 i7core_dev->socket);
2164 mci->dev_name = pci_name(i7core_dev->pdev[0]);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002165 mci->ctl_page_to_phys = NULL;
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03002166
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002167 /* Store pci devices at mci for faster access */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002168 rc = mci_bind_devs(mci, i7core_dev);
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002169 if (unlikely(rc < 0))
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002170 goto fail0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002171
Hidetoshi Seto59398132010-08-20 04:28:25 -03002172
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002173 /* Get dimm basic config */
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -03002174 get_dimm_config(mci);
Hidetoshi Seto59398132010-08-20 04:28:25 -03002175 /* record ptr to the generic device */
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -03002176 mci->pdev = &i7core_dev->pdev[0]->dev;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002177
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002178 /* Enable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002179 if (pvt->enable_scrub)
2180 enable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002181
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002182 /* add this new MC control structure to EDAC's list of MCs */
Takashi Iwai2eace182015-02-04 11:48:55 +01002183 if (unlikely(edac_mc_add_mc_with_groups(mci, i7core_dev_groups))) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002184 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002185 /* FIXME: perhaps some code should go here that disables error
2186 * reporting if we just enabled it
2187 */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002188
2189 rc = -EINVAL;
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002190 goto fail0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002191 }
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03002192 if (i7core_create_sysfs_devices(mci)) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002193 edac_dbg(0, "MC: failed to create sysfs nodes\n");
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03002194 edac_mc_del_mc(mci->pdev);
2195 rc = -EINVAL;
2196 goto fail0;
2197 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002198
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002199 /* Default error mask is any memory */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002200 pvt->inject.channel = 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002201 pvt->inject.dimm = -1;
2202 pvt->inject.rank = -1;
2203 pvt->inject.bank = -1;
2204 pvt->inject.page = -1;
2205 pvt->inject.col = -1;
2206
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002207 /* allocating generic PCI control info */
2208 i7core_pci_ctl_create(pvt);
2209
Nils Carlson535e9c72011-08-08 06:21:26 -03002210 /* DCLK for scrub rate setting */
2211 pvt->dclk_freq = get_dclk_freq();
2212
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002213 return 0;
2214
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002215fail0:
2216 kfree(mci->ctl_name);
2217 edac_mc_free(mci);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002218 i7core_dev->mci = NULL;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002219 return rc;
2220}
2221
2222/*
2223 * i7core_probe Probe for ONE instance of device to see if it is
2224 * present.
2225 * return:
2226 * 0 for FOUND a device
2227 * < 0 for error code
2228 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002229
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002230static int i7core_probe(struct pci_dev *pdev, const struct pci_device_id *id)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002231{
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002232 int rc, count = 0;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002233 struct i7core_dev *i7core_dev;
2234
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002235 /* get the pci devices we want to reserve for our use */
2236 mutex_lock(&i7core_edac_lock);
2237
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002238 /*
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002239 * All memory controllers are allocated at the first pass.
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002240 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002241 if (unlikely(probed >= 1)) {
2242 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehab76a7bd82010-10-24 11:36:19 -02002243 return -ENODEV;
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002244 }
2245 probed++;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03002246
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002247 rc = i7core_get_all_devices();
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002248 if (unlikely(rc < 0))
2249 goto fail0;
2250
2251 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002252 count++;
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002253 rc = i7core_register_mci(i7core_dev);
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002254 if (unlikely(rc < 0))
2255 goto fail1;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03002256 }
2257
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002258 /*
2259 * Nehalem-EX uses a different memory controller. However, as the
2260 * memory controller is not visible on some Nehalem/Nehalem-EP, we
2261 * need to indirectly probe via a X58 PCI device. The same devices
2262 * are found on (some) Nehalem-EX. So, on those machines, the
2263 * probe routine needs to return -ENODEV, as the actual Memory
2264 * Controller registers won't be detected.
2265 */
2266 if (!count) {
2267 rc = -ENODEV;
2268 goto fail1;
2269 }
2270
2271 i7core_printk(KERN_INFO,
2272 "Driver loaded, %d memory controller(s) found.\n",
2273 count);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03002274
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002275 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002276 return 0;
2277
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002278fail1:
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002279 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2280 i7core_unregister_mci(i7core_dev);
2281
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03002282 i7core_put_all_devices();
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002283fail0:
2284 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002285 return rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002286}
2287
2288/*
2289 * i7core_remove destructor for one instance of device
2290 *
2291 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002292static void i7core_remove(struct pci_dev *pdev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002293{
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002294 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002295
Joe Perches956b9ba2012-04-29 17:08:39 -03002296 edac_dbg(0, "\n");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002297
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002298 /*
2299 * we have a trouble here: pdev value for removal will be wrong, since
2300 * it will point to the X58 register used to detect that the machine
2301 * is a Nehalem or upper design. However, due to the way several PCI
2302 * devices are grouped together to provide MC functionality, we need
2303 * to use a different method for releasing the devices
2304 */
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03002305
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002306 mutex_lock(&i7core_edac_lock);
Hidetoshi Seto71fe0172010-08-20 04:29:47 -03002307
2308 if (unlikely(!probed)) {
2309 mutex_unlock(&i7core_edac_lock);
2310 return;
2311 }
2312
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002313 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2314 i7core_unregister_mci(i7core_dev);
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002315
2316 /* Release PCI resources */
2317 i7core_put_all_devices();
2318
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002319 probed--;
2320
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002321 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002322}
2323
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002324MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2325
2326/*
2327 * i7core_driver pci_driver structure for this module
2328 *
2329 */
2330static struct pci_driver i7core_driver = {
2331 .name = "i7core_edac",
2332 .probe = i7core_probe,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002333 .remove = i7core_remove,
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002334 .id_table = i7core_pci_tbl,
2335};
2336
2337/*
2338 * i7core_init Module entry function
2339 * Try to initialize this module for its devices
2340 */
2341static int __init i7core_init(void)
2342{
2343 int pci_rc;
2344
Joe Perches956b9ba2012-04-29 17:08:39 -03002345 edac_dbg(2, "\n");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002346
2347 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2348 opstate_init();
2349
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03002350 if (use_pci_fixup)
2351 i7core_xeon_pci_fixup(pci_dev_table);
Keith Manntheybc2d7242009-09-03 00:05:05 -03002352
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002353 pci_rc = pci_register_driver(&i7core_driver);
2354
Chen Gonge35fca42012-05-08 20:40:12 -03002355 if (pci_rc >= 0) {
2356 mce_register_decode_chain(&i7_mce_dec);
Mauro Carvalho Chehab3ef288a2009-09-02 23:43:33 -03002357 return 0;
Chen Gonge35fca42012-05-08 20:40:12 -03002358 }
Mauro Carvalho Chehab3ef288a2009-09-02 23:43:33 -03002359
2360 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2361 pci_rc);
2362
2363 return pci_rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002364}
2365
2366/*
2367 * i7core_exit() Module exit function
2368 * Unregister the driver
2369 */
2370static void __exit i7core_exit(void)
2371{
Joe Perches956b9ba2012-04-29 17:08:39 -03002372 edac_dbg(2, "\n");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002373 pci_unregister_driver(&i7core_driver);
Chen Gonge35fca42012-05-08 20:40:12 -03002374 mce_unregister_decode_chain(&i7_mce_dec);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002375}
2376
2377module_init(i7core_init);
2378module_exit(i7core_exit);
2379
2380MODULE_LICENSE("GPL");
Mauro Carvalho Chehab37e59f82014-02-07 08:03:07 -02002381MODULE_AUTHOR("Mauro Carvalho Chehab");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002382MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2383MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2384 I7CORE_REVISION);
2385
2386module_param(edac_op_state, int, 0444);
2387MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");