blob: 4e24edccb30d0d964dfc675b57433860620dd766 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __ASM_SH_HITACHI_SE7300_H
2#define __ASM_SH_HITACHI_SE7300_H
3
4/*
5 * linux/include/asm-sh/se/se7300.h
6 *
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
8 *
9 * SH-Mobile SolutionEngine 7300 support
10 */
11
12/* Box specific addresses. */
13
14/* Area 0 */
15#define PA_ROM 0x00000000 /* EPROM */
16#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
17#define PA_FROM 0x00400000 /* Flash ROM */
18#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
19#define PA_SRAM 0x00800000 /* SRAM */
20#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
21/* Area 1 */
22#define PA_EXT1 0x04000000
23#define PA_EXT1_SIZE 0x04000000
24/* Area 2 */
25#define PA_EXT2 0x08000000
26#define PA_EXT2_SIZE 0x04000000
27/* Area 3 */
28#define PA_SDRAM 0x0c000000
29#define PA_SDRAM_SIZE 0x04000000
30/* Area 4 */
31#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
32#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
33#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
34#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
35#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
36#define MRSHPC_OPTION (PA_MRSHPC + 6)
37#define MRSHPC_CSR (PA_MRSHPC + 8)
38#define MRSHPC_ISR (PA_MRSHPC + 10)
39#define MRSHPC_ICR (PA_MRSHPC + 12)
40#define MRSHPC_CPWCR (PA_MRSHPC + 14)
41#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
42#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
43#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
44#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
45#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
46#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
47#define MRSHPC_CDCR (PA_MRSHPC + 28)
48#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49#define PA_LED 0xb0800000 /* LED */
50#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
51#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */
52#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */
53#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */
54/* Area 5 */
55#define PA_EXT5 0x14000000
56#define PA_EXT5_SIZE 0x04000000
57/* Area 6 */
58#define PA_LCD1 0xb8000000
59#define PA_LCD2 0xb8800000
60
Paul Mundt373e68b2006-09-27 15:41:24 +090061#define __IO_PREFIX sh7300se
62#include <asm/io_generic.h>
63
Linus Torvalds1da177e2005-04-16 15:20:36 -070064#endif /* __ASM_SH_HITACHI_SE7300_H */