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Philipp Zabel1c44f5f2008-02-04 22:28:22 -08001/*
Eric Miao38f539a2009-01-20 12:09:06 +08002 * linux/arch/arm/plat-pxa/gpio.c
Philipp Zabel1c44f5f2008-02-04 22:28:22 -08003 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080014#include <linux/module.h>
Haojian Zhuang389eda12011-10-17 21:26:55 +080015#include <linux/clk.h>
16#include <linux/err.h>
Russell King2f8163b2011-07-26 10:53:52 +010017#include <linux/gpio.h>
Haojian Zhuang157d2642011-10-17 20:37:52 +080018#include <linux/gpio-pxa.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080019#include <linux/init.h>
eric miaoe3630db2008-03-04 11:42:26 +080020#include <linux/irq.h>
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080021#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000022#include <linux/irqchip/chained_irq.h>
Russell Kingfced80c2008-09-06 12:10:45 +010023#include <linux/io.h>
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080024#include <linux/of.h>
25#include <linux/of_device.h>
Haojian Zhuang157d2642011-10-17 20:37:52 +080026#include <linux/platform_device.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020027#include <linux/syscore_ops.h>
Daniel Mack4aa78262009-06-19 22:56:09 +020028#include <linux/slab.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080029
Rob Herringfeefe732012-01-03 15:52:42 -060030#include <mach/irqs.h>
31
Haojian Zhuang157d2642011-10-17 20:37:52 +080032/*
33 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
34 * one set of registers. The register offsets are organized below:
35 *
36 * GPLR GPDR GPSR GPCR GRER GFER GEDR
37 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
38 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
39 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
40 *
41 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
42 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
43 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
44 *
45 * NOTE:
46 * BANK 3 is only available on PXA27x and later processors.
47 * BANK 4 and 5 are only available on PXA935
48 */
49
50#define GPLR_OFFSET 0x00
51#define GPDR_OFFSET 0x0C
52#define GPSR_OFFSET 0x18
53#define GPCR_OFFSET 0x24
54#define GRER_OFFSET 0x30
55#define GFER_OFFSET 0x3C
56#define GEDR_OFFSET 0x48
57#define GAFR_OFFSET 0x54
Haojian Zhuangbe241682011-10-17 21:07:15 +080058#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
Haojian Zhuang157d2642011-10-17 20:37:52 +080059
60#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080061
Eric Miao3b8e2852009-01-07 11:30:49 +080062int pxa_last_gpio;
Daniel Mack9450be72012-07-22 16:55:44 +020063static int irq_base;
Eric Miao3b8e2852009-01-07 11:30:49 +080064
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080065#ifdef CONFIG_OF
66static struct irq_domain *domain;
Daniel Mack72121572012-07-25 17:35:39 +020067static struct device_node *pxa_gpio_of_node;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080068#endif
69
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080070struct pxa_gpio_chip {
71 struct gpio_chip chip;
Eric Miao0807da52009-01-07 18:01:51 +080072 void __iomem *regbase;
73 char label[10];
74
75 unsigned long irq_mask;
76 unsigned long irq_edge_rise;
77 unsigned long irq_edge_fall;
Robert Jarzmikb95ace52012-04-22 13:37:24 +020078 int (*set_wake)(unsigned int gpio, unsigned int on);
Eric Miao0807da52009-01-07 18:01:51 +080079
80#ifdef CONFIG_PM
81 unsigned long saved_gplr;
82 unsigned long saved_gpdr;
83 unsigned long saved_grer;
84 unsigned long saved_gfer;
85#endif
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080086};
87
Haojian Zhuang2cab0292013-04-07 16:44:33 +080088enum pxa_gpio_type {
Haojian Zhuang4929f5a2011-10-10 16:03:51 +080089 PXA25X_GPIO = 0,
90 PXA26X_GPIO,
91 PXA27X_GPIO,
92 PXA3XX_GPIO,
93 PXA93X_GPIO,
94 MMP_GPIO = 0x10,
Haojian Zhuang2cab0292013-04-07 16:44:33 +080095 MMP2_GPIO,
96};
97
98struct pxa_gpio_id {
99 enum pxa_gpio_type type;
100 int gpio_nums;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800101};
102
Eric Miao0807da52009-01-07 18:01:51 +0800103static DEFINE_SPINLOCK(gpio_lock);
104static struct pxa_gpio_chip *pxa_gpio_chips;
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800105static enum pxa_gpio_type gpio_type;
Haojian Zhuang157d2642011-10-17 20:37:52 +0800106static void __iomem *gpio_reg_base;
Eric Miao0807da52009-01-07 18:01:51 +0800107
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800108static struct pxa_gpio_id pxa25x_id = {
109 .type = PXA25X_GPIO,
110 .gpio_nums = 85,
111};
112
113static struct pxa_gpio_id pxa26x_id = {
114 .type = PXA26X_GPIO,
115 .gpio_nums = 90,
116};
117
118static struct pxa_gpio_id pxa27x_id = {
119 .type = PXA27X_GPIO,
120 .gpio_nums = 121,
121};
122
123static struct pxa_gpio_id pxa3xx_id = {
124 .type = PXA3XX_GPIO,
125 .gpio_nums = 128,
126};
127
128static struct pxa_gpio_id pxa93x_id = {
129 .type = PXA93X_GPIO,
130 .gpio_nums = 192,
131};
132
133static struct pxa_gpio_id mmp_id = {
134 .type = MMP_GPIO,
135 .gpio_nums = 128,
136};
137
138static struct pxa_gpio_id mmp2_id = {
139 .type = MMP2_GPIO,
140 .gpio_nums = 192,
141};
142
Eric Miao0807da52009-01-07 18:01:51 +0800143#define for_each_gpio_chip(i, c) \
144 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
145
146static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
147{
148 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
149}
150
Linus Walleija0656852011-06-13 10:42:19 +0200151static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
Eric Miao0807da52009-01-07 18:01:51 +0800152{
153 return &pxa_gpio_chips[gpio_to_bank(gpio)];
154}
155
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800156static inline int gpio_is_pxa_type(int type)
157{
158 return (type & MMP_GPIO) == 0;
159}
160
161static inline int gpio_is_mmp_type(int type)
162{
163 return (type & MMP_GPIO) != 0;
164}
165
Haojian Zhuang157d2642011-10-17 20:37:52 +0800166/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
167 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
168 */
169static inline int __gpio_is_inverted(int gpio)
170{
171 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
172 return 1;
173 return 0;
174}
175
176/*
177 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
178 * function of a GPIO, and GPDRx cannot be altered once configured. It
179 * is attributed as "occupied" here (I know this terminology isn't
180 * accurate, you are welcome to propose a better one :-)
181 */
182static inline int __gpio_is_occupied(unsigned gpio)
183{
184 struct pxa_gpio_chip *pxachip;
185 void __iomem *base;
186 unsigned long gafr = 0, gpdr = 0;
187 int ret, af = 0, dir = 0;
188
189 pxachip = gpio_to_pxachip(gpio);
190 base = gpio_chip_base(&pxachip->chip);
191 gpdr = readl_relaxed(base + GPDR_OFFSET);
192
193 switch (gpio_type) {
194 case PXA25X_GPIO:
195 case PXA26X_GPIO:
196 case PXA27X_GPIO:
197 gafr = readl_relaxed(base + GAFR_OFFSET);
198 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
199 dir = gpdr & GPIO_bit(gpio);
200
201 if (__gpio_is_inverted(gpio))
202 ret = (af != 1) || (dir == 0);
203 else
204 ret = (af != 0) || (dir != 0);
205 break;
206 default:
207 ret = gpdr & GPIO_bit(gpio);
208 break;
209 }
210 return ret;
211}
212
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800213static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
214{
Daniel Mack9450be72012-07-22 16:55:44 +0200215 return chip->base + offset + irq_base;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800216}
217
218int pxa_irq_to_gpio(int irq)
219{
Daniel Mack9450be72012-07-22 16:55:44 +0200220 return irq - irq_base;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800221}
222
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800223static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
224{
Eric Miao0807da52009-01-07 18:01:51 +0800225 void __iomem *base = gpio_chip_base(chip);
226 uint32_t value, mask = 1 << offset;
227 unsigned long flags;
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800228
Eric Miao0807da52009-01-07 18:01:51 +0800229 spin_lock_irqsave(&gpio_lock, flags);
230
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800231 value = readl_relaxed(base + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800232 if (__gpio_is_inverted(chip->base + offset))
233 value |= mask;
234 else
235 value &= ~mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800236 writel_relaxed(value, base + GPDR_OFFSET);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800237
Eric Miao0807da52009-01-07 18:01:51 +0800238 spin_unlock_irqrestore(&gpio_lock, flags);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800239 return 0;
240}
241
242static int pxa_gpio_direction_output(struct gpio_chip *chip,
Eric Miao0807da52009-01-07 18:01:51 +0800243 unsigned offset, int value)
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800244{
Eric Miao0807da52009-01-07 18:01:51 +0800245 void __iomem *base = gpio_chip_base(chip);
246 uint32_t tmp, mask = 1 << offset;
247 unsigned long flags;
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800248
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800249 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
Eric Miao0807da52009-01-07 18:01:51 +0800250
251 spin_lock_irqsave(&gpio_lock, flags);
252
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800253 tmp = readl_relaxed(base + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800254 if (__gpio_is_inverted(chip->base + offset))
255 tmp &= ~mask;
256 else
257 tmp |= mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800258 writel_relaxed(tmp, base + GPDR_OFFSET);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800259
Eric Miao0807da52009-01-07 18:01:51 +0800260 spin_unlock_irqrestore(&gpio_lock, flags);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800261 return 0;
262}
263
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800264static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
265{
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800266 return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800267}
268
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800269static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
270{
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800271 writel_relaxed(1 << offset, gpio_chip_base(chip) +
Eric Miao0807da52009-01-07 18:01:51 +0800272 (value ? GPSR_OFFSET : GPCR_OFFSET));
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800273}
274
Daniel Mack72121572012-07-25 17:35:39 +0200275#ifdef CONFIG_OF_GPIO
276static int pxa_gpio_of_xlate(struct gpio_chip *gc,
277 const struct of_phandle_args *gpiospec,
278 u32 *flags)
279{
280 if (gpiospec->args[0] > pxa_last_gpio)
281 return -EINVAL;
282
283 if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip)
284 return -EINVAL;
285
286 if (flags)
287 *flags = gpiospec->args[1];
288
289 return gpiospec->args[0] % 32;
290}
291#endif
292
Bill Pemberton38363092012-11-19 13:22:34 -0500293static int pxa_init_gpio_chip(int gpio_end,
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200294 int (*set_wake)(unsigned int, unsigned int))
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800295{
Eric Miao0807da52009-01-07 18:01:51 +0800296 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
297 struct pxa_gpio_chip *chips;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800298
Daniel Mack4aa78262009-06-19 22:56:09 +0200299 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
Eric Miao0807da52009-01-07 18:01:51 +0800300 if (chips == NULL) {
301 pr_err("%s: failed to allocate GPIO chips\n", __func__);
302 return -ENOMEM;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800303 }
Eric Miao0807da52009-01-07 18:01:51 +0800304
305 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
306 struct gpio_chip *c = &chips[i].chip;
307
308 sprintf(chips[i].label, "gpio-%d", i);
Haojian Zhuang157d2642011-10-17 20:37:52 +0800309 chips[i].regbase = gpio_reg_base + BANK_OFF(i);
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200310 chips[i].set_wake = set_wake;
Eric Miao0807da52009-01-07 18:01:51 +0800311
312 c->base = gpio;
313 c->label = chips[i].label;
314
315 c->direction_input = pxa_gpio_direction_input;
316 c->direction_output = pxa_gpio_direction_output;
317 c->get = pxa_gpio_get;
318 c->set = pxa_gpio_set;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800319 c->to_irq = pxa_gpio_to_irq;
Daniel Mack72121572012-07-25 17:35:39 +0200320#ifdef CONFIG_OF_GPIO
321 c->of_node = pxa_gpio_of_node;
322 c->of_xlate = pxa_gpio_of_xlate;
323 c->of_gpio_n_cells = 2;
324#endif
Eric Miao0807da52009-01-07 18:01:51 +0800325
326 /* number of GPIOs on last bank may be less than 32 */
327 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
328 gpiochip_add(c);
329 }
330 pxa_gpio_chips = chips;
331 return 0;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800332}
333
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800334/* Update only those GRERx and GFERx edge detection register bits if those
335 * bits are set in c->irq_mask
336 */
337static inline void update_edge_detect(struct pxa_gpio_chip *c)
338{
339 uint32_t grer, gfer;
340
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800341 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
342 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800343 grer |= c->irq_edge_rise & c->irq_mask;
344 gfer |= c->irq_edge_fall & c->irq_mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800345 writel_relaxed(grer, c->regbase + GRER_OFFSET);
346 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800347}
348
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100349static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
eric miaoe3630db2008-03-04 11:42:26 +0800350{
Eric Miao0807da52009-01-07 18:01:51 +0800351 struct pxa_gpio_chip *c;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800352 int gpio = pxa_irq_to_gpio(d->irq);
Eric Miao0807da52009-01-07 18:01:51 +0800353 unsigned long gpdr, mask = GPIO_bit(gpio);
eric miaoe3630db2008-03-04 11:42:26 +0800354
Linus Walleija0656852011-06-13 10:42:19 +0200355 c = gpio_to_pxachip(gpio);
eric miaoe3630db2008-03-04 11:42:26 +0800356
357 if (type == IRQ_TYPE_PROBE) {
358 /* Don't mess with enabled GPIOs using preconfigured edges or
359 * GPIOs set to alternate function or to output during probe
360 */
Eric Miao0807da52009-01-07 18:01:51 +0800361 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
eric miaoe3630db2008-03-04 11:42:26 +0800362 return 0;
eric miao689c04a2008-03-04 17:18:38 +0800363
364 if (__gpio_is_occupied(gpio))
eric miaoe3630db2008-03-04 11:42:26 +0800365 return 0;
eric miao689c04a2008-03-04 17:18:38 +0800366
eric miaoe3630db2008-03-04 11:42:26 +0800367 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
368 }
369
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800370 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
Eric Miao0807da52009-01-07 18:01:51 +0800371
Eric Miao067455a2008-11-26 18:12:04 +0800372 if (__gpio_is_inverted(gpio))
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800373 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800374 else
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800375 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800376
377 if (type & IRQ_TYPE_EDGE_RISING)
Eric Miao0807da52009-01-07 18:01:51 +0800378 c->irq_edge_rise |= mask;
eric miaoe3630db2008-03-04 11:42:26 +0800379 else
Eric Miao0807da52009-01-07 18:01:51 +0800380 c->irq_edge_rise &= ~mask;
eric miaoe3630db2008-03-04 11:42:26 +0800381
382 if (type & IRQ_TYPE_EDGE_FALLING)
Eric Miao0807da52009-01-07 18:01:51 +0800383 c->irq_edge_fall |= mask;
eric miaoe3630db2008-03-04 11:42:26 +0800384 else
Eric Miao0807da52009-01-07 18:01:51 +0800385 c->irq_edge_fall &= ~mask;
eric miaoe3630db2008-03-04 11:42:26 +0800386
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800387 update_edge_detect(c);
eric miaoe3630db2008-03-04 11:42:26 +0800388
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100389 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
eric miaoe3630db2008-03-04 11:42:26 +0800390 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
391 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
392 return 0;
393}
394
eric miaoe3630db2008-03-04 11:42:26 +0800395static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
396{
Eric Miao0807da52009-01-07 18:01:51 +0800397 struct pxa_gpio_chip *c;
398 int loop, gpio, gpio_base, n;
399 unsigned long gedr;
Chao Xie0d2ee5d2012-07-31 14:13:09 +0800400 struct irq_chip *chip = irq_desc_get_chip(desc);
401
402 chained_irq_enter(chip, desc);
eric miaoe3630db2008-03-04 11:42:26 +0800403
404 do {
eric miaoe3630db2008-03-04 11:42:26 +0800405 loop = 0;
Eric Miao0807da52009-01-07 18:01:51 +0800406 for_each_gpio_chip(gpio, c) {
407 gpio_base = c->chip.base;
eric miaoe3630db2008-03-04 11:42:26 +0800408
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800409 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
Eric Miao0807da52009-01-07 18:01:51 +0800410 gedr = gedr & c->irq_mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800411 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800412
Wei Yongjund724f1c2012-09-14 10:36:59 +0800413 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
Eric Miao0807da52009-01-07 18:01:51 +0800414 loop = 1;
415
416 generic_handle_irq(gpio_to_irq(gpio_base + n));
Eric Miao0807da52009-01-07 18:01:51 +0800417 }
eric miaoe3630db2008-03-04 11:42:26 +0800418 }
419 } while (loop);
Chao Xie0d2ee5d2012-07-31 14:13:09 +0800420
421 chained_irq_exit(chip, desc);
eric miaoe3630db2008-03-04 11:42:26 +0800422}
423
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100424static void pxa_ack_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800425{
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800426 int gpio = pxa_irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200427 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800428
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800429 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800430}
431
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100432static void pxa_mask_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800433{
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800434 int gpio = pxa_irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200435 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800436 uint32_t grer, gfer;
437
438 c->irq_mask &= ~GPIO_bit(gpio);
439
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800440 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
441 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
442 writel_relaxed(grer, c->regbase + GRER_OFFSET);
443 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800444}
445
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200446static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
447{
448 int gpio = pxa_irq_to_gpio(d->irq);
449 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
450
451 if (c->set_wake)
452 return c->set_wake(gpio, on);
453 else
454 return 0;
455}
456
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100457static void pxa_unmask_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800458{
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800459 int gpio = pxa_irq_to_gpio(d->irq);
Linus Walleija0656852011-06-13 10:42:19 +0200460 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800461
462 c->irq_mask |= GPIO_bit(gpio);
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800463 update_edge_detect(c);
eric miaoe3630db2008-03-04 11:42:26 +0800464}
465
466static struct irq_chip pxa_muxed_gpio_chip = {
467 .name = "GPIO",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100468 .irq_ack = pxa_ack_muxed_gpio,
469 .irq_mask = pxa_mask_muxed_gpio,
470 .irq_unmask = pxa_unmask_muxed_gpio,
471 .irq_set_type = pxa_gpio_irq_type,
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200472 .irq_set_wake = pxa_gpio_set_wake,
eric miaoe3630db2008-03-04 11:42:26 +0800473};
474
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800475static int pxa_gpio_nums(struct platform_device *pdev)
Haojian Zhuang478e2232011-10-14 16:44:07 +0800476{
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800477 const struct platform_device_id *id = platform_get_device_id(pdev);
478 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
Haojian Zhuang478e2232011-10-14 16:44:07 +0800479 int count = 0;
480
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800481 switch (pxa_id->type) {
482 case PXA25X_GPIO:
483 case PXA26X_GPIO:
484 case PXA27X_GPIO:
485 case PXA3XX_GPIO:
486 case PXA93X_GPIO:
487 case MMP_GPIO:
488 case MMP2_GPIO:
489 gpio_type = pxa_id->type;
490 count = pxa_id->gpio_nums - 1;
491 break;
492 default:
493 count = -EINVAL;
494 break;
Haojian Zhuang478e2232011-10-14 16:44:07 +0800495 }
Haojian Zhuang478e2232011-10-14 16:44:07 +0800496 return count;
497}
498
Arnd Bergmannf43e04e2012-08-13 14:36:10 +0000499#ifdef CONFIG_OF
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800500static struct of_device_id pxa_gpio_dt_ids[] = {
Haojian Zhuangf8731172013-04-09 22:27:50 +0800501 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
502 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
503 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
504 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
505 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
506 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
507 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800508 {}
509};
510
511static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
512 irq_hw_number_t hw)
513{
514 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
515 handle_edge_irq);
516 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
517 return 0;
518}
519
520const struct irq_domain_ops pxa_irq_domain_ops = {
521 .map = pxa_irq_domain_map,
Daniel Mack72121572012-07-25 17:35:39 +0200522 .xlate = irq_domain_xlate_twocell,
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800523};
524
Bill Pemberton38363092012-11-19 13:22:34 -0500525static int pxa_gpio_probe_dt(struct platform_device *pdev)
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800526{
Haojian Zhuangf8731172013-04-09 22:27:50 +0800527 int ret, nr_gpios;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800528 struct device_node *prev, *next, *np = pdev->dev.of_node;
529 const struct of_device_id *of_id =
530 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
Haojian Zhuangf8731172013-04-09 22:27:50 +0800531 const struct pxa_gpio_id *gpio_id;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800532
Haojian Zhuangf8731172013-04-09 22:27:50 +0800533 if (!of_id || !of_id->data) {
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800534 dev_err(&pdev->dev, "Failed to find gpio controller\n");
535 return -EFAULT;
536 }
Haojian Zhuangf8731172013-04-09 22:27:50 +0800537 gpio_id = of_id->data;
538 gpio_type = gpio_id->type;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800539
540 next = of_get_next_child(np, NULL);
541 prev = next;
542 if (!next) {
543 dev_err(&pdev->dev, "Failed to find child gpio node\n");
544 ret = -EINVAL;
545 goto err;
546 }
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800547 of_node_put(prev);
Haojian Zhuangf8731172013-04-09 22:27:50 +0800548 nr_gpios = gpio_id->gpio_nums;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800549 pxa_last_gpio = nr_gpios - 1;
550
551 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
552 if (irq_base < 0) {
553 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
554 goto err;
555 }
556 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
557 &pxa_irq_domain_ops, NULL);
Daniel Mack72121572012-07-25 17:35:39 +0200558 pxa_gpio_of_node = np;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800559 return 0;
560err:
561 iounmap(gpio_reg_base);
562 return ret;
563}
564#else
565#define pxa_gpio_probe_dt(pdev) (-1)
566#endif
567
Bill Pemberton38363092012-11-19 13:22:34 -0500568static int pxa_gpio_probe(struct platform_device *pdev)
eric miaoe3630db2008-03-04 11:42:26 +0800569{
Eric Miao0807da52009-01-07 18:01:51 +0800570 struct pxa_gpio_chip *c;
Haojian Zhuang157d2642011-10-17 20:37:52 +0800571 struct resource *res;
Haojian Zhuang389eda12011-10-17 21:26:55 +0800572 struct clk *clk;
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200573 struct pxa_gpio_platform_data *info;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800574 int gpio, irq, ret, use_of = 0;
Haojian Zhuang157d2642011-10-17 20:37:52 +0800575 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
eric miaoe3630db2008-03-04 11:42:26 +0800576
Haojian Zhuangb8f649f2013-04-09 18:12:04 +0800577 info = dev_get_platdata(&pdev->dev);
578 if (info) {
579 irq_base = info->irq_base;
580 if (irq_base <= 0)
581 return -EINVAL;
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800582 pxa_last_gpio = pxa_gpio_nums(pdev);
Daniel Mack9450be72012-07-22 16:55:44 +0200583 } else {
Haojian Zhuangb8f649f2013-04-09 18:12:04 +0800584 irq_base = 0;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800585 use_of = 1;
Haojian Zhuangb8f649f2013-04-09 18:12:04 +0800586 ret = pxa_gpio_probe_dt(pdev);
587 if (ret < 0)
588 return -EINVAL;
Daniel Mack9450be72012-07-22 16:55:44 +0200589 }
590
Haojian Zhuang478e2232011-10-14 16:44:07 +0800591 if (!pxa_last_gpio)
Haojian Zhuang157d2642011-10-17 20:37:52 +0800592 return -EINVAL;
593
594 irq0 = platform_get_irq_byname(pdev, "gpio0");
595 irq1 = platform_get_irq_byname(pdev, "gpio1");
596 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
597 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
598 || (irq_mux <= 0))
599 return -EINVAL;
600 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
601 if (!res)
602 return -EINVAL;
603 gpio_reg_base = ioremap(res->start, resource_size(res));
604 if (!gpio_reg_base)
605 return -EINVAL;
606
607 if (irq0 > 0)
608 gpio_offset = 2;
eric miaoe3630db2008-03-04 11:42:26 +0800609
Haojian Zhuang389eda12011-10-17 21:26:55 +0800610 clk = clk_get(&pdev->dev, NULL);
611 if (IS_ERR(clk)) {
612 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
613 PTR_ERR(clk));
614 iounmap(gpio_reg_base);
615 return PTR_ERR(clk);
616 }
Julia Lawall6ab49f42012-08-26 18:00:55 +0200617 ret = clk_prepare_enable(clk);
Haojian Zhuang389eda12011-10-17 21:26:55 +0800618 if (ret) {
619 clk_put(clk);
620 iounmap(gpio_reg_base);
621 return ret;
622 }
Haojian Zhuang389eda12011-10-17 21:26:55 +0800623
Eric Miao0807da52009-01-07 18:01:51 +0800624 /* Initialize GPIO chips */
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200625 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
Eric Miao0807da52009-01-07 18:01:51 +0800626
eric miaoe3630db2008-03-04 11:42:26 +0800627 /* clear all GPIO edge detects */
Eric Miao0807da52009-01-07 18:01:51 +0800628 for_each_gpio_chip(gpio, c) {
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800629 writel_relaxed(0, c->regbase + GFER_OFFSET);
630 writel_relaxed(0, c->regbase + GRER_OFFSET);
Laurent Navete37f4af2013-03-20 13:15:59 +0100631 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
Haojian Zhuangbe241682011-10-17 21:07:15 +0800632 /* unmask GPIO edge detect for AP side */
633 if (gpio_is_mmp_type(gpio_type))
634 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800635 }
636
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800637 if (!use_of) {
Haojian Zhuang87c49e22011-10-10 14:38:46 +0800638#ifdef CONFIG_ARCH_PXA
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800639 irq = gpio_to_irq(0);
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100640 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
641 handle_edge_irq);
eric miaoe3630db2008-03-04 11:42:26 +0800642 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800643 irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
644
645 irq = gpio_to_irq(1);
646 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
647 handle_edge_irq);
648 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
649 irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
650#endif
651
652 for (irq = gpio_to_irq(gpio_offset);
653 irq <= gpio_to_irq(pxa_last_gpio); irq++) {
654 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
655 handle_edge_irq);
656 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
657 }
eric miaoe3630db2008-03-04 11:42:26 +0800658 }
659
Haojian Zhuang157d2642011-10-17 20:37:52 +0800660 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
661 return 0;
eric miaoe3630db2008-03-04 11:42:26 +0800662}
eric miao663707c2008-03-04 16:13:58 +0800663
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800664static const struct platform_device_id gpio_id_table[] = {
665 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
666 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
667 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
668 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
669 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
670 { "mmp-gpio", (unsigned long)&mmp_id },
671 { "mmp2-gpio", (unsigned long)&mmp2_id },
672 { },
673};
674
Haojian Zhuang157d2642011-10-17 20:37:52 +0800675static struct platform_driver pxa_gpio_driver = {
676 .probe = pxa_gpio_probe,
677 .driver = {
678 .name = "pxa-gpio",
Arnd Bergmannf43e04e2012-08-13 14:36:10 +0000679 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
Haojian Zhuang157d2642011-10-17 20:37:52 +0800680 },
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800681 .id_table = gpio_id_table,
Haojian Zhuang157d2642011-10-17 20:37:52 +0800682};
Linus Walleijcf3fa172013-04-24 21:41:20 +0200683
684static int __init pxa_gpio_init(void)
685{
686 return platform_driver_register(&pxa_gpio_driver);
687}
688postcore_initcall(pxa_gpio_init);
Haojian Zhuang157d2642011-10-17 20:37:52 +0800689
eric miao663707c2008-03-04 16:13:58 +0800690#ifdef CONFIG_PM
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200691static int pxa_gpio_suspend(void)
eric miao663707c2008-03-04 16:13:58 +0800692{
Eric Miao0807da52009-01-07 18:01:51 +0800693 struct pxa_gpio_chip *c;
694 int gpio;
eric miao663707c2008-03-04 16:13:58 +0800695
Eric Miao0807da52009-01-07 18:01:51 +0800696 for_each_gpio_chip(gpio, c) {
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800697 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
698 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
699 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
700 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800701
702 /* Clear GPIO transition detect bits */
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800703 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800704 }
705 return 0;
706}
707
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200708static void pxa_gpio_resume(void)
eric miao663707c2008-03-04 16:13:58 +0800709{
Eric Miao0807da52009-01-07 18:01:51 +0800710 struct pxa_gpio_chip *c;
711 int gpio;
eric miao663707c2008-03-04 16:13:58 +0800712
Eric Miao0807da52009-01-07 18:01:51 +0800713 for_each_gpio_chip(gpio, c) {
eric miao663707c2008-03-04 16:13:58 +0800714 /* restore level with set/clear */
Laurent Navete37f4af2013-03-20 13:15:59 +0100715 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800716 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800717
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800718 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
719 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
720 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800721 }
eric miao663707c2008-03-04 16:13:58 +0800722}
723#else
724#define pxa_gpio_suspend NULL
725#define pxa_gpio_resume NULL
726#endif
727
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200728struct syscore_ops pxa_gpio_syscore_ops = {
eric miao663707c2008-03-04 16:13:58 +0800729 .suspend = pxa_gpio_suspend,
730 .resume = pxa_gpio_resume,
731};
Haojian Zhuang157d2642011-10-17 20:37:52 +0800732
733static int __init pxa_gpio_sysinit(void)
734{
735 register_syscore_ops(&pxa_gpio_syscore_ops);
736 return 0;
737}
738postcore_initcall(pxa_gpio_sysinit);