blob: 1fb90dda299bd32bbfc3d9e92c1dbd00932005fc [file] [log] [blame]
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001/*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080012#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
Nicolas Ferre1ccc4042013-04-03 13:59:19 +080017#include <linux/dmaengine.h>
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080018#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Jean-Christophe PLAGNIOL-VILLARDbcd23602012-10-30 05:12:23 +080022#include <linux/platform_data/atmel.h>
Nicolas Ferre1ccc4042013-04-03 13:59:19 +080023#include <linux/platform_data/dma-atmel.h>
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +010024#include <linux/of.h>
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080025
Wenyou Yangd4820b72013-03-19 15:42:15 +080026#include <linux/io.h>
27#include <linux/gpio.h>
Wenyou Yang5bdfd492014-03-05 09:58:49 +080028#include <linux/pinctrl/consumer.h>
David Brownellbb2d1c32007-02-20 13:58:19 -080029
Grant Likelyca632f52011-06-06 01:16:30 -060030/* SPI register offsets */
31#define SPI_CR 0x0000
32#define SPI_MR 0x0004
33#define SPI_RDR 0x0008
34#define SPI_TDR 0x000c
35#define SPI_SR 0x0010
36#define SPI_IER 0x0014
37#define SPI_IDR 0x0018
38#define SPI_IMR 0x001c
39#define SPI_CSR0 0x0030
40#define SPI_CSR1 0x0034
41#define SPI_CSR2 0x0038
42#define SPI_CSR3 0x003c
Wenyou Yangd4820b72013-03-19 15:42:15 +080043#define SPI_VERSION 0x00fc
Grant Likelyca632f52011-06-06 01:16:30 -060044#define SPI_RPR 0x0100
45#define SPI_RCR 0x0104
46#define SPI_TPR 0x0108
47#define SPI_TCR 0x010c
48#define SPI_RNPR 0x0110
49#define SPI_RNCR 0x0114
50#define SPI_TNPR 0x0118
51#define SPI_TNCR 0x011c
52#define SPI_PTCR 0x0120
53#define SPI_PTSR 0x0124
54
55/* Bitfields in CR */
56#define SPI_SPIEN_OFFSET 0
57#define SPI_SPIEN_SIZE 1
58#define SPI_SPIDIS_OFFSET 1
59#define SPI_SPIDIS_SIZE 1
60#define SPI_SWRST_OFFSET 7
61#define SPI_SWRST_SIZE 1
62#define SPI_LASTXFER_OFFSET 24
63#define SPI_LASTXFER_SIZE 1
64
65/* Bitfields in MR */
66#define SPI_MSTR_OFFSET 0
67#define SPI_MSTR_SIZE 1
68#define SPI_PS_OFFSET 1
69#define SPI_PS_SIZE 1
70#define SPI_PCSDEC_OFFSET 2
71#define SPI_PCSDEC_SIZE 1
72#define SPI_FDIV_OFFSET 3
73#define SPI_FDIV_SIZE 1
74#define SPI_MODFDIS_OFFSET 4
75#define SPI_MODFDIS_SIZE 1
Wenyou Yangd4820b72013-03-19 15:42:15 +080076#define SPI_WDRBT_OFFSET 5
77#define SPI_WDRBT_SIZE 1
Grant Likelyca632f52011-06-06 01:16:30 -060078#define SPI_LLB_OFFSET 7
79#define SPI_LLB_SIZE 1
80#define SPI_PCS_OFFSET 16
81#define SPI_PCS_SIZE 4
82#define SPI_DLYBCS_OFFSET 24
83#define SPI_DLYBCS_SIZE 8
84
85/* Bitfields in RDR */
86#define SPI_RD_OFFSET 0
87#define SPI_RD_SIZE 16
88
89/* Bitfields in TDR */
90#define SPI_TD_OFFSET 0
91#define SPI_TD_SIZE 16
92
93/* Bitfields in SR */
94#define SPI_RDRF_OFFSET 0
95#define SPI_RDRF_SIZE 1
96#define SPI_TDRE_OFFSET 1
97#define SPI_TDRE_SIZE 1
98#define SPI_MODF_OFFSET 2
99#define SPI_MODF_SIZE 1
100#define SPI_OVRES_OFFSET 3
101#define SPI_OVRES_SIZE 1
102#define SPI_ENDRX_OFFSET 4
103#define SPI_ENDRX_SIZE 1
104#define SPI_ENDTX_OFFSET 5
105#define SPI_ENDTX_SIZE 1
106#define SPI_RXBUFF_OFFSET 6
107#define SPI_RXBUFF_SIZE 1
108#define SPI_TXBUFE_OFFSET 7
109#define SPI_TXBUFE_SIZE 1
110#define SPI_NSSR_OFFSET 8
111#define SPI_NSSR_SIZE 1
112#define SPI_TXEMPTY_OFFSET 9
113#define SPI_TXEMPTY_SIZE 1
114#define SPI_SPIENS_OFFSET 16
115#define SPI_SPIENS_SIZE 1
116
117/* Bitfields in CSR0 */
118#define SPI_CPOL_OFFSET 0
119#define SPI_CPOL_SIZE 1
120#define SPI_NCPHA_OFFSET 1
121#define SPI_NCPHA_SIZE 1
122#define SPI_CSAAT_OFFSET 3
123#define SPI_CSAAT_SIZE 1
124#define SPI_BITS_OFFSET 4
125#define SPI_BITS_SIZE 4
126#define SPI_SCBR_OFFSET 8
127#define SPI_SCBR_SIZE 8
128#define SPI_DLYBS_OFFSET 16
129#define SPI_DLYBS_SIZE 8
130#define SPI_DLYBCT_OFFSET 24
131#define SPI_DLYBCT_SIZE 8
132
133/* Bitfields in RCR */
134#define SPI_RXCTR_OFFSET 0
135#define SPI_RXCTR_SIZE 16
136
137/* Bitfields in TCR */
138#define SPI_TXCTR_OFFSET 0
139#define SPI_TXCTR_SIZE 16
140
141/* Bitfields in RNCR */
142#define SPI_RXNCR_OFFSET 0
143#define SPI_RXNCR_SIZE 16
144
145/* Bitfields in TNCR */
146#define SPI_TXNCR_OFFSET 0
147#define SPI_TXNCR_SIZE 16
148
149/* Bitfields in PTCR */
150#define SPI_RXTEN_OFFSET 0
151#define SPI_RXTEN_SIZE 1
152#define SPI_RXTDIS_OFFSET 1
153#define SPI_RXTDIS_SIZE 1
154#define SPI_TXTEN_OFFSET 8
155#define SPI_TXTEN_SIZE 1
156#define SPI_TXTDIS_OFFSET 9
157#define SPI_TXTDIS_SIZE 1
158
159/* Constants for BITS */
160#define SPI_BITS_8_BPT 0
161#define SPI_BITS_9_BPT 1
162#define SPI_BITS_10_BPT 2
163#define SPI_BITS_11_BPT 3
164#define SPI_BITS_12_BPT 4
165#define SPI_BITS_13_BPT 5
166#define SPI_BITS_14_BPT 6
167#define SPI_BITS_15_BPT 7
168#define SPI_BITS_16_BPT 8
169
170/* Bit manipulation macros */
171#define SPI_BIT(name) \
172 (1 << SPI_##name##_OFFSET)
Sachin Kamata536d762013-09-10 17:06:27 +0530173#define SPI_BF(name, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600174 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
Sachin Kamata536d762013-09-10 17:06:27 +0530175#define SPI_BFEXT(name, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600176 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
Sachin Kamata536d762013-09-10 17:06:27 +0530177#define SPI_BFINS(name, value, old) \
178 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
179 | SPI_BF(name, value))
Grant Likelyca632f52011-06-06 01:16:30 -0600180
181/* Register access macros */
Sachin Kamata536d762013-09-10 17:06:27 +0530182#define spi_readl(port, reg) \
Grant Likelyca632f52011-06-06 01:16:30 -0600183 __raw_readl((port)->regs + SPI_##reg)
Sachin Kamata536d762013-09-10 17:06:27 +0530184#define spi_writel(port, reg, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600185 __raw_writel((value), (port)->regs + SPI_##reg)
186
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800187/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
188 * cache operations; better heuristics consider wordsize and bitrate.
189 */
190#define DMA_MIN_BYTES 16
191
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800192#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
193
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800194struct atmel_spi_dma {
195 struct dma_chan *chan_rx;
196 struct dma_chan *chan_tx;
197 struct scatterlist sgrx;
198 struct scatterlist sgtx;
199 struct dma_async_tx_descriptor *data_desc_rx;
200 struct dma_async_tx_descriptor *data_desc_tx;
201
202 struct at_dma_slave dma_slave;
203};
204
Wenyou Yangd4820b72013-03-19 15:42:15 +0800205struct atmel_spi_caps {
206 bool is_spi2;
207 bool has_wdrbt;
208 bool has_dma_support;
209};
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800210
211/*
212 * The core SPI transfer engine just talks to a register bank to set up
213 * DMA transfers; transfer queue progress is driven by IRQs. The clock
214 * framework provides the base clock, subdivided for each spi_device.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800215 */
216struct atmel_spi {
217 spinlock_t lock;
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800218 unsigned long flags;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800219
Nicolas Ferredfab30e2013-04-03 13:57:42 +0800220 phys_addr_t phybase;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800221 void __iomem *regs;
222 int irq;
223 struct clk *clk;
224 struct platform_device *pdev;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800225
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800226 struct spi_transfer *current_transfer;
Axel Lin0c3b9742014-03-27 09:26:38 +0800227 int current_remaining_bytes;
Nicolas Ferre823cd042013-03-19 15:45:01 +0800228 int done_status;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800229
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800230 struct completion xfer_completion;
231
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800232 /* scratch buffer */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800233 void *buffer;
234 dma_addr_t buffer_dma;
Wenyou Yangd4820b72013-03-19 15:42:15 +0800235
236 struct atmel_spi_caps caps;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800237
238 bool use_dma;
239 bool use_pdc;
240 /* dmaengine data */
241 struct atmel_spi_dma dma;
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800242
243 bool keep_cs;
244 bool cs_active;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800245};
246
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800247/* Controller-specific per-slave state */
248struct atmel_spi_device {
249 unsigned int npcs_pin;
250 u32 csr;
251};
252
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800253#define BUFFER_SIZE PAGE_SIZE
254#define INVALID_DMA_ADDRESS 0xffffffff
255
256/*
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800257 * Version 2 of the SPI controller has
258 * - CR.LASTXFER
259 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
260 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
261 * - SPI_CSRx.CSAAT
262 * - SPI_CSRx.SBCR allows faster clocking
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800263 */
Wenyou Yangd4820b72013-03-19 15:42:15 +0800264static bool atmel_spi_is_v2(struct atmel_spi *as)
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800265{
Wenyou Yangd4820b72013-03-19 15:42:15 +0800266 return as->caps.is_spi2;
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800267}
268
269/*
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800270 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
271 * they assume that spi slave device state will not change on deselect, so
David Brownelldefbd3b2007-07-17 04:04:08 -0700272 * that automagic deselection is OK. ("NPCSx rises if no data is to be
273 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
274 * controllers have CSAAT and friends.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800275 *
David Brownelldefbd3b2007-07-17 04:04:08 -0700276 * Since the CSAAT functionality is a bit weird on newer controllers as
277 * well, we use GPIO to control nCSx pins on all controllers, updating
278 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
279 * support active-high chipselects despite the controller's belief that
280 * only active-low devices/systems exists.
281 *
282 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
283 * right when driven with GPIO. ("Mode Fault does not allow more than one
284 * Master on Chip Select 0.") No workaround exists for that ... so for
285 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
286 * and (c) will trigger that first erratum in some cases.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800287 */
288
David Brownelldefbd3b2007-07-17 04:04:08 -0700289static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800290{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800291 struct atmel_spi_device *asd = spi->controller_state;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800292 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700293 u32 mr;
Atsushi Nemotof6febcc2008-02-23 15:23:39 -0800294
Wenyou Yangd4820b72013-03-19 15:42:15 +0800295 if (atmel_spi_is_v2(as)) {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800296 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
297 /* For the low SPI version, there is a issue that PDC transfer
298 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800299 */
300 spi_writel(as, CSR0, asd->csr);
Wenyou Yangd4820b72013-03-19 15:42:15 +0800301 if (as->caps.has_wdrbt) {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800302 spi_writel(as, MR,
303 SPI_BF(PCS, ~(0x01 << spi->chip_select))
304 | SPI_BIT(WDRBT)
305 | SPI_BIT(MODFDIS)
306 | SPI_BIT(MSTR));
Wenyou Yangd4820b72013-03-19 15:42:15 +0800307 } else {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800308 spi_writel(as, MR,
309 SPI_BF(PCS, ~(0x01 << spi->chip_select))
310 | SPI_BIT(MODFDIS)
311 | SPI_BIT(MSTR));
Wenyou Yangd4820b72013-03-19 15:42:15 +0800312 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800313
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800314 mr = spi_readl(as, MR);
315 gpio_set_value(asd->npcs_pin, active);
316 } else {
317 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
318 int i;
319 u32 csr;
320
321 /* Make sure clock polarity is correct */
322 for (i = 0; i < spi->master->num_chipselect; i++) {
323 csr = spi_readl(as, CSR0 + 4 * i);
324 if ((csr ^ cpol) & SPI_BIT(CPOL))
325 spi_writel(as, CSR0 + 4 * i,
326 csr ^ SPI_BIT(CPOL));
327 }
328
329 mr = spi_readl(as, MR);
330 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
331 if (spi->chip_select != 0)
332 gpio_set_value(asd->npcs_pin, active);
333 spi_writel(as, MR, mr);
Atsushi Nemotof6febcc2008-02-23 15:23:39 -0800334 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800335
David Brownelldefbd3b2007-07-17 04:04:08 -0700336 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800337 asd->npcs_pin, active ? " (high)" : "",
David Brownelldefbd3b2007-07-17 04:04:08 -0700338 mr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800339}
340
David Brownelldefbd3b2007-07-17 04:04:08 -0700341static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800342{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800343 struct atmel_spi_device *asd = spi->controller_state;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800344 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700345 u32 mr;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800346
David Brownelldefbd3b2007-07-17 04:04:08 -0700347 /* only deactivate *this* device; sometimes transfers to
348 * another device may be active when this routine is called.
349 */
350 mr = spi_readl(as, MR);
351 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
352 mr = SPI_BFINS(PCS, 0xf, mr);
353 spi_writel(as, MR, mr);
354 }
355
356 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800357 asd->npcs_pin, active ? " (low)" : "",
David Brownelldefbd3b2007-07-17 04:04:08 -0700358 mr);
359
Wenyou Yangd4820b72013-03-19 15:42:15 +0800360 if (atmel_spi_is_v2(as) || spi->chip_select != 0)
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800361 gpio_set_value(asd->npcs_pin, !active);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800362}
363
Mark Brown6c07ef22013-07-28 14:32:27 +0100364static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800365{
366 spin_lock_irqsave(&as->lock, as->flags);
367}
368
Mark Brown6c07ef22013-07-28 14:32:27 +0100369static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800370{
371 spin_unlock_irqrestore(&as->lock, as->flags);
372}
373
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800374static inline bool atmel_spi_use_dma(struct atmel_spi *as,
375 struct spi_transfer *xfer)
376{
377 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
378}
379
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800380static int atmel_spi_dma_slave_config(struct atmel_spi *as,
381 struct dma_slave_config *slave_config,
382 u8 bits_per_word)
383{
384 int err = 0;
385
386 if (bits_per_word > 8) {
387 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
388 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
389 } else {
390 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
391 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
392 }
393
394 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
395 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
396 slave_config->src_maxburst = 1;
397 slave_config->dst_maxburst = 1;
398 slave_config->device_fc = false;
399
400 slave_config->direction = DMA_MEM_TO_DEV;
401 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
402 dev_err(&as->pdev->dev,
403 "failed to configure tx dma channel\n");
404 err = -EINVAL;
405 }
406
407 slave_config->direction = DMA_DEV_TO_MEM;
408 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
409 dev_err(&as->pdev->dev,
410 "failed to configure rx dma channel\n");
411 err = -EINVAL;
412 }
413
414 return err;
415}
416
Richard Genoud2f767a92013-05-31 17:01:59 +0200417static bool filter(struct dma_chan *chan, void *pdata)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800418{
Richard Genoud2f767a92013-05-31 17:01:59 +0200419 struct atmel_spi_dma *sl_pdata = pdata;
420 struct at_dma_slave *sl;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800421
Richard Genoud2f767a92013-05-31 17:01:59 +0200422 if (!sl_pdata)
423 return false;
424
425 sl = &sl_pdata->dma_slave;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800426 if (sl->dma_dev == chan->device->dev) {
427 chan->private = sl;
428 return true;
429 } else {
430 return false;
431 }
432}
433
434static int atmel_spi_configure_dma(struct atmel_spi *as)
435{
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800436 struct dma_slave_config slave_config;
Richard Genoud2f767a92013-05-31 17:01:59 +0200437 struct device *dev = &as->pdev->dev;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800438 int err;
439
Richard Genoud2f767a92013-05-31 17:01:59 +0200440 dma_cap_mask_t mask;
441 dma_cap_zero(mask);
442 dma_cap_set(DMA_SLAVE, mask);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800443
Richard Genoud2f767a92013-05-31 17:01:59 +0200444 as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
445 &as->dma,
446 dev, "tx");
447 if (!as->dma.chan_tx) {
448 dev_err(dev,
449 "DMA TX channel not available, SPI unable to use DMA\n");
450 err = -EBUSY;
451 goto error;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800452 }
Richard Genoud2f767a92013-05-31 17:01:59 +0200453
454 as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
455 &as->dma,
456 dev, "rx");
457
458 if (!as->dma.chan_rx) {
459 dev_err(dev,
460 "DMA RX channel not available, SPI unable to use DMA\n");
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800461 err = -EBUSY;
462 goto error;
463 }
464
465 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
466 if (err)
467 goto error;
468
469 dev_info(&as->pdev->dev,
470 "Using %s (tx) and %s (rx) for DMA transfers\n",
471 dma_chan_name(as->dma.chan_tx),
472 dma_chan_name(as->dma.chan_rx));
473 return 0;
474error:
475 if (as->dma.chan_rx)
476 dma_release_channel(as->dma.chan_rx);
477 if (as->dma.chan_tx)
478 dma_release_channel(as->dma.chan_tx);
479 return err;
480}
481
482static void atmel_spi_stop_dma(struct atmel_spi *as)
483{
484 if (as->dma.chan_rx)
485 as->dma.chan_rx->device->device_control(as->dma.chan_rx,
486 DMA_TERMINATE_ALL, 0);
487 if (as->dma.chan_tx)
488 as->dma.chan_tx->device->device_control(as->dma.chan_tx,
489 DMA_TERMINATE_ALL, 0);
490}
491
492static void atmel_spi_release_dma(struct atmel_spi *as)
493{
494 if (as->dma.chan_rx)
495 dma_release_channel(as->dma.chan_rx);
496 if (as->dma.chan_tx)
497 dma_release_channel(as->dma.chan_tx);
498}
499
500/* This function is called by the DMA driver from tasklet context */
501static void dma_callback(void *data)
502{
503 struct spi_master *master = data;
504 struct atmel_spi *as = spi_master_get_devdata(master);
505
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800506 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800507}
508
509/*
510 * Next transfer using PIO.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800511 */
512static void atmel_spi_next_xfer_pio(struct spi_master *master,
513 struct spi_transfer *xfer)
514{
515 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800516 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800517
518 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
519
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800520 /* Make sure data is not remaining in RDR */
521 spi_readl(as, RDR);
522 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
523 spi_readl(as, RDR);
524 cpu_relax();
525 }
526
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800527 if (xfer->tx_buf) {
Richard Genoudf557c982013-05-02 19:25:11 +0800528 if (xfer->bits_per_word > 8)
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800529 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
Richard Genoudf557c982013-05-02 19:25:11 +0800530 else
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800531 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
532 } else {
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800533 spi_writel(as, TDR, 0);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800534 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800535
536 dev_dbg(master->dev.parent,
Richard Genoudf557c982013-05-02 19:25:11 +0800537 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
538 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
539 xfer->bits_per_word);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800540
541 /* Enable relevant interrupts */
542 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
543}
544
545/*
546 * Submit next transfer for DMA.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800547 */
548static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
549 struct spi_transfer *xfer,
550 u32 *plen)
551{
552 struct atmel_spi *as = spi_master_get_devdata(master);
553 struct dma_chan *rxchan = as->dma.chan_rx;
554 struct dma_chan *txchan = as->dma.chan_tx;
555 struct dma_async_tx_descriptor *rxdesc;
556 struct dma_async_tx_descriptor *txdesc;
557 struct dma_slave_config slave_config;
558 dma_cookie_t cookie;
559 u32 len = *plen;
560
561 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
562
563 /* Check that the channels are available */
564 if (!rxchan || !txchan)
565 return -ENODEV;
566
567 /* release lock for DMA operations */
568 atmel_spi_unlock(as);
569
570 /* prepare the RX dma transfer */
571 sg_init_table(&as->dma.sgrx, 1);
572 if (xfer->rx_buf) {
573 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
574 } else {
575 as->dma.sgrx.dma_address = as->buffer_dma;
576 if (len > BUFFER_SIZE)
577 len = BUFFER_SIZE;
578 }
579
580 /* prepare the TX dma transfer */
581 sg_init_table(&as->dma.sgtx, 1);
582 if (xfer->tx_buf) {
583 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
584 } else {
585 as->dma.sgtx.dma_address = as->buffer_dma;
586 if (len > BUFFER_SIZE)
587 len = BUFFER_SIZE;
588 memset(as->buffer, 0, len);
589 }
590
591 sg_dma_len(&as->dma.sgtx) = len;
592 sg_dma_len(&as->dma.sgrx) = len;
593
594 *plen = len;
595
596 if (atmel_spi_dma_slave_config(as, &slave_config, 8))
597 goto err_exit;
598
599 /* Send both scatterlists */
Geert Uytterhoevenef40eb32014-07-11 18:13:28 +0200600 rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
601 DMA_FROM_DEVICE,
602 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800603 if (!rxdesc)
604 goto err_dma;
605
Geert Uytterhoevenef40eb32014-07-11 18:13:28 +0200606 txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
607 DMA_TO_DEVICE,
608 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800609 if (!txdesc)
610 goto err_dma;
611
612 dev_dbg(master->dev.parent,
Emil Goode2de024b2013-07-30 19:35:35 +0200613 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
614 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
615 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800616
617 /* Enable relevant interrupts */
618 spi_writel(as, IER, SPI_BIT(OVRES));
619
620 /* Put the callback on the RX transfer only, that should finish last */
621 rxdesc->callback = dma_callback;
622 rxdesc->callback_param = master;
623
624 /* Submit and fire RX and TX with TX last so we're ready to read! */
625 cookie = rxdesc->tx_submit(rxdesc);
626 if (dma_submit_error(cookie))
627 goto err_dma;
628 cookie = txdesc->tx_submit(txdesc);
629 if (dma_submit_error(cookie))
630 goto err_dma;
631 rxchan->device->device_issue_pending(rxchan);
632 txchan->device->device_issue_pending(txchan);
633
634 /* take back lock */
635 atmel_spi_lock(as);
636 return 0;
637
638err_dma:
639 spi_writel(as, IDR, SPI_BIT(OVRES));
640 atmel_spi_stop_dma(as);
641err_exit:
642 atmel_spi_lock(as);
643 return -ENOMEM;
644}
645
Silvester Erdeg154443c2008-02-06 01:38:12 -0800646static void atmel_spi_next_xfer_data(struct spi_master *master,
647 struct spi_transfer *xfer,
648 dma_addr_t *tx_dma,
649 dma_addr_t *rx_dma,
650 u32 *plen)
651{
652 struct atmel_spi *as = spi_master_get_devdata(master);
653 u32 len = *plen;
654
655 /* use scratch buffer only when rx or tx data is unspecified */
656 if (xfer->rx_buf)
Ben Nizette6aed4ee2009-12-14 22:20:20 -0800657 *rx_dma = xfer->rx_dma + xfer->len - *plen;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800658 else {
659 *rx_dma = as->buffer_dma;
660 if (len > BUFFER_SIZE)
661 len = BUFFER_SIZE;
662 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800663
Silvester Erdeg154443c2008-02-06 01:38:12 -0800664 if (xfer->tx_buf)
Ben Nizette6aed4ee2009-12-14 22:20:20 -0800665 *tx_dma = xfer->tx_dma + xfer->len - *plen;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800666 else {
667 *tx_dma = as->buffer_dma;
668 if (len > BUFFER_SIZE)
669 len = BUFFER_SIZE;
670 memset(as->buffer, 0, len);
671 dma_sync_single_for_device(&as->pdev->dev,
672 as->buffer_dma, len, DMA_TO_DEVICE);
673 }
674
675 *plen = len;
676}
677
Richard Genoudd3b72c72013-11-07 10:34:06 +0100678static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
679 struct spi_device *spi,
680 struct spi_transfer *xfer)
681{
682 u32 scbr, csr;
683 unsigned long bus_hz;
684
685 /* v1 chips start out at half the peripheral bus speed. */
686 bus_hz = clk_get_rate(as->clk);
687 if (!atmel_spi_is_v2(as))
688 bus_hz /= 2;
689
690 /*
691 * Calculate the lowest divider that satisfies the
692 * constraint, assuming div32/fdiv/mbz == 0.
693 */
694 if (xfer->speed_hz)
695 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
696 else
697 /*
698 * This can happend if max_speed is null.
699 * In this case, we set the lowest possible speed
700 */
701 scbr = 0xff;
702
703 /*
704 * If the resulting divider doesn't fit into the
705 * register bitfield, we can't satisfy the constraint.
706 */
707 if (scbr >= (1 << SPI_SCBR_SIZE)) {
708 dev_err(&spi->dev,
709 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
710 xfer->speed_hz, scbr, bus_hz/255);
711 return -EINVAL;
712 }
713 if (scbr == 0) {
714 dev_err(&spi->dev,
715 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
716 xfer->speed_hz, scbr, bus_hz);
717 return -EINVAL;
718 }
719 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
720 csr = SPI_BFINS(SCBR, scbr, csr);
721 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
722
723 return 0;
724}
725
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800726/*
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800727 * Submit next transfer for PDC.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800728 * lock is held, spi irq is blocked
729 */
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800730static void atmel_spi_pdc_next_xfer(struct spi_master *master,
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800731 struct spi_message *msg,
732 struct spi_transfer *xfer)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800733{
734 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800735 u32 len;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800736 dma_addr_t tx_dma, rx_dma;
737
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800738 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
Silvester Erdeg154443c2008-02-06 01:38:12 -0800739
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800740 len = as->current_remaining_bytes;
741 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
742 as->current_remaining_bytes -= len;
Gerard Kamdc329442008-08-04 13:41:12 -0700743
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800744 spi_writel(as, RPR, rx_dma);
745 spi_writel(as, TPR, tx_dma);
746
747 if (msg->spi->bits_per_word > 8)
748 len >>= 1;
749 spi_writel(as, RCR, len);
750 spi_writel(as, TCR, len);
751
752 dev_dbg(&msg->spi->dev,
753 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
754 xfer, xfer->len, xfer->tx_buf,
755 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
756 (unsigned long long)xfer->rx_dma);
757
758 if (as->current_remaining_bytes) {
759 len = as->current_remaining_bytes;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800760 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800761 as->current_remaining_bytes -= len;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800762
763 spi_writel(as, RNPR, rx_dma);
764 spi_writel(as, TNPR, tx_dma);
765
766 if (msg->spi->bits_per_word > 8)
767 len >>= 1;
768 spi_writel(as, RNCR, len);
769 spi_writel(as, TNCR, len);
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800770
771 dev_dbg(&msg->spi->dev,
Emil Goode2de024b2013-07-30 19:35:35 +0200772 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
773 xfer, xfer->len, xfer->tx_buf,
774 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
775 (unsigned long long)xfer->rx_dma);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800776 }
777
Silvester Erdeg154443c2008-02-06 01:38:12 -0800778 /* REVISIT: We're waiting for ENDRX before we start the next
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800779 * transfer because we need to handle some difficult timing
780 * issues otherwise. If we wait for ENDTX in one transfer and
781 * then starts waiting for ENDRX in the next, it's difficult
782 * to tell the difference between the ENDRX interrupt we're
783 * actually waiting for and the ENDRX interrupt of the
784 * previous transfer.
785 *
786 * It should be doable, though. Just not now...
787 */
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800788 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800789 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
790}
791
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800792/*
David Brownell8da08592007-07-17 04:04:07 -0700793 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
794 * - The buffer is either valid for CPU access, else NULL
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400795 * - If the buffer is valid, so is its DMA address
David Brownell8da08592007-07-17 04:04:07 -0700796 *
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400797 * This driver manages the dma address unless message->is_dma_mapped.
David Brownell8da08592007-07-17 04:04:07 -0700798 */
799static int
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800800atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
801{
David Brownell8da08592007-07-17 04:04:07 -0700802 struct device *dev = &as->pdev->dev;
803
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800804 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
David Brownell8da08592007-07-17 04:04:07 -0700805 if (xfer->tx_buf) {
Jean-Christophe PLAGNIOL-VILLARD214b5742010-11-20 14:52:53 +0800806 /* tx_buf is a const void* where we need a void * for the dma
807 * mapping */
808 void *nonconst_tx = (void *)xfer->tx_buf;
809
David Brownell8da08592007-07-17 04:04:07 -0700810 xfer->tx_dma = dma_map_single(dev,
Jean-Christophe PLAGNIOL-VILLARD214b5742010-11-20 14:52:53 +0800811 nonconst_tx, xfer->len,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800812 DMA_TO_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700813 if (dma_mapping_error(dev, xfer->tx_dma))
David Brownell8da08592007-07-17 04:04:07 -0700814 return -ENOMEM;
815 }
816 if (xfer->rx_buf) {
817 xfer->rx_dma = dma_map_single(dev,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800818 xfer->rx_buf, xfer->len,
819 DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700820 if (dma_mapping_error(dev, xfer->rx_dma)) {
David Brownell8da08592007-07-17 04:04:07 -0700821 if (xfer->tx_buf)
822 dma_unmap_single(dev,
823 xfer->tx_dma, xfer->len,
824 DMA_TO_DEVICE);
825 return -ENOMEM;
826 }
827 }
828 return 0;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800829}
830
831static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
832 struct spi_transfer *xfer)
833{
834 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -0700835 dma_unmap_single(master->dev.parent, xfer->tx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800836 xfer->len, DMA_TO_DEVICE);
837 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -0700838 dma_unmap_single(master->dev.parent, xfer->rx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800839 xfer->len, DMA_FROM_DEVICE);
840}
841
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800842static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
843{
844 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
845}
846
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800847/* Called from IRQ
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800848 *
849 * Must update "current_remaining_bytes" to keep track of data
850 * to transfer.
851 */
852static void
853atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
854{
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800855 u8 *rxp;
Richard Genoudf557c982013-05-02 19:25:11 +0800856 u16 *rxp16;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800857 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
858
859 if (xfer->rx_buf) {
Richard Genoudf557c982013-05-02 19:25:11 +0800860 if (xfer->bits_per_word > 8) {
861 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
862 *rxp16 = spi_readl(as, RDR);
863 } else {
864 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
865 *rxp = spi_readl(as, RDR);
866 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800867 } else {
868 spi_readl(as, RDR);
869 }
Richard Genoudf557c982013-05-02 19:25:11 +0800870 if (xfer->bits_per_word > 8) {
Alexandre Bellonib112f052014-05-06 17:44:41 +0200871 if (as->current_remaining_bytes > 2)
872 as->current_remaining_bytes -= 2;
873 else
Richard Genoudf557c982013-05-02 19:25:11 +0800874 as->current_remaining_bytes = 0;
875 } else {
876 as->current_remaining_bytes--;
877 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800878}
879
880/* Interrupt
881 *
882 * No need for locking in this Interrupt handler: done_status is the
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800883 * only information modified.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800884 */
885static irqreturn_t
886atmel_spi_pio_interrupt(int irq, void *dev_id)
887{
888 struct spi_master *master = dev_id;
889 struct atmel_spi *as = spi_master_get_devdata(master);
890 u32 status, pending, imr;
891 struct spi_transfer *xfer;
892 int ret = IRQ_NONE;
893
894 imr = spi_readl(as, IMR);
895 status = spi_readl(as, SR);
896 pending = status & imr;
897
898 if (pending & SPI_BIT(OVRES)) {
899 ret = IRQ_HANDLED;
900 spi_writel(as, IDR, SPI_BIT(OVRES));
901 dev_warn(master->dev.parent, "overrun\n");
902
903 /*
904 * When we get an overrun, we disregard the current
905 * transfer. Data will not be copied back from any
906 * bounce buffer and msg->actual_len will not be
907 * updated with the last xfer.
908 *
909 * We will also not process any remaning transfers in
910 * the message.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800911 */
912 as->done_status = -EIO;
913 smp_wmb();
914
915 /* Clear any overrun happening while cleaning up */
916 spi_readl(as, SR);
917
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800918 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800919
920 } else if (pending & SPI_BIT(RDRF)) {
921 atmel_spi_lock(as);
922
923 if (as->current_remaining_bytes) {
924 ret = IRQ_HANDLED;
925 xfer = as->current_transfer;
926 atmel_spi_pump_pio_data(as, xfer);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800927 if (!as->current_remaining_bytes)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800928 spi_writel(as, IDR, pending);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800929
930 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800931 }
932
933 atmel_spi_unlock(as);
934 } else {
935 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
936 ret = IRQ_HANDLED;
937 spi_writel(as, IDR, pending);
938 }
939
940 return ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800941}
942
943static irqreturn_t
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800944atmel_spi_pdc_interrupt(int irq, void *dev_id)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800945{
946 struct spi_master *master = dev_id;
947 struct atmel_spi *as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800948 u32 status, pending, imr;
949 int ret = IRQ_NONE;
950
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800951 imr = spi_readl(as, IMR);
952 status = spi_readl(as, SR);
953 pending = status & imr;
954
955 if (pending & SPI_BIT(OVRES)) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800956
957 ret = IRQ_HANDLED;
958
Gerard Kamdc329442008-08-04 13:41:12 -0700959 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800960 | SPI_BIT(OVRES)));
961
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800962 /* Clear any overrun happening while cleaning up */
963 spi_readl(as, SR);
964
Nicolas Ferre823cd042013-03-19 15:45:01 +0800965 as->done_status = -EIO;
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800966
967 complete(&as->xfer_completion);
968
Gerard Kamdc329442008-08-04 13:41:12 -0700969 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800970 ret = IRQ_HANDLED;
971
972 spi_writel(as, IDR, pending);
973
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800974 complete(&as->xfer_completion);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800975 }
976
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800977 return ret;
978}
979
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800980static int atmel_spi_setup(struct spi_device *spi)
981{
982 struct atmel_spi *as;
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800983 struct atmel_spi_device *asd;
Richard Genoudd3b72c72013-11-07 10:34:06 +0100984 u32 csr;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800985 unsigned int bits = spi->bits_per_word;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800986 unsigned int npcs_pin;
987 int ret;
988
989 as = spi_master_get_devdata(spi->master);
990
David Brownelldefbd3b2007-07-17 04:04:08 -0700991 /* see notes above re chipselect */
Wenyou Yangd4820b72013-03-19 15:42:15 +0800992 if (!atmel_spi_is_v2(as)
David Brownelldefbd3b2007-07-17 04:04:08 -0700993 && spi->chip_select == 0
994 && (spi->mode & SPI_CS_HIGH)) {
995 dev_dbg(&spi->dev, "setup: can't be active-high\n");
996 return -EINVAL;
997 }
998
Richard Genoudd3b72c72013-11-07 10:34:06 +0100999 csr = SPI_BF(BITS, bits - 8);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001000 if (spi->mode & SPI_CPOL)
1001 csr |= SPI_BIT(CPOL);
1002 if (!(spi->mode & SPI_CPHA))
1003 csr |= SPI_BIT(NCPHA);
1004
Haavard Skinnemoen1eed29d2008-02-06 01:38:11 -08001005 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1006 *
1007 * DLYBCT would add delays between words, slowing down transfers.
1008 * It could potentially be useful to cope with DMA bottlenecks, but
1009 * in those cases it's probably best to just use a lower bitrate.
1010 */
1011 csr |= SPI_BF(DLYBS, 0);
1012 csr |= SPI_BF(DLYBCT, 0);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001013
1014 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1015 npcs_pin = (unsigned int)spi->controller_data;
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001016
1017 if (gpio_is_valid(spi->cs_gpio))
1018 npcs_pin = spi->cs_gpio;
1019
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001020 asd = spi->controller_state;
1021 if (!asd) {
1022 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1023 if (!asd)
1024 return -ENOMEM;
1025
Kay Sievers6c7377a2009-03-24 16:38:21 -07001026 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001027 if (ret) {
1028 kfree(asd);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001029 return ret;
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001030 }
1031
1032 asd->npcs_pin = npcs_pin;
1033 spi->controller_state = asd;
David Brownell28735a72007-03-16 13:38:14 -08001034 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001035 }
1036
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001037 asd->csr = csr;
1038
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001039 dev_dbg(&spi->dev,
Richard Genoudd3b72c72013-11-07 10:34:06 +01001040 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1041 bits, spi->mode, spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001042
Wenyou Yangd4820b72013-03-19 15:42:15 +08001043 if (!atmel_spi_is_v2(as))
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001044 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001045
1046 return 0;
1047}
1048
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001049static int atmel_spi_one_transfer(struct spi_master *master,
1050 struct spi_message *msg,
1051 struct spi_transfer *xfer)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001052{
1053 struct atmel_spi *as;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001054 struct spi_device *spi = msg->spi;
Matthias Bruggerb9d228f2010-10-13 17:51:02 +02001055 u8 bits;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001056 u32 len;
Matthias Bruggerb9d228f2010-10-13 17:51:02 +02001057 struct atmel_spi_device *asd;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001058 int timeout;
1059 int ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001060
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001061 as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001062
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001063 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1064 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1065 return -EINVAL;
1066 }
1067
1068 if (xfer->bits_per_word) {
1069 asd = spi->controller_state;
1070 bits = (asd->csr >> 4) & 0xf;
1071 if (bits != xfer->bits_per_word - 8) {
1072 dev_dbg(&spi->dev,
1073 "you can't yet change bits_per_word in transfers\n");
1074 return -ENOPROTOOPT;
1075 }
1076 }
1077
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001078 /*
1079 * DMA map early, for performance (empties dcache ASAP) and
1080 * better fault reporting.
1081 */
1082 if ((!msg->is_dma_mapped)
1083 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1084 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1085 return -ENOMEM;
1086 }
1087
1088 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1089
1090 as->done_status = 0;
1091 as->current_transfer = xfer;
1092 as->current_remaining_bytes = xfer->len;
1093 while (as->current_remaining_bytes) {
1094 reinit_completion(&as->xfer_completion);
1095
1096 if (as->use_pdc) {
1097 atmel_spi_pdc_next_xfer(master, msg, xfer);
1098 } else if (atmel_spi_use_dma(as, xfer)) {
1099 len = as->current_remaining_bytes;
1100 ret = atmel_spi_next_xfer_dma_submit(master,
1101 xfer, &len);
1102 if (ret) {
1103 dev_err(&spi->dev,
1104 "unable to use DMA, fallback to PIO\n");
1105 atmel_spi_next_xfer_pio(master, xfer);
1106 } else {
1107 as->current_remaining_bytes -= len;
Axel Lin0c3b9742014-03-27 09:26:38 +08001108 if (as->current_remaining_bytes < 0)
1109 as->current_remaining_bytes = 0;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001110 }
1111 } else {
1112 atmel_spi_next_xfer_pio(master, xfer);
1113 }
1114
Alexander Stein16760142014-04-13 12:45:10 +02001115 /* interrupts are disabled, so free the lock for schedule */
1116 atmel_spi_unlock(as);
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001117 ret = wait_for_completion_timeout(&as->xfer_completion,
1118 SPI_DMA_TIMEOUT);
Alexander Stein16760142014-04-13 12:45:10 +02001119 atmel_spi_lock(as);
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001120 if (WARN_ON(ret == 0)) {
1121 dev_err(&spi->dev,
1122 "spi trasfer timeout, err %d\n", ret);
1123 as->done_status = -EIO;
1124 } else {
1125 ret = 0;
1126 }
1127
1128 if (as->done_status)
1129 break;
1130 }
1131
1132 if (as->done_status) {
1133 if (as->use_pdc) {
1134 dev_warn(master->dev.parent,
1135 "overrun (%u/%u remaining)\n",
1136 spi_readl(as, TCR), spi_readl(as, RCR));
1137
1138 /*
1139 * Clean up DMA registers and make sure the data
1140 * registers are empty.
1141 */
1142 spi_writel(as, RNCR, 0);
1143 spi_writel(as, TNCR, 0);
1144 spi_writel(as, RCR, 0);
1145 spi_writel(as, TCR, 0);
1146 for (timeout = 1000; timeout; timeout--)
1147 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1148 break;
1149 if (!timeout)
1150 dev_warn(master->dev.parent,
1151 "timeout waiting for TXEMPTY");
1152 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1153 spi_readl(as, RDR);
1154
1155 /* Clear any overrun happening while cleaning up */
1156 spi_readl(as, SR);
1157
1158 } else if (atmel_spi_use_dma(as, xfer)) {
1159 atmel_spi_stop_dma(as);
1160 }
1161
1162 if (!msg->is_dma_mapped
1163 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1164 atmel_spi_dma_unmap_xfer(master, xfer);
1165
1166 return 0;
1167
1168 } else {
1169 /* only update length if no error */
1170 msg->actual_length += xfer->len;
1171 }
1172
1173 if (!msg->is_dma_mapped
1174 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1175 atmel_spi_dma_unmap_xfer(master, xfer);
1176
1177 if (xfer->delay_usecs)
1178 udelay(xfer->delay_usecs);
1179
1180 if (xfer->cs_change) {
1181 if (list_is_last(&xfer->transfer_list,
1182 &msg->transfers)) {
1183 as->keep_cs = true;
1184 } else {
1185 as->cs_active = !as->cs_active;
1186 if (as->cs_active)
1187 cs_activate(as, msg->spi);
1188 else
1189 cs_deactivate(as, msg->spi);
1190 }
1191 }
1192
1193 return 0;
1194}
1195
1196static int atmel_spi_transfer_one_message(struct spi_master *master,
1197 struct spi_message *msg)
1198{
1199 struct atmel_spi *as;
1200 struct spi_transfer *xfer;
1201 struct spi_device *spi = msg->spi;
1202 int ret = 0;
1203
1204 as = spi_master_get_devdata(master);
1205
1206 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1207 msg, dev_name(&spi->dev));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001208
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001209 atmel_spi_lock(as);
1210 cs_activate(as, spi);
1211
1212 as->cs_active = true;
1213 as->keep_cs = false;
1214
1215 msg->status = 0;
1216 msg->actual_length = 0;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001217
1218 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001219 ret = atmel_spi_one_transfer(master, msg, xfer);
1220 if (ret)
1221 goto msg_done;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001222 }
1223
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001224 if (as->use_pdc)
1225 atmel_spi_disable_pdc_transfer(as);
1226
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001227 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001228 dev_dbg(&spi->dev,
Randy Dunlap54f4c512014-03-21 08:53:41 -07001229 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001230 xfer, xfer->len,
Randy Dunlap54f4c512014-03-21 08:53:41 -07001231 xfer->tx_buf, &xfer->tx_dma,
1232 xfer->rx_buf, &xfer->rx_dma);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001233 }
1234
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001235msg_done:
1236 if (!as->keep_cs)
1237 cs_deactivate(as, msg->spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001238
Nicolas Ferre8aad7922013-04-03 13:58:36 +08001239 atmel_spi_unlock(as);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001240
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001241 msg->status = as->done_status;
1242 spi_finalize_current_message(spi->master);
1243
1244 return ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001245}
1246
David Brownellbb2d1c32007-02-20 13:58:19 -08001247static void atmel_spi_cleanup(struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001248{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001249 struct atmel_spi_device *asd = spi->controller_state;
David Brownelldefbd3b2007-07-17 04:04:08 -07001250 unsigned gpio = (unsigned) spi->controller_data;
David Brownelldefbd3b2007-07-17 04:04:08 -07001251
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001252 if (!asd)
David Brownelldefbd3b2007-07-17 04:04:08 -07001253 return;
1254
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001255 spi->controller_state = NULL;
David Brownelldefbd3b2007-07-17 04:04:08 -07001256 gpio_free(gpio);
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001257 kfree(asd);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001258}
1259
Wenyou Yangd4820b72013-03-19 15:42:15 +08001260static inline unsigned int atmel_get_version(struct atmel_spi *as)
1261{
1262 return spi_readl(as, VERSION) & 0x00000fff;
1263}
1264
1265static void atmel_get_caps(struct atmel_spi *as)
1266{
1267 unsigned int version;
1268
1269 version = atmel_get_version(as);
1270 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1271
1272 as->caps.is_spi2 = version > 0x121;
1273 as->caps.has_wdrbt = version >= 0x210;
1274 as->caps.has_dma_support = version >= 0x212;
1275}
1276
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001277/*-------------------------------------------------------------------------*/
1278
Grant Likelyfd4a3192012-12-07 16:57:14 +00001279static int atmel_spi_probe(struct platform_device *pdev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001280{
1281 struct resource *regs;
1282 int irq;
1283 struct clk *clk;
1284 int ret;
1285 struct spi_master *master;
1286 struct atmel_spi *as;
1287
Wenyou Yang5bdfd492014-03-05 09:58:49 +08001288 /* Select default pin state */
1289 pinctrl_pm_select_default_state(&pdev->dev);
1290
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001291 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292 if (!regs)
1293 return -ENXIO;
1294
1295 irq = platform_get_irq(pdev, 0);
1296 if (irq < 0)
1297 return irq;
1298
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001299 clk = devm_clk_get(&pdev->dev, "spi_clk");
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001300 if (IS_ERR(clk))
1301 return PTR_ERR(clk);
1302
1303 /* setup spi core then atmel-specific driver state */
1304 ret = -ENOMEM;
Sachin Kamata536d762013-09-10 17:06:27 +05301305 master = spi_alloc_master(&pdev->dev, sizeof(*as));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001306 if (!master)
1307 goto out_free;
1308
David Brownelle7db06b2009-06-17 16:26:04 -07001309 /* the spi->mode bits understood by this driver: */
1310 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Stephen Warren24778be2013-05-21 20:36:35 -06001311 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001312 master->dev.of_node = pdev->dev.of_node;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001313 master->bus_num = pdev->id;
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001314 master->num_chipselect = master->dev.of_node ? 0 : 4;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001315 master->setup = atmel_spi_setup;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001316 master->transfer_one_message = atmel_spi_transfer_one_message;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001317 master->cleanup = atmel_spi_cleanup;
1318 platform_set_drvdata(pdev, master);
1319
1320 as = spi_master_get_devdata(master);
1321
David Brownell8da08592007-07-17 04:04:07 -07001322 /*
1323 * Scratch buffer is used for throwaway rx and tx data.
1324 * It's coherent to minimize dcache pollution.
1325 */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001326 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1327 &as->buffer_dma, GFP_KERNEL);
1328 if (!as->buffer)
1329 goto out_free;
1330
1331 spin_lock_init(&as->lock);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001332
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001333 as->pdev = pdev;
Mark Brown31407472013-10-16 13:22:35 +01001334 as->regs = devm_ioremap_resource(&pdev->dev, regs);
Wei Yongjun543c9542013-10-21 11:12:02 +08001335 if (IS_ERR(as->regs)) {
1336 ret = PTR_ERR(as->regs);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001337 goto out_free_buffer;
Wei Yongjun543c9542013-10-21 11:12:02 +08001338 }
Nicolas Ferredfab30e2013-04-03 13:57:42 +08001339 as->phybase = regs->start;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001340 as->irq = irq;
1341 as->clk = clk;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001342
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001343 init_completion(&as->xfer_completion);
1344
Wenyou Yangd4820b72013-03-19 15:42:15 +08001345 atmel_get_caps(as);
1346
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001347 as->use_dma = false;
1348 as->use_pdc = false;
1349 if (as->caps.has_dma_support) {
1350 if (atmel_spi_configure_dma(as) == 0)
1351 as->use_dma = true;
1352 } else {
1353 as->use_pdc = true;
1354 }
1355
1356 if (as->caps.has_dma_support && !as->use_dma)
1357 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1358
1359 if (as->use_pdc) {
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001360 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1361 0, dev_name(&pdev->dev), master);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001362 } else {
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001363 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1364 0, dev_name(&pdev->dev), master);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001365 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001366 if (ret)
1367 goto out_unmap_regs;
1368
1369 /* Initialize the hardware */
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001370 ret = clk_prepare_enable(clk);
1371 if (ret)
Sachin Kamatde8cc232013-09-10 17:06:26 +05301372 goto out_free_irq;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001373 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001374 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Wenyou Yangd4820b72013-03-19 15:42:15 +08001375 if (as->caps.has_wdrbt) {
1376 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1377 | SPI_BIT(MSTR));
1378 } else {
1379 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1380 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001381
1382 if (as->use_pdc)
1383 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001384 spi_writel(as, CR, SPI_BIT(SPIEN));
1385
1386 /* go! */
1387 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1388 (unsigned long)regs->start, irq);
1389
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001390 ret = devm_spi_register_master(&pdev->dev, master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001391 if (ret)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001392 goto out_free_dma;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001393
1394 return 0;
1395
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001396out_free_dma:
1397 if (as->use_dma)
1398 atmel_spi_release_dma(as);
1399
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001400 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001401 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001402 clk_disable_unprepare(clk);
Sachin Kamatde8cc232013-09-10 17:06:26 +05301403out_free_irq:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001404out_unmap_regs:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001405out_free_buffer:
1406 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1407 as->buffer_dma);
1408out_free:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001409 spi_master_put(master);
1410 return ret;
1411}
1412
Grant Likelyfd4a3192012-12-07 16:57:14 +00001413static int atmel_spi_remove(struct platform_device *pdev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001414{
1415 struct spi_master *master = platform_get_drvdata(pdev);
1416 struct atmel_spi *as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001417
1418 /* reset the hardware and block queue progress */
1419 spin_lock_irq(&as->lock);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001420 if (as->use_dma) {
1421 atmel_spi_stop_dma(as);
1422 atmel_spi_release_dma(as);
1423 }
1424
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001425 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001426 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001427 spi_readl(as, SR);
1428 spin_unlock_irq(&as->lock);
1429
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001430 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1431 as->buffer_dma);
1432
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001433 clk_disable_unprepare(as->clk);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001434
1435 return 0;
1436}
1437
Jingoo Hanec60dd32013-09-09 17:54:12 +09001438#ifdef CONFIG_PM_SLEEP
1439static int atmel_spi_suspend(struct device *dev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001440{
Jingoo Hanec60dd32013-09-09 17:54:12 +09001441 struct spi_master *master = dev_get_drvdata(dev);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001442 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yangba938f32014-03-05 11:29:01 +08001443 int ret;
1444
1445 /* Stop the queue running */
1446 ret = spi_master_suspend(master);
1447 if (ret) {
1448 dev_warn(dev, "cannot suspend master\n");
1449 return ret;
1450 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001451
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001452 clk_disable_unprepare(as->clk);
Wenyou Yang5bdfd492014-03-05 09:58:49 +08001453
1454 pinctrl_pm_select_sleep_state(dev);
1455
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001456 return 0;
1457}
1458
Jingoo Hanec60dd32013-09-09 17:54:12 +09001459static int atmel_spi_resume(struct device *dev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001460{
Jingoo Hanec60dd32013-09-09 17:54:12 +09001461 struct spi_master *master = dev_get_drvdata(dev);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001462 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yangba938f32014-03-05 11:29:01 +08001463 int ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001464
Wenyou Yang5bdfd492014-03-05 09:58:49 +08001465 pinctrl_pm_select_default_state(dev);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001466
Jingoo Hanec60dd32013-09-09 17:54:12 +09001467 clk_prepare_enable(as->clk);
Wenyou Yangba938f32014-03-05 11:29:01 +08001468
1469 /* Start the queue running */
1470 ret = spi_master_resume(master);
1471 if (ret)
1472 dev_err(dev, "problem starting queue (%d)\n", ret);
1473
1474 return ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001475}
1476
Jingoo Hanec60dd32013-09-09 17:54:12 +09001477static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume);
1478
1479#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001480#else
Jingoo Hanec60dd32013-09-09 17:54:12 +09001481#define ATMEL_SPI_PM_OPS NULL
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001482#endif
1483
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001484#if defined(CONFIG_OF)
1485static const struct of_device_id atmel_spi_dt_ids[] = {
1486 { .compatible = "atmel,at91rm9200-spi" },
1487 { /* sentinel */ }
1488};
1489
1490MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1491#endif
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001492
1493static struct platform_driver atmel_spi_driver = {
1494 .driver = {
1495 .name = "atmel_spi",
1496 .owner = THIS_MODULE,
Jingoo Hanec60dd32013-09-09 17:54:12 +09001497 .pm = ATMEL_SPI_PM_OPS,
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001498 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001499 },
Jean-Christophe PLAGNIOL-VILLARD1cb201a2011-11-04 01:20:21 +08001500 .probe = atmel_spi_probe,
Grant Likely2deff8d2013-02-05 13:27:35 +00001501 .remove = atmel_spi_remove,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001502};
Grant Likely940ab882011-10-05 11:29:49 -06001503module_platform_driver(atmel_spi_driver);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001504
1505MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
Jean Delvaree05503e2011-05-18 16:49:24 +02001506MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001507MODULE_LICENSE("GPL");
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001508MODULE_ALIAS("platform:atmel_spi");