blob: 868ed40cb6bf070ba5b6b5a4156cda73f54fa9fa [file] [log] [blame]
Rob Herringa900e5d2013-02-12 16:04:52 -06001/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Combiner irqchip for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/err.h>
12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/io.h>
Arnd Bergmannd34f03d2013-04-10 15:31:11 +020015#include <linux/slab.h>
Rob Herringa900e5d2013-02-12 16:04:52 -060016#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000017#include <linux/irqchip/chained_irq.h>
Rob Herringa900e5d2013-02-12 16:04:52 -060018#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <asm/mach/irq.h>
21
Rob Herringa900e5d2013-02-12 16:04:52 -060022#include "irqchip.h"
23
24#define COMBINER_ENABLE_SET 0x0
25#define COMBINER_ENABLE_CLEAR 0x4
26#define COMBINER_INT_STATUS 0xC
27
Arnd Bergmann6761dcf2013-04-10 15:17:47 +020028#define IRQ_IN_COMBINER 8
29
Rob Herringa900e5d2013-02-12 16:04:52 -060030static DEFINE_SPINLOCK(irq_controller_lock);
31
32struct combiner_chip_data {
Arnd Bergmann20adee82013-04-18 23:57:26 +020033 unsigned int hwirq_offset;
Rob Herringa900e5d2013-02-12 16:04:52 -060034 unsigned int irq_mask;
35 void __iomem *base;
Chanho Parkdf7ef462012-12-12 14:02:45 +090036 unsigned int parent_irq;
Rob Herringa900e5d2013-02-12 16:04:52 -060037};
38
39static struct irq_domain *combiner_irq_domain;
Rob Herringa900e5d2013-02-12 16:04:52 -060040
41static inline void __iomem *combiner_base(struct irq_data *data)
42{
43 struct combiner_chip_data *combiner_data =
44 irq_data_get_irq_chip_data(data);
45
46 return combiner_data->base;
47}
48
49static void combiner_mask_irq(struct irq_data *data)
50{
51 u32 mask = 1 << (data->hwirq % 32);
52
53 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
54}
55
56static void combiner_unmask_irq(struct irq_data *data)
57{
58 u32 mask = 1 << (data->hwirq % 32);
59
60 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
61}
62
63static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
64{
65 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
66 struct irq_chip *chip = irq_get_chip(irq);
67 unsigned int cascade_irq, combiner_irq;
68 unsigned long status;
69
70 chained_irq_enter(chip, desc);
71
72 spin_lock(&irq_controller_lock);
73 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
74 spin_unlock(&irq_controller_lock);
75 status &= chip_data->irq_mask;
76
77 if (status == 0)
78 goto out;
79
Arnd Bergmann20adee82013-04-18 23:57:26 +020080 combiner_irq = chip_data->hwirq_offset + __ffs(status);
81 cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq);
Rob Herringa900e5d2013-02-12 16:04:52 -060082
Arnd Bergmann20adee82013-04-18 23:57:26 +020083 if (unlikely(!cascade_irq))
84 do_bad_IRQ(irq, desc);
Rob Herringa900e5d2013-02-12 16:04:52 -060085 else
86 generic_handle_irq(cascade_irq);
87
88 out:
89 chained_irq_exit(chip, desc);
90}
91
Chanho Parkdf7ef462012-12-12 14:02:45 +090092#ifdef CONFIG_SMP
93static int combiner_set_affinity(struct irq_data *d,
94 const struct cpumask *mask_val, bool force)
95{
96 struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
97 struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
98 struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
99
100 if (chip && chip->irq_set_affinity)
101 return chip->irq_set_affinity(data, mask_val, force);
102 else
103 return -EINVAL;
104}
105#endif
106
Rob Herringa900e5d2013-02-12 16:04:52 -0600107static struct irq_chip combiner_chip = {
Chanho Parkdf7ef462012-12-12 14:02:45 +0900108 .name = "COMBINER",
109 .irq_mask = combiner_mask_irq,
110 .irq_unmask = combiner_unmask_irq,
111#ifdef CONFIG_SMP
112 .irq_set_affinity = combiner_set_affinity,
113#endif
Rob Herringa900e5d2013-02-12 16:04:52 -0600114};
115
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200116static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data,
Chanho Park4e164dc2012-12-12 14:02:49 +0900117 unsigned int irq)
118{
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200119 if (irq_set_handler_data(irq, combiner_data) != 0)
Rob Herringa900e5d2013-02-12 16:04:52 -0600120 BUG();
121 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
122}
123
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200124static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
125 unsigned int combiner_nr,
Chanho Parkdf7ef462012-12-12 14:02:45 +0900126 void __iomem *base, unsigned int irq)
Rob Herringa900e5d2013-02-12 16:04:52 -0600127{
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200128 combiner_data->base = base;
Arnd Bergmann20adee82013-04-18 23:57:26 +0200129 combiner_data->hwirq_offset = (combiner_nr & ~3) * IRQ_IN_COMBINER;
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200130 combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
131 combiner_data->parent_irq = irq;
Rob Herringa900e5d2013-02-12 16:04:52 -0600132
133 /* Disable all interrupts */
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200134 __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
Rob Herringa900e5d2013-02-12 16:04:52 -0600135}
136
Rob Herringa900e5d2013-02-12 16:04:52 -0600137static int combiner_irq_domain_xlate(struct irq_domain *d,
138 struct device_node *controller,
139 const u32 *intspec, unsigned int intsize,
140 unsigned long *out_hwirq,
141 unsigned int *out_type)
142{
143 if (d->of_node != controller)
144 return -EINVAL;
145
146 if (intsize < 2)
147 return -EINVAL;
148
Arnd Bergmann6761dcf2013-04-10 15:17:47 +0200149 *out_hwirq = intspec[0] * IRQ_IN_COMBINER + intspec[1];
Rob Herringa900e5d2013-02-12 16:04:52 -0600150 *out_type = 0;
151
152 return 0;
153}
Rob Herringa900e5d2013-02-12 16:04:52 -0600154
155static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
156 irq_hw_number_t hw)
157{
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200158 struct combiner_chip_data *combiner_data = d->host_data;
159
Rob Herringa900e5d2013-02-12 16:04:52 -0600160 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
161 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
162 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
163
164 return 0;
165}
166
167static struct irq_domain_ops combiner_irq_domain_ops = {
168 .xlate = combiner_irq_domain_xlate,
169 .map = combiner_irq_domain_map,
170};
171
Sachin Kamatb8394de2013-06-26 17:06:37 +0530172static void __init combiner_init(void __iomem *combiner_base,
173 struct device_node *np,
174 unsigned int max_nr,
175 int irq_base)
Rob Herringa900e5d2013-02-12 16:04:52 -0600176{
Arnd Bergmann863a08d2013-04-12 15:27:09 +0200177 int i, irq;
Arnd Bergmann6761dcf2013-04-10 15:17:47 +0200178 unsigned int nr_irq;
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200179 struct combiner_chip_data *combiner_data;
Rob Herringa900e5d2013-02-12 16:04:52 -0600180
Arnd Bergmann6761dcf2013-04-10 15:17:47 +0200181 nr_irq = max_nr * IRQ_IN_COMBINER;
Chanho Park4e164dc2012-12-12 14:02:49 +0900182
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200183 combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL);
184 if (!combiner_data) {
185 pr_warning("%s: could not allocate combiner data\n", __func__);
186 return;
Rob Herringa900e5d2013-02-12 16:04:52 -0600187 }
Chanho Park4e164dc2012-12-12 14:02:49 +0900188
Arnd Bergmann863a08d2013-04-12 15:27:09 +0200189 combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base,
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200190 &combiner_irq_domain_ops, combiner_data);
Rob Herringa900e5d2013-02-12 16:04:52 -0600191 if (WARN_ON(!combiner_irq_domain)) {
192 pr_warning("%s: irq domain init failed\n", __func__);
193 return;
194 }
195
196 for (i = 0; i < max_nr; i++) {
Kukjin Kim0f561512013-07-16 12:18:19 +0900197 irq = irq_of_parse_and_map(np, i);
Arnd Bergmann92c8e492013-04-10 15:59:58 +0200198
Arnd Bergmannd34f03d2013-04-10 15:31:11 +0200199 combiner_init_one(&combiner_data[i], i,
200 combiner_base + (i >> 2) * 0x10, irq);
201 combiner_cascade_irq(&combiner_data[i], irq);
Rob Herringa900e5d2013-02-12 16:04:52 -0600202 }
203}
204
Rob Herringa900e5d2013-02-12 16:04:52 -0600205static int __init combiner_of_init(struct device_node *np,
206 struct device_node *parent)
207{
208 void __iomem *combiner_base;
Arnd Bergmann6761dcf2013-04-10 15:17:47 +0200209 unsigned int max_nr = 20;
Arnd Bergmann863a08d2013-04-12 15:27:09 +0200210 int irq_base = -1;
Rob Herringa900e5d2013-02-12 16:04:52 -0600211
212 combiner_base = of_iomap(np, 0);
213 if (!combiner_base) {
214 pr_err("%s: failed to map combiner registers\n", __func__);
215 return -ENXIO;
216 }
217
Arnd Bergmann6761dcf2013-04-10 15:17:47 +0200218 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
219 pr_info("%s: number of combiners not specified, "
220 "setting default as %d.\n",
221 __func__, max_nr);
222 }
223
Arnd Bergmann863a08d2013-04-12 15:27:09 +0200224 /*
225 * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices
226 * get their IRQ from DT, remove this in order to get dynamic
227 * allocation.
228 */
229 irq_base = 160;
230
231 combiner_init(combiner_base, np, max_nr, irq_base);
Rob Herringa900e5d2013-02-12 16:04:52 -0600232
233 return 0;
234}
235IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
236 combiner_of_init);