blob: c66ccbcdc11b820a3b1d7bf57b53452c4d00f648 [file] [log] [blame]
Sascha Hauer90292ea2008-07-05 10:02:50 +02001/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
Valentin Longchampb7222632009-01-28 15:13:50 +01004 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
Sascha Hauer90292ea2008-07-05 10:02:50 +02005 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
Valentin Longchampb7222632009-01-28 15:13:50 +010024#include <linux/kernel.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010025#include <mach/hardware.h>
26#include <mach/gpio.h>
27#include <mach/iomux-mx3.h>
Sascha Hauer90292ea2008-07-05 10:02:50 +020028
29/*
30 * IOMUX register (base) addresses
31 */
32#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR)
33#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
34#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
35#define IOMUXGPR (IOMUX_BASE + 0x008)
36#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
37#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
38
39static DEFINE_SPINLOCK(gpio_mux_lock);
40
41#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
Valentin Longchampb7222632009-01-28 15:13:50 +010042
43unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
Sascha Hauer90292ea2008-07-05 10:02:50 +020044/*
45 * set the mode for a IOMUX pin.
46 */
47int mxc_iomux_mode(unsigned int pin_mode)
48{
Luotao Fudefa8c32008-09-09 10:19:43 +020049 u32 field, l, mode, ret = 0;
50 void __iomem *reg;
Sascha Hauer90292ea2008-07-05 10:02:50 +020051
52 reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
53 field = pin_mode & 0x3;
54 mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
55
Sascha Hauer90292ea2008-07-05 10:02:50 +020056 spin_lock(&gpio_mux_lock);
57
58 l = __raw_readl(reg);
59 l &= ~(0xff << (field * 8));
60 l |= mode << (field * 8);
61 __raw_writel(l, reg);
62
63 spin_unlock(&gpio_mux_lock);
64
65 return ret;
66}
67EXPORT_SYMBOL(mxc_iomux_mode);
68
69/*
70 * This function configures the pad value for a IOMUX pin.
71 */
72void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
73{
Luotao Fudefa8c32008-09-09 10:19:43 +020074 u32 field, l;
75 void __iomem *reg;
Sascha Hauer90292ea2008-07-05 10:02:50 +020076
Guennadi Liakhovetski4a7b98d2008-11-13 12:20:49 +010077 pin &= IOMUX_PADNUM_MASK;
78 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
Sascha Hauer90292ea2008-07-05 10:02:50 +020079 field = (pin + 2) % 3;
80
Guennadi Liakhovetski4a7b98d2008-11-13 12:20:49 +010081 pr_debug("%s: reg offset = 0x%x, field = %d\n",
Sascha Hauer90292ea2008-07-05 10:02:50 +020082 __func__, (pin + 2) / 3, field);
83
84 spin_lock(&gpio_mux_lock);
85
86 l = __raw_readl(reg);
Guennadi Liakhovetski4a7b98d2008-11-13 12:20:49 +010087 l &= ~(0x1ff << (field * 10));
88 l |= config << (field * 10);
Sascha Hauer90292ea2008-07-05 10:02:50 +020089 __raw_writel(l, reg);
90
91 spin_unlock(&gpio_mux_lock);
92}
93EXPORT_SYMBOL(mxc_iomux_set_pad);
94
95/*
Valentin Longchampef754d62009-05-06 11:44:20 +020096 * allocs a single pin:
Valentin Longchampb7222632009-01-28 15:13:50 +010097 * - reserves the pin so that it is not claimed by another driver
98 * - setups the iomux according to the configuration
Valentin Longchampb7222632009-01-28 15:13:50 +010099 */
Valentin Longchampef754d62009-05-06 11:44:20 +0200100int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
Valentin Longchampb7222632009-01-28 15:13:50 +0100101{
102 unsigned pad = pin & IOMUX_PADNUM_MASK;
Valentin Longchampb7222632009-01-28 15:13:50 +0100103
104 if (pad >= (PIN_MAX + 1)) {
105 printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
106 pad, label ? label : "?");
107 return -EINVAL;
108 }
109
110 if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
111 printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
112 pad, label ? label : "?");
Valentin Longchampef754d62009-05-06 11:44:20 +0200113 return -EBUSY;
Valentin Longchampb7222632009-01-28 15:13:50 +0100114 }
115 mxc_iomux_mode(pin);
116
Valentin Longchampb7222632009-01-28 15:13:50 +0100117 return 0;
118}
Valentin Longchampef754d62009-05-06 11:44:20 +0200119EXPORT_SYMBOL(mxc_iomux_alloc_pin);
Valentin Longchampb7222632009-01-28 15:13:50 +0100120
121int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
122 const char *label)
123{
124 unsigned int *p = pin_list;
125 int i;
126 int ret = -EINVAL;
127
128 for (i = 0; i < count; i++) {
Valentin Longchampef754d62009-05-06 11:44:20 +0200129 ret = mxc_iomux_alloc_pin(*p, label);
130 if (ret)
Valentin Longchampb7222632009-01-28 15:13:50 +0100131 goto setup_error;
132 p++;
133 }
134 return 0;
135
136setup_error:
137 mxc_iomux_release_multiple_pins(pin_list, i);
138 return ret;
139}
140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
141
142void mxc_iomux_release_pin(const unsigned int pin)
143{
144 unsigned pad = pin & IOMUX_PADNUM_MASK;
Valentin Longchampb7222632009-01-28 15:13:50 +0100145
146 if (pad < (PIN_MAX + 1))
147 clear_bit(pad, mxc_pin_alloc_map);
Valentin Longchampb7222632009-01-28 15:13:50 +0100148}
149EXPORT_SYMBOL(mxc_iomux_release_pin);
150
151void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
152{
153 unsigned int *p = pin_list;
154 int i;
155
156 for (i = 0; i < count; i++) {
157 mxc_iomux_release_pin(*p);
158 p++;
159 }
160}
161EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
162
163/*
Sascha Hauer90292ea2008-07-05 10:02:50 +0200164 * This function enables/disables the general purpose function for a particular
165 * signal.
166 */
167void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
168{
169 u32 l;
170
171 spin_lock(&gpio_mux_lock);
172 l = __raw_readl(IOMUXGPR);
173 if (en)
174 l |= gp;
175 else
176 l &= ~gp;
177
178 __raw_writel(l, IOMUXGPR);
179 spin_unlock(&gpio_mux_lock);
180}
181EXPORT_SYMBOL(mxc_iomux_set_gpr);