blob: 12a100389e2c4f682c27d9f51e6da9dfb118ab99 [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040030#include <linux/export.h>
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070035#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010036#include <drm/i915_drm.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070037#include "i915_drv.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070038
Keith Packarda4fc5ed2009-04-07 16:16:42 -070039#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080041struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080060static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
Chon Ming Lee58f6e632013-09-25 15:47:51 +080062 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080063 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
Chon Ming Leeef9348c2014-04-09 13:28:18 +030067/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070085/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070097}
98
Imre Deak68b4d822013-05-08 13:14:06 +030099static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700100{
Imre Deak68b4d822013-05-08 13:14:06 +0300101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700104}
105
Chris Wilsondf0e9242010-09-09 16:20:55 +0100106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
Paulo Zanonifa90ece2012-10-26 19:05:44 -0200108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
Chris Wilsondf0e9242010-09-09 16:20:55 +0100109}
110
Chris Wilsonea5b2132010-08-04 13:50:23 +0100111static void intel_dp_link_down(struct intel_dp *intel_dp);
Jani Nikulaadddaaf2014-03-14 16:51:13 +0200112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +0100113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700114
115static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100116intel_dp_max_link_bw(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700117{
Jesse Barnes7183dc22011-07-07 11:10:58 -0700118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
Todd Previte06ea66b2014-01-20 10:19:39 -0700119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
Imre Deakd4eead52013-07-09 17:05:26 +0300125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
Todd Previte06ea66b2014-01-20 10:19:39 -0700126 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
128 max_link_bw = DP_LINK_BW_5_4;
129 else
130 max_link_bw = DP_LINK_BW_2_7;
Imre Deakd4eead52013-07-09 17:05:26 +0300131 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700132 default:
Imre Deakd4eead52013-07-09 17:05:26 +0300133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
134 max_link_bw);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700135 max_link_bw = DP_LINK_BW_1_62;
136 break;
137 }
138 return max_link_bw;
139}
140
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400141/*
142 * The units on the numbers in the next two are... bizarre. Examples will
143 * make it clearer; this one parallels an example in the eDP spec.
144 *
145 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
146 *
147 * 270000 * 1 * 8 / 10 == 216000
148 *
149 * The actual data capacity of that configuration is 2.16Gbit/s, so the
150 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
151 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
152 * 119000. At 18bpp that's 2142000 kilobits per second.
153 *
154 * Thus the strange-looking division by 10 in intel_dp_link_required, to
155 * get the result in decakilobits instead of kilobits.
156 */
157
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700158static int
Keith Packardc8982612012-01-25 08:16:25 -0800159intel_dp_link_required(int pixel_clock, int bpp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700160{
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400161 return (pixel_clock * bpp + 9) / 10;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700162}
163
164static int
Dave Airliefe27d532010-06-30 11:46:17 +1000165intel_dp_max_data_rate(int max_link_clock, int max_lanes)
166{
167 return (max_link_clock * max_lanes * 8) / 10;
168}
169
Damien Lespiauc19de8e2013-11-28 15:29:18 +0000170static enum drm_mode_status
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700171intel_dp_mode_valid(struct drm_connector *connector,
172 struct drm_display_mode *mode)
173{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100174 struct intel_dp *intel_dp = intel_attached_dp(connector);
Jani Nikuladd06f902012-10-19 14:51:50 +0300175 struct intel_connector *intel_connector = to_intel_connector(connector);
176 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
Daniel Vetter36008362013-03-27 00:44:59 +0100177 int target_clock = mode->clock;
178 int max_rate, mode_rate, max_lanes, max_link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700179
Jani Nikuladd06f902012-10-19 14:51:50 +0300180 if (is_edp(intel_dp) && fixed_mode) {
181 if (mode->hdisplay > fixed_mode->hdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100182 return MODE_PANEL;
183
Jani Nikuladd06f902012-10-19 14:51:50 +0300184 if (mode->vdisplay > fixed_mode->vdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100185 return MODE_PANEL;
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200186
187 target_clock = fixed_mode->clock;
Zhao Yakui7de56f42010-07-19 09:43:14 +0100188 }
189
Daniel Vetter36008362013-03-27 00:44:59 +0100190 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
191 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
192
193 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
194 mode_rate = intel_dp_link_required(target_clock, 18);
195
196 if (mode_rate > max_rate)
Daniel Vetterc4867932012-04-10 10:42:36 +0200197 return MODE_CLOCK_HIGH;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700198
199 if (mode->clock < 10000)
200 return MODE_CLOCK_LOW;
201
Daniel Vetter0af78a22012-05-23 11:30:55 +0200202 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
203 return MODE_H_ILLEGAL;
204
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700205 return MODE_OK;
206}
207
208static uint32_t
209pack_aux(uint8_t *src, int src_bytes)
210{
211 int i;
212 uint32_t v = 0;
213
214 if (src_bytes > 4)
215 src_bytes = 4;
216 for (i = 0; i < src_bytes; i++)
217 v |= ((uint32_t) src[i]) << ((3-i) * 8);
218 return v;
219}
220
221static void
222unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
223{
224 int i;
225 if (dst_bytes > 4)
226 dst_bytes = 4;
227 for (i = 0; i < dst_bytes; i++)
228 dst[i] = src >> ((3-i) * 8);
229}
230
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700231/* hrawclock is 1/4 the FSB frequency */
232static int
233intel_hrawclk(struct drm_device *dev)
234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 uint32_t clkcfg;
237
Vijay Purushothaman9473c8f2012-09-27 19:13:01 +0530238 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
239 if (IS_VALLEYVIEW(dev))
240 return 200;
241
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700242 clkcfg = I915_READ(CLKCFG);
243 switch (clkcfg & CLKCFG_FSB_MASK) {
244 case CLKCFG_FSB_400:
245 return 100;
246 case CLKCFG_FSB_533:
247 return 133;
248 case CLKCFG_FSB_667:
249 return 166;
250 case CLKCFG_FSB_800:
251 return 200;
252 case CLKCFG_FSB_1067:
253 return 266;
254 case CLKCFG_FSB_1333:
255 return 333;
256 /* these two are just a guess; one of them might be right */
257 case CLKCFG_FSB_1600:
258 case CLKCFG_FSB_1600_ALT:
259 return 400;
260 default:
261 return 133;
262 }
263}
264
Jani Nikulabf13e812013-09-06 07:40:05 +0300265static void
266intel_dp_init_panel_power_sequencer(struct drm_device *dev,
267 struct intel_dp *intel_dp,
268 struct edp_power_seq *out);
269static void
270intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
271 struct intel_dp *intel_dp,
272 struct edp_power_seq *out);
273
274static enum pipe
275vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
276{
277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
278 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
279 struct drm_device *dev = intel_dig_port->base.base.dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 enum port port = intel_dig_port->port;
282 enum pipe pipe;
283
284 /* modeset should have pipe */
285 if (crtc)
286 return to_intel_crtc(crtc)->pipe;
287
288 /* init time, try to find a pipe with this port selected */
289 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
290 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
291 PANEL_PORT_SELECT_MASK;
292 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
293 return pipe;
294 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
295 return pipe;
296 }
297
298 /* shrug */
299 return PIPE_A;
300}
301
302static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
303{
304 struct drm_device *dev = intel_dp_to_dev(intel_dp);
305
306 if (HAS_PCH_SPLIT(dev))
307 return PCH_PP_CONTROL;
308 else
309 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
310}
311
312static u32 _pp_stat_reg(struct intel_dp *intel_dp)
313{
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315
316 if (HAS_PCH_SPLIT(dev))
317 return PCH_PP_STATUS;
318 else
319 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
320}
321
Daniel Vetter4be73782014-01-17 14:39:48 +0100322static bool edp_have_panel_power(struct intel_dp *intel_dp)
Keith Packardebf33b12011-09-29 15:53:27 -0700323{
Paulo Zanoni30add222012-10-26 19:05:45 -0200324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700325 struct drm_i915_private *dev_priv = dev->dev_private;
326
Jani Nikulabf13e812013-09-06 07:40:05 +0300327 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700328}
329
Daniel Vetter4be73782014-01-17 14:39:48 +0100330static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
Keith Packardebf33b12011-09-29 15:53:27 -0700331{
Paulo Zanoni30add222012-10-26 19:05:45 -0200332 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700333 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbb4932c2014-04-14 20:24:33 +0300334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct intel_encoder *intel_encoder = &intel_dig_port->base;
336 enum intel_display_power_domain power_domain;
Keith Packardebf33b12011-09-29 15:53:27 -0700337
Imre Deakbb4932c2014-04-14 20:24:33 +0300338 power_domain = intel_display_port_power_domain(intel_encoder);
339 return intel_display_power_enabled(dev_priv, power_domain) &&
Paulo Zanoniefbc20a2014-04-01 14:55:09 -0300340 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700341}
342
Keith Packard9b984da2011-09-19 13:54:47 -0700343static void
344intel_dp_check_edp(struct intel_dp *intel_dp)
345{
Paulo Zanoni30add222012-10-26 19:05:45 -0200346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard9b984da2011-09-19 13:54:47 -0700347 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardebf33b12011-09-29 15:53:27 -0700348
Keith Packard9b984da2011-09-19 13:54:47 -0700349 if (!is_edp(intel_dp))
350 return;
Jesse Barnes453c5422013-03-28 09:55:41 -0700351
Daniel Vetter4be73782014-01-17 14:39:48 +0100352 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
Keith Packard9b984da2011-09-19 13:54:47 -0700353 WARN(1, "eDP powered off while attempting aux channel communication.\n");
354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
Jani Nikulabf13e812013-09-06 07:40:05 +0300355 I915_READ(_pp_stat_reg(intel_dp)),
356 I915_READ(_pp_ctrl_reg(intel_dp)));
Keith Packard9b984da2011-09-19 13:54:47 -0700357 }
358}
359
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100360static uint32_t
361intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
362{
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300366 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100367 uint32_t status;
368 bool done;
369
Daniel Vetteref04f002012-12-01 21:03:59 +0100370#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100371 if (has_aux_irq)
Paulo Zanonib18ac462013-02-18 19:00:24 -0300372 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
Imre Deak35987062013-05-21 20:03:20 +0300373 msecs_to_jiffies_timeout(10));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100374 else
375 done = wait_for_atomic(C, 10) == 0;
376 if (!done)
377 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
378 has_aux_irq);
379#undef C
380
381 return status;
382}
383
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000384static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
385{
386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
387 struct drm_device *dev = intel_dig_port->base.base.dev;
388
389 /*
390 * The clock divider is based off the hrawclk, and would like to run at
391 * 2MHz. So, take the hrawclk value and divide by 2 and use that
392 */
393 return index ? 0 : intel_hrawclk(dev) / 2;
394}
395
396static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400
401 if (index)
402 return 0;
403
404 if (intel_dig_port->port == PORT_A) {
405 if (IS_GEN6(dev) || IS_GEN7(dev))
406 return 200; /* SNB & IVB eDP input clock at 400Mhz */
407 else
408 return 225; /* eDP input clock at 450Mhz */
409 } else {
410 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
411 }
412}
413
414static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300415{
416 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
417 struct drm_device *dev = intel_dig_port->base.base.dev;
418 struct drm_i915_private *dev_priv = dev->dev_private;
419
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000420 if (intel_dig_port->port == PORT_A) {
Chris Wilsonbc866252013-07-21 16:00:03 +0100421 if (index)
422 return 0;
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000423 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300424 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
425 /* Workaround for non-ULT HSW */
Chris Wilsonbc866252013-07-21 16:00:03 +0100426 switch (index) {
427 case 0: return 63;
428 case 1: return 72;
429 default: return 0;
430 }
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000431 } else {
Chris Wilsonbc866252013-07-21 16:00:03 +0100432 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300433 }
434}
435
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000436static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
437{
438 return index ? 0 : 100;
439}
440
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000441static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
442 bool has_aux_irq,
443 int send_bytes,
444 uint32_t aux_clock_divider)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448 uint32_t precharge, timeout;
449
450 if (IS_GEN6(dev))
451 precharge = 3;
452 else
453 precharge = 5;
454
455 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
456 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
457 else
458 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
459
460 return DP_AUX_CH_CTL_SEND_BUSY |
Damien Lespiau788d4432014-01-20 15:52:31 +0000461 DP_AUX_CH_CTL_DONE |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
Damien Lespiau788d4432014-01-20 15:52:31 +0000463 DP_AUX_CH_CTL_TIME_OUT_ERROR |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000464 timeout |
Damien Lespiau788d4432014-01-20 15:52:31 +0000465 DP_AUX_CH_CTL_RECEIVE_ERROR |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000466 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
467 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
Damien Lespiau788d4432014-01-20 15:52:31 +0000468 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000469}
470
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700471static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100472intel_dp_aux_ch(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700473 uint8_t *send, int send_bytes,
474 uint8_t *recv, int recv_size)
475{
Paulo Zanoni174edf12012-10-26 19:05:50 -0200476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
477 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700478 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300479 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700480 uint32_t ch_data = ch_ctl + 4;
Chris Wilsonbc866252013-07-21 16:00:03 +0100481 uint32_t aux_clock_divider;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100482 int i, ret, recv_bytes;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700483 uint32_t status;
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000484 int try, clock = 0;
Daniel Vetter4e6b7882014-02-07 16:33:20 +0100485 bool has_aux_irq = HAS_AUX_IRQ(dev);
Jani Nikula884f19e2014-03-14 16:51:14 +0200486 bool vdd;
487
488 vdd = _edp_panel_vdd_on(intel_dp);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100489
490 /* dp aux is extremely sensitive to irq latency, hence request the
491 * lowest possible wakeup latency and so prevent the cpu from going into
492 * deep sleep states.
493 */
494 pm_qos_update_request(&dev_priv->pm_qos, 0);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700495
Keith Packard9b984da2011-09-19 13:54:47 -0700496 intel_dp_check_edp(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800497
Paulo Zanonic67a4702013-08-19 13:18:09 -0300498 intel_aux_display_runtime_get(dev_priv);
499
Jesse Barnes11bee432011-08-01 15:02:20 -0700500 /* Try to wait for any previous AUX channel activity */
501 for (try = 0; try < 3; try++) {
Daniel Vetteref04f002012-12-01 21:03:59 +0100502 status = I915_READ_NOTRACE(ch_ctl);
Jesse Barnes11bee432011-08-01 15:02:20 -0700503 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
504 break;
505 msleep(1);
506 }
507
508 if (try == 3) {
509 WARN(1, "dp_aux_ch not started status 0x%08x\n",
510 I915_READ(ch_ctl));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100511 ret = -EBUSY;
512 goto out;
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100513 }
514
Paulo Zanoni46a5ae92013-09-17 11:14:10 -0300515 /* Only 5 data registers! */
516 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
517 ret = -E2BIG;
518 goto out;
519 }
520
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000521 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
Damien Lespiau153b1102014-01-21 13:37:15 +0000522 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
523 has_aux_irq,
524 send_bytes,
525 aux_clock_divider);
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000526
Chris Wilsonbc866252013-07-21 16:00:03 +0100527 /* Must try at least 3 times according to DP spec */
528 for (try = 0; try < 5; try++) {
529 /* Load the send data into the aux channel data registers */
530 for (i = 0; i < send_bytes; i += 4)
531 I915_WRITE(ch_data + i,
532 pack_aux(send + i, send_bytes - i));
Akshay Joshi0206e352011-08-16 15:34:10 -0400533
Chris Wilsonbc866252013-07-21 16:00:03 +0100534 /* Send the command and wait for it to complete */
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000535 I915_WRITE(ch_ctl, send_ctl);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100536
Chris Wilsonbc866252013-07-21 16:00:03 +0100537 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
Akshay Joshi0206e352011-08-16 15:34:10 -0400538
Chris Wilsonbc866252013-07-21 16:00:03 +0100539 /* Clear done status and any errors */
540 I915_WRITE(ch_ctl,
541 status |
542 DP_AUX_CH_CTL_DONE |
543 DP_AUX_CH_CTL_TIME_OUT_ERROR |
544 DP_AUX_CH_CTL_RECEIVE_ERROR);
Adam Jacksond7e96fe2011-07-26 15:39:46 -0400545
Chris Wilsonbc866252013-07-21 16:00:03 +0100546 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
547 DP_AUX_CH_CTL_RECEIVE_ERROR))
548 continue;
549 if (status & DP_AUX_CH_CTL_DONE)
550 break;
551 }
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100552 if (status & DP_AUX_CH_CTL_DONE)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700553 break;
554 }
555
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700556 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700557 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100558 ret = -EBUSY;
559 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700560 }
561
562 /* Check for timeout or receive error.
563 * Timeouts occur when the sink is not connected
564 */
Keith Packarda5b3da52009-06-11 22:30:32 -0700565 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700566 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100567 ret = -EIO;
568 goto out;
Keith Packarda5b3da52009-06-11 22:30:32 -0700569 }
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700570
571 /* Timeouts occur when the device isn't connected, so they're
572 * "normal" -- don't fill the kernel log with these */
Keith Packarda5b3da52009-06-11 22:30:32 -0700573 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
Zhao Yakui28c97732009-10-09 11:39:41 +0800574 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100575 ret = -ETIMEDOUT;
576 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700577 }
578
579 /* Unload any bytes sent back from the other side */
580 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
581 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700582 if (recv_bytes > recv_size)
583 recv_bytes = recv_size;
Akshay Joshi0206e352011-08-16 15:34:10 -0400584
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100585 for (i = 0; i < recv_bytes; i += 4)
586 unpack_aux(I915_READ(ch_data + i),
587 recv + i, recv_bytes - i);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700588
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100589 ret = recv_bytes;
590out:
591 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
Paulo Zanonic67a4702013-08-19 13:18:09 -0300592 intel_aux_display_runtime_put(dev_priv);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100593
Jani Nikula884f19e2014-03-14 16:51:14 +0200594 if (vdd)
595 edp_panel_vdd_off(intel_dp, false);
596
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100597 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700598}
599
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300600#define BARE_ADDRESS_SIZE 3
601#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
Jani Nikula9d1a1032014-03-14 16:51:15 +0200602static ssize_t
603intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700604{
Jani Nikula9d1a1032014-03-14 16:51:15 +0200605 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
606 uint8_t txbuf[20], rxbuf[20];
607 size_t txsize, rxsize;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700608 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700609
Jani Nikula9d1a1032014-03-14 16:51:15 +0200610 txbuf[0] = msg->request << 4;
611 txbuf[1] = msg->address >> 8;
612 txbuf[2] = msg->address & 0xff;
613 txbuf[3] = msg->size - 1;
Paulo Zanoni46a5ae92013-09-17 11:14:10 -0300614
Jani Nikula9d1a1032014-03-14 16:51:15 +0200615 switch (msg->request & ~DP_AUX_I2C_MOT) {
616 case DP_AUX_NATIVE_WRITE:
617 case DP_AUX_I2C_WRITE:
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300618 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200619 rxsize = 1;
Jani Nikulaf51a44b2014-02-11 11:52:05 +0200620
Jani Nikula9d1a1032014-03-14 16:51:15 +0200621 if (WARN_ON(txsize > 20))
622 return -E2BIG;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700623
Jani Nikula9d1a1032014-03-14 16:51:15 +0200624 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700625
Jani Nikula9d1a1032014-03-14 16:51:15 +0200626 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
627 if (ret > 0) {
628 msg->reply = rxbuf[0] >> 4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700629
Jani Nikula9d1a1032014-03-14 16:51:15 +0200630 /* Return payload size. */
631 ret = msg->size;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700632 }
Jani Nikula9d1a1032014-03-14 16:51:15 +0200633 break;
634
635 case DP_AUX_NATIVE_READ:
636 case DP_AUX_I2C_READ:
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300637 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200638 rxsize = msg->size + 1;
639
640 if (WARN_ON(rxsize > 20))
641 return -E2BIG;
642
643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
646 /*
647 * Assume happy day, and copy the data. The caller is
648 * expected to check msg->reply before touching it.
649 *
650 * Return payload size.
651 */
652 ret--;
653 memcpy(msg->buffer, rxbuf + 1, ret);
654 }
655 break;
656
657 default:
658 ret = -EINVAL;
659 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700660 }
Jani Nikulaf51a44b2014-02-11 11:52:05 +0200661
Jani Nikula9d1a1032014-03-14 16:51:15 +0200662 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700663}
664
Jani Nikula9d1a1032014-03-14 16:51:15 +0200665static void
666intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700667{
Jani Nikula9d1a1032014-03-14 16:51:15 +0200668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jani Nikula33ad6622014-03-14 16:51:16 +0200669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 enum port port = intel_dig_port->port;
Jani Nikula0b998362014-03-14 16:51:17 +0200671 const char *name = NULL;
Dave Airlieab2c0672009-12-04 10:55:24 +1000672 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700673
Jani Nikula33ad6622014-03-14 16:51:16 +0200674 switch (port) {
675 case PORT_A:
676 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200677 name = "DPDDC-A";
Dave Airlieab2c0672009-12-04 10:55:24 +1000678 break;
Jani Nikula33ad6622014-03-14 16:51:16 +0200679 case PORT_B:
680 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200681 name = "DPDDC-B";
Jani Nikula33ad6622014-03-14 16:51:16 +0200682 break;
683 case PORT_C:
684 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200685 name = "DPDDC-C";
Jani Nikula33ad6622014-03-14 16:51:16 +0200686 break;
687 case PORT_D:
688 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200689 name = "DPDDC-D";
Dave Airlieab2c0672009-12-04 10:55:24 +1000690 break;
691 default:
Jani Nikula33ad6622014-03-14 16:51:16 +0200692 BUG();
Dave Airlieab2c0672009-12-04 10:55:24 +1000693 }
694
Jani Nikula33ad6622014-03-14 16:51:16 +0200695 if (!HAS_DDI(dev))
696 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
David Flynn8316f332010-12-08 16:10:21 +0000697
Jani Nikula0b998362014-03-14 16:51:17 +0200698 intel_dp->aux.name = name;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200699 intel_dp->aux.dev = dev->dev;
700 intel_dp->aux.transfer = intel_dp_aux_transfer;
David Flynn8316f332010-12-08 16:10:21 +0000701
Jani Nikula0b998362014-03-14 16:51:17 +0200702 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
703 connector->base.kdev->kobj.name);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700704
Jani Nikula0b998362014-03-14 16:51:17 +0200705 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
706 if (ret < 0) {
707 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
708 name, ret);
709 return;
Dave Airlieab2c0672009-12-04 10:55:24 +1000710 }
David Flynn8316f332010-12-08 16:10:21 +0000711
Jani Nikula0b998362014-03-14 16:51:17 +0200712 ret = sysfs_create_link(&connector->base.kdev->kobj,
713 &intel_dp->aux.ddc.dev.kobj,
714 intel_dp->aux.ddc.dev.kobj.name);
715 if (ret < 0) {
716 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
717 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700718 }
719}
720
Imre Deak80f65de2014-02-11 17:12:49 +0200721static void
722intel_dp_connector_unregister(struct intel_connector *intel_connector)
723{
724 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
725
726 sysfs_remove_link(&intel_connector->base.kdev->kobj,
Jani Nikula0b998362014-03-14 16:51:17 +0200727 intel_dp->aux.ddc.dev.kobj.name);
Imre Deak80f65de2014-02-11 17:12:49 +0200728 intel_connector_unregister(intel_connector);
729}
730
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200731static void
732intel_dp_set_clock(struct intel_encoder *encoder,
733 struct intel_crtc_config *pipe_config, int link_bw)
734{
735 struct drm_device *dev = encoder->base.dev;
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800736 const struct dp_link_dpll *divisor = NULL;
737 int i, count = 0;
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200738
739 if (IS_G4X(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800740 divisor = gen4_dpll;
741 count = ARRAY_SIZE(gen4_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200742 } else if (IS_HASWELL(dev)) {
743 /* Haswell has special-purpose DP DDI clocks. */
744 } else if (HAS_PCH_SPLIT(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800745 divisor = pch_dpll;
746 count = ARRAY_SIZE(pch_dpll);
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300747 } else if (IS_CHERRYVIEW(dev)) {
748 divisor = chv_dpll;
749 count = ARRAY_SIZE(chv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200750 } else if (IS_VALLEYVIEW(dev)) {
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +0800751 divisor = vlv_dpll;
752 count = ARRAY_SIZE(vlv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200753 }
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800754
755 if (divisor && count) {
756 for (i = 0; i < count; i++) {
757 if (link_bw == divisor[i].link_bw) {
758 pipe_config->dpll = divisor[i].dpll;
759 pipe_config->clock_set = true;
760 break;
761 }
762 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200763 }
764}
765
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530766static void
767intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
768{
769 struct drm_device *dev = crtc->base.dev;
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 enum transcoder transcoder = crtc->config.cpu_transcoder;
772
773 I915_WRITE(PIPE_DATA_M2(transcoder),
774 TU_SIZE(m_n->tu) | m_n->gmch_m);
775 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
776 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
777 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
778}
779
Paulo Zanoni00c09d72012-10-26 19:05:52 -0200780bool
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100781intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700783{
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100784 struct drm_device *dev = encoder->base.dev;
Daniel Vetter36008362013-03-27 00:44:59 +0100785 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +0300788 enum port port = dp_to_dig_port(intel_dp)->port;
Jesse Barnes2dd24552013-04-25 12:55:01 -0700789 struct intel_crtc *intel_crtc = encoder->new_crtc;
Jani Nikuladd06f902012-10-19 14:51:50 +0300790 struct intel_connector *intel_connector = intel_dp->attached_connector;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700791 int lane_count, clock;
Daniel Vetter397fe152012-10-22 22:56:43 +0200792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
Todd Previte06ea66b2014-01-20 10:19:39 -0700793 /* Conveniently, the link BW constants become indices with a shift...*/
794 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
Daniel Vetter083f9562012-04-20 20:23:49 +0200795 int bpp, mode_rate;
Todd Previte06ea66b2014-01-20 10:19:39 -0700796 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
Daniel Vetterff9a6752013-06-01 17:16:21 +0200797 int link_avail, link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700798
Imre Deakbc7d38a2013-05-16 14:40:36 +0300799 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100800 pipe_config->has_pch_encoder = true;
801
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200802 pipe_config->has_dp_encoder = true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700803
Jani Nikuladd06f902012-10-19 14:51:50 +0300804 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
805 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
806 adjusted_mode);
Jesse Barnes2dd24552013-04-25 12:55:01 -0700807 if (!HAS_PCH_SPLIT(dev))
808 intel_gmch_panel_fitting(intel_crtc, pipe_config,
809 intel_connector->panel.fitting_mode);
810 else
Jesse Barnesb074cec2013-04-25 12:55:02 -0700811 intel_pch_panel_fitting(intel_crtc, pipe_config,
812 intel_connector->panel.fitting_mode);
Zhao Yakui0d3a1be2010-07-19 09:43:13 +0100813 }
814
Daniel Vettercb1793c2012-06-04 18:39:21 +0200815 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
Daniel Vetter0af78a22012-05-23 11:30:55 +0200816 return false;
817
Daniel Vetter083f9562012-04-20 20:23:49 +0200818 DRM_DEBUG_KMS("DP link computation with max lane count %i "
819 "max bw %02x pixel clock %iKHz\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +0100820 max_lane_count, bws[max_clock],
821 adjusted_mode->crtc_clock);
Daniel Vetter083f9562012-04-20 20:23:49 +0200822
Daniel Vetter36008362013-03-27 00:44:59 +0100823 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
824 * bpc in between. */
Daniel Vetter3e7ca982013-06-01 19:45:56 +0200825 bpp = pipe_config->pipe_bpp;
Jani Nikula6da7f102013-10-16 17:06:17 +0300826 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
827 dev_priv->vbt.edp_bpp < bpp) {
Imre Deak79842112013-07-18 17:44:13 +0300828 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
829 dev_priv->vbt.edp_bpp);
Jani Nikula6da7f102013-10-16 17:06:17 +0300830 bpp = dev_priv->vbt.edp_bpp;
Imre Deak79842112013-07-18 17:44:13 +0300831 }
Daniel Vetter657445f2013-05-04 10:09:18 +0200832
Daniel Vetter36008362013-03-27 00:44:59 +0100833 for (; bpp >= 6*3; bpp -= 2*3) {
Damien Lespiau241bfc32013-09-25 16:45:37 +0100834 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
835 bpp);
Daniel Vetterc4867932012-04-10 10:42:36 +0200836
Daniel Vetter38aecea2014-03-03 11:18:10 +0100837 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
838 for (clock = 0; clock <= max_clock; clock++) {
Daniel Vetter36008362013-03-27 00:44:59 +0100839 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
840 link_avail = intel_dp_max_data_rate(link_clock,
841 lane_count);
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200842
Daniel Vetter36008362013-03-27 00:44:59 +0100843 if (mode_rate <= link_avail) {
844 goto found;
845 }
846 }
847 }
848 }
849
850 return false;
851
852found:
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200853 if (intel_dp->color_range_auto) {
854 /*
855 * See:
856 * CEA-861-E - 5.1 Default Encoding Parameters
857 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
858 */
Thierry Reding18316c82012-12-20 15:41:44 +0100859 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200860 intel_dp->color_range = DP_COLOR_RANGE_16_235;
861 else
862 intel_dp->color_range = 0;
863 }
864
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200865 if (intel_dp->color_range)
Daniel Vetter50f3b012013-03-27 00:44:56 +0100866 pipe_config->limited_color_range = true;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200867
Daniel Vetter36008362013-03-27 00:44:59 +0100868 intel_dp->link_bw = bws[clock];
869 intel_dp->lane_count = lane_count;
Daniel Vetter657445f2013-05-04 10:09:18 +0200870 pipe_config->pipe_bpp = bpp;
Daniel Vetterff9a6752013-06-01 17:16:21 +0200871 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
Daniel Vetterc4867932012-04-10 10:42:36 +0200872
Daniel Vetter36008362013-03-27 00:44:59 +0100873 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
874 intel_dp->link_bw, intel_dp->lane_count,
Daniel Vetterff9a6752013-06-01 17:16:21 +0200875 pipe_config->port_clock, bpp);
Daniel Vetter36008362013-03-27 00:44:59 +0100876 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
877 mode_rate, link_avail);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700878
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200879 intel_link_compute_m_n(bpp, lane_count,
Damien Lespiau241bfc32013-09-25 16:45:37 +0100880 adjusted_mode->crtc_clock,
881 pipe_config->port_clock,
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200882 &pipe_config->dp_m_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700883
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530884 if (intel_connector->panel.downclock_mode != NULL &&
885 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
886 intel_link_compute_m_n(bpp, lane_count,
887 intel_connector->panel.downclock_mode->clock,
888 pipe_config->port_clock,
889 &pipe_config->dp_m2_n2);
890 }
891
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200892 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
893
Daniel Vetter36008362013-03-27 00:44:59 +0100894 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700895}
896
Daniel Vetter7c62a162013-06-01 17:16:20 +0200897static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
Daniel Vetterea9b6002012-11-29 15:59:31 +0100898{
Daniel Vetter7c62a162013-06-01 17:16:20 +0200899 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
900 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
901 struct drm_device *dev = crtc->base.dev;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100902 struct drm_i915_private *dev_priv = dev->dev_private;
903 u32 dpa_ctl;
904
Daniel Vetterff9a6752013-06-01 17:16:21 +0200905 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
Daniel Vetterea9b6002012-11-29 15:59:31 +0100906 dpa_ctl = I915_READ(DP_A);
907 dpa_ctl &= ~DP_PLL_FREQ_MASK;
908
Daniel Vetterff9a6752013-06-01 17:16:21 +0200909 if (crtc->config.port_clock == 162000) {
Daniel Vetter1ce17032012-11-29 15:59:32 +0100910 /* For a long time we've carried around a ILK-DevA w/a for the
911 * 160MHz clock. If we're really unlucky, it's still required.
912 */
913 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
Daniel Vetterea9b6002012-11-29 15:59:31 +0100914 dpa_ctl |= DP_PLL_FREQ_160MHZ;
Daniel Vetter7c62a162013-06-01 17:16:20 +0200915 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100916 } else {
917 dpa_ctl |= DP_PLL_FREQ_270MHZ;
Daniel Vetter7c62a162013-06-01 17:16:20 +0200918 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100919 }
Daniel Vetter1ce17032012-11-29 15:59:32 +0100920
Daniel Vetterea9b6002012-11-29 15:59:31 +0100921 I915_WRITE(DP_A, dpa_ctl);
922
923 POSTING_READ(DP_A);
924 udelay(500);
925}
926
Daniel Vetterb934223d2013-07-21 21:37:05 +0200927static void intel_dp_mode_set(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700928{
Daniel Vetterb934223d2013-07-21 21:37:05 +0200929 struct drm_device *dev = encoder->base.dev;
Keith Packard417e8222011-11-01 19:54:11 -0700930 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200931 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +0300932 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200933 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
934 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700935
Keith Packard417e8222011-11-01 19:54:11 -0700936 /*
Keith Packard1a2eb462011-11-16 16:26:07 -0800937 * There are four kinds of DP registers:
Keith Packard417e8222011-11-01 19:54:11 -0700938 *
939 * IBX PCH
Keith Packard1a2eb462011-11-16 16:26:07 -0800940 * SNB CPU
941 * IVB CPU
Keith Packard417e8222011-11-01 19:54:11 -0700942 * CPT PCH
943 *
944 * IBX PCH and CPU are the same for almost everything,
945 * except that the CPU DP PLL is configured in this
946 * register
947 *
948 * CPT PCH is quite different, having many bits moved
949 * to the TRANS_DP_CTL register instead. That
950 * configuration happens (oddly) in ironlake_pch_enable
951 */
Adam Jackson9c9e7922010-04-05 17:57:59 -0400952
Keith Packard417e8222011-11-01 19:54:11 -0700953 /* Preserve the BIOS-computed detected bit. This is
954 * supposed to be read-only.
955 */
956 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700957
Keith Packard417e8222011-11-01 19:54:11 -0700958 /* Handle DP bits in common between all three register formats */
Keith Packard417e8222011-11-01 19:54:11 -0700959 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Daniel Vetter17aa6be2013-04-30 14:01:40 +0200960 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700961
Wu Fengguange0dac652011-09-05 14:25:34 +0800962 if (intel_dp->has_audio) {
963 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
Daniel Vetter7c62a162013-06-01 17:16:20 +0200964 pipe_name(crtc->pipe));
Chris Wilsonea5b2132010-08-04 13:50:23 +0100965 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200966 intel_write_eld(&encoder->base, adjusted_mode);
Wu Fengguange0dac652011-09-05 14:25:34 +0800967 }
Paulo Zanoni247d89f2012-10-15 15:51:33 -0300968
Keith Packard417e8222011-11-01 19:54:11 -0700969 /* Split out the IBX/CPU vs CPT settings */
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800970
Imre Deakbc7d38a2013-05-16 14:40:36 +0300971 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
Keith Packard1a2eb462011-11-16 16:26:07 -0800972 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
973 intel_dp->DP |= DP_SYNC_HS_HIGH;
974 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
975 intel_dp->DP |= DP_SYNC_VS_HIGH;
976 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
977
Jani Nikula6aba5b62013-10-04 15:08:10 +0300978 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
Keith Packard1a2eb462011-11-16 16:26:07 -0800979 intel_dp->DP |= DP_ENHANCED_FRAMING;
980
Daniel Vetter7c62a162013-06-01 17:16:20 +0200981 intel_dp->DP |= crtc->pipe << 29;
Imre Deakbc7d38a2013-05-16 14:40:36 +0300982 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
Jesse Barnesb2634012013-03-28 09:55:40 -0700983 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200984 intel_dp->DP |= intel_dp->color_range;
Keith Packard417e8222011-11-01 19:54:11 -0700985
986 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
987 intel_dp->DP |= DP_SYNC_HS_HIGH;
988 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
989 intel_dp->DP |= DP_SYNC_VS_HIGH;
990 intel_dp->DP |= DP_LINK_TRAIN_OFF;
991
Jani Nikula6aba5b62013-10-04 15:08:10 +0300992 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
Keith Packard417e8222011-11-01 19:54:11 -0700993 intel_dp->DP |= DP_ENHANCED_FRAMING;
994
Daniel Vetter7c62a162013-06-01 17:16:20 +0200995 if (crtc->pipe == 1)
Keith Packard417e8222011-11-01 19:54:11 -0700996 intel_dp->DP |= DP_PIPEB_SELECT;
Keith Packard417e8222011-11-01 19:54:11 -0700997 } else {
998 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800999 }
Daniel Vetterea9b6002012-11-29 15:59:31 +01001000
Imre Deakbc7d38a2013-05-16 14:40:36 +03001001 if (port == PORT_A && !IS_VALLEYVIEW(dev))
Daniel Vetter7c62a162013-06-01 17:16:20 +02001002 ironlake_set_pll_cpu_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001003}
1004
Paulo Zanoniffd6749d2013-12-19 14:29:42 -02001005#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1006#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
Keith Packard99ea7122011-11-01 19:57:50 -07001007
Paulo Zanoni1a5ef5b2013-12-19 14:29:43 -02001008#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1009#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
Keith Packard99ea7122011-11-01 19:57:50 -07001010
Paulo Zanoniffd6749d2013-12-19 14:29:42 -02001011#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1012#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
Keith Packard99ea7122011-11-01 19:57:50 -07001013
Daniel Vetter4be73782014-01-17 14:39:48 +01001014static void wait_panel_status(struct intel_dp *intel_dp,
Keith Packard99ea7122011-11-01 19:57:50 -07001015 u32 mask,
1016 u32 value)
1017{
Paulo Zanoni30add222012-10-26 19:05:45 -02001018 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001019 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -07001020 u32 pp_stat_reg, pp_ctrl_reg;
1021
Jani Nikulabf13e812013-09-06 07:40:05 +03001022 pp_stat_reg = _pp_stat_reg(intel_dp);
1023 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001024
1025 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001026 mask, value,
1027 I915_READ(pp_stat_reg),
1028 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001029
Jesse Barnes453c5422013-03-28 09:55:41 -07001030 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
Keith Packard99ea7122011-11-01 19:57:50 -07001031 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001032 I915_READ(pp_stat_reg),
1033 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001034 }
Chris Wilson54c136d2013-12-02 09:57:16 +00001035
1036 DRM_DEBUG_KMS("Wait complete\n");
Keith Packard99ea7122011-11-01 19:57:50 -07001037}
1038
Daniel Vetter4be73782014-01-17 14:39:48 +01001039static void wait_panel_on(struct intel_dp *intel_dp)
Keith Packard99ea7122011-11-01 19:57:50 -07001040{
1041 DRM_DEBUG_KMS("Wait for panel power on\n");
Daniel Vetter4be73782014-01-17 14:39:48 +01001042 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
Keith Packard99ea7122011-11-01 19:57:50 -07001043}
1044
Daniel Vetter4be73782014-01-17 14:39:48 +01001045static void wait_panel_off(struct intel_dp *intel_dp)
Keith Packardbd943152011-09-18 23:09:52 -07001046{
Keith Packardbd943152011-09-18 23:09:52 -07001047 DRM_DEBUG_KMS("Wait for panel power off time\n");
Daniel Vetter4be73782014-01-17 14:39:48 +01001048 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
Keith Packardbd943152011-09-18 23:09:52 -07001049}
Keith Packardbd943152011-09-18 23:09:52 -07001050
Daniel Vetter4be73782014-01-17 14:39:48 +01001051static void wait_panel_power_cycle(struct intel_dp *intel_dp)
Keith Packard99ea7122011-11-01 19:57:50 -07001052{
1053 DRM_DEBUG_KMS("Wait for panel power cycle\n");
Paulo Zanonidce56b32013-12-19 14:29:40 -02001054
1055 /* When we disable the VDD override bit last we have to do the manual
1056 * wait. */
1057 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1058 intel_dp->panel_power_cycle_delay);
1059
Daniel Vetter4be73782014-01-17 14:39:48 +01001060 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
Keith Packard99ea7122011-11-01 19:57:50 -07001061}
Keith Packardbd943152011-09-18 23:09:52 -07001062
Daniel Vetter4be73782014-01-17 14:39:48 +01001063static void wait_backlight_on(struct intel_dp *intel_dp)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001064{
1065 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1066 intel_dp->backlight_on_delay);
1067}
1068
Daniel Vetter4be73782014-01-17 14:39:48 +01001069static void edp_wait_backlight_off(struct intel_dp *intel_dp)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001070{
1071 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1072 intel_dp->backlight_off_delay);
1073}
Keith Packard99ea7122011-11-01 19:57:50 -07001074
Keith Packard832dd3c2011-11-01 19:34:06 -07001075/* Read the current pp_control value, unlocking the register if it
1076 * is locked
1077 */
1078
Jesse Barnes453c5422013-03-28 09:55:41 -07001079static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
Keith Packard832dd3c2011-11-01 19:34:06 -07001080{
Jesse Barnes453c5422013-03-28 09:55:41 -07001081 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1083 u32 control;
Jesse Barnes453c5422013-03-28 09:55:41 -07001084
Jani Nikulabf13e812013-09-06 07:40:05 +03001085 control = I915_READ(_pp_ctrl_reg(intel_dp));
Keith Packard832dd3c2011-11-01 19:34:06 -07001086 control &= ~PANEL_UNLOCK_MASK;
1087 control |= PANEL_UNLOCK_REGS;
1088 return control;
Keith Packardbd943152011-09-18 23:09:52 -07001089}
1090
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001091static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001092{
Paulo Zanoni30add222012-10-26 19:05:45 -02001093 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deak4e6e1a52014-03-27 17:45:11 +02001094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1095 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Jesse Barnes5d613502011-01-24 17:10:54 -08001096 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak4e6e1a52014-03-27 17:45:11 +02001097 enum intel_display_power_domain power_domain;
Jesse Barnes5d613502011-01-24 17:10:54 -08001098 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001099 u32 pp_stat_reg, pp_ctrl_reg;
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001100 bool need_to_disable = !intel_dp->want_panel_vdd;
Jesse Barnes5d613502011-01-24 17:10:54 -08001101
Keith Packard97af61f572011-09-28 16:23:51 -07001102 if (!is_edp(intel_dp))
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001103 return false;
Keith Packardbd943152011-09-18 23:09:52 -07001104
1105 intel_dp->want_panel_vdd = true;
Keith Packard99ea7122011-11-01 19:57:50 -07001106
Daniel Vetter4be73782014-01-17 14:39:48 +01001107 if (edp_have_panel_vdd(intel_dp))
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001108 return need_to_disable;
Paulo Zanonib0665d52013-10-30 19:50:27 -02001109
Imre Deak4e6e1a52014-03-27 17:45:11 +02001110 power_domain = intel_display_port_power_domain(intel_encoder);
1111 intel_display_power_get(dev_priv, power_domain);
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001112
Paulo Zanonib0665d52013-10-30 19:50:27 -02001113 DRM_DEBUG_KMS("Turning eDP VDD on\n");
Keith Packardbd943152011-09-18 23:09:52 -07001114
Daniel Vetter4be73782014-01-17 14:39:48 +01001115 if (!edp_have_panel_power(intel_dp))
1116 wait_panel_power_cycle(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001117
Jesse Barnes453c5422013-03-28 09:55:41 -07001118 pp = ironlake_get_pp_control(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001119 pp |= EDP_FORCE_VDD;
Keith Packardebf33b12011-09-29 15:53:27 -07001120
Jani Nikulabf13e812013-09-06 07:40:05 +03001121 pp_stat_reg = _pp_stat_reg(intel_dp);
1122 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001123
1124 I915_WRITE(pp_ctrl_reg, pp);
1125 POSTING_READ(pp_ctrl_reg);
1126 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1127 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Keith Packardebf33b12011-09-29 15:53:27 -07001128 /*
1129 * If the panel wasn't on, delay before accessing aux channel
1130 */
Daniel Vetter4be73782014-01-17 14:39:48 +01001131 if (!edp_have_panel_power(intel_dp)) {
Keith Packardbd943152011-09-18 23:09:52 -07001132 DRM_DEBUG_KMS("eDP was not running\n");
Keith Packardf01eca22011-09-28 16:48:10 -07001133 msleep(intel_dp->panel_power_up_delay);
Keith Packardf01eca22011-09-28 16:48:10 -07001134 }
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001135
1136 return need_to_disable;
1137}
1138
Daniel Vetterb80d6c72014-03-19 15:54:37 +01001139void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001140{
1141 if (is_edp(intel_dp)) {
1142 bool vdd = _edp_panel_vdd_on(intel_dp);
1143
1144 WARN(!vdd, "eDP VDD already requested on\n");
1145 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001146}
1147
Daniel Vetter4be73782014-01-17 14:39:48 +01001148static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001149{
Paulo Zanoni30add222012-10-26 19:05:45 -02001150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001153 u32 pp_stat_reg, pp_ctrl_reg;
Jesse Barnes5d613502011-01-24 17:10:54 -08001154
Daniel Vettera0e99e62012-12-02 01:05:46 +01001155 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1156
Daniel Vetter4be73782014-01-17 14:39:48 +01001157 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
Imre Deak4e6e1a52014-03-27 17:45:11 +02001158 struct intel_digital_port *intel_dig_port =
1159 dp_to_dig_port(intel_dp);
1160 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1161 enum intel_display_power_domain power_domain;
1162
Paulo Zanonib0665d52013-10-30 19:50:27 -02001163 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1164
Jesse Barnes453c5422013-03-28 09:55:41 -07001165 pp = ironlake_get_pp_control(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001166 pp &= ~EDP_FORCE_VDD;
Jesse Barnes453c5422013-03-28 09:55:41 -07001167
Paulo Zanoni9f08ef52013-10-31 12:44:21 -02001168 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1169 pp_stat_reg = _pp_stat_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001170
1171 I915_WRITE(pp_ctrl_reg, pp);
1172 POSTING_READ(pp_ctrl_reg);
Jesse Barnes5d613502011-01-24 17:10:54 -08001173
Keith Packardbd943152011-09-18 23:09:52 -07001174 /* Make sure sequencer is idle before allowing subsequent activity */
Jesse Barnes453c5422013-03-28 09:55:41 -07001175 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1176 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Paulo Zanoni90791a52013-12-06 17:32:42 -02001177
1178 if ((pp & POWER_TARGET_ON) == 0)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001179 intel_dp->last_power_cycle = jiffies;
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001180
Imre Deak4e6e1a52014-03-27 17:45:11 +02001181 power_domain = intel_display_port_power_domain(intel_encoder);
1182 intel_display_power_put(dev_priv, power_domain);
Keith Packardbd943152011-09-18 23:09:52 -07001183 }
1184}
1185
Daniel Vetter4be73782014-01-17 14:39:48 +01001186static void edp_panel_vdd_work(struct work_struct *__work)
Keith Packardbd943152011-09-18 23:09:52 -07001187{
1188 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1189 struct intel_dp, panel_vdd_work);
Paulo Zanoni30add222012-10-26 19:05:45 -02001190 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001191
Keith Packard627f7672011-10-31 11:30:10 -07001192 mutex_lock(&dev->mode_config.mutex);
Daniel Vetter4be73782014-01-17 14:39:48 +01001193 edp_panel_vdd_off_sync(intel_dp);
Keith Packard627f7672011-10-31 11:30:10 -07001194 mutex_unlock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001195}
1196
Daniel Vetter4be73782014-01-17 14:39:48 +01001197static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
Keith Packardbd943152011-09-18 23:09:52 -07001198{
Keith Packard97af61f572011-09-28 16:23:51 -07001199 if (!is_edp(intel_dp))
1200 return;
Jesse Barnes5d613502011-01-24 17:10:54 -08001201
Keith Packardbd943152011-09-18 23:09:52 -07001202 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
Keith Packardf2e8b182011-11-01 20:01:35 -07001203
Keith Packardbd943152011-09-18 23:09:52 -07001204 intel_dp->want_panel_vdd = false;
1205
1206 if (sync) {
Daniel Vetter4be73782014-01-17 14:39:48 +01001207 edp_panel_vdd_off_sync(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001208 } else {
1209 /*
1210 * Queue the timer to fire a long
1211 * time from now (relative to the power down delay)
1212 * to keep the panel power up across a sequence of operations
1213 */
1214 schedule_delayed_work(&intel_dp->panel_vdd_work,
1215 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1216 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001217}
1218
Daniel Vetter4be73782014-01-17 14:39:48 +01001219void intel_edp_panel_on(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001220{
Paulo Zanoni30add222012-10-26 19:05:45 -02001221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001222 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packard99ea7122011-11-01 19:57:50 -07001223 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001224 u32 pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07001225
Keith Packard97af61f572011-09-28 16:23:51 -07001226 if (!is_edp(intel_dp))
Keith Packardbd943152011-09-18 23:09:52 -07001227 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001228
1229 DRM_DEBUG_KMS("Turn eDP power on\n");
1230
Daniel Vetter4be73782014-01-17 14:39:48 +01001231 if (edp_have_panel_power(intel_dp)) {
Keith Packard99ea7122011-11-01 19:57:50 -07001232 DRM_DEBUG_KMS("eDP power already on\n");
Keith Packard7d639f32011-09-29 16:05:34 -07001233 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001234 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001235
Daniel Vetter4be73782014-01-17 14:39:48 +01001236 wait_panel_power_cycle(intel_dp);
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001237
Jani Nikulabf13e812013-09-06 07:40:05 +03001238 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001239 pp = ironlake_get_pp_control(intel_dp);
Keith Packard05ce1a42011-09-29 16:33:01 -07001240 if (IS_GEN5(dev)) {
1241 /* ILK workaround: disable reset around power sequence */
1242 pp &= ~PANEL_POWER_RESET;
Jani Nikulabf13e812013-09-06 07:40:05 +03001243 I915_WRITE(pp_ctrl_reg, pp);
1244 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07001245 }
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001246
Keith Packard1c0ae802011-09-19 13:59:29 -07001247 pp |= POWER_TARGET_ON;
Keith Packard99ea7122011-11-01 19:57:50 -07001248 if (!IS_GEN5(dev))
1249 pp |= PANEL_POWER_RESET;
1250
Jesse Barnes453c5422013-03-28 09:55:41 -07001251 I915_WRITE(pp_ctrl_reg, pp);
1252 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07001253
Daniel Vetter4be73782014-01-17 14:39:48 +01001254 wait_panel_on(intel_dp);
Paulo Zanonidce56b32013-12-19 14:29:40 -02001255 intel_dp->last_power_on = jiffies;
Jesse Barnes9934c132010-07-22 13:18:19 -07001256
Keith Packard05ce1a42011-09-29 16:33:01 -07001257 if (IS_GEN5(dev)) {
1258 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
Jani Nikulabf13e812013-09-06 07:40:05 +03001259 I915_WRITE(pp_ctrl_reg, pp);
1260 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07001261 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001262}
1263
Daniel Vetter4be73782014-01-17 14:39:48 +01001264void intel_edp_panel_off(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001265{
Imre Deak4e6e1a52014-03-27 17:45:11 +02001266 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1267 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanoni30add222012-10-26 19:05:45 -02001268 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001269 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak4e6e1a52014-03-27 17:45:11 +02001270 enum intel_display_power_domain power_domain;
Keith Packard99ea7122011-11-01 19:57:50 -07001271 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001272 u32 pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07001273
Keith Packard97af61f572011-09-28 16:23:51 -07001274 if (!is_edp(intel_dp))
1275 return;
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001276
Keith Packard99ea7122011-11-01 19:57:50 -07001277 DRM_DEBUG_KMS("Turn eDP power off\n");
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001278
Daniel Vetter4be73782014-01-17 14:39:48 +01001279 edp_wait_backlight_off(intel_dp);
Paulo Zanonidce56b32013-12-19 14:29:40 -02001280
Jani Nikula24f3e092014-03-17 16:43:36 +02001281 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1282
Jesse Barnes453c5422013-03-28 09:55:41 -07001283 pp = ironlake_get_pp_control(intel_dp);
Daniel Vetter35a38552012-08-12 22:17:14 +02001284 /* We need to switch off panel power _and_ force vdd, for otherwise some
1285 * panels get very unhappy and cease to work. */
Patrik Jakobssonb3064152014-03-04 00:42:44 +01001286 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1287 EDP_BLC_ENABLE);
Jesse Barnes453c5422013-03-28 09:55:41 -07001288
Jani Nikulabf13e812013-09-06 07:40:05 +03001289 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001290
Paulo Zanoni849e39f2014-03-07 20:05:20 -03001291 intel_dp->want_panel_vdd = false;
1292
Jesse Barnes453c5422013-03-28 09:55:41 -07001293 I915_WRITE(pp_ctrl_reg, pp);
1294 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07001295
Paulo Zanonidce56b32013-12-19 14:29:40 -02001296 intel_dp->last_power_cycle = jiffies;
Daniel Vetter4be73782014-01-17 14:39:48 +01001297 wait_panel_off(intel_dp);
Paulo Zanoni849e39f2014-03-07 20:05:20 -03001298
1299 /* We got a reference when we enabled the VDD. */
Imre Deak4e6e1a52014-03-27 17:45:11 +02001300 power_domain = intel_display_port_power_domain(intel_encoder);
1301 intel_display_power_put(dev_priv, power_domain);
Jesse Barnes9934c132010-07-22 13:18:19 -07001302}
1303
Daniel Vetter4be73782014-01-17 14:39:48 +01001304void intel_edp_backlight_on(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001305{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1307 struct drm_device *dev = intel_dig_port->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001308 struct drm_i915_private *dev_priv = dev->dev_private;
1309 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001310 u32 pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001311
Keith Packardf01eca22011-09-28 16:48:10 -07001312 if (!is_edp(intel_dp))
1313 return;
1314
Zhao Yakui28c97732009-10-09 11:39:41 +08001315 DRM_DEBUG_KMS("\n");
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001316 /*
1317 * If we enable the backlight right away following a panel power
1318 * on, we may see slight flicker as the panel syncs with the eDP
1319 * link. So delay a bit to make sure the image is solid before
1320 * allowing it to appear.
1321 */
Daniel Vetter4be73782014-01-17 14:39:48 +01001322 wait_backlight_on(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001323 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001324 pp |= EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07001325
Jani Nikulabf13e812013-09-06 07:40:05 +03001326 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001327
1328 I915_WRITE(pp_ctrl_reg, pp);
1329 POSTING_READ(pp_ctrl_reg);
Daniel Vetter035aa3d2012-10-20 20:57:42 +02001330
Jesse Barnes752aa882013-10-31 18:55:49 +02001331 intel_panel_enable_backlight(intel_dp->attached_connector);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001332}
1333
Daniel Vetter4be73782014-01-17 14:39:48 +01001334void intel_edp_backlight_off(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001335{
Paulo Zanoni30add222012-10-26 19:05:45 -02001336 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001339 u32 pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001340
Keith Packardf01eca22011-09-28 16:48:10 -07001341 if (!is_edp(intel_dp))
1342 return;
1343
Jesse Barnes752aa882013-10-31 18:55:49 +02001344 intel_panel_disable_backlight(intel_dp->attached_connector);
Daniel Vetter035aa3d2012-10-20 20:57:42 +02001345
Zhao Yakui28c97732009-10-09 11:39:41 +08001346 DRM_DEBUG_KMS("\n");
Jesse Barnes453c5422013-03-28 09:55:41 -07001347 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001348 pp &= ~EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07001349
Jani Nikulabf13e812013-09-06 07:40:05 +03001350 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001351
1352 I915_WRITE(pp_ctrl_reg, pp);
1353 POSTING_READ(pp_ctrl_reg);
Paulo Zanonidce56b32013-12-19 14:29:40 -02001354 intel_dp->last_backlight_off = jiffies;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001355}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001356
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001357static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07001358{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001359 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1360 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1361 struct drm_device *dev = crtc->dev;
Jesse Barnesd240f202010-08-13 15:43:26 -07001362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 u32 dpa_ctl;
1364
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001365 assert_pipe_disabled(dev_priv,
1366 to_intel_crtc(crtc)->pipe);
1367
Jesse Barnesd240f202010-08-13 15:43:26 -07001368 DRM_DEBUG_KMS("\n");
1369 dpa_ctl = I915_READ(DP_A);
Daniel Vetter07679352012-09-06 22:15:42 +02001370 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1371 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1372
1373 /* We don't adjust intel_dp->DP while tearing down the link, to
1374 * facilitate link retraining (e.g. after hotplug). Hence clear all
1375 * enable bits here to ensure that we don't enable too much. */
1376 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1377 intel_dp->DP |= DP_PLL_ENABLE;
1378 I915_WRITE(DP_A, intel_dp->DP);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001379 POSTING_READ(DP_A);
1380 udelay(200);
Jesse Barnesd240f202010-08-13 15:43:26 -07001381}
1382
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001383static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07001384{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1386 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1387 struct drm_device *dev = crtc->dev;
Jesse Barnesd240f202010-08-13 15:43:26 -07001388 struct drm_i915_private *dev_priv = dev->dev_private;
1389 u32 dpa_ctl;
1390
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001391 assert_pipe_disabled(dev_priv,
1392 to_intel_crtc(crtc)->pipe);
1393
Jesse Barnesd240f202010-08-13 15:43:26 -07001394 dpa_ctl = I915_READ(DP_A);
Daniel Vetter07679352012-09-06 22:15:42 +02001395 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1396 "dp pll off, should be on\n");
1397 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1398
1399 /* We can't rely on the value tracked for the DP register in
1400 * intel_dp->DP because link_down must not change that (otherwise link
1401 * re-training will fail. */
Jesse Barnes298b0b32010-10-07 16:01:24 -07001402 dpa_ctl &= ~DP_PLL_ENABLE;
Jesse Barnesd240f202010-08-13 15:43:26 -07001403 I915_WRITE(DP_A, dpa_ctl);
Chris Wilson1af5fa12010-09-08 21:07:28 +01001404 POSTING_READ(DP_A);
Jesse Barnesd240f202010-08-13 15:43:26 -07001405 udelay(200);
1406}
1407
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001408/* If the sink supports it, try to set the power state appropriately */
Paulo Zanonic19b0662012-10-15 15:51:41 -03001409void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001410{
1411 int ret, i;
1412
1413 /* Should have a valid DPCD by this point */
1414 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1415 return;
1416
1417 if (mode != DRM_MODE_DPMS_ON) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02001418 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1419 DP_SET_POWER_D3);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001420 if (ret != 1)
1421 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1422 } else {
1423 /*
1424 * When turning on, we need to retry for 1ms to give the sink
1425 * time to wake up.
1426 */
1427 for (i = 0; i < 3; i++) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02001428 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1429 DP_SET_POWER_D0);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001430 if (ret == 1)
1431 break;
1432 msleep(1);
1433 }
1434 }
1435}
1436
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001437static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1438 enum pipe *pipe)
Jesse Barnesd240f202010-08-13 15:43:26 -07001439{
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001440 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001441 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001442 struct drm_device *dev = encoder->base.dev;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak6d129be2014-03-05 16:20:54 +02001444 enum intel_display_power_domain power_domain;
1445 u32 tmp;
1446
1447 power_domain = intel_display_port_power_domain(encoder);
1448 if (!intel_display_power_enabled(dev_priv, power_domain))
1449 return false;
1450
1451 tmp = I915_READ(intel_dp->output_reg);
Jesse Barnesd240f202010-08-13 15:43:26 -07001452
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001453 if (!(tmp & DP_PORT_EN))
1454 return false;
1455
Imre Deakbc7d38a2013-05-16 14:40:36 +03001456 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001457 *pipe = PORT_TO_PIPE_CPT(tmp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001458 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001459 *pipe = PORT_TO_PIPE(tmp);
1460 } else {
1461 u32 trans_sel;
1462 u32 trans_dp;
1463 int i;
1464
1465 switch (intel_dp->output_reg) {
1466 case PCH_DP_B:
1467 trans_sel = TRANS_DP_PORT_SEL_B;
1468 break;
1469 case PCH_DP_C:
1470 trans_sel = TRANS_DP_PORT_SEL_C;
1471 break;
1472 case PCH_DP_D:
1473 trans_sel = TRANS_DP_PORT_SEL_D;
1474 break;
1475 default:
1476 return true;
1477 }
1478
1479 for_each_pipe(i) {
1480 trans_dp = I915_READ(TRANS_DP_CTL(i));
1481 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1482 *pipe = i;
1483 return true;
1484 }
1485 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001486
Daniel Vetter4a0833e2012-10-26 10:58:11 +02001487 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1488 intel_dp->output_reg);
1489 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001490
1491 return true;
1492}
1493
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001494static void intel_dp_get_config(struct intel_encoder *encoder,
1495 struct intel_crtc_config *pipe_config)
1496{
1497 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001498 u32 tmp, flags = 0;
Xiong Zhang63000ef2013-06-28 12:59:06 +08001499 struct drm_device *dev = encoder->base.dev;
1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 enum port port = dp_to_dig_port(intel_dp)->port;
1502 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Ville Syrjälä18442d02013-09-13 16:00:08 +03001503 int dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001504
Xiong Zhang63000ef2013-06-28 12:59:06 +08001505 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1506 tmp = I915_READ(intel_dp->output_reg);
1507 if (tmp & DP_SYNC_HS_HIGH)
1508 flags |= DRM_MODE_FLAG_PHSYNC;
1509 else
1510 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001511
Xiong Zhang63000ef2013-06-28 12:59:06 +08001512 if (tmp & DP_SYNC_VS_HIGH)
1513 flags |= DRM_MODE_FLAG_PVSYNC;
1514 else
1515 flags |= DRM_MODE_FLAG_NVSYNC;
1516 } else {
1517 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1518 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1519 flags |= DRM_MODE_FLAG_PHSYNC;
1520 else
1521 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001522
Xiong Zhang63000ef2013-06-28 12:59:06 +08001523 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1524 flags |= DRM_MODE_FLAG_PVSYNC;
1525 else
1526 flags |= DRM_MODE_FLAG_NVSYNC;
1527 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001528
1529 pipe_config->adjusted_mode.flags |= flags;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03001530
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03001531 pipe_config->has_dp_encoder = true;
1532
1533 intel_dp_get_m_n(crtc, pipe_config);
1534
Ville Syrjälä18442d02013-09-13 16:00:08 +03001535 if (port == PORT_A) {
Jesse Barnesf1f644d2013-06-27 00:39:25 +03001536 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1537 pipe_config->port_clock = 162000;
1538 else
1539 pipe_config->port_clock = 270000;
1540 }
Ville Syrjälä18442d02013-09-13 16:00:08 +03001541
1542 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1543 &pipe_config->dp_m_n);
1544
1545 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1546 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1547
Damien Lespiau241bfc32013-09-25 16:45:37 +01001548 pipe_config->adjusted_mode.crtc_clock = dotclock;
Daniel Vetter7f16e5c2013-11-04 16:28:47 +01001549
Jani Nikulac6cd2ee2013-10-21 10:52:07 +03001550 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1551 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1552 /*
1553 * This is a big fat ugly hack.
1554 *
1555 * Some machines in UEFI boot mode provide us a VBT that has 18
1556 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1557 * unknown we fail to light up. Yet the same BIOS boots up with
1558 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1559 * max, not what it tells us to use.
1560 *
1561 * Note: This will still be broken if the eDP panel is not lit
1562 * up by the BIOS, and thus we can't get the mode at module
1563 * load.
1564 */
1565 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1566 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1567 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1568 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001569}
1570
Rodrigo Vivia031d702013-10-03 16:15:06 -03001571static bool is_edp_psr(struct drm_device *dev)
Shobhit Kumar2293bb52013-07-11 18:44:56 -03001572{
Rodrigo Vivia031d702013-10-03 16:15:06 -03001573 struct drm_i915_private *dev_priv = dev->dev_private;
1574
1575 return dev_priv->psr.sink_support;
Shobhit Kumar2293bb52013-07-11 18:44:56 -03001576}
1577
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001578static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1579{
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581
Ben Widawsky18b59922013-09-20 09:35:30 -07001582 if (!HAS_PSR(dev))
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001583 return false;
1584
Ben Widawsky18b59922013-09-20 09:35:30 -07001585 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001586}
1587
1588static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1589 struct edp_vsc_psr *vsc_psr)
1590{
1591 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1592 struct drm_device *dev = dig_port->base.base.dev;
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1594 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1595 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1596 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1597 uint32_t *data = (uint32_t *) vsc_psr;
1598 unsigned int i;
1599
1600 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1601 the video DIP being updated before program video DIP data buffer
1602 registers for DIP being updated. */
1603 I915_WRITE(ctl_reg, 0);
1604 POSTING_READ(ctl_reg);
1605
1606 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1607 if (i < sizeof(struct edp_vsc_psr))
1608 I915_WRITE(data_reg + i, *data++);
1609 else
1610 I915_WRITE(data_reg + i, 0);
1611 }
1612
1613 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1614 POSTING_READ(ctl_reg);
1615}
1616
1617static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1618{
1619 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 struct edp_vsc_psr psr_vsc;
1622
1623 if (intel_dp->psr_setup_done)
1624 return;
1625
1626 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1627 memset(&psr_vsc, 0, sizeof(psr_vsc));
1628 psr_vsc.sdp_header.HB0 = 0;
1629 psr_vsc.sdp_header.HB1 = 0x7;
1630 psr_vsc.sdp_header.HB2 = 0x2;
1631 psr_vsc.sdp_header.HB3 = 0x8;
1632 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1633
1634 /* Avoid continuous PSR exit by masking memup and hpd */
Ben Widawsky18b59922013-09-20 09:35:30 -07001635 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
Rodrigo Vivi0cc4b692013-10-03 13:31:26 -03001636 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001637
1638 intel_dp->psr_setup_done = true;
1639}
1640
1641static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1642{
1643 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1644 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiauec5b01d2014-01-21 13:35:39 +00001645 uint32_t aux_clock_divider;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001646 int precharge = 0x3;
1647 int msg_size = 5; /* Header(4) + Message(1) */
1648
Damien Lespiauec5b01d2014-01-21 13:35:39 +00001649 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1650
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001651 /* Enable PSR in sink */
1652 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
Jani Nikula9d1a1032014-03-14 16:51:15 +02001653 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1654 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001655 else
Jani Nikula9d1a1032014-03-14 16:51:15 +02001656 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1657 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001658
1659 /* Setup AUX registers */
Ben Widawsky18b59922013-09-20 09:35:30 -07001660 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1661 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1662 I915_WRITE(EDP_PSR_AUX_CTL(dev),
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001663 DP_AUX_CH_CTL_TIME_OUT_400us |
1664 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1665 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1666 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1667}
1668
1669static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1670{
1671 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 uint32_t max_sleep_time = 0x1f;
1674 uint32_t idle_frames = 1;
1675 uint32_t val = 0x0;
Ben Widawskyed8546a2013-11-04 22:45:05 -08001676 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001677
1678 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1679 val |= EDP_PSR_LINK_STANDBY;
1680 val |= EDP_PSR_TP2_TP3_TIME_0us;
1681 val |= EDP_PSR_TP1_TIME_0us;
1682 val |= EDP_PSR_SKIP_AUX_EXIT;
1683 } else
1684 val |= EDP_PSR_LINK_DISABLE;
1685
Ben Widawsky18b59922013-09-20 09:35:30 -07001686 I915_WRITE(EDP_PSR_CTL(dev), val |
Ben Widawsky24bd9bf2014-03-04 22:38:10 -08001687 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001688 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1689 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1690 EDP_PSR_ENABLE);
1691}
1692
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001693static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1694{
1695 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1696 struct drm_device *dev = dig_port->base.base.dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 struct drm_crtc *crtc = dig_port->base.base.crtc;
1699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roperf4510a22014-04-01 15:22:40 -07001700 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001701 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1702
Rodrigo Vivia031d702013-10-03 16:15:06 -03001703 dev_priv->psr.source_ok = false;
1704
Ben Widawsky18b59922013-09-20 09:35:30 -07001705 if (!HAS_PSR(dev)) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001706 DRM_DEBUG_KMS("PSR not supported on this platform\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001707 return false;
1708 }
1709
1710 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1711 (dig_port->port != PORT_A)) {
1712 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001713 return false;
1714 }
1715
Jani Nikulad330a952014-01-21 11:24:25 +02001716 if (!i915.enable_psr) {
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001717 DRM_DEBUG_KMS("PSR disable by flag\n");
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001718 return false;
1719 }
1720
Chris Wilsoncd234b02013-08-02 20:39:49 +01001721 crtc = dig_port->base.base.crtc;
1722 if (crtc == NULL) {
1723 DRM_DEBUG_KMS("crtc not active for PSR\n");
Chris Wilsoncd234b02013-08-02 20:39:49 +01001724 return false;
1725 }
1726
1727 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001728 if (!intel_crtc_active(crtc)) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001729 DRM_DEBUG_KMS("crtc not active for PSR\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001730 return false;
1731 }
1732
Matt Roperf4510a22014-04-01 15:22:40 -07001733 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001734 if (obj->tiling_mode != I915_TILING_X ||
1735 obj->fence_reg == I915_FENCE_REG_NONE) {
1736 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001737 return false;
1738 }
1739
1740 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1741 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001742 return false;
1743 }
1744
1745 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1746 S3D_ENABLE) {
1747 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001748 return false;
1749 }
1750
Ville Syrjäläca73b4f2013-09-04 18:25:24 +03001751 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001752 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001753 return false;
1754 }
1755
Rodrigo Vivia031d702013-10-03 16:15:06 -03001756 dev_priv->psr.source_ok = true;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001757 return true;
1758}
1759
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001760static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001761{
1762 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1763
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001764 if (!intel_edp_psr_match_conditions(intel_dp) ||
1765 intel_edp_is_psr_enabled(dev))
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001766 return;
1767
1768 /* Setup PSR once */
1769 intel_edp_psr_setup(intel_dp);
1770
1771 /* Enable PSR on the panel */
1772 intel_edp_psr_enable_sink(intel_dp);
1773
1774 /* Enable PSR on the host */
1775 intel_edp_psr_enable_source(intel_dp);
1776}
1777
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001778void intel_edp_psr_enable(struct intel_dp *intel_dp)
1779{
1780 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1781
1782 if (intel_edp_psr_match_conditions(intel_dp) &&
1783 !intel_edp_is_psr_enabled(dev))
1784 intel_edp_psr_do_enable(intel_dp);
1785}
1786
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001787void intel_edp_psr_disable(struct intel_dp *intel_dp)
1788{
1789 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791
1792 if (!intel_edp_is_psr_enabled(dev))
1793 return;
1794
Ben Widawsky18b59922013-09-20 09:35:30 -07001795 I915_WRITE(EDP_PSR_CTL(dev),
1796 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001797
1798 /* Wait till PSR is idle */
Ben Widawsky18b59922013-09-20 09:35:30 -07001799 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001800 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1801 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1802}
1803
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001804void intel_edp_psr_update(struct drm_device *dev)
1805{
1806 struct intel_encoder *encoder;
1807 struct intel_dp *intel_dp = NULL;
1808
1809 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1810 if (encoder->type == INTEL_OUTPUT_EDP) {
1811 intel_dp = enc_to_intel_dp(&encoder->base);
1812
Rodrigo Vivia031d702013-10-03 16:15:06 -03001813 if (!is_edp_psr(dev))
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001814 return;
1815
1816 if (!intel_edp_psr_match_conditions(intel_dp))
1817 intel_edp_psr_disable(intel_dp);
1818 else
1819 if (!intel_edp_is_psr_enabled(dev))
1820 intel_edp_psr_do_enable(intel_dp);
1821 }
1822}
1823
Daniel Vettere8cb4552012-07-01 13:05:48 +02001824static void intel_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001825{
Daniel Vettere8cb4552012-07-01 13:05:48 +02001826 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03001827 enum port port = dp_to_dig_port(intel_dp)->port;
1828 struct drm_device *dev = encoder->base.dev;
Daniel Vetter6cb49832012-05-20 17:14:50 +02001829
1830 /* Make sure the panel is off before trying to change the mode. But also
1831 * ensure that we have vdd while we switch off the panel. */
Jani Nikula24f3e092014-03-17 16:43:36 +02001832 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001833 intel_edp_backlight_off(intel_dp);
Jani Nikulafdbc3b12013-11-12 17:10:13 +02001834 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
Daniel Vetter4be73782014-01-17 14:39:48 +01001835 intel_edp_panel_off(intel_dp);
Daniel Vetter37398502012-09-06 22:15:44 +02001836
1837 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
Imre Deak982a3862013-05-23 19:39:40 +03001838 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
Daniel Vetter37398502012-09-06 22:15:44 +02001839 intel_dp_link_down(intel_dp);
Jesse Barnesd240f202010-08-13 15:43:26 -07001840}
1841
Ville Syrjälä49277c32014-03-31 18:21:26 +03001842static void g4x_post_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001843{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001844 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03001845 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001846
Ville Syrjälä49277c32014-03-31 18:21:26 +03001847 if (port != PORT_A)
1848 return;
1849
1850 intel_dp_link_down(intel_dp);
1851 ironlake_edp_pll_off(intel_dp);
1852}
1853
1854static void vlv_post_disable_dp(struct intel_encoder *encoder)
1855{
1856 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1857
1858 intel_dp_link_down(intel_dp);
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001859}
1860
Daniel Vettere8cb4552012-07-01 13:05:48 +02001861static void intel_enable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001862{
Daniel Vettere8cb4552012-07-01 13:05:48 +02001863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864 struct drm_device *dev = encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001865 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001866 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001867
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02001868 if (WARN_ON(dp_reg & DP_PORT_EN))
1869 return;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001870
Jani Nikula24f3e092014-03-17 16:43:36 +02001871 intel_edp_panel_vdd_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001872 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1873 intel_dp_start_link_train(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001874 intel_edp_panel_on(intel_dp);
1875 edp_panel_vdd_off(intel_dp, true);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001876 intel_dp_complete_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03001877 intel_dp_stop_link_train(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001878}
Jesse Barnes89b667f2013-04-18 14:51:36 -07001879
Jani Nikulaecff4f32013-09-06 07:38:29 +03001880static void g4x_enable_dp(struct intel_encoder *encoder)
1881{
Jani Nikula828f5c62013-09-05 16:44:45 +03001882 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1883
Jani Nikulaecff4f32013-09-06 07:38:29 +03001884 intel_enable_dp(encoder);
Daniel Vetter4be73782014-01-17 14:39:48 +01001885 intel_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001886}
Jesse Barnes89b667f2013-04-18 14:51:36 -07001887
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001888static void vlv_enable_dp(struct intel_encoder *encoder)
1889{
Jani Nikula828f5c62013-09-05 16:44:45 +03001890 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1891
Daniel Vetter4be73782014-01-17 14:39:48 +01001892 intel_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001893}
1894
Jani Nikulaecff4f32013-09-06 07:38:29 +03001895static void g4x_pre_enable_dp(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001896{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001897 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001898 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001899
1900 if (dport->port == PORT_A)
1901 ironlake_edp_pll_on(intel_dp);
1902}
1903
1904static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1905{
1906 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1907 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jesse Barnesb2634012013-03-28 09:55:40 -07001908 struct drm_device *dev = encoder->base.dev;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001909 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001910 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001911 enum dpio_channel port = vlv_dport_to_channel(dport);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001912 int pipe = intel_crtc->pipe;
Jani Nikulabf13e812013-09-06 07:40:05 +03001913 struct edp_power_seq power_seq;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001914 u32 val;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001915
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001916 mutex_lock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001917
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001918 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001919 val = 0;
1920 if (pipe)
1921 val |= (1<<21);
1922 else
1923 val &= ~(1<<21);
1924 val |= 0x001000c4;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001925 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1926 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1927 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001928
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001929 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001930
Imre Deak2cac6132014-01-30 16:50:42 +02001931 if (is_edp(intel_dp)) {
1932 /* init power sequencer on this pipe and port */
1933 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1934 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1935 &power_seq);
1936 }
Jani Nikulabf13e812013-09-06 07:40:05 +03001937
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001938 intel_enable_dp(encoder);
1939
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001940 vlv_wait_port_ready(dev_priv, dport);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001941}
1942
Jani Nikulaecff4f32013-09-06 07:38:29 +03001943static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001944{
1945 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1946 struct drm_device *dev = encoder->base.dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001948 struct intel_crtc *intel_crtc =
1949 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001950 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001951 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001952
Jesse Barnes89b667f2013-04-18 14:51:36 -07001953 /* Program Tx lane resets to default */
Chris Wilson0980a602013-07-26 19:57:35 +01001954 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001955 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001956 DPIO_PCS_TX_LANE2_RESET |
1957 DPIO_PCS_TX_LANE1_RESET);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001958 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001959 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1960 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1961 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1962 DPIO_PCS_CLK_SOFT_RESET);
1963
1964 /* Fix up inter-pair skew failure */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001965 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1966 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1967 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
Chris Wilson0980a602013-07-26 19:57:35 +01001968 mutex_unlock(&dev_priv->dpio_lock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001969}
1970
1971/*
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001972 * Native read with retry for link status and receiver capability reads for
1973 * cases where the sink may still be asleep.
Jani Nikula9d1a1032014-03-14 16:51:15 +02001974 *
1975 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1976 * supposed to retry 3 times per the spec.
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001977 */
Jani Nikula9d1a1032014-03-14 16:51:15 +02001978static ssize_t
1979intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1980 void *buffer, size_t size)
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001981{
Jani Nikula9d1a1032014-03-14 16:51:15 +02001982 ssize_t ret;
1983 int i;
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001984
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001985 for (i = 0; i < 3; i++) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02001986 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1987 if (ret == size)
1988 return ret;
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001989 msleep(1);
1990 }
1991
Jani Nikula9d1a1032014-03-14 16:51:15 +02001992 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001993}
1994
1995/*
1996 * Fetch AUX CH registers 0x202 - 0x207 which contain
1997 * link status information
1998 */
1999static bool
Keith Packard93f62da2011-11-01 19:45:03 -07002000intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002001{
Jani Nikula9d1a1032014-03-14 16:51:15 +02002002 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2003 DP_LANE0_1_STATUS,
2004 link_status,
2005 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002006}
2007
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002008/*
2009 * These are source-specific values; current Intel hardware supports
2010 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2011 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002012
2013static uint8_t
Keith Packard1a2eb462011-11-16 16:26:07 -08002014intel_dp_voltage_max(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002015{
Paulo Zanoni30add222012-10-26 19:05:45 -02002016 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002017 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08002018
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07002019 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002020 return DP_TRAIN_VOLTAGE_SWING_1200;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002021 else if (IS_GEN7(dev) && port == PORT_A)
Keith Packard1a2eb462011-11-16 16:26:07 -08002022 return DP_TRAIN_VOLTAGE_SWING_800;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002023 else if (HAS_PCH_CPT(dev) && port != PORT_A)
Keith Packard1a2eb462011-11-16 16:26:07 -08002024 return DP_TRAIN_VOLTAGE_SWING_1200;
2025 else
2026 return DP_TRAIN_VOLTAGE_SWING_800;
2027}
2028
2029static uint8_t
2030intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2031{
Paulo Zanoni30add222012-10-26 19:05:45 -02002032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002033 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08002034
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07002035 if (IS_BROADWELL(dev)) {
2036 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2037 case DP_TRAIN_VOLTAGE_SWING_400:
2038 case DP_TRAIN_VOLTAGE_SWING_600:
2039 return DP_TRAIN_PRE_EMPHASIS_6;
2040 case DP_TRAIN_VOLTAGE_SWING_800:
2041 return DP_TRAIN_PRE_EMPHASIS_3_5;
2042 case DP_TRAIN_VOLTAGE_SWING_1200:
2043 default:
2044 return DP_TRAIN_PRE_EMPHASIS_0;
2045 }
2046 } else if (IS_HASWELL(dev)) {
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002047 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2048 case DP_TRAIN_VOLTAGE_SWING_400:
2049 return DP_TRAIN_PRE_EMPHASIS_9_5;
2050 case DP_TRAIN_VOLTAGE_SWING_600:
2051 return DP_TRAIN_PRE_EMPHASIS_6;
2052 case DP_TRAIN_VOLTAGE_SWING_800:
2053 return DP_TRAIN_PRE_EMPHASIS_3_5;
2054 case DP_TRAIN_VOLTAGE_SWING_1200:
2055 default:
2056 return DP_TRAIN_PRE_EMPHASIS_0;
2057 }
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002058 } else if (IS_VALLEYVIEW(dev)) {
2059 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2060 case DP_TRAIN_VOLTAGE_SWING_400:
2061 return DP_TRAIN_PRE_EMPHASIS_9_5;
2062 case DP_TRAIN_VOLTAGE_SWING_600:
2063 return DP_TRAIN_PRE_EMPHASIS_6;
2064 case DP_TRAIN_VOLTAGE_SWING_800:
2065 return DP_TRAIN_PRE_EMPHASIS_3_5;
2066 case DP_TRAIN_VOLTAGE_SWING_1200:
2067 default:
2068 return DP_TRAIN_PRE_EMPHASIS_0;
2069 }
Imre Deakbc7d38a2013-05-16 14:40:36 +03002070 } else if (IS_GEN7(dev) && port == PORT_A) {
Keith Packard1a2eb462011-11-16 16:26:07 -08002071 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2072 case DP_TRAIN_VOLTAGE_SWING_400:
2073 return DP_TRAIN_PRE_EMPHASIS_6;
2074 case DP_TRAIN_VOLTAGE_SWING_600:
2075 case DP_TRAIN_VOLTAGE_SWING_800:
2076 return DP_TRAIN_PRE_EMPHASIS_3_5;
2077 default:
2078 return DP_TRAIN_PRE_EMPHASIS_0;
2079 }
2080 } else {
2081 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2082 case DP_TRAIN_VOLTAGE_SWING_400:
2083 return DP_TRAIN_PRE_EMPHASIS_6;
2084 case DP_TRAIN_VOLTAGE_SWING_600:
2085 return DP_TRAIN_PRE_EMPHASIS_6;
2086 case DP_TRAIN_VOLTAGE_SWING_800:
2087 return DP_TRAIN_PRE_EMPHASIS_3_5;
2088 case DP_TRAIN_VOLTAGE_SWING_1200:
2089 default:
2090 return DP_TRAIN_PRE_EMPHASIS_0;
2091 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002092 }
2093}
2094
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002095static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2096{
2097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002100 struct intel_crtc *intel_crtc =
2101 to_intel_crtc(dport->base.base.crtc);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002102 unsigned long demph_reg_value, preemph_reg_value,
2103 uniqtranscale_reg_value;
2104 uint8_t train_set = intel_dp->train_set[0];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002105 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002106 int pipe = intel_crtc->pipe;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002107
2108 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2109 case DP_TRAIN_PRE_EMPHASIS_0:
2110 preemph_reg_value = 0x0004000;
2111 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2112 case DP_TRAIN_VOLTAGE_SWING_400:
2113 demph_reg_value = 0x2B405555;
2114 uniqtranscale_reg_value = 0x552AB83A;
2115 break;
2116 case DP_TRAIN_VOLTAGE_SWING_600:
2117 demph_reg_value = 0x2B404040;
2118 uniqtranscale_reg_value = 0x5548B83A;
2119 break;
2120 case DP_TRAIN_VOLTAGE_SWING_800:
2121 demph_reg_value = 0x2B245555;
2122 uniqtranscale_reg_value = 0x5560B83A;
2123 break;
2124 case DP_TRAIN_VOLTAGE_SWING_1200:
2125 demph_reg_value = 0x2B405555;
2126 uniqtranscale_reg_value = 0x5598DA3A;
2127 break;
2128 default:
2129 return 0;
2130 }
2131 break;
2132 case DP_TRAIN_PRE_EMPHASIS_3_5:
2133 preemph_reg_value = 0x0002000;
2134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2135 case DP_TRAIN_VOLTAGE_SWING_400:
2136 demph_reg_value = 0x2B404040;
2137 uniqtranscale_reg_value = 0x5552B83A;
2138 break;
2139 case DP_TRAIN_VOLTAGE_SWING_600:
2140 demph_reg_value = 0x2B404848;
2141 uniqtranscale_reg_value = 0x5580B83A;
2142 break;
2143 case DP_TRAIN_VOLTAGE_SWING_800:
2144 demph_reg_value = 0x2B404040;
2145 uniqtranscale_reg_value = 0x55ADDA3A;
2146 break;
2147 default:
2148 return 0;
2149 }
2150 break;
2151 case DP_TRAIN_PRE_EMPHASIS_6:
2152 preemph_reg_value = 0x0000000;
2153 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2154 case DP_TRAIN_VOLTAGE_SWING_400:
2155 demph_reg_value = 0x2B305555;
2156 uniqtranscale_reg_value = 0x5570B83A;
2157 break;
2158 case DP_TRAIN_VOLTAGE_SWING_600:
2159 demph_reg_value = 0x2B2B4040;
2160 uniqtranscale_reg_value = 0x55ADDA3A;
2161 break;
2162 default:
2163 return 0;
2164 }
2165 break;
2166 case DP_TRAIN_PRE_EMPHASIS_9_5:
2167 preemph_reg_value = 0x0006000;
2168 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2169 case DP_TRAIN_VOLTAGE_SWING_400:
2170 demph_reg_value = 0x1B405555;
2171 uniqtranscale_reg_value = 0x55ADDA3A;
2172 break;
2173 default:
2174 return 0;
2175 }
2176 break;
2177 default:
2178 return 0;
2179 }
2180
Chris Wilson0980a602013-07-26 19:57:35 +01002181 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002182 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2183 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2184 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002185 uniqtranscale_reg_value);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002186 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2187 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2188 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2189 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
Chris Wilson0980a602013-07-26 19:57:35 +01002190 mutex_unlock(&dev_priv->dpio_lock);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002191
2192 return 0;
2193}
2194
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002195static void
Jani Nikula0301b3a2013-10-15 09:36:08 +03002196intel_get_adjust_train(struct intel_dp *intel_dp,
2197 const uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002198{
2199 uint8_t v = 0;
2200 uint8_t p = 0;
2201 int lane;
Keith Packard1a2eb462011-11-16 16:26:07 -08002202 uint8_t voltage_max;
2203 uint8_t preemph_max;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002204
Jesse Barnes33a34e42010-09-08 12:42:02 -07002205 for (lane = 0; lane < intel_dp->lane_count; lane++) {
Daniel Vetter0f037bd2012-10-18 10:15:27 +02002206 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2207 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002208
2209 if (this_v > v)
2210 v = this_v;
2211 if (this_p > p)
2212 p = this_p;
2213 }
2214
Keith Packard1a2eb462011-11-16 16:26:07 -08002215 voltage_max = intel_dp_voltage_max(intel_dp);
Keith Packard417e8222011-11-01 19:54:11 -07002216 if (v >= voltage_max)
2217 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002218
Keith Packard1a2eb462011-11-16 16:26:07 -08002219 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2220 if (p >= preemph_max)
2221 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002222
2223 for (lane = 0; lane < 4; lane++)
Jesse Barnes33a34e42010-09-08 12:42:02 -07002224 intel_dp->train_set[lane] = v | p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002225}
2226
2227static uint32_t
Paulo Zanonif0a34242012-12-06 16:51:50 -02002228intel_gen4_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002229{
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002230 uint32_t signal_levels = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002231
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002232 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002233 case DP_TRAIN_VOLTAGE_SWING_400:
2234 default:
2235 signal_levels |= DP_VOLTAGE_0_4;
2236 break;
2237 case DP_TRAIN_VOLTAGE_SWING_600:
2238 signal_levels |= DP_VOLTAGE_0_6;
2239 break;
2240 case DP_TRAIN_VOLTAGE_SWING_800:
2241 signal_levels |= DP_VOLTAGE_0_8;
2242 break;
2243 case DP_TRAIN_VOLTAGE_SWING_1200:
2244 signal_levels |= DP_VOLTAGE_1_2;
2245 break;
2246 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002247 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002248 case DP_TRAIN_PRE_EMPHASIS_0:
2249 default:
2250 signal_levels |= DP_PRE_EMPHASIS_0;
2251 break;
2252 case DP_TRAIN_PRE_EMPHASIS_3_5:
2253 signal_levels |= DP_PRE_EMPHASIS_3_5;
2254 break;
2255 case DP_TRAIN_PRE_EMPHASIS_6:
2256 signal_levels |= DP_PRE_EMPHASIS_6;
2257 break;
2258 case DP_TRAIN_PRE_EMPHASIS_9_5:
2259 signal_levels |= DP_PRE_EMPHASIS_9_5;
2260 break;
2261 }
2262 return signal_levels;
2263}
2264
Zhenyu Wange3421a12010-04-08 09:43:27 +08002265/* Gen6's DP voltage swing and pre-emphasis control */
2266static uint32_t
2267intel_gen6_edp_signal_levels(uint8_t train_set)
2268{
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002269 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2270 DP_TRAIN_PRE_EMPHASIS_MASK);
2271 switch (signal_levels) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08002272 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002273 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2274 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2275 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2276 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002277 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002278 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2279 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002280 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002281 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2282 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002283 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002284 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2285 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002286 default:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002287 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2288 "0x%x\n", signal_levels);
2289 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002290 }
2291}
2292
Keith Packard1a2eb462011-11-16 16:26:07 -08002293/* Gen7's DP voltage swing and pre-emphasis control */
2294static uint32_t
2295intel_gen7_edp_signal_levels(uint8_t train_set)
2296{
2297 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2298 DP_TRAIN_PRE_EMPHASIS_MASK);
2299 switch (signal_levels) {
2300 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2301 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2302 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2303 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2305 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2306
2307 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2308 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2309 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2310 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2311
2312 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2313 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2314 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2315 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2316
2317 default:
2318 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2319 "0x%x\n", signal_levels);
2320 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2321 }
2322}
2323
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002324/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2325static uint32_t
Paulo Zanonif0a34242012-12-06 16:51:50 -02002326intel_hsw_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002327{
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002328 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2329 DP_TRAIN_PRE_EMPHASIS_MASK);
2330 switch (signal_levels) {
2331 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2332 return DDI_BUF_EMP_400MV_0DB_HSW;
2333 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2334 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2335 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2336 return DDI_BUF_EMP_400MV_6DB_HSW;
2337 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2338 return DDI_BUF_EMP_400MV_9_5DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002339
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002340 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2341 return DDI_BUF_EMP_600MV_0DB_HSW;
2342 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2343 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2344 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2345 return DDI_BUF_EMP_600MV_6DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002346
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002347 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2348 return DDI_BUF_EMP_800MV_0DB_HSW;
2349 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2350 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2351 default:
2352 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2353 "0x%x\n", signal_levels);
2354 return DDI_BUF_EMP_400MV_0DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002355 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002356}
2357
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07002358static uint32_t
2359intel_bdw_signal_levels(uint8_t train_set)
2360{
2361 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2362 DP_TRAIN_PRE_EMPHASIS_MASK);
2363 switch (signal_levels) {
2364 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2365 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2366 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2367 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2368 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2369 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2370
2371 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2372 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2373 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2374 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2375 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2376 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2377
2378 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2379 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2380 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2381 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2382
2383 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2384 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2385
2386 default:
2387 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2388 "0x%x\n", signal_levels);
2389 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2390 }
2391}
2392
Paulo Zanonif0a34242012-12-06 16:51:50 -02002393/* Properly updates "DP" with the correct signal levels. */
2394static void
2395intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2396{
2397 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002398 enum port port = intel_dig_port->port;
Paulo Zanonif0a34242012-12-06 16:51:50 -02002399 struct drm_device *dev = intel_dig_port->base.base.dev;
2400 uint32_t signal_levels, mask;
2401 uint8_t train_set = intel_dp->train_set[0];
2402
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07002403 if (IS_BROADWELL(dev)) {
2404 signal_levels = intel_bdw_signal_levels(train_set);
2405 mask = DDI_BUF_EMP_MASK;
2406 } else if (IS_HASWELL(dev)) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002407 signal_levels = intel_hsw_signal_levels(train_set);
2408 mask = DDI_BUF_EMP_MASK;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002409 } else if (IS_VALLEYVIEW(dev)) {
2410 signal_levels = intel_vlv_signal_levels(intel_dp);
2411 mask = 0;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002412 } else if (IS_GEN7(dev) && port == PORT_A) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002413 signal_levels = intel_gen7_edp_signal_levels(train_set);
2414 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002415 } else if (IS_GEN6(dev) && port == PORT_A) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002416 signal_levels = intel_gen6_edp_signal_levels(train_set);
2417 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2418 } else {
2419 signal_levels = intel_gen4_signal_levels(train_set);
2420 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2421 }
2422
2423 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2424
2425 *DP = (*DP & ~mask) | signal_levels;
2426}
2427
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002428static bool
Chris Wilsonea5b2132010-08-04 13:50:23 +01002429intel_dp_set_link_train(struct intel_dp *intel_dp,
Jani Nikula70aff662013-09-27 15:10:44 +03002430 uint32_t *DP,
Chris Wilson58e10eb2010-10-03 10:56:11 +01002431 uint8_t dp_train_pat)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002432{
Paulo Zanoni174edf12012-10-26 19:05:50 -02002433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2434 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002435 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02002436 enum port port = intel_dig_port->port;
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03002437 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2438 int ret, len;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002439
Paulo Zanoni22b8bf12013-02-18 19:00:23 -03002440 if (HAS_DDI(dev)) {
Imre Deak3ab9c632013-05-03 12:57:41 +03002441 uint32_t temp = I915_READ(DP_TP_CTL(port));
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002442
2443 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2444 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2445 else
2446 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2447
2448 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2449 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2450 case DP_TRAINING_PATTERN_DISABLE:
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002451 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2452
2453 break;
2454 case DP_TRAINING_PATTERN_1:
2455 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2456 break;
2457 case DP_TRAINING_PATTERN_2:
2458 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2459 break;
2460 case DP_TRAINING_PATTERN_3:
2461 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2462 break;
2463 }
Paulo Zanoni174edf12012-10-26 19:05:50 -02002464 I915_WRITE(DP_TP_CTL(port), temp);
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002465
Imre Deakbc7d38a2013-05-16 14:40:36 +03002466 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
Jani Nikula70aff662013-09-27 15:10:44 +03002467 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002468
2469 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2470 case DP_TRAINING_PATTERN_DISABLE:
Jani Nikula70aff662013-09-27 15:10:44 +03002471 *DP |= DP_LINK_TRAIN_OFF_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002472 break;
2473 case DP_TRAINING_PATTERN_1:
Jani Nikula70aff662013-09-27 15:10:44 +03002474 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002475 break;
2476 case DP_TRAINING_PATTERN_2:
Jani Nikula70aff662013-09-27 15:10:44 +03002477 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002478 break;
2479 case DP_TRAINING_PATTERN_3:
2480 DRM_ERROR("DP training pattern 3 not supported\n");
Jani Nikula70aff662013-09-27 15:10:44 +03002481 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002482 break;
2483 }
2484
2485 } else {
Jani Nikula70aff662013-09-27 15:10:44 +03002486 *DP &= ~DP_LINK_TRAIN_MASK;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002487
2488 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2489 case DP_TRAINING_PATTERN_DISABLE:
Jani Nikula70aff662013-09-27 15:10:44 +03002490 *DP |= DP_LINK_TRAIN_OFF;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002491 break;
2492 case DP_TRAINING_PATTERN_1:
Jani Nikula70aff662013-09-27 15:10:44 +03002493 *DP |= DP_LINK_TRAIN_PAT_1;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002494 break;
2495 case DP_TRAINING_PATTERN_2:
Jani Nikula70aff662013-09-27 15:10:44 +03002496 *DP |= DP_LINK_TRAIN_PAT_2;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002497 break;
2498 case DP_TRAINING_PATTERN_3:
2499 DRM_ERROR("DP training pattern 3 not supported\n");
Jani Nikula70aff662013-09-27 15:10:44 +03002500 *DP |= DP_LINK_TRAIN_PAT_2;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002501 break;
2502 }
2503 }
2504
Jani Nikula70aff662013-09-27 15:10:44 +03002505 I915_WRITE(intel_dp->output_reg, *DP);
Chris Wilsonea5b2132010-08-04 13:50:23 +01002506 POSTING_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002507
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03002508 buf[0] = dp_train_pat;
2509 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002510 DP_TRAINING_PATTERN_DISABLE) {
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03002511 /* don't write DP_TRAINING_LANEx_SET on disable */
2512 len = 1;
2513 } else {
2514 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2515 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2516 len = intel_dp->lane_count + 1;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002517 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002518
Jani Nikula9d1a1032014-03-14 16:51:15 +02002519 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2520 buf, len);
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03002521
2522 return ret == len;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002523}
2524
Jani Nikula70aff662013-09-27 15:10:44 +03002525static bool
2526intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2527 uint8_t dp_train_pat)
2528{
Jani Nikula953d22e2013-10-04 15:08:47 +03002529 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
Jani Nikula70aff662013-09-27 15:10:44 +03002530 intel_dp_set_signal_levels(intel_dp, DP);
2531 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2532}
2533
2534static bool
2535intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
Jani Nikula0301b3a2013-10-15 09:36:08 +03002536 const uint8_t link_status[DP_LINK_STATUS_SIZE])
Jani Nikula70aff662013-09-27 15:10:44 +03002537{
2538 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2539 struct drm_device *dev = intel_dig_port->base.base.dev;
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2541 int ret;
2542
2543 intel_get_adjust_train(intel_dp, link_status);
2544 intel_dp_set_signal_levels(intel_dp, DP);
2545
2546 I915_WRITE(intel_dp->output_reg, *DP);
2547 POSTING_READ(intel_dp->output_reg);
2548
Jani Nikula9d1a1032014-03-14 16:51:15 +02002549 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2550 intel_dp->train_set, intel_dp->lane_count);
Jani Nikula70aff662013-09-27 15:10:44 +03002551
2552 return ret == intel_dp->lane_count;
2553}
2554
Imre Deak3ab9c632013-05-03 12:57:41 +03002555static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2556{
2557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2558 struct drm_device *dev = intel_dig_port->base.base.dev;
2559 struct drm_i915_private *dev_priv = dev->dev_private;
2560 enum port port = intel_dig_port->port;
2561 uint32_t val;
2562
2563 if (!HAS_DDI(dev))
2564 return;
2565
2566 val = I915_READ(DP_TP_CTL(port));
2567 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2568 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2569 I915_WRITE(DP_TP_CTL(port), val);
2570
2571 /*
2572 * On PORT_A we can have only eDP in SST mode. There the only reason
2573 * we need to set idle transmission mode is to work around a HW issue
2574 * where we enable the pipe while not in idle link-training mode.
2575 * In this case there is requirement to wait for a minimum number of
2576 * idle patterns to be sent.
2577 */
2578 if (port == PORT_A)
2579 return;
2580
2581 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2582 1))
2583 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2584}
2585
Jesse Barnes33a34e42010-09-08 12:42:02 -07002586/* Enable corresponding port and start training pattern 1 */
Paulo Zanonic19b0662012-10-15 15:51:41 -03002587void
Jesse Barnes33a34e42010-09-08 12:42:02 -07002588intel_dp_start_link_train(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002589{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002590 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
Paulo Zanonic19b0662012-10-15 15:51:41 -03002591 struct drm_device *dev = encoder->dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002592 int i;
2593 uint8_t voltage;
Keith Packardcdb0e952011-11-01 20:00:06 -07002594 int voltage_tries, loop_tries;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002595 uint32_t DP = intel_dp->DP;
Jani Nikula6aba5b62013-10-04 15:08:10 +03002596 uint8_t link_config[2];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002597
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002598 if (HAS_DDI(dev))
Paulo Zanonic19b0662012-10-15 15:51:41 -03002599 intel_ddi_prepare_link_retrain(encoder);
2600
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002601 /* Write the link configuration data */
Jani Nikula6aba5b62013-10-04 15:08:10 +03002602 link_config[0] = intel_dp->link_bw;
2603 link_config[1] = intel_dp->lane_count;
2604 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2605 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
Jani Nikula9d1a1032014-03-14 16:51:15 +02002606 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
Jani Nikula6aba5b62013-10-04 15:08:10 +03002607
2608 link_config[0] = 0;
2609 link_config[1] = DP_SET_ANSI_8B10B;
Jani Nikula9d1a1032014-03-14 16:51:15 +02002610 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002611
2612 DP |= DP_PORT_EN;
Keith Packard1a2eb462011-11-16 16:26:07 -08002613
Jani Nikula70aff662013-09-27 15:10:44 +03002614 /* clock recovery */
2615 if (!intel_dp_reset_link_train(intel_dp, &DP,
2616 DP_TRAINING_PATTERN_1 |
2617 DP_LINK_SCRAMBLING_DISABLE)) {
2618 DRM_ERROR("failed to enable link training\n");
2619 return;
2620 }
2621
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002622 voltage = 0xff;
Keith Packardcdb0e952011-11-01 20:00:06 -07002623 voltage_tries = 0;
2624 loop_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002625 for (;;) {
Jani Nikula70aff662013-09-27 15:10:44 +03002626 uint8_t link_status[DP_LINK_STATUS_SIZE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002627
Daniel Vettera7c96552012-10-18 10:15:30 +02002628 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
Keith Packard93f62da2011-11-01 19:45:03 -07002629 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2630 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002631 break;
Keith Packard93f62da2011-11-01 19:45:03 -07002632 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002633
Daniel Vetter01916272012-10-18 10:15:25 +02002634 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Keith Packard93f62da2011-11-01 19:45:03 -07002635 DRM_DEBUG_KMS("clock recovery OK\n");
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002636 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002637 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002638
2639 /* Check to see if we've tried the max voltage */
2640 for (i = 0; i < intel_dp->lane_count; i++)
2641 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2642 break;
Takashi Iwai3b4f8192013-03-11 18:40:16 +01002643 if (i == intel_dp->lane_count) {
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002644 ++loop_tries;
2645 if (loop_tries == 5) {
Jani Nikula3def84b2013-10-05 16:13:56 +03002646 DRM_ERROR("too many full retries, give up\n");
Keith Packardcdb0e952011-11-01 20:00:06 -07002647 break;
2648 }
Jani Nikula70aff662013-09-27 15:10:44 +03002649 intel_dp_reset_link_train(intel_dp, &DP,
2650 DP_TRAINING_PATTERN_1 |
2651 DP_LINK_SCRAMBLING_DISABLE);
Keith Packardcdb0e952011-11-01 20:00:06 -07002652 voltage_tries = 0;
2653 continue;
2654 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002655
2656 /* Check to see if we've tried the same voltage 5 times */
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002657 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
Chris Wilson24773672012-09-26 16:48:30 +01002658 ++voltage_tries;
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002659 if (voltage_tries == 5) {
Jani Nikula3def84b2013-10-05 16:13:56 +03002660 DRM_ERROR("too many voltage retries, give up\n");
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002661 break;
2662 }
2663 } else
2664 voltage_tries = 0;
2665 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002666
Jani Nikula70aff662013-09-27 15:10:44 +03002667 /* Update training set as requested by target */
2668 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2669 DRM_ERROR("failed to update link training\n");
2670 break;
2671 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002672 }
2673
Jesse Barnes33a34e42010-09-08 12:42:02 -07002674 intel_dp->DP = DP;
2675}
2676
Paulo Zanonic19b0662012-10-15 15:51:41 -03002677void
Jesse Barnes33a34e42010-09-08 12:42:02 -07002678intel_dp_complete_link_train(struct intel_dp *intel_dp)
2679{
Jesse Barnes33a34e42010-09-08 12:42:02 -07002680 bool channel_eq = false;
Jesse Barnes37f80972011-01-05 14:45:24 -08002681 int tries, cr_tries;
Jesse Barnes33a34e42010-09-08 12:42:02 -07002682 uint32_t DP = intel_dp->DP;
Todd Previte06ea66b2014-01-20 10:19:39 -07002683 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2684
2685 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2686 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2687 training_pattern = DP_TRAINING_PATTERN_3;
Jesse Barnes33a34e42010-09-08 12:42:02 -07002688
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002689 /* channel equalization */
Jani Nikula70aff662013-09-27 15:10:44 +03002690 if (!intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07002691 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03002692 DP_LINK_SCRAMBLING_DISABLE)) {
2693 DRM_ERROR("failed to start channel equalization\n");
2694 return;
2695 }
2696
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002697 tries = 0;
Jesse Barnes37f80972011-01-05 14:45:24 -08002698 cr_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002699 channel_eq = false;
2700 for (;;) {
Jani Nikula70aff662013-09-27 15:10:44 +03002701 uint8_t link_status[DP_LINK_STATUS_SIZE];
Zhenyu Wange3421a12010-04-08 09:43:27 +08002702
Jesse Barnes37f80972011-01-05 14:45:24 -08002703 if (cr_tries > 5) {
2704 DRM_ERROR("failed to train DP, aborting\n");
Jesse Barnes37f80972011-01-05 14:45:24 -08002705 break;
2706 }
2707
Daniel Vettera7c96552012-10-18 10:15:30 +02002708 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
Jani Nikula70aff662013-09-27 15:10:44 +03002709 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2710 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002711 break;
Jani Nikula70aff662013-09-27 15:10:44 +03002712 }
Jesse Barnes869184a2010-10-07 16:01:22 -07002713
Jesse Barnes37f80972011-01-05 14:45:24 -08002714 /* Make sure clock is still ok */
Daniel Vetter01916272012-10-18 10:15:25 +02002715 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Jesse Barnes37f80972011-01-05 14:45:24 -08002716 intel_dp_start_link_train(intel_dp);
Jani Nikula70aff662013-09-27 15:10:44 +03002717 intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07002718 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03002719 DP_LINK_SCRAMBLING_DISABLE);
Jesse Barnes37f80972011-01-05 14:45:24 -08002720 cr_tries++;
2721 continue;
2722 }
2723
Daniel Vetter1ffdff12012-10-18 10:15:24 +02002724 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002725 channel_eq = true;
2726 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002727 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002728
Jesse Barnes37f80972011-01-05 14:45:24 -08002729 /* Try 5 times, then try clock recovery if that fails */
2730 if (tries > 5) {
2731 intel_dp_link_down(intel_dp);
2732 intel_dp_start_link_train(intel_dp);
Jani Nikula70aff662013-09-27 15:10:44 +03002733 intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07002734 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03002735 DP_LINK_SCRAMBLING_DISABLE);
Jesse Barnes37f80972011-01-05 14:45:24 -08002736 tries = 0;
2737 cr_tries++;
2738 continue;
2739 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002740
Jani Nikula70aff662013-09-27 15:10:44 +03002741 /* Update training set as requested by target */
2742 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2743 DRM_ERROR("failed to update link training\n");
2744 break;
2745 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002746 ++tries;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002747 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002748
Imre Deak3ab9c632013-05-03 12:57:41 +03002749 intel_dp_set_idle_link_train(intel_dp);
2750
2751 intel_dp->DP = DP;
2752
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002753 if (channel_eq)
Masanari Iida07f42252013-03-20 11:00:34 +09002754 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002755
Imre Deak3ab9c632013-05-03 12:57:41 +03002756}
2757
2758void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2759{
Jani Nikula70aff662013-09-27 15:10:44 +03002760 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
Imre Deak3ab9c632013-05-03 12:57:41 +03002761 DP_TRAINING_PATTERN_DISABLE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002762}
2763
2764static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01002765intel_dp_link_down(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002766{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002767 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002768 enum port port = intel_dig_port->port;
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002769 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002770 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterab527ef2012-11-29 15:59:33 +01002771 struct intel_crtc *intel_crtc =
2772 to_intel_crtc(intel_dig_port->base.base.crtc);
Chris Wilsonea5b2132010-08-04 13:50:23 +01002773 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002774
Paulo Zanonic19b0662012-10-15 15:51:41 -03002775 /*
2776 * DDI code has a strict mode set sequence and we should try to respect
2777 * it, otherwise we might hang the machine in many different ways. So we
2778 * really should be disabling the port only on a complete crtc_disable
2779 * sequence. This function is just called under two conditions on DDI
2780 * code:
2781 * - Link train failed while doing crtc_enable, and on this case we
2782 * really should respect the mode set sequence and wait for a
2783 * crtc_disable.
2784 * - Someone turned the monitor off and intel_dp_check_link_status
2785 * called us. We don't need to disable the whole port on this case, so
2786 * when someone turns the monitor on again,
2787 * intel_ddi_prepare_link_retrain will take care of redoing the link
2788 * train.
2789 */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002790 if (HAS_DDI(dev))
Paulo Zanonic19b0662012-10-15 15:51:41 -03002791 return;
2792
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02002793 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
Chris Wilson1b39d6f2010-12-06 11:20:45 +00002794 return;
2795
Zhao Yakui28c97732009-10-09 11:39:41 +08002796 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002797
Imre Deakbc7d38a2013-05-16 14:40:36 +03002798 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08002799 DP &= ~DP_LINK_TRAIN_MASK_CPT;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002800 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
Zhenyu Wange3421a12010-04-08 09:43:27 +08002801 } else {
2802 DP &= ~DP_LINK_TRAIN_MASK;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002803 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
Zhenyu Wange3421a12010-04-08 09:43:27 +08002804 }
Chris Wilsonfe255d02010-09-11 21:37:48 +01002805 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002806
Daniel Vetter493a7082012-05-30 12:31:56 +02002807 if (HAS_PCH_IBX(dev) &&
Chris Wilson1b39d6f2010-12-06 11:20:45 +00002808 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002809 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
Chris Wilson31acbcc2011-04-17 06:38:35 +01002810
Eric Anholt5bddd172010-11-18 09:32:59 +08002811 /* Hardware workaround: leaving our transcoder select
2812 * set to transcoder B while it's off will prevent the
2813 * corresponding HDMI output on transcoder A.
2814 *
2815 * Combine this with another hardware workaround:
2816 * transcoder select bit can only be cleared while the
2817 * port is enabled.
2818 */
2819 DP &= ~DP_PIPEB_SELECT;
2820 I915_WRITE(intel_dp->output_reg, DP);
2821
2822 /* Changes to enable or select take place the vblank
2823 * after being written.
2824 */
Daniel Vetterff50afe2012-11-29 15:59:34 +01002825 if (WARN_ON(crtc == NULL)) {
2826 /* We should never try to disable a port without a crtc
2827 * attached. For paranoia keep the code around for a
2828 * bit. */
Chris Wilson31acbcc2011-04-17 06:38:35 +01002829 POSTING_READ(intel_dp->output_reg);
2830 msleep(50);
2831 } else
Daniel Vetterab527ef2012-11-29 15:59:33 +01002832 intel_wait_for_vblank(dev, intel_crtc->pipe);
Eric Anholt5bddd172010-11-18 09:32:59 +08002833 }
2834
Wu Fengguang832afda2011-12-09 20:42:21 +08002835 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002836 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2837 POSTING_READ(intel_dp->output_reg);
Keith Packardf01eca22011-09-28 16:48:10 -07002838 msleep(intel_dp->panel_power_down_delay);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002839}
2840
Keith Packard26d61aa2011-07-25 20:01:09 -07002841static bool
2842intel_dp_get_dpcd(struct intel_dp *intel_dp)
Keith Packard92fd8fd2011-07-25 19:50:10 -07002843{
Rodrigo Vivia031d702013-10-03 16:15:06 -03002844 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2845 struct drm_device *dev = dig_port->base.base.dev;
2846 struct drm_i915_private *dev_priv = dev->dev_private;
2847
Damien Lespiau577c7a52012-12-13 16:09:02 +00002848 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2849
Jani Nikula9d1a1032014-03-14 16:51:15 +02002850 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2851 sizeof(intel_dp->dpcd)) < 0)
Adam Jacksonedb39242012-09-18 10:58:49 -04002852 return false; /* aux transfer failed */
Keith Packard92fd8fd2011-07-25 19:50:10 -07002853
Damien Lespiau577c7a52012-12-13 16:09:02 +00002854 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2855 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2856 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2857
Adam Jacksonedb39242012-09-18 10:58:49 -04002858 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2859 return false; /* DPCD not present */
2860
Shobhit Kumar2293bb52013-07-11 18:44:56 -03002861 /* Check if the panel supports PSR */
2862 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
Jani Nikula50003932013-09-20 16:42:17 +03002863 if (is_edp(intel_dp)) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02002864 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2865 intel_dp->psr_dpcd,
2866 sizeof(intel_dp->psr_dpcd));
Rodrigo Vivia031d702013-10-03 16:15:06 -03002867 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2868 dev_priv->psr.sink_support = true;
Jani Nikula50003932013-09-20 16:42:17 +03002869 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
Rodrigo Vivia031d702013-10-03 16:15:06 -03002870 }
Jani Nikula50003932013-09-20 16:42:17 +03002871 }
2872
Todd Previte06ea66b2014-01-20 10:19:39 -07002873 /* Training Pattern 3 support */
2874 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2875 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2876 intel_dp->use_tps3 = true;
2877 DRM_DEBUG_KMS("Displayport TPS3 supported");
2878 } else
2879 intel_dp->use_tps3 = false;
2880
Adam Jacksonedb39242012-09-18 10:58:49 -04002881 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2882 DP_DWN_STRM_PORT_PRESENT))
2883 return true; /* native DP sink */
2884
2885 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2886 return true; /* no per-port downstream info */
2887
Jani Nikula9d1a1032014-03-14 16:51:15 +02002888 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2889 intel_dp->downstream_ports,
2890 DP_MAX_DOWNSTREAM_PORTS) < 0)
Adam Jacksonedb39242012-09-18 10:58:49 -04002891 return false; /* downstream port status fetch failed */
2892
2893 return true;
Keith Packard92fd8fd2011-07-25 19:50:10 -07002894}
2895
Adam Jackson0d198322012-05-14 16:05:47 -04002896static void
2897intel_dp_probe_oui(struct intel_dp *intel_dp)
2898{
2899 u8 buf[3];
2900
2901 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2902 return;
2903
Jani Nikula24f3e092014-03-17 16:43:36 +02002904 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter351cfc32012-06-12 13:20:47 +02002905
Jani Nikula9d1a1032014-03-14 16:51:15 +02002906 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
Adam Jackson0d198322012-05-14 16:05:47 -04002907 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2908 buf[0], buf[1], buf[2]);
2909
Jani Nikula9d1a1032014-03-14 16:51:15 +02002910 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
Adam Jackson0d198322012-05-14 16:05:47 -04002911 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2912 buf[0], buf[1], buf[2]);
Daniel Vetter351cfc32012-06-12 13:20:47 +02002913
Daniel Vetter4be73782014-01-17 14:39:48 +01002914 edp_panel_vdd_off(intel_dp, false);
Adam Jackson0d198322012-05-14 16:05:47 -04002915}
2916
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002917int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2918{
2919 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2920 struct drm_device *dev = intel_dig_port->base.base.dev;
2921 struct intel_crtc *intel_crtc =
2922 to_intel_crtc(intel_dig_port->base.base.crtc);
2923 u8 buf[1];
2924
Jani Nikula9d1a1032014-03-14 16:51:15 +02002925 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002926 return -EAGAIN;
2927
2928 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2929 return -ENOTTY;
2930
Jani Nikula9d1a1032014-03-14 16:51:15 +02002931 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2932 DP_TEST_SINK_START) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002933 return -EAGAIN;
2934
2935 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2936 intel_wait_for_vblank(dev, intel_crtc->pipe);
2937 intel_wait_for_vblank(dev, intel_crtc->pipe);
2938
Jani Nikula9d1a1032014-03-14 16:51:15 +02002939 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002940 return -EAGAIN;
2941
Jani Nikula9d1a1032014-03-14 16:51:15 +02002942 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002943 return 0;
2944}
2945
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002946static bool
2947intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2948{
Jani Nikula9d1a1032014-03-14 16:51:15 +02002949 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2950 DP_DEVICE_SERVICE_IRQ_VECTOR,
2951 sink_irq_vector, 1) == 1;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002952}
2953
2954static void
2955intel_dp_handle_test_request(struct intel_dp *intel_dp)
2956{
2957 /* NAK by default */
Jani Nikula9d1a1032014-03-14 16:51:15 +02002958 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002959}
2960
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002961/*
2962 * According to DP spec
2963 * 5.1.2:
2964 * 1. Read DPCD
2965 * 2. Configure link according to Receiver Capabilities
2966 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2967 * 4. Check link status on receipt of hot-plug interrupt
2968 */
2969
Paulo Zanoni00c09d72012-10-26 19:05:52 -02002970void
Chris Wilsonea5b2132010-08-04 13:50:23 +01002971intel_dp_check_link_status(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002972{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002973 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002974 u8 sink_irq_vector;
Keith Packard93f62da2011-11-01 19:45:03 -07002975 u8 link_status[DP_LINK_STATUS_SIZE];
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002976
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002977 if (!intel_encoder->connectors_active)
Keith Packardd2b996a2011-07-25 22:37:51 -07002978 return;
Jesse Barnes59cd09e2011-07-07 11:10:59 -07002979
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002980 if (WARN_ON(!intel_encoder->base.crtc))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002981 return;
2982
Keith Packard92fd8fd2011-07-25 19:50:10 -07002983 /* Try to read receiver status if the link appears to be up */
Keith Packard93f62da2011-11-01 19:45:03 -07002984 if (!intel_dp_get_link_status(intel_dp, link_status)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002985 return;
2986 }
2987
Keith Packard92fd8fd2011-07-25 19:50:10 -07002988 /* Now read the DPCD to see if it's actually running */
Keith Packard26d61aa2011-07-25 20:01:09 -07002989 if (!intel_dp_get_dpcd(intel_dp)) {
Jesse Barnes59cd09e2011-07-07 11:10:59 -07002990 return;
2991 }
2992
Jesse Barnesa60f0e32011-10-20 15:09:17 -07002993 /* Try to read the source of the interrupt */
2994 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2995 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2996 /* Clear interrupt source */
Jani Nikula9d1a1032014-03-14 16:51:15 +02002997 drm_dp_dpcd_writeb(&intel_dp->aux,
2998 DP_DEVICE_SERVICE_IRQ_VECTOR,
2999 sink_irq_vector);
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003000
3001 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3002 intel_dp_handle_test_request(intel_dp);
3003 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3004 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3005 }
3006
Daniel Vetter1ffdff12012-10-18 10:15:24 +02003007 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
Keith Packard92fd8fd2011-07-25 19:50:10 -07003008 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003009 drm_get_encoder_name(&intel_encoder->base));
Jesse Barnes33a34e42010-09-08 12:42:02 -07003010 intel_dp_start_link_train(intel_dp);
3011 intel_dp_complete_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03003012 intel_dp_stop_link_train(intel_dp);
Jesse Barnes33a34e42010-09-08 12:42:02 -07003013 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003014}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003015
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003016/* XXX this is probably wrong for multiple downstream ports */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003017static enum drm_connector_status
Keith Packard26d61aa2011-07-25 20:01:09 -07003018intel_dp_detect_dpcd(struct intel_dp *intel_dp)
Adam Jackson71ba90002011-07-12 17:38:04 -04003019{
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003020 uint8_t *dpcd = intel_dp->dpcd;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003021 uint8_t type;
3022
3023 if (!intel_dp_get_dpcd(intel_dp))
3024 return connector_status_disconnected;
3025
3026 /* if there's no downstream port, we're done */
3027 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
Keith Packard26d61aa2011-07-25 20:01:09 -07003028 return connector_status_connected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003029
3030 /* If we're HPD-aware, SINK_COUNT changes dynamically */
Jani Nikulac9ff1602013-09-27 14:48:42 +03003031 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3032 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
Adam Jackson23235172012-09-20 16:42:45 -04003033 uint8_t reg;
Jani Nikula9d1a1032014-03-14 16:51:15 +02003034
3035 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3036 &reg, 1) < 0)
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003037 return connector_status_unknown;
Jani Nikula9d1a1032014-03-14 16:51:15 +02003038
Adam Jackson23235172012-09-20 16:42:45 -04003039 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3040 : connector_status_disconnected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003041 }
3042
3043 /* If no HPD, poke DDC gently */
Jani Nikula0b998362014-03-14 16:51:17 +02003044 if (drm_probe_ddc(&intel_dp->aux.ddc))
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003045 return connector_status_connected;
3046
3047 /* Well we tried, say unknown for unreliable port types */
Jani Nikulac9ff1602013-09-27 14:48:42 +03003048 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3049 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3050 if (type == DP_DS_PORT_TYPE_VGA ||
3051 type == DP_DS_PORT_TYPE_NON_EDID)
3052 return connector_status_unknown;
3053 } else {
3054 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3055 DP_DWN_STRM_PORT_TYPE_MASK;
3056 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3057 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3058 return connector_status_unknown;
3059 }
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003060
3061 /* Anything else is out of spec, warn and ignore */
3062 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
Keith Packard26d61aa2011-07-25 20:01:09 -07003063 return connector_status_disconnected;
Adam Jackson71ba90002011-07-12 17:38:04 -04003064}
3065
3066static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003067ironlake_dp_detect(struct intel_dp *intel_dp)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003068{
Paulo Zanoni30add222012-10-26 19:05:45 -02003069 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Damien Lespiau1b469632012-12-13 16:09:01 +00003070 struct drm_i915_private *dev_priv = dev->dev_private;
3071 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003072 enum drm_connector_status status;
3073
Chris Wilsonfe16d942011-02-12 10:29:38 +00003074 /* Can't disconnect eDP, but you can close the lid... */
3075 if (is_edp(intel_dp)) {
Paulo Zanoni30add222012-10-26 19:05:45 -02003076 status = intel_panel_detect(dev);
Chris Wilsonfe16d942011-02-12 10:29:38 +00003077 if (status == connector_status_unknown)
3078 status = connector_status_connected;
3079 return status;
3080 }
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003081
Damien Lespiau1b469632012-12-13 16:09:01 +00003082 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3083 return connector_status_disconnected;
3084
Keith Packard26d61aa2011-07-25 20:01:09 -07003085 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003086}
3087
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003088static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003089g4x_dp_detect(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003090{
Paulo Zanoni30add222012-10-26 19:05:45 -02003091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003092 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä34f2be42013-01-24 15:29:27 +02003093 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Chris Wilson10f76a32012-05-11 18:01:32 +01003094 uint32_t bit;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003095
Jesse Barnes35aad752013-03-01 13:14:31 -08003096 /* Can't disconnect eDP, but you can close the lid... */
3097 if (is_edp(intel_dp)) {
3098 enum drm_connector_status status;
3099
3100 status = intel_panel_detect(dev);
3101 if (status == connector_status_unknown)
3102 status = connector_status_connected;
3103 return status;
3104 }
3105
Todd Previte232a6ee2014-01-23 00:13:41 -07003106 if (IS_VALLEYVIEW(dev)) {
3107 switch (intel_dig_port->port) {
3108 case PORT_B:
3109 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3110 break;
3111 case PORT_C:
3112 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3113 break;
3114 case PORT_D:
3115 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3116 break;
3117 default:
3118 return connector_status_unknown;
3119 }
3120 } else {
3121 switch (intel_dig_port->port) {
3122 case PORT_B:
3123 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3124 break;
3125 case PORT_C:
3126 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3127 break;
3128 case PORT_D:
3129 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3130 break;
3131 default:
3132 return connector_status_unknown;
3133 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003134 }
3135
Chris Wilson10f76a32012-05-11 18:01:32 +01003136 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003137 return connector_status_disconnected;
3138
Keith Packard26d61aa2011-07-25 20:01:09 -07003139 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003140}
3141
Keith Packard8c241fe2011-09-28 16:38:44 -07003142static struct edid *
3143intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3144{
Jani Nikula9cd300e2012-10-19 14:51:52 +03003145 struct intel_connector *intel_connector = to_intel_connector(connector);
Keith Packard8c241fe2011-09-28 16:38:44 -07003146
Jani Nikula9cd300e2012-10-19 14:51:52 +03003147 /* use cached edid if we have one */
3148 if (intel_connector->edid) {
Jani Nikula9cd300e2012-10-19 14:51:52 +03003149 /* invalid edid */
3150 if (IS_ERR(intel_connector->edid))
Jesse Barnesd6f24d02012-06-14 15:28:33 -04003151 return NULL;
3152
Jani Nikula55e9ede2013-10-01 10:38:54 +03003153 return drm_edid_duplicate(intel_connector->edid);
Jesse Barnesd6f24d02012-06-14 15:28:33 -04003154 }
3155
Jani Nikula9cd300e2012-10-19 14:51:52 +03003156 return drm_get_edid(connector, adapter);
Keith Packard8c241fe2011-09-28 16:38:44 -07003157}
3158
3159static int
3160intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3161{
Jani Nikula9cd300e2012-10-19 14:51:52 +03003162 struct intel_connector *intel_connector = to_intel_connector(connector);
Keith Packard8c241fe2011-09-28 16:38:44 -07003163
Jani Nikula9cd300e2012-10-19 14:51:52 +03003164 /* use cached edid if we have one */
3165 if (intel_connector->edid) {
3166 /* invalid edid */
3167 if (IS_ERR(intel_connector->edid))
3168 return 0;
3169
3170 return intel_connector_update_modes(connector,
3171 intel_connector->edid);
Jesse Barnesd6f24d02012-06-14 15:28:33 -04003172 }
3173
Jani Nikula9cd300e2012-10-19 14:51:52 +03003174 return intel_ddc_get_modes(connector, adapter);
Keith Packard8c241fe2011-09-28 16:38:44 -07003175}
3176
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003177static enum drm_connector_status
3178intel_dp_detect(struct drm_connector *connector, bool force)
3179{
3180 struct intel_dp *intel_dp = intel_attached_dp(connector);
Paulo Zanonid63885d2012-10-26 19:05:49 -02003181 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3182 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003183 struct drm_device *dev = connector->dev;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003184 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003185 enum drm_connector_status status;
Imre Deak671dedd2014-03-05 16:20:53 +02003186 enum intel_display_power_domain power_domain;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003187 struct edid *edid = NULL;
3188
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003189 intel_runtime_pm_get(dev_priv);
3190
Imre Deak671dedd2014-03-05 16:20:53 +02003191 power_domain = intel_display_port_power_domain(intel_encoder);
3192 intel_display_power_get(dev_priv, power_domain);
3193
Chris Wilson164c8592013-07-20 20:27:08 +01003194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3195 connector->base.id, drm_get_connector_name(connector));
3196
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003197 intel_dp->has_audio = false;
3198
3199 if (HAS_PCH_SPLIT(dev))
3200 status = ironlake_dp_detect(intel_dp);
3201 else
3202 status = g4x_dp_detect(intel_dp);
Adam Jackson1b9be9d2011-07-12 17:38:01 -04003203
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003204 if (status != connector_status_connected)
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003205 goto out;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003206
Adam Jackson0d198322012-05-14 16:05:47 -04003207 intel_dp_probe_oui(intel_dp);
3208
Daniel Vetterc3e5f672012-02-23 17:14:47 +01003209 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3210 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
Chris Wilsonf6849602010-09-19 09:29:33 +01003211 } else {
Jani Nikula0b998362014-03-14 16:51:17 +02003212 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
Chris Wilsonf6849602010-09-19 09:29:33 +01003213 if (edid) {
3214 intel_dp->has_audio = drm_detect_monitor_audio(edid);
Chris Wilsonf6849602010-09-19 09:29:33 +01003215 kfree(edid);
3216 }
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003217 }
3218
Paulo Zanonid63885d2012-10-26 19:05:49 -02003219 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3220 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003221 status = connector_status_connected;
3222
3223out:
Imre Deak671dedd2014-03-05 16:20:53 +02003224 intel_display_power_put(dev_priv, power_domain);
3225
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003226 intel_runtime_pm_put(dev_priv);
Imre Deak671dedd2014-03-05 16:20:53 +02003227
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003228 return status;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003229}
3230
3231static int intel_dp_get_modes(struct drm_connector *connector)
3232{
Chris Wilsondf0e9242010-09-09 16:20:55 +01003233 struct intel_dp *intel_dp = intel_attached_dp(connector);
Imre Deak671dedd2014-03-05 16:20:53 +02003234 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3235 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Jani Nikuladd06f902012-10-19 14:51:50 +03003236 struct intel_connector *intel_connector = to_intel_connector(connector);
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003237 struct drm_device *dev = connector->dev;
Imre Deak671dedd2014-03-05 16:20:53 +02003238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 enum intel_display_power_domain power_domain;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003240 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003241
3242 /* We should parse the EDID data and find out if it has an audio sink
3243 */
3244
Imre Deak671dedd2014-03-05 16:20:53 +02003245 power_domain = intel_display_port_power_domain(intel_encoder);
3246 intel_display_power_get(dev_priv, power_domain);
3247
Jani Nikula0b998362014-03-14 16:51:17 +02003248 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
Imre Deak671dedd2014-03-05 16:20:53 +02003249 intel_display_power_put(dev_priv, power_domain);
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003250 if (ret)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003251 return ret;
3252
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003253 /* if eDP has no EDID, fall back to fixed mode */
Jani Nikuladd06f902012-10-19 14:51:50 +03003254 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003255 struct drm_display_mode *mode;
Jani Nikuladd06f902012-10-19 14:51:50 +03003256 mode = drm_mode_duplicate(dev,
3257 intel_connector->panel.fixed_mode);
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003258 if (mode) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003259 drm_mode_probed_add(connector, mode);
3260 return 1;
3261 }
3262 }
3263 return 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003264}
3265
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003266static bool
3267intel_dp_detect_audio(struct drm_connector *connector)
3268{
3269 struct intel_dp *intel_dp = intel_attached_dp(connector);
Imre Deak671dedd2014-03-05 16:20:53 +02003270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3271 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3272 struct drm_device *dev = connector->dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 enum intel_display_power_domain power_domain;
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003275 struct edid *edid;
3276 bool has_audio = false;
3277
Imre Deak671dedd2014-03-05 16:20:53 +02003278 power_domain = intel_display_port_power_domain(intel_encoder);
3279 intel_display_power_get(dev_priv, power_domain);
3280
Jani Nikula0b998362014-03-14 16:51:17 +02003281 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003282 if (edid) {
3283 has_audio = drm_detect_monitor_audio(edid);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003284 kfree(edid);
3285 }
3286
Imre Deak671dedd2014-03-05 16:20:53 +02003287 intel_display_power_put(dev_priv, power_domain);
3288
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003289 return has_audio;
3290}
3291
Chris Wilsonf6849602010-09-19 09:29:33 +01003292static int
3293intel_dp_set_property(struct drm_connector *connector,
3294 struct drm_property *property,
3295 uint64_t val)
3296{
Chris Wilsone953fd72011-02-21 22:23:52 +00003297 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Yuly Novikov53b41832012-10-26 12:04:00 +03003298 struct intel_connector *intel_connector = to_intel_connector(connector);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003299 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3300 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonf6849602010-09-19 09:29:33 +01003301 int ret;
3302
Rob Clark662595d2012-10-11 20:36:04 -05003303 ret = drm_object_property_set_value(&connector->base, property, val);
Chris Wilsonf6849602010-09-19 09:29:33 +01003304 if (ret)
3305 return ret;
3306
Chris Wilson3f43c482011-05-12 22:17:24 +01003307 if (property == dev_priv->force_audio_property) {
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003308 int i = val;
3309 bool has_audio;
3310
3311 if (i == intel_dp->force_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01003312 return 0;
3313
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003314 intel_dp->force_audio = i;
Chris Wilsonf6849602010-09-19 09:29:33 +01003315
Daniel Vetterc3e5f672012-02-23 17:14:47 +01003316 if (i == HDMI_AUDIO_AUTO)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003317 has_audio = intel_dp_detect_audio(connector);
3318 else
Daniel Vetterc3e5f672012-02-23 17:14:47 +01003319 has_audio = (i == HDMI_AUDIO_ON);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003320
3321 if (has_audio == intel_dp->has_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01003322 return 0;
3323
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003324 intel_dp->has_audio = has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +01003325 goto done;
3326 }
3327
Chris Wilsone953fd72011-02-21 22:23:52 +00003328 if (property == dev_priv->broadcast_rgb_property) {
Daniel Vetterae4edb82013-04-22 17:07:23 +02003329 bool old_auto = intel_dp->color_range_auto;
3330 uint32_t old_range = intel_dp->color_range;
3331
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003332 switch (val) {
3333 case INTEL_BROADCAST_RGB_AUTO:
3334 intel_dp->color_range_auto = true;
3335 break;
3336 case INTEL_BROADCAST_RGB_FULL:
3337 intel_dp->color_range_auto = false;
3338 intel_dp->color_range = 0;
3339 break;
3340 case INTEL_BROADCAST_RGB_LIMITED:
3341 intel_dp->color_range_auto = false;
3342 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3343 break;
3344 default:
3345 return -EINVAL;
3346 }
Daniel Vetterae4edb82013-04-22 17:07:23 +02003347
3348 if (old_auto == intel_dp->color_range_auto &&
3349 old_range == intel_dp->color_range)
3350 return 0;
3351
Chris Wilsone953fd72011-02-21 22:23:52 +00003352 goto done;
3353 }
3354
Yuly Novikov53b41832012-10-26 12:04:00 +03003355 if (is_edp(intel_dp) &&
3356 property == connector->dev->mode_config.scaling_mode_property) {
3357 if (val == DRM_MODE_SCALE_NONE) {
3358 DRM_DEBUG_KMS("no scaling not supported\n");
3359 return -EINVAL;
3360 }
3361
3362 if (intel_connector->panel.fitting_mode == val) {
3363 /* the eDP scaling property is not changed */
3364 return 0;
3365 }
3366 intel_connector->panel.fitting_mode = val;
3367
3368 goto done;
3369 }
3370
Chris Wilsonf6849602010-09-19 09:29:33 +01003371 return -EINVAL;
3372
3373done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00003374 if (intel_encoder->base.crtc)
3375 intel_crtc_restore_mode(intel_encoder->base.crtc);
Chris Wilsonf6849602010-09-19 09:29:33 +01003376
3377 return 0;
3378}
3379
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003380static void
Paulo Zanoni73845ad2013-06-12 17:27:30 -03003381intel_dp_connector_destroy(struct drm_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003382{
Jani Nikula1d508702012-10-19 14:51:49 +03003383 struct intel_connector *intel_connector = to_intel_connector(connector);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02003384
Jani Nikula9cd300e2012-10-19 14:51:52 +03003385 if (!IS_ERR_OR_NULL(intel_connector->edid))
3386 kfree(intel_connector->edid);
3387
Paulo Zanoniacd8db102013-06-12 17:27:23 -03003388 /* Can't call is_edp() since the encoder may have been destroyed
3389 * already. */
3390 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
Jani Nikula1d508702012-10-19 14:51:49 +03003391 intel_panel_fini(&intel_connector->panel);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02003392
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003393 drm_connector_cleanup(connector);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08003394 kfree(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003395}
3396
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003397void intel_dp_encoder_destroy(struct drm_encoder *encoder)
Daniel Vetter24d05922010-08-20 18:08:28 +02003398{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003399 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3400 struct intel_dp *intel_dp = &intel_dig_port->dp;
Daniel Vetterbd173812013-03-25 11:24:10 +01003401 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Daniel Vetter24d05922010-08-20 18:08:28 +02003402
Jani Nikula0b998362014-03-14 16:51:17 +02003403 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
Daniel Vetter24d05922010-08-20 18:08:28 +02003404 drm_encoder_cleanup(encoder);
Keith Packardbd943152011-09-18 23:09:52 -07003405 if (is_edp(intel_dp)) {
3406 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
Daniel Vetterbd173812013-03-25 11:24:10 +01003407 mutex_lock(&dev->mode_config.mutex);
Daniel Vetter4be73782014-01-17 14:39:48 +01003408 edp_panel_vdd_off_sync(intel_dp);
Daniel Vetterbd173812013-03-25 11:24:10 +01003409 mutex_unlock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07003410 }
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003411 kfree(intel_dig_port);
Daniel Vetter24d05922010-08-20 18:08:28 +02003412}
3413
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003414static const struct drm_connector_funcs intel_dp_connector_funcs = {
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02003415 .dpms = intel_connector_dpms,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003416 .detect = intel_dp_detect,
3417 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilsonf6849602010-09-19 09:29:33 +01003418 .set_property = intel_dp_set_property,
Paulo Zanoni73845ad2013-06-12 17:27:30 -03003419 .destroy = intel_dp_connector_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003420};
3421
3422static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3423 .get_modes = intel_dp_get_modes,
3424 .mode_valid = intel_dp_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01003425 .best_encoder = intel_best_encoder,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003426};
3427
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003428static const struct drm_encoder_funcs intel_dp_enc_funcs = {
Daniel Vetter24d05922010-08-20 18:08:28 +02003429 .destroy = intel_dp_encoder_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003430};
3431
Chris Wilson995b6762010-08-20 13:23:26 +01003432static void
Eric Anholt21d40d32010-03-25 11:11:14 -07003433intel_dp_hot_plug(struct intel_encoder *intel_encoder)
Keith Packardc8110e52009-05-06 11:51:10 -07003434{
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003435 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Keith Packardc8110e52009-05-06 11:51:10 -07003436
Jesse Barnes885a5012011-07-07 11:11:01 -07003437 intel_dp_check_link_status(intel_dp);
Keith Packardc8110e52009-05-06 11:51:10 -07003438}
3439
Zhenyu Wange3421a12010-04-08 09:43:27 +08003440/* Return which DP Port should be selected for Transcoder DP control */
3441int
Akshay Joshi0206e352011-08-16 15:34:10 -04003442intel_trans_dp_port_sel(struct drm_crtc *crtc)
Zhenyu Wange3421a12010-04-08 09:43:27 +08003443{
3444 struct drm_device *dev = crtc->dev;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003445 struct intel_encoder *intel_encoder;
3446 struct intel_dp *intel_dp;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003447
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003448 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3449 intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003450
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003451 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3452 intel_encoder->type == INTEL_OUTPUT_EDP)
Chris Wilsonea5b2132010-08-04 13:50:23 +01003453 return intel_dp->output_reg;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003454 }
Chris Wilsonea5b2132010-08-04 13:50:23 +01003455
Zhenyu Wange3421a12010-04-08 09:43:27 +08003456 return -1;
3457}
3458
Zhao Yakui36e83a12010-06-12 14:32:21 +08003459/* check the VBT to see whether the eDP is on DP-D port */
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02003460bool intel_dp_is_edp(struct drm_device *dev, enum port port)
Zhao Yakui36e83a12010-06-12 14:32:21 +08003461{
3462 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03003463 union child_device_config *p_child;
Zhao Yakui36e83a12010-06-12 14:32:21 +08003464 int i;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02003465 static const short port_mapping[] = {
3466 [PORT_B] = PORT_IDPB,
3467 [PORT_C] = PORT_IDPC,
3468 [PORT_D] = PORT_IDPD,
3469 };
Zhao Yakui36e83a12010-06-12 14:32:21 +08003470
Ville Syrjälä3b32a352013-11-01 18:22:41 +02003471 if (port == PORT_A)
3472 return true;
3473
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003474 if (!dev_priv->vbt.child_dev_num)
Zhao Yakui36e83a12010-06-12 14:32:21 +08003475 return false;
3476
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003477 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3478 p_child = dev_priv->vbt.child_dev + i;
Zhao Yakui36e83a12010-06-12 14:32:21 +08003479
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02003480 if (p_child->common.dvo_port == port_mapping[port] &&
Ville Syrjäläf02586d2013-11-01 20:32:08 +02003481 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3482 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
Zhao Yakui36e83a12010-06-12 14:32:21 +08003483 return true;
3484 }
3485 return false;
3486}
3487
Chris Wilsonf6849602010-09-19 09:29:33 +01003488static void
3489intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3490{
Yuly Novikov53b41832012-10-26 12:04:00 +03003491 struct intel_connector *intel_connector = to_intel_connector(connector);
3492
Chris Wilson3f43c482011-05-12 22:17:24 +01003493 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00003494 intel_attach_broadcast_rgb_property(connector);
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003495 intel_dp->color_range_auto = true;
Yuly Novikov53b41832012-10-26 12:04:00 +03003496
3497 if (is_edp(intel_dp)) {
3498 drm_mode_create_scaling_mode_property(connector->dev);
Rob Clark6de6d842012-10-11 20:36:04 -05003499 drm_object_attach_property(
3500 &connector->base,
Yuly Novikov53b41832012-10-26 12:04:00 +03003501 connector->dev->mode_config.scaling_mode_property,
Yuly Novikov8e740cd2012-10-26 12:04:01 +03003502 DRM_MODE_SCALE_ASPECT);
3503 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
Yuly Novikov53b41832012-10-26 12:04:00 +03003504 }
Chris Wilsonf6849602010-09-19 09:29:33 +01003505}
3506
Imre Deakdada1a92014-01-29 13:25:41 +02003507static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3508{
3509 intel_dp->last_power_cycle = jiffies;
3510 intel_dp->last_power_on = jiffies;
3511 intel_dp->last_backlight_off = jiffies;
3512}
3513
Daniel Vetter67a54562012-10-20 20:57:45 +02003514static void
3515intel_dp_init_panel_power_sequencer(struct drm_device *dev,
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003516 struct intel_dp *intel_dp,
3517 struct edp_power_seq *out)
Daniel Vetter67a54562012-10-20 20:57:45 +02003518{
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 struct edp_power_seq cur, vbt, spec, final;
3521 u32 pp_on, pp_off, pp_div, pp;
Jani Nikulabf13e812013-09-06 07:40:05 +03003522 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
Jesse Barnes453c5422013-03-28 09:55:41 -07003523
3524 if (HAS_PCH_SPLIT(dev)) {
Jani Nikulabf13e812013-09-06 07:40:05 +03003525 pp_ctrl_reg = PCH_PP_CONTROL;
Jesse Barnes453c5422013-03-28 09:55:41 -07003526 pp_on_reg = PCH_PP_ON_DELAYS;
3527 pp_off_reg = PCH_PP_OFF_DELAYS;
3528 pp_div_reg = PCH_PP_DIVISOR;
3529 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03003530 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3531
3532 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3533 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3534 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3535 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07003536 }
Daniel Vetter67a54562012-10-20 20:57:45 +02003537
3538 /* Workaround: Need to write PP_CONTROL with the unlock key as
3539 * the very first thing. */
Jesse Barnes453c5422013-03-28 09:55:41 -07003540 pp = ironlake_get_pp_control(intel_dp);
Jani Nikulabf13e812013-09-06 07:40:05 +03003541 I915_WRITE(pp_ctrl_reg, pp);
Daniel Vetter67a54562012-10-20 20:57:45 +02003542
Jesse Barnes453c5422013-03-28 09:55:41 -07003543 pp_on = I915_READ(pp_on_reg);
3544 pp_off = I915_READ(pp_off_reg);
3545 pp_div = I915_READ(pp_div_reg);
Daniel Vetter67a54562012-10-20 20:57:45 +02003546
3547 /* Pull timing values out of registers */
3548 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3549 PANEL_POWER_UP_DELAY_SHIFT;
3550
3551 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3552 PANEL_LIGHT_ON_DELAY_SHIFT;
3553
3554 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3555 PANEL_LIGHT_OFF_DELAY_SHIFT;
3556
3557 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3558 PANEL_POWER_DOWN_DELAY_SHIFT;
3559
3560 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3561 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3562
3563 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3564 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3565
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003566 vbt = dev_priv->vbt.edp_pps;
Daniel Vetter67a54562012-10-20 20:57:45 +02003567
3568 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3569 * our hw here, which are all in 100usec. */
3570 spec.t1_t3 = 210 * 10;
3571 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3572 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3573 spec.t10 = 500 * 10;
3574 /* This one is special and actually in units of 100ms, but zero
3575 * based in the hw (so we need to add 100 ms). But the sw vbt
3576 * table multiplies it with 1000 to make it in units of 100usec,
3577 * too. */
3578 spec.t11_t12 = (510 + 100) * 10;
3579
3580 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3581 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3582
3583 /* Use the max of the register settings and vbt. If both are
3584 * unset, fall back to the spec limits. */
3585#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3586 spec.field : \
3587 max(cur.field, vbt.field))
3588 assign_final(t1_t3);
3589 assign_final(t8);
3590 assign_final(t9);
3591 assign_final(t10);
3592 assign_final(t11_t12);
3593#undef assign_final
3594
3595#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3596 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3597 intel_dp->backlight_on_delay = get_delay(t8);
3598 intel_dp->backlight_off_delay = get_delay(t9);
3599 intel_dp->panel_power_down_delay = get_delay(t10);
3600 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3601#undef get_delay
3602
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003603 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3604 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3605 intel_dp->panel_power_cycle_delay);
3606
3607 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3608 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3609
3610 if (out)
3611 *out = final;
3612}
3613
3614static void
3615intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3616 struct intel_dp *intel_dp,
3617 struct edp_power_seq *seq)
3618{
3619 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -07003620 u32 pp_on, pp_off, pp_div, port_sel = 0;
3621 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3622 int pp_on_reg, pp_off_reg, pp_div_reg;
3623
3624 if (HAS_PCH_SPLIT(dev)) {
3625 pp_on_reg = PCH_PP_ON_DELAYS;
3626 pp_off_reg = PCH_PP_OFF_DELAYS;
3627 pp_div_reg = PCH_PP_DIVISOR;
3628 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03003629 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3630
3631 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3632 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3633 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07003634 }
3635
Paulo Zanonib2f19d12013-12-19 14:29:44 -02003636 /*
3637 * And finally store the new values in the power sequencer. The
3638 * backlight delays are set to 1 because we do manual waits on them. For
3639 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3640 * we'll end up waiting for the backlight off delay twice: once when we
3641 * do the manual sleep, and once when we disable the panel and wait for
3642 * the PP_STATUS bit to become zero.
3643 */
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003644 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
Paulo Zanonib2f19d12013-12-19 14:29:44 -02003645 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3646 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003647 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
Daniel Vetter67a54562012-10-20 20:57:45 +02003648 /* Compute the divisor for the pp clock, simply match the Bspec
3649 * formula. */
Jesse Barnes453c5422013-03-28 09:55:41 -07003650 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003651 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
Daniel Vetter67a54562012-10-20 20:57:45 +02003652 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3653
3654 /* Haswell doesn't have any port selection bits for the panel
3655 * power sequencer any more. */
Imre Deakbc7d38a2013-05-16 14:40:36 +03003656 if (IS_VALLEYVIEW(dev)) {
Jani Nikulabf13e812013-09-06 07:40:05 +03003657 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3658 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3659 else
3660 port_sel = PANEL_PORT_SELECT_DPC_VLV;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003661 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3662 if (dp_to_dig_port(intel_dp)->port == PORT_A)
Jani Nikulaa24c1442013-09-05 16:44:46 +03003663 port_sel = PANEL_PORT_SELECT_DPA;
Daniel Vetter67a54562012-10-20 20:57:45 +02003664 else
Jani Nikulaa24c1442013-09-05 16:44:46 +03003665 port_sel = PANEL_PORT_SELECT_DPD;
Daniel Vetter67a54562012-10-20 20:57:45 +02003666 }
3667
Jesse Barnes453c5422013-03-28 09:55:41 -07003668 pp_on |= port_sel;
3669
3670 I915_WRITE(pp_on_reg, pp_on);
3671 I915_WRITE(pp_off_reg, pp_off);
3672 I915_WRITE(pp_div_reg, pp_div);
Daniel Vetter67a54562012-10-20 20:57:45 +02003673
Daniel Vetter67a54562012-10-20 20:57:45 +02003674 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07003675 I915_READ(pp_on_reg),
3676 I915_READ(pp_off_reg),
3677 I915_READ(pp_div_reg));
Keith Packardc8110e52009-05-06 11:51:10 -07003678}
3679
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05303680void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3681{
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_encoder *encoder;
3684 struct intel_dp *intel_dp = NULL;
3685 struct intel_crtc_config *config = NULL;
3686 struct intel_crtc *intel_crtc = NULL;
3687 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3688 u32 reg, val;
3689 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3690
3691 if (refresh_rate <= 0) {
3692 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3693 return;
3694 }
3695
3696 if (intel_connector == NULL) {
3697 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3698 return;
3699 }
3700
3701 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3702 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3703 return;
3704 }
3705
3706 encoder = intel_attached_encoder(&intel_connector->base);
3707 intel_dp = enc_to_intel_dp(&encoder->base);
3708 intel_crtc = encoder->new_crtc;
3709
3710 if (!intel_crtc) {
3711 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3712 return;
3713 }
3714
3715 config = &intel_crtc->config;
3716
3717 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3718 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3719 return;
3720 }
3721
3722 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3723 index = DRRS_LOW_RR;
3724
3725 if (index == intel_dp->drrs_state.refresh_rate_type) {
3726 DRM_DEBUG_KMS(
3727 "DRRS requested for previously set RR...ignoring\n");
3728 return;
3729 }
3730
3731 if (!intel_crtc->active) {
3732 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3733 return;
3734 }
3735
3736 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3737 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3738 val = I915_READ(reg);
3739 if (index > DRRS_HIGH_RR) {
3740 val |= PIPECONF_EDP_RR_MODE_SWITCH;
3741 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3742 } else {
3743 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3744 }
3745 I915_WRITE(reg, val);
3746 }
3747
3748 /*
3749 * mutex taken to ensure that there is no race between differnt
3750 * drrs calls trying to update refresh rate. This scenario may occur
3751 * in future when idleness detection based DRRS in kernel and
3752 * possible calls from user space to set differnt RR are made.
3753 */
3754
3755 mutex_lock(&intel_dp->drrs_state.mutex);
3756
3757 intel_dp->drrs_state.refresh_rate_type = index;
3758
3759 mutex_unlock(&intel_dp->drrs_state.mutex);
3760
3761 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3762}
3763
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05303764static struct drm_display_mode *
3765intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
3766 struct intel_connector *intel_connector,
3767 struct drm_display_mode *fixed_mode)
3768{
3769 struct drm_connector *connector = &intel_connector->base;
3770 struct intel_dp *intel_dp = &intel_dig_port->dp;
3771 struct drm_device *dev = intel_dig_port->base.base.dev;
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3773 struct drm_display_mode *downclock_mode = NULL;
3774
3775 if (INTEL_INFO(dev)->gen <= 6) {
3776 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3777 return NULL;
3778 }
3779
3780 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
3781 DRM_INFO("VBT doesn't support DRRS\n");
3782 return NULL;
3783 }
3784
3785 downclock_mode = intel_find_panel_downclock
3786 (dev, fixed_mode, connector);
3787
3788 if (!downclock_mode) {
3789 DRM_INFO("DRRS not supported\n");
3790 return NULL;
3791 }
3792
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05303793 dev_priv->drrs.connector = intel_connector;
3794
3795 mutex_init(&intel_dp->drrs_state.mutex);
3796
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05303797 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
3798
3799 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
3800 DRM_INFO("seamless DRRS supported for eDP panel.\n");
3801 return downclock_mode;
3802}
3803
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003804static bool intel_edp_init_connector(struct intel_dp *intel_dp,
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02003805 struct intel_connector *intel_connector,
3806 struct edp_power_seq *power_seq)
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003807{
3808 struct drm_connector *connector = &intel_connector->base;
3809 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Paulo Zanoni63635212014-04-22 19:55:42 -03003810 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3811 struct drm_device *dev = intel_encoder->base.dev;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct drm_display_mode *fixed_mode = NULL;
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05303814 struct drm_display_mode *downclock_mode = NULL;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003815 bool has_dpcd;
3816 struct drm_display_mode *scan;
3817 struct edid *edid;
3818
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05303819 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
3820
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003821 if (!is_edp(intel_dp))
3822 return true;
3823
Paulo Zanoni63635212014-04-22 19:55:42 -03003824 /* The VDD bit needs a power domain reference, so if the bit is already
3825 * enabled when we boot, grab this reference. */
3826 if (edp_have_panel_vdd(intel_dp)) {
3827 enum intel_display_power_domain power_domain;
3828 power_domain = intel_display_port_power_domain(intel_encoder);
3829 intel_display_power_get(dev_priv, power_domain);
3830 }
3831
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003832 /* Cache DPCD and EDID for edp. */
Jani Nikula24f3e092014-03-17 16:43:36 +02003833 intel_edp_panel_vdd_on(intel_dp);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003834 has_dpcd = intel_dp_get_dpcd(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01003835 edp_panel_vdd_off(intel_dp, false);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003836
3837 if (has_dpcd) {
3838 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3839 dev_priv->no_aux_handshake =
3840 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3841 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3842 } else {
3843 /* if this fails, presume the device is a ghost */
3844 DRM_INFO("failed to retrieve link info, disabling eDP\n");
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003845 return false;
3846 }
3847
3848 /* We now know it's not a ghost, init power sequence regs. */
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02003849 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003850
Daniel Vetter060c8772014-03-21 23:22:35 +01003851 mutex_lock(&dev->mode_config.mutex);
Jani Nikula0b998362014-03-14 16:51:17 +02003852 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003853 if (edid) {
3854 if (drm_add_edid_modes(connector, edid)) {
3855 drm_mode_connector_update_edid_property(connector,
3856 edid);
3857 drm_edid_to_eld(connector, edid);
3858 } else {
3859 kfree(edid);
3860 edid = ERR_PTR(-EINVAL);
3861 }
3862 } else {
3863 edid = ERR_PTR(-ENOENT);
3864 }
3865 intel_connector->edid = edid;
3866
3867 /* prefer fixed mode from EDID if available */
3868 list_for_each_entry(scan, &connector->probed_modes, head) {
3869 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3870 fixed_mode = drm_mode_duplicate(dev, scan);
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05303871 downclock_mode = intel_dp_drrs_init(
3872 intel_dig_port,
3873 intel_connector, fixed_mode);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003874 break;
3875 }
3876 }
3877
3878 /* fallback to VBT if available for eDP */
3879 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3880 fixed_mode = drm_mode_duplicate(dev,
3881 dev_priv->vbt.lfp_lvds_vbt_mode);
3882 if (fixed_mode)
3883 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3884 }
Daniel Vetter060c8772014-03-21 23:22:35 +01003885 mutex_unlock(&dev->mode_config.mutex);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003886
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05303887 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03003888 intel_panel_setup_backlight(connector);
3889
3890 return true;
3891}
3892
Paulo Zanoni16c25532013-06-12 17:27:25 -03003893bool
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003894intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3895 struct intel_connector *intel_connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003896{
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003897 struct drm_connector *connector = &intel_connector->base;
3898 struct intel_dp *intel_dp = &intel_dig_port->dp;
3899 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3900 struct drm_device *dev = intel_encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003901 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02003902 enum port port = intel_dig_port->port;
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02003903 struct edp_power_seq power_seq = { 0 };
Jani Nikula0b998362014-03-14 16:51:17 +02003904 int type;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003905
Damien Lespiauec5b01d2014-01-21 13:35:39 +00003906 /* intel_dp vfuncs */
3907 if (IS_VALLEYVIEW(dev))
3908 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3909 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3910 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3911 else if (HAS_PCH_SPLIT(dev))
3912 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3913 else
3914 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3915
Damien Lespiau153b1102014-01-21 13:37:15 +00003916 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3917
Daniel Vetter07679352012-09-06 22:15:42 +02003918 /* Preserve the current hw state. */
3919 intel_dp->DP = I915_READ(intel_dp->output_reg);
Jani Nikuladd06f902012-10-19 14:51:50 +03003920 intel_dp->attached_connector = intel_connector;
Chris Wilson3d3dc142011-02-12 10:33:12 +00003921
Ville Syrjälä3b32a352013-11-01 18:22:41 +02003922 if (intel_dp_is_edp(dev, port))
Gajanan Bhat19c03922012-09-27 19:13:07 +05303923 type = DRM_MODE_CONNECTOR_eDP;
Ville Syrjälä3b32a352013-11-01 18:22:41 +02003924 else
3925 type = DRM_MODE_CONNECTOR_DisplayPort;
Adam Jacksonb3295302010-07-16 14:46:28 -04003926
Imre Deakf7d24902013-05-08 13:14:05 +03003927 /*
3928 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3929 * for DP the encoder type can be set by the caller to
3930 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3931 */
3932 if (type == DRM_MODE_CONNECTOR_eDP)
3933 intel_encoder->type = INTEL_OUTPUT_EDP;
3934
Imre Deake7281ea2013-05-08 13:14:08 +03003935 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3936 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3937 port_name(port));
3938
Adam Jacksonb3295302010-07-16 14:46:28 -04003939 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003940 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3941
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02003942 connector->interlace_allowed = true;
3943 connector->doublescan_allowed = 0;
Ma Lingf8aed702009-08-24 13:50:24 +08003944
Daniel Vetter66a92782012-07-12 20:08:18 +02003945 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
Daniel Vetter4be73782014-01-17 14:39:48 +01003946 edp_panel_vdd_work);
Zhenyu Wang6251ec02010-01-12 05:38:32 +08003947
Chris Wilsondf0e9242010-09-09 16:20:55 +01003948 intel_connector_attach_encoder(intel_connector, intel_encoder);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003949 drm_sysfs_connector_add(connector);
3950
Paulo Zanoniaffa9352012-11-23 15:30:39 -02003951 if (HAS_DDI(dev))
Paulo Zanonibcbc8892012-10-26 19:05:51 -02003952 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3953 else
3954 intel_connector->get_hw_state = intel_connector_get_hw_state;
Imre Deak80f65de2014-02-11 17:12:49 +02003955 intel_connector->unregister = intel_dp_connector_unregister;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02003956
Jani Nikula0b998362014-03-14 16:51:17 +02003957 /* Set up the hotplug pin. */
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003958 switch (port) {
3959 case PORT_A:
Egbert Eich1d843f92013-02-25 12:06:49 -05003960 intel_encoder->hpd_pin = HPD_PORT_A;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003961 break;
3962 case PORT_B:
Egbert Eich1d843f92013-02-25 12:06:49 -05003963 intel_encoder->hpd_pin = HPD_PORT_B;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003964 break;
3965 case PORT_C:
Egbert Eich1d843f92013-02-25 12:06:49 -05003966 intel_encoder->hpd_pin = HPD_PORT_C;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003967 break;
3968 case PORT_D:
Egbert Eich1d843f92013-02-25 12:06:49 -05003969 intel_encoder->hpd_pin = HPD_PORT_D;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03003970 break;
3971 default:
Damien Lespiauad1c0b12013-03-07 15:30:28 +00003972 BUG();
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003973 }
3974
Imre Deakdada1a92014-01-29 13:25:41 +02003975 if (is_edp(intel_dp)) {
3976 intel_dp_init_panel_power_timestamps(intel_dp);
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02003977 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
Imre Deakdada1a92014-01-29 13:25:41 +02003978 }
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02003979
Jani Nikula9d1a1032014-03-14 16:51:15 +02003980 intel_dp_aux_init(intel_dp, intel_connector);
Dave Airliec1f05262012-08-30 11:06:18 +10003981
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03003982 intel_dp->psr_setup_done = false;
3983
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02003984 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
Jani Nikula0b998362014-03-14 16:51:17 +02003985 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03003986 if (is_edp(intel_dp)) {
3987 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3988 mutex_lock(&dev->mode_config.mutex);
Daniel Vetter4be73782014-01-17 14:39:48 +01003989 edp_panel_vdd_off_sync(intel_dp);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03003990 mutex_unlock(&dev->mode_config.mutex);
3991 }
Paulo Zanonib2f246a2013-06-12 17:27:26 -03003992 drm_sysfs_connector_remove(connector);
3993 drm_connector_cleanup(connector);
Paulo Zanoni16c25532013-06-12 17:27:25 -03003994 return false;
Paulo Zanonib2f246a2013-06-12 17:27:26 -03003995 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003996
Chris Wilsonf6849602010-09-19 09:29:33 +01003997 intel_dp_add_properties(intel_dp, connector);
3998
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003999 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4000 * 0xd. Failure to do so will result in spurious interrupts being
4001 * generated on the port when a cable is not attached.
4002 */
4003 if (IS_G4X(dev) && !IS_GM45(dev)) {
4004 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4005 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4006 }
Paulo Zanoni16c25532013-06-12 17:27:25 -03004007
4008 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004009}
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004010
4011void
4012intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4013{
4014 struct intel_digital_port *intel_dig_port;
4015 struct intel_encoder *intel_encoder;
4016 struct drm_encoder *encoder;
4017 struct intel_connector *intel_connector;
4018
Daniel Vetterb14c5672013-09-19 12:18:32 +02004019 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004020 if (!intel_dig_port)
4021 return;
4022
Daniel Vetterb14c5672013-09-19 12:18:32 +02004023 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004024 if (!intel_connector) {
4025 kfree(intel_dig_port);
4026 return;
4027 }
4028
4029 intel_encoder = &intel_dig_port->base;
4030 encoder = &intel_encoder->base;
4031
4032 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4033 DRM_MODE_ENCODER_TMDS);
4034
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004035 intel_encoder->compute_config = intel_dp_compute_config;
Daniel Vetterb934223d2013-07-21 21:37:05 +02004036 intel_encoder->mode_set = intel_dp_mode_set;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004037 intel_encoder->disable = intel_disable_dp;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004038 intel_encoder->get_hw_state = intel_dp_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07004039 intel_encoder->get_config = intel_dp_get_config;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004040 if (IS_VALLEYVIEW(dev)) {
Jani Nikulaecff4f32013-09-06 07:38:29 +03004041 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004042 intel_encoder->pre_enable = vlv_pre_enable_dp;
4043 intel_encoder->enable = vlv_enable_dp;
Ville Syrjälä49277c32014-03-31 18:21:26 +03004044 intel_encoder->post_disable = vlv_post_disable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004045 } else {
Jani Nikulaecff4f32013-09-06 07:38:29 +03004046 intel_encoder->pre_enable = g4x_pre_enable_dp;
4047 intel_encoder->enable = g4x_enable_dp;
Ville Syrjälä49277c32014-03-31 18:21:26 +03004048 intel_encoder->post_disable = g4x_post_disable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004049 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004050
Paulo Zanoni174edf12012-10-26 19:05:50 -02004051 intel_dig_port->port = port;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004052 intel_dig_port->dp.output_reg = output_reg;
4053
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004054 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004055 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Ville Syrjäläbc079e82014-03-03 16:15:28 +02004056 intel_encoder->cloneable = 0;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004057 intel_encoder->hot_plug = intel_dp_hot_plug;
4058
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004059 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4060 drm_encoder_cleanup(encoder);
4061 kfree(intel_dig_port);
Paulo Zanonib2f246a2013-06-12 17:27:26 -03004062 kfree(intel_connector);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004063 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004064}