Afzal Mohammed | 4730bcf | 2013-06-14 19:33:34 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | /* AM43x EPOS EVM */ |
| 10 | |
| 11 | /dts-v1/; |
| 12 | |
| 13 | #include "am4372.dtsi" |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 14 | #include <dt-bindings/pinctrl/am43xx.h> |
| 15 | #include <dt-bindings/gpio/gpio.h> |
Sourav Poddar | 2e3a938 | 2013-12-19 18:03:34 +0530 | [diff] [blame] | 16 | #include <dt-bindings/pwm/pwm.h> |
Afzal Mohammed | 4730bcf | 2013-06-14 19:33:34 +0530 | [diff] [blame] | 17 | |
| 18 | / { |
| 19 | model = "TI AM43x EPOS EVM"; |
| 20 | compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 21 | |
Tomi Valkeinen | 999c3f1 | 2014-05-02 13:54:21 +0300 | [diff] [blame] | 22 | aliases { |
| 23 | display0 = &lcd0; |
| 24 | }; |
| 25 | |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 26 | vmmcsd_fixed: fixedregulator-sd { |
| 27 | compatible = "regulator-fixed"; |
| 28 | regulator-name = "vmmcsd_fixed"; |
| 29 | regulator-min-microvolt = <3300000>; |
| 30 | regulator-max-microvolt = <3300000>; |
| 31 | enable-active-high; |
| 32 | }; |
| 33 | |
Tomi Valkeinen | 999c3f1 | 2014-05-02 13:54:21 +0300 | [diff] [blame] | 34 | lcd0: display { |
| 35 | compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; |
| 36 | label = "lcd"; |
| 37 | |
| 38 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&lcd_pins>; |
| 40 | |
| 41 | /* |
| 42 | * SelLCDorHDMI, LOW to select HDMI. This is not really the |
| 43 | * panel's enable GPIO, but we don't have HDMI driver support nor |
| 44 | * support to switch between two displays, so using this gpio as |
| 45 | * panel's enable should be safe. |
| 46 | */ |
| 47 | enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; |
| 48 | |
| 49 | panel-timing { |
| 50 | clock-frequency = <33000000>; |
| 51 | hactive = <800>; |
| 52 | vactive = <480>; |
| 53 | hfront-porch = <210>; |
| 54 | hback-porch = <16>; |
| 55 | hsync-len = <30>; |
| 56 | vback-porch = <10>; |
| 57 | vfront-porch = <22>; |
| 58 | vsync-len = <13>; |
| 59 | hsync-active = <0>; |
| 60 | vsync-active = <0>; |
| 61 | de-active = <1>; |
| 62 | pixelclk-active = <1>; |
| 63 | }; |
| 64 | |
| 65 | port { |
| 66 | lcd_in: endpoint { |
| 67 | remote-endpoint = <&dpi_out>; |
| 68 | }; |
| 69 | }; |
| 70 | }; |
| 71 | |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 72 | am43xx_pinmux: pinmux@44e10800 { |
| 73 | cpsw_default: cpsw_default { |
| 74 | pinctrl-single,pins = < |
| 75 | /* Slave 1 */ |
| 76 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ |
| 77 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ |
| 78 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ |
| 79 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ |
| 80 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ |
| 81 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ |
| 82 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ |
| 83 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ |
| 84 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ |
| 85 | >; |
| 86 | }; |
| 87 | |
| 88 | cpsw_sleep: cpsw_sleep { |
| 89 | pinctrl-single,pins = < |
| 90 | /* Slave 1 reset value */ |
| 91 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 92 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 93 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 94 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 95 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 96 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 97 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 98 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 99 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 100 | >; |
| 101 | }; |
| 102 | |
| 103 | davinci_mdio_default: davinci_mdio_default { |
| 104 | pinctrl-single,pins = < |
| 105 | /* MDIO */ |
| 106 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 107 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| 108 | >; |
| 109 | }; |
| 110 | |
| 111 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 112 | pinctrl-single,pins = < |
| 113 | /* MDIO reset value */ |
| 114 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 115 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 116 | >; |
| 117 | }; |
| 118 | |
| 119 | i2c0_pins: pinmux_i2c0_pins { |
| 120 | pinctrl-single,pins = < |
| 121 | 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 122 | 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| 123 | >; |
| 124 | }; |
Pekon Gupta | f68e355 | 2014-02-05 18:58:34 +0530 | [diff] [blame] | 125 | |
| 126 | nand_flash_x8: nand_flash_x8 { |
| 127 | pinctrl-single,pins = < |
| 128 | 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ |
| 129 | 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ |
| 130 | 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ |
| 131 | 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ |
| 132 | 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ |
| 133 | 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ |
| 134 | 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ |
| 135 | 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ |
| 136 | 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ |
| 137 | 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ |
| 138 | 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ |
| 139 | 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ |
| 140 | 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ |
| 141 | 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ |
| 142 | 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ |
| 143 | 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ |
| 144 | >; |
| 145 | }; |
Tony Lindgren | f777ba1 | 2014-03-02 14:22:03 -0800 | [diff] [blame] | 146 | |
Sourav Poddar | 2e3a938 | 2013-12-19 18:03:34 +0530 | [diff] [blame] | 147 | ecap0_pins: backlight_pins { |
| 148 | pinctrl-single,pins = < |
| 149 | 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ |
| 150 | >; |
| 151 | }; |
Sourav Poddar | 0aeaf1c | 2013-12-19 18:03:36 +0530 | [diff] [blame] | 152 | |
| 153 | i2c2_pins: pinmux_i2c2_pins { |
| 154 | pinctrl-single,pins = < |
| 155 | 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ |
| 156 | 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ |
| 157 | >; |
| 158 | }; |
Sourav Poddar | 416f3d5 | 2013-12-19 18:03:37 +0530 | [diff] [blame] | 159 | |
| 160 | spi0_pins: pinmux_spi0_pins { |
| 161 | pinctrl-single,pins = < |
| 162 | 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ |
| 163 | 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ |
| 164 | 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ |
| 165 | 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ |
| 166 | >; |
| 167 | }; |
| 168 | |
| 169 | spi1_pins: pinmux_spi1_pins { |
| 170 | pinctrl-single,pins = < |
| 171 | 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ |
| 172 | 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ |
| 173 | 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ |
| 174 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ |
| 175 | >; |
| 176 | }; |
Balaji T K | d2885db | 2014-03-03 20:20:20 +0530 | [diff] [blame] | 177 | |
| 178 | mmc1_pins: pinmux_mmc1_pins { |
| 179 | pinctrl-single,pins = < |
| 180 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
| 181 | >; |
| 182 | }; |
Sourav Poddar | 2a1a504 | 2014-04-28 19:12:30 +0530 | [diff] [blame] | 183 | |
| 184 | qspi1_default: qspi1_default { |
| 185 | pinctrl-single,pins = < |
| 186 | 0x7c (PIN_INPUT_PULLUP | MUX_MODE3) |
| 187 | 0x88 (PIN_INPUT_PULLUP | MUX_MODE2) |
| 188 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) |
| 189 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) |
| 190 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) |
| 191 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) |
| 192 | >; |
| 193 | }; |
Roger Quadros | 6cfcb5b | 2014-04-30 15:43:24 +0300 | [diff] [blame] | 194 | |
| 195 | pixcir_ts_pins: pixcir_ts_pins { |
| 196 | pinctrl-single,pins = < |
| 197 | 0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ |
| 198 | >; |
| 199 | }; |
Sourav Poddar | 741cac5 | 2014-05-08 11:30:07 +0530 | [diff] [blame] | 200 | |
| 201 | hdq_pins: pinmux_hdq_pins { |
| 202 | pinctrl-single,pins = < |
| 203 | 0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ |
| 204 | >; |
| 205 | }; |
Tomi Valkeinen | 999c3f1 | 2014-05-02 13:54:21 +0300 | [diff] [blame] | 206 | |
| 207 | dss_pins: dss_pins { |
| 208 | pinctrl-single,pins = < |
| 209 | 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ |
| 210 | 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) |
| 211 | 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) |
| 212 | 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1) |
| 213 | 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) |
| 214 | 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) |
| 215 | 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) |
| 216 | 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ |
| 217 | 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ |
| 218 | 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 219 | 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 220 | 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 221 | 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 222 | 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 223 | 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 224 | 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 225 | 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 226 | 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 227 | 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 228 | 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 229 | 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 230 | 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 231 | 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0) |
| 232 | 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ |
| 233 | 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ |
| 234 | 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ |
| 235 | 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ |
| 236 | 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ |
| 237 | >; |
| 238 | }; |
| 239 | |
| 240 | lcd_pins: lcd_pins { |
| 241 | pinctrl-single,pins = < |
| 242 | /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ |
| 243 | 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) |
| 244 | >; |
| 245 | }; |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 246 | }; |
| 247 | |
| 248 | matrix_keypad: matrix_keypad@0 { |
| 249 | compatible = "gpio-matrix-keypad"; |
| 250 | debounce-delay-ms = <5>; |
| 251 | col-scan-delay-us = <2>; |
| 252 | |
| 253 | row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ |
| 254 | &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ |
| 255 | &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ |
| 256 | &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ |
| 257 | |
| 258 | col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ |
| 259 | &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ |
| 260 | &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ |
| 261 | &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ |
| 262 | |
| 263 | linux,keymap = <0x00000201 /* P1 */ |
| 264 | 0x01000204 /* P4 */ |
| 265 | 0x02000207 /* P7 */ |
| 266 | 0x0300020a /* NUMERIC_STAR */ |
| 267 | 0x00010202 /* P2 */ |
| 268 | 0x01010205 /* P5 */ |
| 269 | 0x02010208 /* P8 */ |
| 270 | 0x03010200 /* P0 */ |
| 271 | 0x00020203 /* P3 */ |
| 272 | 0x01020206 /* P6 */ |
| 273 | 0x02020209 /* P9 */ |
| 274 | 0x0302020b /* NUMERIC_POUND */ |
| 275 | 0x00030067 /* UP */ |
| 276 | 0x0103006a /* RIGHT */ |
| 277 | 0x0203006c /* DOWN */ |
| 278 | 0x03030069>; /* LEFT */ |
| 279 | }; |
Sourav Poddar | 2e3a938 | 2013-12-19 18:03:34 +0530 | [diff] [blame] | 280 | |
| 281 | backlight { |
| 282 | compatible = "pwm-backlight"; |
| 283 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; |
| 284 | brightness-levels = <0 51 53 56 62 75 101 152 255>; |
| 285 | default-brightness-level = <8>; |
| 286 | }; |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | &mmc1 { |
| 290 | status = "okay"; |
| 291 | vmmc-supply = <&vmmcsd_fixed>; |
| 292 | bus-width = <4>; |
Balaji T K | d2885db | 2014-03-03 20:20:20 +0530 | [diff] [blame] | 293 | pinctrl-names = "default"; |
| 294 | pinctrl-0 = <&mmc1_pins>; |
| 295 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 296 | }; |
| 297 | |
| 298 | &mac { |
| 299 | pinctrl-names = "default", "sleep"; |
| 300 | pinctrl-0 = <&cpsw_default>; |
| 301 | pinctrl-1 = <&cpsw_sleep>; |
| 302 | status = "okay"; |
| 303 | }; |
| 304 | |
| 305 | &davinci_mdio { |
| 306 | pinctrl-names = "default", "sleep"; |
| 307 | pinctrl-0 = <&davinci_mdio_default>; |
| 308 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 309 | status = "okay"; |
| 310 | }; |
| 311 | |
| 312 | &cpsw_emac0 { |
| 313 | phy_id = <&davinci_mdio>, <16>; |
| 314 | phy-mode = "rmii"; |
| 315 | }; |
| 316 | |
| 317 | &cpsw_emac1 { |
| 318 | phy_id = <&davinci_mdio>, <1>; |
| 319 | phy-mode = "rmii"; |
| 320 | }; |
| 321 | |
George Cherian | fe79755 | 2014-06-06 11:47:34 +0530 | [diff] [blame] | 322 | &phy_sel { |
| 323 | rmii-clock-ext; |
| 324 | }; |
| 325 | |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 326 | &i2c0 { |
| 327 | status = "okay"; |
| 328 | pinctrl-names = "default"; |
| 329 | pinctrl-0 = <&i2c0_pins>; |
Keerthy | 497d64a | 2014-07-09 11:06:30 +0530 | [diff] [blame] | 330 | clock-frequency = <400000>; |
| 331 | |
| 332 | tps65218: tps65218@24 { |
| 333 | reg = <0x24>; |
| 334 | compatible = "ti,tps65218"; |
| 335 | interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ |
| 336 | interrupt-parent = <&gic>; |
| 337 | interrupt-controller; |
| 338 | #interrupt-cells = <2>; |
| 339 | |
| 340 | dcdc1: regulator-dcdc1 { |
| 341 | compatible = "ti,tps65218-dcdc1"; |
| 342 | regulator-name = "vdd_core"; |
| 343 | regulator-min-microvolt = <912000>; |
| 344 | regulator-max-microvolt = <1144000>; |
| 345 | regulator-boot-on; |
| 346 | regulator-always-on; |
| 347 | }; |
| 348 | |
| 349 | dcdc2: regulator-dcdc2 { |
| 350 | compatible = "ti,tps65218-dcdc2"; |
| 351 | regulator-name = "vdd_mpu"; |
| 352 | regulator-min-microvolt = <912000>; |
| 353 | regulator-max-microvolt = <1378000>; |
| 354 | regulator-boot-on; |
| 355 | regulator-always-on; |
| 356 | }; |
| 357 | |
| 358 | dcdc3: regulator-dcdc3 { |
| 359 | compatible = "ti,tps65218-dcdc3"; |
| 360 | regulator-name = "vdcdc3"; |
| 361 | regulator-min-microvolt = <1350000>; |
| 362 | regulator-max-microvolt = <1350000>; |
| 363 | regulator-boot-on; |
| 364 | regulator-always-on; |
| 365 | }; |
| 366 | |
| 367 | dcdc5: regulator-dcdc5 { |
| 368 | compatible = "ti,tps65218-dcdc5"; |
| 369 | regulator-name = "v1_0bat"; |
| 370 | regulator-min-microvolt = <1000000>; |
| 371 | regulator-max-microvolt = <1000000>; |
| 372 | }; |
| 373 | |
| 374 | dcdc6: regulator-dcdc6 { |
| 375 | compatible = "ti,tps65218-dcdc6"; |
| 376 | regulator-name = "v1_8bat"; |
| 377 | regulator-min-microvolt = <1800000>; |
| 378 | regulator-max-microvolt = <1800000>; |
| 379 | }; |
| 380 | |
| 381 | ldo1: regulator-ldo1 { |
| 382 | compatible = "ti,tps65218-ldo1"; |
| 383 | regulator-min-microvolt = <1800000>; |
| 384 | regulator-max-microvolt = <1800000>; |
| 385 | regulator-boot-on; |
| 386 | regulator-always-on; |
| 387 | }; |
| 388 | }; |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 389 | |
| 390 | at24@50 { |
| 391 | compatible = "at24,24c256"; |
| 392 | pagesize = <64>; |
| 393 | reg = <0x50>; |
| 394 | }; |
| 395 | |
| 396 | pixcir_ts@5c { |
Roger Quadros | 6cfcb5b | 2014-04-30 15:43:24 +0300 | [diff] [blame] | 397 | compatible = "pixcir,pixcir_tangoc"; |
| 398 | pinctrl-names = "default"; |
| 399 | pinctrl-0 = <&pixcir_ts_pins>; |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 400 | reg = <0x5c>; |
| 401 | interrupt-parent = <&gpio1>; |
| 402 | interrupts = <17 0>; |
| 403 | |
| 404 | attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; |
| 405 | |
Roger Quadros | 342666c | 2014-07-28 10:10:58 -0700 | [diff] [blame] | 406 | touchscreen-size-x = <1024>; |
| 407 | touchscreen-size-y = <600>; |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 408 | }; |
| 409 | }; |
| 410 | |
Sourav Poddar | 0aeaf1c | 2013-12-19 18:03:36 +0530 | [diff] [blame] | 411 | &i2c2 { |
| 412 | pinctrl-names = "default"; |
| 413 | pinctrl-0 = <&i2c2_pins>; |
| 414 | status = "okay"; |
| 415 | }; |
| 416 | |
Mugunthan V N | e54686e | 2013-10-11 00:44:54 +0530 | [diff] [blame] | 417 | &gpio0 { |
| 418 | status = "okay"; |
| 419 | }; |
| 420 | |
| 421 | &gpio1 { |
| 422 | status = "okay"; |
| 423 | }; |
| 424 | |
| 425 | &gpio2 { |
| 426 | status = "okay"; |
| 427 | }; |
| 428 | |
| 429 | &gpio3 { |
| 430 | status = "okay"; |
Afzal Mohammed | 4730bcf | 2013-06-14 19:33:34 +0530 | [diff] [blame] | 431 | }; |
Pekon Gupta | f68e355 | 2014-02-05 18:58:34 +0530 | [diff] [blame] | 432 | |
| 433 | &elm { |
| 434 | status = "okay"; |
| 435 | }; |
| 436 | |
| 437 | &gpmc { |
Roger Quadros | 331bbb5 | 2014-09-02 16:57:07 +0300 | [diff] [blame] | 438 | status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ |
Pekon Gupta | f68e355 | 2014-02-05 18:58:34 +0530 | [diff] [blame] | 439 | pinctrl-names = "default"; |
| 440 | pinctrl-0 = <&nand_flash_x8>; |
| 441 | ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ |
| 442 | nand@0,0 { |
| 443 | reg = <0 0 0>; /* CS0, offset 0 */ |
Roger Quadros | db01e6c | 2014-09-02 16:57:02 +0300 | [diff] [blame] | 444 | ti,nand-ecc-opt = "bch16"; |
Pekon Gupta | f68e355 | 2014-02-05 18:58:34 +0530 | [diff] [blame] | 445 | ti,elm-id = <&elm>; |
| 446 | nand-bus-width = <8>; |
| 447 | gpmc,device-width = <1>; |
| 448 | gpmc,sync-clk-ps = <0>; |
| 449 | gpmc,cs-on-ns = <0>; |
| 450 | gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ |
| 451 | gpmc,cs-wr-off-ns = <40>; |
| 452 | gpmc,adv-on-ns = <0>; /* cs-on-ns */ |
| 453 | gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ |
| 454 | gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ |
| 455 | gpmc,we-on-ns = <0>; /* cs-on-ns */ |
| 456 | gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ |
| 457 | gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ |
| 458 | gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ |
| 459 | gpmc,access-ns = <30>; /* tCEA + 4*/ |
| 460 | gpmc,rd-cycle-ns = <40>; |
| 461 | gpmc,wr-cycle-ns = <40>; |
Roger Quadros | e47acd9 | 2014-09-02 16:57:05 +0300 | [diff] [blame] | 462 | gpmc,wait-pin = <0>; |
Pekon Gupta | f68e355 | 2014-02-05 18:58:34 +0530 | [diff] [blame] | 463 | gpmc,bus-turnaround-ns = <0>; |
| 464 | gpmc,cycle2cycle-delay-ns = <0>; |
| 465 | gpmc,clk-activation-ns = <0>; |
| 466 | gpmc,wait-monitoring-ns = <0>; |
| 467 | gpmc,wr-access-ns = <40>; |
| 468 | gpmc,wr-data-mux-bus-ns = <0>; |
| 469 | /* MTD partition table */ |
| 470 | /* All SPL-* partitions are sized to minimal length |
| 471 | * which can be independently programmable. For |
| 472 | * NAND flash this is equal to size of erase-block */ |
| 473 | #address-cells = <1>; |
| 474 | #size-cells = <1>; |
| 475 | partition@0 { |
| 476 | label = "NAND.SPL"; |
| 477 | reg = <0x00000000 0x00040000>; |
| 478 | }; |
| 479 | partition@1 { |
| 480 | label = "NAND.SPL.backup1"; |
| 481 | reg = <0x00040000 0x00040000>; |
| 482 | }; |
| 483 | partition@2 { |
| 484 | label = "NAND.SPL.backup2"; |
| 485 | reg = <0x00080000 0x00040000>; |
| 486 | }; |
| 487 | partition@3 { |
| 488 | label = "NAND.SPL.backup3"; |
| 489 | reg = <0x000C0000 0x00040000>; |
| 490 | }; |
| 491 | partition@4 { |
| 492 | label = "NAND.u-boot-spl-os"; |
| 493 | reg = <0x00100000 0x00080000>; |
| 494 | }; |
| 495 | partition@5 { |
| 496 | label = "NAND.u-boot"; |
| 497 | reg = <0x00180000 0x00100000>; |
| 498 | }; |
| 499 | partition@6 { |
| 500 | label = "NAND.u-boot-env"; |
| 501 | reg = <0x00280000 0x00040000>; |
| 502 | }; |
| 503 | partition@7 { |
| 504 | label = "NAND.u-boot-env.backup1"; |
| 505 | reg = <0x002C0000 0x00040000>; |
| 506 | }; |
| 507 | partition@8 { |
| 508 | label = "NAND.kernel"; |
| 509 | reg = <0x00300000 0x00700000>; |
| 510 | }; |
| 511 | partition@9 { |
| 512 | label = "NAND.file-system"; |
Pekon Gupta | c4de4ec | 2014-05-19 14:45:48 +0530 | [diff] [blame] | 513 | reg = <0x00a00000 0x1f600000>; |
Pekon Gupta | f68e355 | 2014-02-05 18:58:34 +0530 | [diff] [blame] | 514 | }; |
| 515 | }; |
| 516 | }; |
Tony Lindgren | f777ba1 | 2014-03-02 14:22:03 -0800 | [diff] [blame] | 517 | |
Sourav Poddar | 2e3a938 | 2013-12-19 18:03:34 +0530 | [diff] [blame] | 518 | &epwmss0 { |
| 519 | status = "okay"; |
| 520 | }; |
| 521 | |
| 522 | &ecap0 { |
| 523 | status = "okay"; |
| 524 | pinctrl-names = "default"; |
| 525 | pinctrl-0 = <&ecap0_pins>; |
| 526 | }; |
Sourav Poddar | 416f3d5 | 2013-12-19 18:03:37 +0530 | [diff] [blame] | 527 | |
| 528 | &spi0 { |
| 529 | pinctrl-names = "default"; |
| 530 | pinctrl-0 = <&spi0_pins>; |
| 531 | status = "okay"; |
| 532 | }; |
| 533 | |
| 534 | &spi1 { |
| 535 | pinctrl-names = "default"; |
| 536 | pinctrl-0 = <&spi1_pins>; |
| 537 | status = "okay"; |
| 538 | }; |
George Cherian | 61d5924 | 2014-03-19 15:40:03 +0530 | [diff] [blame] | 539 | |
| 540 | &usb2_phy1 { |
| 541 | status = "okay"; |
| 542 | }; |
| 543 | |
| 544 | &usb1 { |
| 545 | dr_mode = "peripheral"; |
| 546 | status = "okay"; |
| 547 | }; |
| 548 | |
| 549 | &usb2_phy2 { |
| 550 | status = "okay"; |
| 551 | }; |
| 552 | |
| 553 | &usb2 { |
| 554 | dr_mode = "host"; |
| 555 | status = "okay"; |
| 556 | }; |
Sourav Poddar | 2a1a504 | 2014-04-28 19:12:30 +0530 | [diff] [blame] | 557 | |
| 558 | &qspi { |
Roger Quadros | 331bbb5 | 2014-09-02 16:57:07 +0300 | [diff] [blame] | 559 | status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ |
Sourav Poddar | 2a1a504 | 2014-04-28 19:12:30 +0530 | [diff] [blame] | 560 | pinctrl-names = "default"; |
| 561 | pinctrl-0 = <&qspi1_default>; |
| 562 | |
| 563 | spi-max-frequency = <48000000>; |
| 564 | m25p80@0 { |
| 565 | compatible = "mx66l51235l"; |
| 566 | spi-max-frequency = <48000000>; |
| 567 | reg = <0>; |
| 568 | spi-cpol; |
| 569 | spi-cpha; |
| 570 | spi-tx-bus-width = <1>; |
| 571 | spi-rx-bus-width = <4>; |
| 572 | #address-cells = <1>; |
| 573 | #size-cells = <1>; |
| 574 | |
| 575 | /* MTD partition table. |
| 576 | * The ROM checks the first 512KiB |
| 577 | * for a valid file to boot(XIP). |
| 578 | */ |
| 579 | partition@0 { |
| 580 | label = "QSPI.U_BOOT"; |
| 581 | reg = <0x00000000 0x000080000>; |
| 582 | }; |
| 583 | partition@1 { |
| 584 | label = "QSPI.U_BOOT.backup"; |
| 585 | reg = <0x00080000 0x00080000>; |
| 586 | }; |
| 587 | partition@2 { |
| 588 | label = "QSPI.U-BOOT-SPL_OS"; |
| 589 | reg = <0x00100000 0x00010000>; |
| 590 | }; |
| 591 | partition@3 { |
| 592 | label = "QSPI.U_BOOT_ENV"; |
| 593 | reg = <0x00110000 0x00010000>; |
| 594 | }; |
| 595 | partition@4 { |
| 596 | label = "QSPI.U-BOOT-ENV.backup"; |
| 597 | reg = <0x00120000 0x00010000>; |
| 598 | }; |
| 599 | partition@5 { |
| 600 | label = "QSPI.KERNEL"; |
| 601 | reg = <0x00130000 0x0800000>; |
| 602 | }; |
| 603 | partition@6 { |
| 604 | label = "QSPI.FILESYSTEM"; |
| 605 | reg = <0x00930000 0x36D0000>; |
| 606 | }; |
| 607 | }; |
| 608 | }; |
Sourav Poddar | 741cac5 | 2014-05-08 11:30:07 +0530 | [diff] [blame] | 609 | |
| 610 | &hdq { |
| 611 | status = "okay"; |
| 612 | pinctrl-names = "default"; |
| 613 | pinctrl-0 = <&hdq_pins>; |
| 614 | }; |
Tomi Valkeinen | 999c3f1 | 2014-05-02 13:54:21 +0300 | [diff] [blame] | 615 | |
| 616 | &dss { |
| 617 | status = "ok"; |
| 618 | |
| 619 | pinctrl-names = "default"; |
| 620 | pinctrl-0 = <&dss_pins>; |
| 621 | |
| 622 | port { |
| 623 | dpi_out: endpoint@0 { |
| 624 | remote-endpoint = <&lcd_in>; |
| 625 | data-lines = <24>; |
| 626 | }; |
| 627 | }; |
| 628 | }; |