Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> |
| 3 | * |
| 4 | * This file is licensed under the terms of the GNU General Public |
| 5 | * License version 2. This program is licensed "as is" without any |
| 6 | * warranty of any kind, whether express or implied. |
| 7 | */ |
| 8 | |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 9 | #include <dt-bindings/clock/berlin2q.h> |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | |
| 12 | #include "skeleton.dtsi" |
| 13 | |
| 14 | / { |
| 15 | model = "Marvell Armada 1500 pro (BG2-Q) SoC"; |
| 16 | compatible = "marvell,berlin2q", "marvell,berlin"; |
| 17 | |
| 18 | cpus { |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <0>; |
Antoine Ténart | d19c936 | 2014-06-04 18:03:46 +0200 | [diff] [blame] | 21 | enable-method = "marvell,berlin-smp"; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 22 | |
| 23 | cpu@0 { |
| 24 | compatible = "arm,cortex-a9"; |
| 25 | device_type = "cpu"; |
| 26 | next-level-cache = <&l2>; |
| 27 | reg = <0>; |
| 28 | }; |
| 29 | |
| 30 | cpu@1 { |
| 31 | compatible = "arm,cortex-a9"; |
| 32 | device_type = "cpu"; |
| 33 | next-level-cache = <&l2>; |
| 34 | reg = <1>; |
| 35 | }; |
| 36 | |
| 37 | cpu@2 { |
| 38 | compatible = "arm,cortex-a9"; |
| 39 | device_type = "cpu"; |
| 40 | next-level-cache = <&l2>; |
| 41 | reg = <2>; |
| 42 | }; |
| 43 | |
| 44 | cpu@3 { |
| 45 | compatible = "arm,cortex-a9"; |
| 46 | device_type = "cpu"; |
| 47 | next-level-cache = <&l2>; |
| 48 | reg = <3>; |
| 49 | }; |
| 50 | }; |
| 51 | |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 52 | refclk: oscillator { |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 53 | compatible = "fixed-clock"; |
| 54 | #clock-cells = <0>; |
| 55 | clock-frequency = <25000000>; |
| 56 | }; |
| 57 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 58 | soc { |
| 59 | compatible = "simple-bus"; |
| 60 | #address-cells = <1>; |
| 61 | #size-cells = <1>; |
| 62 | |
| 63 | ranges = <0 0xf7000000 0x1000000>; |
| 64 | interrupt-parent = <&gic>; |
| 65 | |
Antoine Tenart | 0d859a6 | 2014-05-19 22:03:00 +0200 | [diff] [blame] | 66 | sdhci0: sdhci@ab0000 { |
| 67 | compatible = "mrvl,pxav3-mmc"; |
| 68 | reg = <0xab0000 0x200>; |
| 69 | clocks = <&chip CLKID_SDIO1XIN>; |
| 70 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 71 | status = "disabled"; |
| 72 | }; |
| 73 | |
| 74 | sdhci1: sdhci@ab0800 { |
| 75 | compatible = "mrvl,pxav3-mmc"; |
| 76 | reg = <0xab0800 0x200>; |
| 77 | clocks = <&chip CLKID_SDIO1XIN>; |
| 78 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 79 | status = "disabled"; |
| 80 | }; |
| 81 | |
| 82 | sdhci2: sdhci@ab1000 { |
| 83 | compatible = "mrvl,pxav3-mmc"; |
| 84 | reg = <0xab1000 0x200>; |
| 85 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 86 | clocks = <&chip CLKID_SDIO1XIN>; |
| 87 | status = "disabled"; |
| 88 | }; |
| 89 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 90 | l2: l2-cache-controller@ac0000 { |
| 91 | compatible = "arm,pl310-cache"; |
| 92 | reg = <0xac0000 0x1000>; |
| 93 | cache-level = <2>; |
Jisheng Zhang | 44991eb | 2014-06-12 17:38:40 +0800 | [diff] [blame] | 94 | arm,data-latency = <2 2 2>; |
| 95 | arm,tag-latency = <2 2 2>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 96 | }; |
| 97 | |
Sebastian Hesselbarth | 0bd4b34 | 2014-03-13 13:32:34 +0100 | [diff] [blame] | 98 | scu: snoop-control-unit@ad0000 { |
| 99 | compatible = "arm,cortex-a9-scu"; |
| 100 | reg = <0xad0000 0x58>; |
| 101 | }; |
| 102 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 103 | local-timer@ad0600 { |
| 104 | compatible = "arm,cortex-a9-twd-timer"; |
| 105 | reg = <0xad0600 0x20>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 106 | clocks = <&chip CLKID_TWD>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 107 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 108 | }; |
| 109 | |
| 110 | gic: interrupt-controller@ad1000 { |
| 111 | compatible = "arm,cortex-a9-gic"; |
| 112 | reg = <0xad1000 0x1000>, <0xad0100 0x100>; |
| 113 | interrupt-controller; |
| 114 | #interrupt-cells = <3>; |
| 115 | }; |
| 116 | |
Antoine Ténart | bdc06cd | 2014-09-30 16:28:15 +0200 | [diff] [blame] | 117 | eth0: ethernet@b90000 { |
| 118 | compatible = "marvell,pxa168-eth"; |
| 119 | reg = <0xb90000 0x10000>; |
| 120 | clocks = <&chip CLKID_GETH0>; |
| 121 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| 122 | /* set by bootloader */ |
| 123 | local-mac-address = [00 00 00 00 00 00]; |
| 124 | #address-cells = <1>; |
| 125 | #size-cells = <0>; |
| 126 | phy-handle = <ðphy0>; |
| 127 | status = "disabled"; |
| 128 | |
| 129 | ethphy0: ethernet-phy@0 { |
| 130 | reg = <0>; |
| 131 | }; |
| 132 | }; |
| 133 | |
Antoine Ténart | d19c936 | 2014-06-04 18:03:46 +0200 | [diff] [blame] | 134 | cpu-ctrl@dd0000 { |
| 135 | compatible = "marvell,berlin-cpu-ctrl"; |
| 136 | reg = <0xdd0000 0x10000>; |
| 137 | }; |
| 138 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 139 | apb@e80000 { |
| 140 | compatible = "simple-bus"; |
| 141 | #address-cells = <1>; |
| 142 | #size-cells = <1>; |
| 143 | |
| 144 | ranges = <0 0xe80000 0x10000>; |
| 145 | interrupt-parent = <&aic>; |
| 146 | |
Antoine Tenart | cedf57f | 2014-04-16 21:18:41 +0200 | [diff] [blame] | 147 | gpio0: gpio@0400 { |
| 148 | compatible = "snps,dw-apb-gpio"; |
| 149 | reg = <0x0400 0x400>; |
| 150 | #address-cells = <1>; |
| 151 | #size-cells = <0>; |
| 152 | |
| 153 | porta: gpio-port@0 { |
| 154 | compatible = "snps,dw-apb-gpio-port"; |
| 155 | gpio-controller; |
| 156 | #gpio-cells = <2>; |
| 157 | snps,nr-gpios = <32>; |
| 158 | reg = <0>; |
| 159 | interrupt-controller; |
| 160 | #interrupt-cells = <2>; |
| 161 | interrupts = <0>; |
| 162 | }; |
| 163 | }; |
| 164 | |
| 165 | gpio1: gpio@0800 { |
| 166 | compatible = "snps,dw-apb-gpio"; |
| 167 | reg = <0x0800 0x400>; |
| 168 | #address-cells = <1>; |
| 169 | #size-cells = <0>; |
| 170 | |
| 171 | portb: gpio-port@1 { |
| 172 | compatible = "snps,dw-apb-gpio-port"; |
| 173 | gpio-controller; |
| 174 | #gpio-cells = <2>; |
| 175 | snps,nr-gpios = <32>; |
| 176 | reg = <0>; |
| 177 | interrupt-controller; |
| 178 | #interrupt-cells = <2>; |
| 179 | interrupts = <1>; |
| 180 | }; |
| 181 | }; |
| 182 | |
| 183 | gpio2: gpio@0c00 { |
| 184 | compatible = "snps,dw-apb-gpio"; |
| 185 | reg = <0x0c00 0x400>; |
| 186 | #address-cells = <1>; |
| 187 | #size-cells = <0>; |
| 188 | |
| 189 | portc: gpio-port@2 { |
| 190 | compatible = "snps,dw-apb-gpio-port"; |
| 191 | gpio-controller; |
| 192 | #gpio-cells = <2>; |
| 193 | snps,nr-gpios = <32>; |
| 194 | reg = <0>; |
| 195 | interrupt-controller; |
| 196 | #interrupt-cells = <2>; |
| 197 | interrupts = <2>; |
| 198 | }; |
| 199 | }; |
| 200 | |
| 201 | gpio3: gpio@1000 { |
| 202 | compatible = "snps,dw-apb-gpio"; |
| 203 | reg = <0x1000 0x400>; |
| 204 | #address-cells = <1>; |
| 205 | #size-cells = <0>; |
| 206 | |
| 207 | portd: gpio-port@3 { |
| 208 | compatible = "snps,dw-apb-gpio-port"; |
| 209 | gpio-controller; |
| 210 | #gpio-cells = <2>; |
| 211 | snps,nr-gpios = <32>; |
| 212 | reg = <0>; |
| 213 | interrupt-controller; |
| 214 | #interrupt-cells = <2>; |
| 215 | interrupts = <3>; |
| 216 | }; |
| 217 | }; |
| 218 | |
Antoine Ténart | 99f3deb | 2014-06-03 09:33:09 +0200 | [diff] [blame] | 219 | i2c0: i2c@1400 { |
| 220 | compatible = "snps,designware-i2c"; |
| 221 | #address-cells = <1>; |
| 222 | #size-cells = <0>; |
| 223 | reg = <0x1400 0x100>; |
| 224 | interrupt-parent = <&aic>; |
| 225 | interrupts = <4>; |
| 226 | clocks = <&chip CLKID_CFG>; |
| 227 | pinctrl-0 = <&twsi0_pmux>; |
| 228 | pinctrl-names = "default"; |
| 229 | status = "disabled"; |
| 230 | }; |
| 231 | |
| 232 | i2c1: i2c@1800 { |
| 233 | compatible = "snps,designware-i2c"; |
| 234 | #address-cells = <1>; |
| 235 | #size-cells = <0>; |
| 236 | reg = <0x1800 0x100>; |
| 237 | interrupt-parent = <&aic>; |
| 238 | interrupts = <5>; |
| 239 | clocks = <&chip CLKID_CFG>; |
| 240 | pinctrl-0 = <&twsi1_pmux>; |
| 241 | pinctrl-names = "default"; |
| 242 | status = "disabled"; |
| 243 | }; |
| 244 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 245 | timer0: timer@2c00 { |
| 246 | compatible = "snps,dw-apb-timer"; |
| 247 | reg = <0x2c00 0x14>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 248 | clocks = <&chip CLKID_CFG>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 249 | clock-names = "timer"; |
| 250 | interrupts = <8>; |
| 251 | }; |
| 252 | |
| 253 | timer1: timer@2c14 { |
| 254 | compatible = "snps,dw-apb-timer"; |
| 255 | reg = <0x2c14 0x14>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 256 | clocks = <&chip CLKID_CFG>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 257 | clock-names = "timer"; |
| 258 | status = "disabled"; |
| 259 | }; |
| 260 | |
| 261 | timer2: timer@2c28 { |
| 262 | compatible = "snps,dw-apb-timer"; |
| 263 | reg = <0x2c28 0x14>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 264 | clocks = <&chip CLKID_CFG>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 265 | clock-names = "timer"; |
| 266 | status = "disabled"; |
| 267 | }; |
| 268 | |
| 269 | timer3: timer@2c3c { |
| 270 | compatible = "snps,dw-apb-timer"; |
| 271 | reg = <0x2c3c 0x14>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 272 | clocks = <&chip CLKID_CFG>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 273 | clock-names = "timer"; |
| 274 | status = "disabled"; |
| 275 | }; |
| 276 | |
| 277 | timer4: timer@2c50 { |
| 278 | compatible = "snps,dw-apb-timer"; |
| 279 | reg = <0x2c50 0x14>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 280 | clocks = <&chip CLKID_CFG>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 281 | clock-names = "timer"; |
| 282 | status = "disabled"; |
| 283 | }; |
| 284 | |
| 285 | timer5: timer@2c64 { |
| 286 | compatible = "snps,dw-apb-timer"; |
| 287 | reg = <0x2c64 0x14>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 288 | clocks = <&chip CLKID_CFG>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 289 | clock-names = "timer"; |
| 290 | status = "disabled"; |
| 291 | }; |
| 292 | |
| 293 | timer6: timer@2c78 { |
| 294 | compatible = "snps,dw-apb-timer"; |
| 295 | reg = <0x2c78 0x14>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 296 | clocks = <&chip CLKID_CFG>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 297 | clock-names = "timer"; |
| 298 | status = "disabled"; |
| 299 | }; |
| 300 | |
| 301 | timer7: timer@2c8c { |
| 302 | compatible = "snps,dw-apb-timer"; |
| 303 | reg = <0x2c8c 0x14>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 304 | clocks = <&chip CLKID_CFG>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 305 | clock-names = "timer"; |
| 306 | status = "disabled"; |
| 307 | }; |
| 308 | |
| 309 | aic: interrupt-controller@3800 { |
| 310 | compatible = "snps,dw-apb-ictl"; |
| 311 | reg = <0x3800 0x30>; |
| 312 | interrupt-controller; |
| 313 | #interrupt-cells = <1>; |
| 314 | interrupt-parent = <&gic>; |
| 315 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| 316 | }; |
Antoine Tenart | cedf57f | 2014-04-16 21:18:41 +0200 | [diff] [blame] | 317 | |
| 318 | gpio4: gpio@5000 { |
| 319 | compatible = "snps,dw-apb-gpio"; |
| 320 | reg = <0x5000 0x400>; |
| 321 | #address-cells = <1>; |
| 322 | #size-cells = <0>; |
| 323 | |
| 324 | porte: gpio-port@4 { |
| 325 | compatible = "snps,dw-apb-gpio-port"; |
| 326 | gpio-controller; |
| 327 | #gpio-cells = <2>; |
| 328 | snps,nr-gpios = <32>; |
| 329 | reg = <0>; |
| 330 | }; |
| 331 | }; |
| 332 | |
| 333 | gpio5: gpio@c000 { |
| 334 | compatible = "snps,dw-apb-gpio"; |
| 335 | reg = <0xc000 0x400>; |
| 336 | #address-cells = <1>; |
| 337 | #size-cells = <0>; |
| 338 | |
| 339 | portf: gpio-port@5 { |
| 340 | compatible = "snps,dw-apb-gpio-port"; |
| 341 | gpio-controller; |
| 342 | #gpio-cells = <2>; |
| 343 | snps,nr-gpios = <32>; |
| 344 | reg = <0>; |
| 345 | }; |
| 346 | }; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 347 | }; |
| 348 | |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 349 | chip: chip-control@ea0000 { |
| 350 | compatible = "marvell,berlin2q-chip-ctrl"; |
| 351 | #clock-cells = <1>; |
| 352 | reg = <0xea0000 0x400>, <0xdd0170 0x10>; |
| 353 | clocks = <&refclk>; |
| 354 | clock-names = "refclk"; |
Antoine Ténart | 99f3deb | 2014-06-03 09:33:09 +0200 | [diff] [blame] | 355 | |
| 356 | twsi0_pmux: twsi0-pmux { |
| 357 | groups = "G6"; |
| 358 | function = "twsi0"; |
| 359 | }; |
| 360 | |
| 361 | twsi1_pmux: twsi1-pmux { |
| 362 | groups = "G7"; |
| 363 | function = "twsi1"; |
| 364 | }; |
Sebastian Hesselbarth | 0bd4b34 | 2014-03-13 13:32:34 +0100 | [diff] [blame] | 365 | }; |
| 366 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 367 | apb@fc0000 { |
| 368 | compatible = "simple-bus"; |
| 369 | #address-cells = <1>; |
| 370 | #size-cells = <1>; |
| 371 | |
| 372 | ranges = <0 0xfc0000 0x10000>; |
| 373 | interrupt-parent = <&sic>; |
| 374 | |
Antoine Ténart | 99f3deb | 2014-06-03 09:33:09 +0200 | [diff] [blame] | 375 | i2c2: i2c@7000 { |
| 376 | compatible = "snps,designware-i2c"; |
| 377 | #address-cells = <1>; |
| 378 | #size-cells = <0>; |
| 379 | reg = <0x7000 0x100>; |
| 380 | interrupt-parent = <&sic>; |
| 381 | interrupts = <6>; |
| 382 | clocks = <&refclk>; |
| 383 | pinctrl-0 = <&twsi2_pmux>; |
| 384 | pinctrl-names = "default"; |
| 385 | status = "disabled"; |
| 386 | }; |
| 387 | |
| 388 | i2c3: i2c@8000 { |
| 389 | compatible = "snps,designware-i2c"; |
| 390 | #address-cells = <1>; |
| 391 | #size-cells = <0>; |
| 392 | reg = <0x8000 0x100>; |
| 393 | interrupt-parent = <&sic>; |
| 394 | interrupts = <7>; |
| 395 | clocks = <&refclk>; |
| 396 | pinctrl-0 = <&twsi3_pmux>; |
| 397 | pinctrl-names = "default"; |
| 398 | status = "disabled"; |
| 399 | }; |
| 400 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 401 | uart0: uart@9000 { |
| 402 | compatible = "snps,dw-apb-uart"; |
| 403 | reg = <0x9000 0x100>; |
| 404 | interrupt-parent = <&sic>; |
| 405 | interrupts = <8>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 406 | clocks = <&refclk>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 407 | reg-shift = <2>; |
Antoine Tenart | 50cc24f | 2014-05-18 20:15:57 +0200 | [diff] [blame] | 408 | pinctrl-0 = <&uart0_pmux>; |
| 409 | pinctrl-names = "default"; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 410 | status = "disabled"; |
| 411 | }; |
| 412 | |
| 413 | uart1: uart@a000 { |
| 414 | compatible = "snps,dw-apb-uart"; |
| 415 | reg = <0xa000 0x100>; |
| 416 | interrupt-parent = <&sic>; |
| 417 | interrupts = <9>; |
Alexandre Belloni | 414dcf8 | 2014-05-12 22:07:35 +0200 | [diff] [blame] | 418 | clocks = <&refclk>; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 419 | reg-shift = <2>; |
Antoine Tenart | 50cc24f | 2014-05-18 20:15:57 +0200 | [diff] [blame] | 420 | pinctrl-0 = <&uart1_pmux>; |
| 421 | pinctrl-names = "default"; |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 422 | status = "disabled"; |
| 423 | }; |
| 424 | |
Antoine Tenart | 50cc24f | 2014-05-18 20:15:57 +0200 | [diff] [blame] | 425 | sysctrl: pin-controller@d000 { |
| 426 | compatible = "marvell,berlin2q-system-ctrl"; |
| 427 | reg = <0xd000 0x100>; |
| 428 | |
| 429 | uart0_pmux: uart0-pmux { |
| 430 | groups = "GSM12"; |
| 431 | function = "uart0"; |
| 432 | }; |
| 433 | |
| 434 | uart1_pmux: uart1-pmux { |
| 435 | groups = "GSM14"; |
| 436 | function = "uart1"; |
| 437 | }; |
Antoine Ténart | 99f3deb | 2014-06-03 09:33:09 +0200 | [diff] [blame] | 438 | |
| 439 | twsi2_pmux: twsi2-pmux { |
| 440 | groups = "GSM13"; |
| 441 | function = "twsi2"; |
| 442 | }; |
| 443 | |
| 444 | twsi3_pmux: twsi3-pmux { |
| 445 | groups = "GSM14"; |
| 446 | function = "twsi3"; |
| 447 | }; |
Antoine Tenart | 50cc24f | 2014-05-18 20:15:57 +0200 | [diff] [blame] | 448 | }; |
| 449 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 450 | sic: interrupt-controller@e000 { |
| 451 | compatible = "snps,dw-apb-ictl"; |
| 452 | reg = <0xe000 0x30>; |
| 453 | interrupt-controller; |
| 454 | #interrupt-cells = <1>; |
| 455 | interrupt-parent = <&gic>; |
| 456 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 457 | }; |
| 458 | }; |
| 459 | }; |
| 460 | }; |