Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | /dts-v1/; |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 14 | #include "imx6q.dtsi" |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 15 | |
| 16 | / { |
Dirk Behme | 752baf5 | 2011-12-08 08:22:01 +0100 | [diff] [blame] | 17 | model = "Freescale i.MX6 Quad Armadillo2 Board"; |
| 18 | compatible = "fsl,imx6q-arm2", "fsl,imx6q"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 19 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 20 | memory { |
| 21 | reg = <0x10000000 0x80000000>; |
| 22 | }; |
| 23 | |
Shawn Guo | 648162a | 2012-02-27 17:11:12 +0800 | [diff] [blame] | 24 | regulators { |
| 25 | compatible = "simple-bus"; |
Shawn Guo | 56160e3 | 2014-02-07 23:22:50 +0800 | [diff] [blame] | 26 | #address-cells = <1>; |
| 27 | #size-cells = <0>; |
Shawn Guo | 648162a | 2012-02-27 17:11:12 +0800 | [diff] [blame] | 28 | |
Shawn Guo | 56160e3 | 2014-02-07 23:22:50 +0800 | [diff] [blame] | 29 | reg_3p3v: regulator@0 { |
Shawn Guo | 648162a | 2012-02-27 17:11:12 +0800 | [diff] [blame] | 30 | compatible = "regulator-fixed"; |
Shawn Guo | 56160e3 | 2014-02-07 23:22:50 +0800 | [diff] [blame] | 31 | reg = <0>; |
Shawn Guo | 648162a | 2012-02-27 17:11:12 +0800 | [diff] [blame] | 32 | regulator-name = "3P3V"; |
| 33 | regulator-min-microvolt = <3300000>; |
| 34 | regulator-max-microvolt = <3300000>; |
| 35 | regulator-always-on; |
| 36 | }; |
Peter Chen | 67339b3 | 2013-10-28 14:05:02 +0800 | [diff] [blame] | 37 | |
Shawn Guo | 56160e3 | 2014-02-07 23:22:50 +0800 | [diff] [blame] | 38 | reg_usb_otg_vbus: regulator@1 { |
Peter Chen | 67339b3 | 2013-10-28 14:05:02 +0800 | [diff] [blame] | 39 | compatible = "regulator-fixed"; |
Shawn Guo | 56160e3 | 2014-02-07 23:22:50 +0800 | [diff] [blame] | 40 | reg = <1>; |
Peter Chen | 67339b3 | 2013-10-28 14:05:02 +0800 | [diff] [blame] | 41 | regulator-name = "usb_otg_vbus"; |
| 42 | regulator-min-microvolt = <5000000>; |
| 43 | regulator-max-microvolt = <5000000>; |
| 44 | gpio = <&gpio3 22 0>; |
| 45 | enable-active-high; |
| 46 | }; |
Shawn Guo | 648162a | 2012-02-27 17:11:12 +0800 | [diff] [blame] | 47 | }; |
| 48 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 49 | leds { |
| 50 | compatible = "gpio-leds"; |
| 51 | |
| 52 | debug-led { |
| 53 | label = "Heartbeat"; |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 54 | gpios = <&gpio3 25 0>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 55 | linux,default-trigger = "heartbeat"; |
| 56 | }; |
| 57 | }; |
| 58 | }; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 59 | |
| 60 | &gpmi { |
| 61 | pinctrl-names = "default"; |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 62 | pinctrl-0 = <&pinctrl_gpmi_nand>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 63 | status = "disabled"; /* gpmi nand conflicts with SD */ |
| 64 | }; |
| 65 | |
| 66 | &iomuxc { |
| 67 | pinctrl-names = "default"; |
| 68 | pinctrl-0 = <&pinctrl_hog>; |
| 69 | |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 70 | imx6q-arm2 { |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 71 | pinctrl_hog: hoggrp { |
| 72 | fsl,pins = < |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 73 | MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 74 | >; |
| 75 | }; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 76 | |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 77 | pinctrl_enet: enetgrp { |
| 78 | fsl,pins = < |
| 79 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 |
| 80 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 |
| 81 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| 82 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| 83 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| 84 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| 85 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| 86 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| 87 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| 88 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 89 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 90 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 91 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 92 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 93 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
Troy Kisky | 4c2620e7 | 2013-12-20 11:47:13 -0700 | [diff] [blame] | 94 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 95 | >; |
| 96 | }; |
| 97 | |
| 98 | pinctrl_gpmi_nand: gpminandgrp { |
| 99 | fsl,pins = < |
| 100 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 |
| 101 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 |
| 102 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 |
| 103 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 |
| 104 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 |
| 105 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 |
| 106 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
| 107 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 |
| 108 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 |
| 109 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 |
| 110 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 |
| 111 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 |
| 112 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 |
| 113 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 |
| 114 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 |
| 115 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 |
| 116 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 |
| 117 | >; |
| 118 | }; |
| 119 | |
| 120 | pinctrl_uart2: uart2grp { |
| 121 | fsl,pins = < |
| 122 | MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 |
| 123 | MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 |
| 124 | MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 |
| 125 | MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 |
| 126 | >; |
| 127 | }; |
| 128 | |
| 129 | pinctrl_uart4: uart4grp { |
| 130 | fsl,pins = < |
| 131 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 |
| 132 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 |
| 133 | >; |
| 134 | }; |
| 135 | |
| 136 | pinctrl_usbotg: usbotggrp { |
| 137 | fsl,pins = < |
| 138 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 |
| 139 | >; |
| 140 | }; |
| 141 | |
| 142 | pinctrl_usdhc3: usdhc3grp { |
| 143 | fsl,pins = < |
| 144 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 145 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 146 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 147 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 148 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 149 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 150 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| 151 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| 152 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| 153 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| 154 | >; |
| 155 | }; |
| 156 | |
| 157 | pinctrl_usdhc3_cdwp: usdhc3cdwp { |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 158 | fsl,pins = < |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 159 | MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 |
| 160 | MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 161 | >; |
| 162 | }; |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 163 | |
| 164 | pinctrl_usdhc4: usdhc4grp { |
| 165 | fsl,pins = < |
| 166 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 |
| 167 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 |
| 168 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| 169 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| 170 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| 171 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| 172 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 |
| 173 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 |
| 174 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 |
| 175 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 |
| 176 | >; |
| 177 | }; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 178 | }; |
| 179 | }; |
| 180 | |
| 181 | &fec { |
| 182 | pinctrl-names = "default"; |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 183 | pinctrl-0 = <&pinctrl_enet>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 184 | phy-mode = "rgmii"; |
Troy Kisky | 4c2620e7 | 2013-12-20 11:47:13 -0700 | [diff] [blame] | 185 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, |
| 186 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 187 | status = "okay"; |
| 188 | }; |
| 189 | |
Peter Chen | 67339b3 | 2013-10-28 14:05:02 +0800 | [diff] [blame] | 190 | &usbotg { |
| 191 | vbus-supply = <®_usb_otg_vbus>; |
| 192 | pinctrl-names = "default"; |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 193 | pinctrl-0 = <&pinctrl_usbotg>; |
Peter Chen | 67339b3 | 2013-10-28 14:05:02 +0800 | [diff] [blame] | 194 | disable-over-current; |
| 195 | status = "okay"; |
| 196 | }; |
| 197 | |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 198 | &usdhc3 { |
| 199 | cd-gpios = <&gpio6 11 0>; |
| 200 | wp-gpios = <&gpio6 14 0>; |
| 201 | vmmc-supply = <®_3p3v>; |
| 202 | pinctrl-names = "default"; |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 203 | pinctrl-0 = <&pinctrl_usdhc3 |
| 204 | &pinctrl_usdhc3_cdwp>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 205 | status = "okay"; |
| 206 | }; |
| 207 | |
| 208 | &usdhc4 { |
| 209 | non-removable; |
| 210 | vmmc-supply = <®_3p3v>; |
| 211 | pinctrl-names = "default"; |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 212 | pinctrl-0 = <&pinctrl_usdhc4>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 213 | status = "okay"; |
| 214 | }; |
| 215 | |
Huang Shijie | 51056d9 | 2013-07-08 17:14:22 +0800 | [diff] [blame] | 216 | &uart2 { |
| 217 | pinctrl-names = "default"; |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 218 | pinctrl-0 = <&pinctrl_uart2>; |
Huang Shijie | 51056d9 | 2013-07-08 17:14:22 +0800 | [diff] [blame] | 219 | fsl,dte-mode; |
| 220 | fsl,uart-has-rtscts; |
Huang Shijie | 51056d9 | 2013-07-08 17:14:22 +0800 | [diff] [blame] | 221 | status = "okay"; |
| 222 | }; |
| 223 | |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 224 | &uart4 { |
| 225 | pinctrl-names = "default"; |
Shawn Guo | 817c27a | 2013-10-23 15:36:09 +0800 | [diff] [blame] | 226 | pinctrl-0 = <&pinctrl_uart4>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 227 | status = "okay"; |
| 228 | }; |