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Benoit Coussond9fda072011-08-09 17:15:17 +02001/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
Florian Vaussard6d624ea2013-05-31 14:32:56 +02009#include <dt-bindings/gpio/gpio.h>
Florian Vaussard8fea7d52013-05-31 14:32:57 +020010#include <dt-bindings/interrupt-controller/arm-gic.h>
Florian Vaussardbcd3cca2013-05-31 14:32:59 +020011#include <dt-bindings/pinctrl/omap.h>
Benoit Coussond9fda072011-08-09 17:15:17 +020012
Florian Vaussard98ef79572013-05-31 14:32:55 +020013#include "skeleton.dtsi"
Benoit Coussond9fda072011-08-09 17:15:17 +020014
15/ {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
18
19 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -050020 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +053024 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
Benoit Coussond9fda072011-08-09 17:15:17 +020028 };
29
Benoit Cousson476b6792011-08-16 11:49:08 +020030 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +010031 #address-cells = <1>;
32 #size-cells = <0>;
33
Benoit Cousson476b6792011-08-16 11:49:08 +020034 cpu@0 {
35 compatible = "arm,cortex-a9";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +010036 device_type = "cpu";
Santosh Shilimkar926fd452012-07-04 17:57:34 +053037 next-level-cache = <&L2>;
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +010038 reg = <0x0>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -060039
40 clocks = <&dpll_mpu_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
Benoit Cousson476b6792011-08-16 11:49:08 +020044 };
45 cpu@1 {
46 compatible = "arm,cortex-a9";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +010047 device_type = "cpu";
Santosh Shilimkar926fd452012-07-04 17:57:34 +053048 next-level-cache = <&L2>;
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +010049 reg = <0x1>;
Benoit Cousson476b6792011-08-16 11:49:08 +020050 };
51 };
52
Benoit Cousson56351212012-09-03 17:56:32 +020053 gic: interrupt-controller@48241000 {
54 compatible = "arm,cortex-a9-gic";
55 interrupt-controller;
56 #interrupt-cells = <3>;
57 reg = <0x48241000 0x1000>,
58 <0x48240100 0x0100>;
59 };
60
Santosh Shilimkar926fd452012-07-04 17:57:34 +053061 L2: l2-cache-controller@48242000 {
62 compatible = "arm,pl310-cache";
63 reg = <0x48242000 0x1000>;
64 cache-unified;
65 cache-level = <2>;
66 };
67
Lee Jones75d71d42013-07-22 11:52:36 +010068 local-timer@48240600 {
Santosh Shilimkareed0de22012-07-04 18:32:32 +053069 compatible = "arm,cortex-a9-twd-timer";
Gilles Chanteperdrix23c47372014-04-07 22:05:39 +020070 clocks = <&mpu_periphclk>;
Santosh Shilimkareed0de22012-07-04 18:32:32 +053071 reg = <0x48240600 0x20>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +020072 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
Santosh Shilimkareed0de22012-07-04 18:32:32 +053073 };
74
Benoit Coussond9fda072011-08-09 17:15:17 +020075 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +010076 * The soc node represents the soc top level view. It is used for IPs
Benoit Coussond9fda072011-08-09 17:15:17 +020077 * that are not memory mapped in the MPU view or for the MPU itself.
78 */
79 soc {
80 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +020081 mpu {
82 compatible = "ti,omap4-mpu";
83 ti,hwmods = "mpu";
Rajendra Nayak1306c082014-09-10 11:04:04 -050084 sram = <&ocmcram>;
Benoit Cousson476b6792011-08-16 11:49:08 +020085 };
86
87 dsp {
88 compatible = "ti,omap3-c64";
89 ti,hwmods = "dsp";
90 };
91
92 iva {
93 compatible = "ti,ivahd";
94 ti,hwmods = "iva";
95 };
Benoit Coussond9fda072011-08-09 17:15:17 +020096 };
97
98 /*
99 * XXX: Use a flat representation of the OMAP4 interconnect.
100 * The real OMAP interconnect network is quite complex.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100101 * Since it will not bring real advantage to represent that in DT for
Benoit Coussond9fda072011-08-09 17:15:17 +0200102 * the moment, just use a fake OCP bus entry to represent the whole bus
103 * hierarchy.
104 */
105 ocp {
Benoit Coussonad8dfac2011-08-12 13:48:47 +0200106 compatible = "ti,omap4-l3-noc", "simple-bus";
Benoit Coussond9fda072011-08-09 17:15:17 +0200107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
Benoit Coussonad8dfac2011-08-12 13:48:47 +0200110 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
Santosh Shilimkar20a60ea2013-02-26 17:36:14 +0530111 reg = <0x44000000 0x1000>,
112 <0x44800000 0x2000>,
113 <0x45000000 0x1000>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200114 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussond9fda072011-08-09 17:15:17 +0200116
Tero Kristo2488ff62013-07-18 12:42:02 +0300117 cm1: cm1@4a004000 {
118 compatible = "ti,omap4-cm1";
119 reg = <0x4a004000 0x2000>;
120
121 cm1_clocks: clocks {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125
126 cm1_clockdomains: clockdomains {
127 };
128 };
129
130 prm: prm@4a306000 {
131 compatible = "ti,omap4-prm";
132 reg = <0x4a306000 0x3000>;
Nishanth Menon5081ce62014-08-22 09:03:50 -0500133 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
Tero Kristo2488ff62013-07-18 12:42:02 +0300134
135 prm_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139
140 prm_clockdomains: clockdomains {
141 };
142 };
143
144 cm2: cm2@4a008000 {
145 compatible = "ti,omap4-cm2";
146 reg = <0x4a008000 0x3000>;
147
148 cm2_clocks: clocks {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 };
152
153 cm2_clockdomains: clockdomains {
154 };
155 };
156
157 scrm: scrm@4a30a000 {
158 compatible = "ti,omap4-scrm";
159 reg = <0x4a30a000 0x2000>;
160
161 scrm_clocks: clocks {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 };
165
166 scrm_clockdomains: clockdomains {
167 };
168 };
169
Jon Hunter510c0ff2012-10-25 14:24:14 -0500170 counter32k: counter@4a304000 {
171 compatible = "ti,omap-counter32k";
172 reg = <0x4a304000 0x20>;
173 ti,hwmods = "counter_32k";
174 };
175
Tony Lindgren679e3312012-09-10 10:34:51 -0700176 omap4_pmx_core: pinmux@4a100040 {
177 compatible = "ti,omap4-padconf", "pinctrl-single";
178 reg = <0x4a100040 0x0196>;
179 #address-cells = <1>;
180 #size-cells = <0>;
Tony Lindgren30a69ef2013-10-10 15:45:13 -0700181 #interrupt-cells = <1>;
182 interrupt-controller;
Tony Lindgren679e3312012-09-10 10:34:51 -0700183 pinctrl-single,register-width = <16>;
184 pinctrl-single,function-mask = <0x7fff>;
185 };
186 omap4_pmx_wkup: pinmux@4a31e040 {
187 compatible = "ti,omap4-padconf", "pinctrl-single";
188 reg = <0x4a31e040 0x0038>;
189 #address-cells = <1>;
190 #size-cells = <0>;
Tony Lindgren30a69ef2013-10-10 15:45:13 -0700191 #interrupt-cells = <1>;
192 interrupt-controller;
Tony Lindgren679e3312012-09-10 10:34:51 -0700193 pinctrl-single,register-width = <16>;
194 pinctrl-single,function-mask = <0x7fff>;
195 };
196
Balaji T Kcd042fe2014-02-19 20:26:40 +0530197 omap4_padconf_global: tisyscon@4a1005a0 {
198 compatible = "syscon";
199 reg = <0x4a1005a0 0x170>;
200 };
201
202 pbias_regulator: pbias_regulator {
203 compatible = "ti,pbias-omap";
204 reg = <0x60 0x4>;
205 syscon = <&omap4_padconf_global>;
206 pbias_mmc_reg: pbias_mmc_omap4 {
207 regulator-name = "pbias_mmc_omap4";
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <3000000>;
210 };
211 };
212
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500213 ocmcram: ocmcram@40304000 {
214 compatible = "mmio-sram";
215 reg = <0x40304000 0xa000>; /* 40k */
216 };
217
Jon Hunter2c2dc542012-04-26 13:47:59 -0500218 sdma: dma-controller@4a056000 {
219 compatible = "ti,omap4430-sdma";
220 reg = <0x4a056000 0x1000>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500225 #dma-cells = <1>;
226 #dma-channels = <32>;
227 #dma-requests = <127>;
228 };
229
Benoit Coussone3e5a922011-08-16 11:51:54 +0200230 gpio1: gpio@4a310000 {
231 compatible = "ti,omap4-gpio";
Benoit Cousson48420db2012-09-05 11:38:23 +0200232 reg = <0x4a310000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200233 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200234 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500235 ti,gpio-always-on;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200236 gpio-controller;
237 #gpio-cells = <2>;
238 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600239 #interrupt-cells = <2>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200240 };
241
242 gpio2: gpio@48055000 {
243 compatible = "ti,omap4-gpio";
Benoit Cousson48420db2012-09-05 11:38:23 +0200244 reg = <0x48055000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200245 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200246 ti,hwmods = "gpio2";
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600250 #interrupt-cells = <2>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200251 };
252
253 gpio3: gpio@48057000 {
254 compatible = "ti,omap4-gpio";
Benoit Cousson48420db2012-09-05 11:38:23 +0200255 reg = <0x48057000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200256 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200257 ti,hwmods = "gpio3";
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600261 #interrupt-cells = <2>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200262 };
263
264 gpio4: gpio@48059000 {
265 compatible = "ti,omap4-gpio";
Benoit Cousson48420db2012-09-05 11:38:23 +0200266 reg = <0x48059000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200267 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200268 ti,hwmods = "gpio4";
269 gpio-controller;
270 #gpio-cells = <2>;
271 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600272 #interrupt-cells = <2>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200273 };
274
275 gpio5: gpio@4805b000 {
276 compatible = "ti,omap4-gpio";
Benoit Cousson48420db2012-09-05 11:38:23 +0200277 reg = <0x4805b000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200278 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200279 ti,hwmods = "gpio5";
280 gpio-controller;
281 #gpio-cells = <2>;
282 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600283 #interrupt-cells = <2>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200284 };
285
286 gpio6: gpio@4805d000 {
287 compatible = "ti,omap4-gpio";
Benoit Cousson48420db2012-09-05 11:38:23 +0200288 reg = <0x4805d000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200289 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200290 ti,hwmods = "gpio6";
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600294 #interrupt-cells = <2>;
Benoit Coussone3e5a922011-08-16 11:51:54 +0200295 };
296
Jon Hunter1c7dbb52013-02-22 15:33:31 -0600297 gpmc: gpmc@50000000 {
298 compatible = "ti,omap4430-gpmc";
299 reg = <0x50000000 0x1000>;
300 #address-cells = <2>;
301 #size-cells = <1>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200302 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunter1c7dbb52013-02-22 15:33:31 -0600303 gpmc,num-cs = <8>;
304 gpmc,num-waitpins = <4>;
305 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530306 ti,no-idle-on-init;
Florian Vaussard7b8b6af2014-02-26 11:38:09 +0100307 clocks = <&l3_div_ck>;
308 clock-names = "fck";
Jon Hunter1c7dbb52013-02-22 15:33:31 -0600309 };
310
Benoit Cousson19bfb762012-02-16 11:55:27 +0100311 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530312 compatible = "ti,omap4-uart";
Benoit Cousson48420db2012-09-05 11:38:23 +0200313 reg = <0x4806a000 0x100>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200314 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530315 ti,hwmods = "uart1";
316 clock-frequency = <48000000>;
317 };
318
Benoit Cousson19bfb762012-02-16 11:55:27 +0100319 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530320 compatible = "ti,omap4-uart";
Benoit Cousson48420db2012-09-05 11:38:23 +0200321 reg = <0x4806c000 0x100>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700322 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530323 ti,hwmods = "uart2";
324 clock-frequency = <48000000>;
325 };
326
Benoit Cousson19bfb762012-02-16 11:55:27 +0100327 uart3: serial@48020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530328 compatible = "ti,omap4-uart";
Benoit Cousson48420db2012-09-05 11:38:23 +0200329 reg = <0x48020000 0x100>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700330 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530331 ti,hwmods = "uart3";
332 clock-frequency = <48000000>;
333 };
334
Benoit Cousson19bfb762012-02-16 11:55:27 +0100335 uart4: serial@4806e000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530336 compatible = "ti,omap4-uart";
Benoit Cousson48420db2012-09-05 11:38:23 +0200337 reg = <0x4806e000 0x100>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700338 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530339 ti,hwmods = "uart4";
340 clock-frequency = <48000000>;
341 };
Benoit Cousson58e778f2011-08-17 19:00:03 +0530342
Suman Anna04c7d922013-10-10 16:15:33 -0500343 hwspinlock: spinlock@4a0f6000 {
344 compatible = "ti,omap4-hwspinlock";
345 reg = <0x4a0f6000 0x1000>;
346 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600347 #hwlock-cells = <1>;
Suman Anna04c7d922013-10-10 16:15:33 -0500348 };
349
Benoit Cousson58e778f2011-08-17 19:00:03 +0530350 i2c1: i2c@48070000 {
351 compatible = "ti,omap4-i2c";
Benoit Cousson48420db2012-09-05 11:38:23 +0200352 reg = <0x48070000 0x100>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200353 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
Benoit Cousson58e778f2011-08-17 19:00:03 +0530354 #address-cells = <1>;
355 #size-cells = <0>;
356 ti,hwmods = "i2c1";
357 };
358
359 i2c2: i2c@48072000 {
360 compatible = "ti,omap4-i2c";
Benoit Cousson48420db2012-09-05 11:38:23 +0200361 reg = <0x48072000 0x100>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200362 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
Benoit Cousson58e778f2011-08-17 19:00:03 +0530363 #address-cells = <1>;
364 #size-cells = <0>;
365 ti,hwmods = "i2c2";
366 };
367
368 i2c3: i2c@48060000 {
369 compatible = "ti,omap4-i2c";
Benoit Cousson48420db2012-09-05 11:38:23 +0200370 reg = <0x48060000 0x100>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200371 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
Benoit Cousson58e778f2011-08-17 19:00:03 +0530372 #address-cells = <1>;
373 #size-cells = <0>;
374 ti,hwmods = "i2c3";
375 };
376
377 i2c4: i2c@48350000 {
378 compatible = "ti,omap4-i2c";
Benoit Cousson48420db2012-09-05 11:38:23 +0200379 reg = <0x48350000 0x100>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200380 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
Benoit Cousson58e778f2011-08-17 19:00:03 +0530381 #address-cells = <1>;
382 #size-cells = <0>;
383 ti,hwmods = "i2c4";
384 };
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100385
386 mcspi1: spi@48098000 {
387 compatible = "ti,omap4-mcspi";
Benoit Cousson48420db2012-09-05 11:38:23 +0200388 reg = <0x48098000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200389 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100390 #address-cells = <1>;
391 #size-cells = <0>;
392 ti,hwmods = "mcspi1";
393 ti,spi-num-cs = <4>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500394 dmas = <&sdma 35>,
395 <&sdma 36>,
396 <&sdma 37>,
397 <&sdma 38>,
398 <&sdma 39>,
399 <&sdma 40>,
400 <&sdma 41>,
401 <&sdma 42>;
402 dma-names = "tx0", "rx0", "tx1", "rx1",
403 "tx2", "rx2", "tx3", "rx3";
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100404 };
405
406 mcspi2: spi@4809a000 {
407 compatible = "ti,omap4-mcspi";
Benoit Cousson48420db2012-09-05 11:38:23 +0200408 reg = <0x4809a000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200409 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100410 #address-cells = <1>;
411 #size-cells = <0>;
412 ti,hwmods = "mcspi2";
413 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500414 dmas = <&sdma 43>,
415 <&sdma 44>,
416 <&sdma 45>,
417 <&sdma 46>;
418 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100419 };
420
421 mcspi3: spi@480b8000 {
422 compatible = "ti,omap4-mcspi";
Benoit Cousson48420db2012-09-05 11:38:23 +0200423 reg = <0x480b8000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200424 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100425 #address-cells = <1>;
426 #size-cells = <0>;
427 ti,hwmods = "mcspi3";
428 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500429 dmas = <&sdma 15>, <&sdma 16>;
430 dma-names = "tx0", "rx0";
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100431 };
432
433 mcspi4: spi@480ba000 {
434 compatible = "ti,omap4-mcspi";
Benoit Cousson48420db2012-09-05 11:38:23 +0200435 reg = <0x480ba000 0x200>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200436 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100437 #address-cells = <1>;
438 #size-cells = <0>;
439 ti,hwmods = "mcspi4";
440 ti,spi-num-cs = <1>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500441 dmas = <&sdma 70>, <&sdma 71>;
442 dma-names = "tx0", "rx0";
Benoit Coussonefcf1e52012-01-20 14:15:58 +0100443 };
Rajendra Nayak74981762011-10-04 17:10:27 +0530444
445 mmc1: mmc@4809c000 {
446 compatible = "ti,omap4-hsmmc";
Benoit Cousson48420db2012-09-05 11:38:23 +0200447 reg = <0x4809c000 0x400>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200448 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayak74981762011-10-04 17:10:27 +0530449 ti,hwmods = "mmc1";
450 ti,dual-volt;
451 ti,needs-special-reset;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500452 dmas = <&sdma 61>, <&sdma 62>;
453 dma-names = "tx", "rx";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530454 pbias-supply = <&pbias_mmc_reg>;
Rajendra Nayak74981762011-10-04 17:10:27 +0530455 };
456
457 mmc2: mmc@480b4000 {
458 compatible = "ti,omap4-hsmmc";
Benoit Cousson48420db2012-09-05 11:38:23 +0200459 reg = <0x480b4000 0x400>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200460 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayak74981762011-10-04 17:10:27 +0530461 ti,hwmods = "mmc2";
462 ti,needs-special-reset;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500463 dmas = <&sdma 47>, <&sdma 48>;
464 dma-names = "tx", "rx";
Rajendra Nayak74981762011-10-04 17:10:27 +0530465 };
466
467 mmc3: mmc@480ad000 {
468 compatible = "ti,omap4-hsmmc";
Benoit Cousson48420db2012-09-05 11:38:23 +0200469 reg = <0x480ad000 0x400>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200470 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayak74981762011-10-04 17:10:27 +0530471 ti,hwmods = "mmc3";
472 ti,needs-special-reset;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500473 dmas = <&sdma 77>, <&sdma 78>;
474 dma-names = "tx", "rx";
Rajendra Nayak74981762011-10-04 17:10:27 +0530475 };
476
477 mmc4: mmc@480d1000 {
478 compatible = "ti,omap4-hsmmc";
Benoit Cousson48420db2012-09-05 11:38:23 +0200479 reg = <0x480d1000 0x400>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200480 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayak74981762011-10-04 17:10:27 +0530481 ti,hwmods = "mmc4";
482 ti,needs-special-reset;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500483 dmas = <&sdma 57>, <&sdma 58>;
484 dma-names = "tx", "rx";
Rajendra Nayak74981762011-10-04 17:10:27 +0530485 };
486
487 mmc5: mmc@480d5000 {
488 compatible = "ti,omap4-hsmmc";
Benoit Cousson48420db2012-09-05 11:38:23 +0200489 reg = <0x480d5000 0x400>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200490 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
Rajendra Nayak74981762011-10-04 17:10:27 +0530491 ti,hwmods = "mmc5";
492 ti,needs-special-reset;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500493 dmas = <&sdma 59>, <&sdma 60>;
494 dma-names = "tx", "rx";
Rajendra Nayak74981762011-10-04 17:10:27 +0530495 };
Xiao Jiang94c30732012-06-01 12:44:14 +0800496
Florian Vaussard21bd85a2014-03-05 18:24:18 -0600497 mmu_dsp: mmu@4a066000 {
498 compatible = "ti,omap4-iommu";
499 reg = <0x4a066000 0x100>;
500 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
501 ti,hwmods = "mmu_dsp";
502 };
503
504 mmu_ipu: mmu@55082000 {
505 compatible = "ti,omap4-iommu";
506 reg = <0x55082000 0x100>;
507 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
508 ti,hwmods = "mmu_ipu";
509 ti,iommu-bus-err-back;
510 };
511
Xiao Jiang94c30732012-06-01 12:44:14 +0800512 wdt2: wdt@4a314000 {
513 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
Benoit Cousson48420db2012-09-05 11:38:23 +0200514 reg = <0x4a314000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200515 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
Xiao Jiang94c30732012-06-01 12:44:14 +0800516 ti,hwmods = "wd_timer2";
517 };
Peter Ujfalusi4f4b5c72012-06-08 17:01:59 +0300518
519 mcpdm: mcpdm@40132000 {
520 compatible = "ti,omap4-mcpdm";
521 reg = <0x40132000 0x7f>, /* MPU private access */
522 <0x49032000 0x7f>; /* L3 Interconnect */
Peter Ujfalusi63467cf2012-08-29 16:31:06 +0300523 reg-names = "mpu", "dma";
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200524 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
Peter Ujfalusi4f4b5c72012-06-08 17:01:59 +0300525 ti,hwmods = "mcpdm";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100526 dmas = <&sdma 65>,
527 <&sdma 66>;
528 dma-names = "up_link", "dn_link";
Peter Ujfalusi7adb0932014-01-24 10:19:01 +0200529 status = "disabled";
Peter Ujfalusi4f4b5c72012-06-08 17:01:59 +0300530 };
Peter Ujfalusia4c38312012-06-08 17:02:00 +0300531
532 dmic: dmic@4012e000 {
533 compatible = "ti,omap4-dmic";
534 reg = <0x4012e000 0x7f>, /* MPU private access */
535 <0x4902e000 0x7f>; /* L3 Interconnect */
Peter Ujfalusi63467cf2012-08-29 16:31:06 +0300536 reg-names = "mpu", "dma";
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200537 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
Peter Ujfalusia4c38312012-06-08 17:02:00 +0300538 ti,hwmods = "dmic";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100539 dmas = <&sdma 67>;
540 dma-names = "up_link";
Peter Ujfalusi7adb0932014-01-24 10:19:01 +0200541 status = "disabled";
Peter Ujfalusia4c38312012-06-08 17:02:00 +0300542 };
Sourav Poddar61bc3542012-08-14 16:45:37 +0530543
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300544 mcbsp1: mcbsp@40122000 {
545 compatible = "ti,omap4-mcbsp";
546 reg = <0x40122000 0xff>, /* MPU private access */
547 <0x49022000 0xff>; /* L3 Interconnect */
548 reg-names = "mpu", "dma";
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200549 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300550 interrupt-names = "common";
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300551 ti,buffer-size = <128>;
552 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100553 dmas = <&sdma 33>,
554 <&sdma 34>;
555 dma-names = "tx", "rx";
Peter Ujfalusi7adb0932014-01-24 10:19:01 +0200556 status = "disabled";
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300557 };
558
559 mcbsp2: mcbsp@40124000 {
560 compatible = "ti,omap4-mcbsp";
561 reg = <0x40124000 0xff>, /* MPU private access */
562 <0x49024000 0xff>; /* L3 Interconnect */
563 reg-names = "mpu", "dma";
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200564 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300565 interrupt-names = "common";
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300566 ti,buffer-size = <128>;
567 ti,hwmods = "mcbsp2";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100568 dmas = <&sdma 17>,
569 <&sdma 18>;
570 dma-names = "tx", "rx";
Peter Ujfalusi7adb0932014-01-24 10:19:01 +0200571 status = "disabled";
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300572 };
573
574 mcbsp3: mcbsp@40126000 {
575 compatible = "ti,omap4-mcbsp";
576 reg = <0x40126000 0xff>, /* MPU private access */
577 <0x49026000 0xff>; /* L3 Interconnect */
578 reg-names = "mpu", "dma";
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200579 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300580 interrupt-names = "common";
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300581 ti,buffer-size = <128>;
582 ti,hwmods = "mcbsp3";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100583 dmas = <&sdma 19>,
584 <&sdma 20>;
585 dma-names = "tx", "rx";
Peter Ujfalusi7adb0932014-01-24 10:19:01 +0200586 status = "disabled";
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300587 };
588
589 mcbsp4: mcbsp@48096000 {
590 compatible = "ti,omap4-mcbsp";
591 reg = <0x48096000 0xff>; /* L4 Interconnect */
592 reg-names = "mpu";
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200593 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300594 interrupt-names = "common";
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300595 ti,buffer-size = <128>;
596 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100597 dmas = <&sdma 31>,
598 <&sdma 32>;
599 dma-names = "tx", "rx";
Peter Ujfalusi7adb0932014-01-24 10:19:01 +0200600 status = "disabled";
Peter Ujfalusi2995a102012-07-26 17:13:21 +0300601 };
602
Sourav Poddar61bc3542012-08-14 16:45:37 +0530603 keypad: keypad@4a31c000 {
604 compatible = "ti,omap4-keypad";
Benoit Cousson48420db2012-09-05 11:38:23 +0200605 reg = <0x4a31c000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200606 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
Benoit Cousson48420db2012-09-05 11:38:23 +0200607 reg-names = "mpu";
Sourav Poddar61bc3542012-08-14 16:45:37 +0530608 ti,hwmods = "kbd";
609 };
Aneesh V11c27062012-01-20 20:35:26 +0530610
Archit Taneja1a5fe3c2013-12-17 15:32:21 +0530611 dmm@4e000000 {
612 compatible = "ti,omap4-dmm";
613 reg = <0x4e000000 0x800>;
614 interrupts = <0 113 0x4>;
615 ti,hwmods = "dmm";
616 };
617
Aneesh V11c27062012-01-20 20:35:26 +0530618 emif1: emif@4c000000 {
619 compatible = "ti,emif-4d";
Benoit Cousson48420db2012-09-05 11:38:23 +0200620 reg = <0x4c000000 0x100>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200621 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
Aneesh V11c27062012-01-20 20:35:26 +0530622 ti,hwmods = "emif1";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530623 ti,no-idle-on-init;
Aneesh V11c27062012-01-20 20:35:26 +0530624 phy-type = <1>;
625 hw-caps-read-idle-ctrl;
626 hw-caps-ll-interface;
627 hw-caps-temp-alert;
628 };
629
630 emif2: emif@4d000000 {
631 compatible = "ti,emif-4d";
Benoit Cousson48420db2012-09-05 11:38:23 +0200632 reg = <0x4d000000 0x100>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200633 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
Aneesh V11c27062012-01-20 20:35:26 +0530634 ti,hwmods = "emif2";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530635 ti,no-idle-on-init;
Aneesh V11c27062012-01-20 20:35:26 +0530636 phy-type = <1>;
637 hw-caps-read-idle-ctrl;
638 hw-caps-ll-interface;
639 hw-caps-temp-alert;
640 };
Linus Torvalds8f446a72012-10-01 18:46:13 -0700641
Kishon Vijay Abraham I3ce0a992012-09-19 16:02:51 +0530642 ocp2scp@4a0ad000 {
Kishon Vijay Abraham I59bafcf2012-08-22 14:10:03 +0530643 compatible = "ti,omap-ocp2scp";
Kishon Vijay Abraham I3ce0a992012-09-19 16:02:51 +0530644 reg = <0x4a0ad000 0x1f>;
Kishon Vijay Abraham I59bafcf2012-08-22 14:10:03 +0530645 #address-cells = <1>;
646 #size-cells = <1>;
647 ranges;
648 ti,hwmods = "ocp2scp_usb_phy";
Kishon Vijay Abraham Icf0d8692013-03-07 19:05:15 +0530649 usb2_phy: usb2phy@4a0ad080 {
650 compatible = "ti,omap-usb2";
651 reg = <0x4a0ad080 0x58>;
Roger Quadros470019a2013-10-03 18:12:36 +0300652 ctrl-module = <&omap_control_usb2phy>;
Roger Quadrosc65d0ad2014-05-05 12:54:42 +0300653 clocks = <&usb_phy_cm_clk32k>;
654 clock-names = "wkupclk";
Kishon Vijay Abraham I975d9632013-09-27 11:53:29 +0530655 #phy-cells = <0>;
Kishon Vijay Abraham Icf0d8692013-03-07 19:05:15 +0530656 };
Kishon Vijay Abraham I59bafcf2012-08-22 14:10:03 +0530657 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500658
Suman Anna8ebc30d2014-07-11 16:44:35 -0500659 mailbox: mailbox@4a0f4000 {
660 compatible = "ti,omap4-mailbox";
661 reg = <0x4a0f4000 0x200>;
662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
663 ti,hwmods = "mailbox";
664 ti,mbox-num-users = <3>;
665 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500666 mbox_ipu: mbox_ipu {
667 ti,mbox-tx = <0 0 0>;
668 ti,mbox-rx = <1 0 0>;
669 };
670 mbox_dsp: mbox_dsp {
671 ti,mbox-tx = <3 0 0>;
672 ti,mbox-rx = <2 0 0>;
673 };
Suman Anna8ebc30d2014-07-11 16:44:35 -0500674 };
675
Jon Hunterfab8ad02012-10-19 09:59:00 -0500676 timer1: timer@4a318000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500677 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500678 reg = <0x4a318000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200679 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500680 ti,hwmods = "timer1";
681 ti,timer-alwon;
682 };
683
684 timer2: timer@48032000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500685 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500686 reg = <0x48032000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200687 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500688 ti,hwmods = "timer2";
689 };
690
691 timer3: timer@48034000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500692 compatible = "ti,omap4430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500693 reg = <0x48034000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200694 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500695 ti,hwmods = "timer3";
696 };
697
698 timer4: timer@48036000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500699 compatible = "ti,omap4430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500700 reg = <0x48036000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200701 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500702 ti,hwmods = "timer4";
703 };
704
Jon Hunterd03a93b2012-11-01 08:57:08 -0500705 timer5: timer@40138000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500706 compatible = "ti,omap4430-timer";
Jon Hunterd03a93b2012-11-01 08:57:08 -0500707 reg = <0x40138000 0x80>,
708 <0x49038000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200709 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500710 ti,hwmods = "timer5";
711 ti,timer-dsp;
712 };
713
Jon Hunterd03a93b2012-11-01 08:57:08 -0500714 timer6: timer@4013a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500715 compatible = "ti,omap4430-timer";
Jon Hunterd03a93b2012-11-01 08:57:08 -0500716 reg = <0x4013a000 0x80>,
717 <0x4903a000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200718 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500719 ti,hwmods = "timer6";
720 ti,timer-dsp;
721 };
722
Jon Hunterd03a93b2012-11-01 08:57:08 -0500723 timer7: timer@4013c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500724 compatible = "ti,omap4430-timer";
Jon Hunterd03a93b2012-11-01 08:57:08 -0500725 reg = <0x4013c000 0x80>,
726 <0x4903c000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200727 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500728 ti,hwmods = "timer7";
729 ti,timer-dsp;
730 };
731
Jon Hunterd03a93b2012-11-01 08:57:08 -0500732 timer8: timer@4013e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500733 compatible = "ti,omap4430-timer";
Jon Hunterd03a93b2012-11-01 08:57:08 -0500734 reg = <0x4013e000 0x80>,
735 <0x4903e000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200736 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500737 ti,hwmods = "timer8";
738 ti,timer-pwm;
739 ti,timer-dsp;
740 };
741
742 timer9: timer@4803e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500743 compatible = "ti,omap4430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500744 reg = <0x4803e000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200745 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500746 ti,hwmods = "timer9";
747 ti,timer-pwm;
748 };
749
750 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500751 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500752 reg = <0x48086000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200753 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500754 ti,hwmods = "timer10";
755 ti,timer-pwm;
756 };
757
758 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500759 compatible = "ti,omap4430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500760 reg = <0x48088000 0x80>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200761 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
Jon Hunterfab8ad02012-10-19 09:59:00 -0500762 ti,hwmods = "timer11";
763 ti,timer-pwm;
764 };
Roger Quadrosf17c8992013-03-20 17:44:58 +0200765
766 usbhstll: usbhstll@4a062000 {
767 compatible = "ti,usbhs-tll";
768 reg = <0x4a062000 0x1000>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200769 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosf17c8992013-03-20 17:44:58 +0200770 ti,hwmods = "usb_tll_hs";
771 };
772
773 usbhshost: usbhshost@4a064000 {
774 compatible = "ti,usbhs-host";
775 reg = <0x4a064000 0x800>;
776 ti,hwmods = "usb_host_hs";
777 #address-cells = <1>;
778 #size-cells = <1>;
779 ranges;
Roger Quadros051fc062014-02-27 16:18:26 +0200780 clocks = <&init_60m_fclk>,
781 <&xclk60mhsp1_ck>,
782 <&xclk60mhsp2_ck>;
783 clock-names = "refclk_60m_int",
784 "refclk_60m_ext_p1",
785 "refclk_60m_ext_p2";
Roger Quadrosf17c8992013-03-20 17:44:58 +0200786
787 usbhsohci: ohci@4a064800 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200788 compatible = "ti,ohci-omap3";
Roger Quadrosf17c8992013-03-20 17:44:58 +0200789 reg = <0x4a064800 0x400>;
790 interrupt-parent = <&gic>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200791 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosf17c8992013-03-20 17:44:58 +0200792 };
793
794 usbhsehci: ehci@4a064c00 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200795 compatible = "ti,ehci-omap";
Roger Quadrosf17c8992013-03-20 17:44:58 +0200796 reg = <0x4a064c00 0x400>;
797 interrupt-parent = <&gic>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200798 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
Roger Quadrosf17c8992013-03-20 17:44:58 +0200799 };
800 };
Kishon Vijay Abraham I840e5fd2013-03-07 19:05:14 +0530801
Roger Quadros470019a2013-10-03 18:12:36 +0300802 omap_control_usb2phy: control-phy@4a002300 {
803 compatible = "ti,control-phy-usb2";
804 reg = <0x4a002300 0x4>;
805 reg-names = "power";
806 };
807
808 omap_control_usbotg: control-phy@4a00233c {
809 compatible = "ti,control-phy-otghs";
810 reg = <0x4a00233c 0x4>;
811 reg-names = "otghs_control";
Kishon Vijay Abraham I840e5fd2013-03-07 19:05:14 +0530812 };
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530813
814 usb_otg_hs: usb_otg_hs@4a0ab000 {
815 compatible = "ti,omap4-musb";
816 reg = <0x4a0ab000 0x7ff>;
Florian Vaussard8fea7d52013-05-31 14:32:57 +0200817 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530818 interrupt-names = "mc", "dma";
819 ti,hwmods = "usb_otg_hs";
820 usb-phy = <&usb2_phy>;
Kishon Vijay Abraham I975d9632013-09-27 11:53:29 +0530821 phys = <&usb2_phy>;
822 phy-names = "usb2-phy";
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530823 multipoint = <1>;
824 num-eps = <16>;
825 ram-bits = <12>;
Roger Quadros470019a2013-10-03 18:12:36 +0300826 ctrl-module = <&omap_control_usbotg>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530827 };
Joel Fernandesdd6317d2013-07-11 18:20:05 -0500828
829 aes: aes@4b501000 {
830 compatible = "ti,omap4-aes";
831 ti,hwmods = "aes";
832 reg = <0x4b501000 0xa0>;
833 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
834 dmas = <&sdma 111>, <&sdma 110>;
835 dma-names = "tx", "rx";
836 };
Joel Fernandes806e9432013-09-24 15:23:33 -0500837
838 des: des@480a5000 {
839 compatible = "ti,omap4-des";
840 ti,hwmods = "des";
841 reg = <0x480a5000 0xa0>;
842 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
843 dmas = <&sdma 117>, <&sdma 116>;
844 dma-names = "tx", "rx";
845 };
Andrii.Tseglytskyie12c7732014-03-03 20:20:22 +0530846
847 abb_mpu: regulator-abb-mpu {
848 compatible = "ti,abb-v2";
849 regulator-name = "abb_mpu";
850 #address-cells = <0>;
851 #size-cells = <0>;
852 ti,tranxdone-status-mask = <0x80>;
853 clocks = <&sys_clkin_ck>;
854 ti,settling-time = <50>;
855 ti,clock-cycles = <16>;
856
857 status = "disabled";
858 };
859
860 abb_iva: regulator-abb-iva {
861 compatible = "ti,abb-v2";
862 regulator-name = "abb_iva";
863 #address-cells = <0>;
864 #size-cells = <0>;
865 ti,tranxdone-status-mask = <0x80000000>;
866 clocks = <&sys_clkin_ck>;
867 ti,settling-time = <50>;
868 ti,clock-cycles = <16>;
869
870 status = "disabled";
871 };
Tomi Valkeinencfe86fc2012-08-21 15:34:50 +0300872
873 dss: dss@58000000 {
874 compatible = "ti,omap4-dss";
875 reg = <0x58000000 0x80>;
876 status = "disabled";
877 ti,hwmods = "dss_core";
878 clocks = <&dss_dss_clk>;
879 clock-names = "fck";
880 #address-cells = <1>;
881 #size-cells = <1>;
882 ranges;
883
884 dispc@58001000 {
885 compatible = "ti,omap4-dispc";
886 reg = <0x58001000 0x1000>;
887 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
888 ti,hwmods = "dss_dispc";
889 clocks = <&dss_dss_clk>;
890 clock-names = "fck";
891 };
892
893 rfbi: encoder@58002000 {
894 compatible = "ti,omap4-rfbi";
895 reg = <0x58002000 0x1000>;
896 status = "disabled";
897 ti,hwmods = "dss_rfbi";
898 clocks = <&dss_dss_clk>, <&dss_fck>;
899 clock-names = "fck", "ick";
900 };
901
902 venc: encoder@58003000 {
903 compatible = "ti,omap4-venc";
904 reg = <0x58003000 0x1000>;
905 status = "disabled";
906 ti,hwmods = "dss_venc";
907 clocks = <&dss_tv_clk>;
908 clock-names = "fck";
909 };
910
911 dsi1: encoder@58004000 {
912 compatible = "ti,omap4-dsi";
913 reg = <0x58004000 0x200>,
914 <0x58004200 0x40>,
915 <0x58004300 0x20>;
916 reg-names = "proto", "phy", "pll";
917 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
918 status = "disabled";
919 ti,hwmods = "dss_dsi1";
920 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
921 clock-names = "fck", "sys_clk";
922 };
923
924 dsi2: encoder@58005000 {
925 compatible = "ti,omap4-dsi";
926 reg = <0x58005000 0x200>,
927 <0x58005200 0x40>,
928 <0x58005300 0x20>;
929 reg-names = "proto", "phy", "pll";
930 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
931 status = "disabled";
932 ti,hwmods = "dss_dsi2";
933 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
934 clock-names = "fck", "sys_clk";
935 };
936
937 hdmi: encoder@58006000 {
938 compatible = "ti,omap4-hdmi";
939 reg = <0x58006000 0x200>,
940 <0x58006200 0x100>,
941 <0x58006300 0x100>,
942 <0x58006400 0x1000>;
943 reg-names = "wp", "pll", "phy", "core";
944 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
945 status = "disabled";
946 ti,hwmods = "dss_hdmi";
947 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
948 clock-names = "fck", "sys_clk";
Jyri Sarha53855b32014-05-12 12:12:24 +0300949 dmas = <&sdma 76>;
950 dma-names = "audio_tx";
Tomi Valkeinencfe86fc2012-08-21 15:34:50 +0300951 };
952 };
Benoit Coussond9fda072011-08-09 17:15:17 +0200953 };
954};
Tero Kristo2488ff62013-07-18 12:42:02 +0300955
956/include/ "omap44xx-clocks.dtsi"