R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 10 | #include <dt-bindings/gpio/gpio.h> |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 12 | #include <dt-bindings/pinctrl/omap.h> |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 13 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 14 | #include "skeleton.dtsi" |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 15 | |
| 16 | / { |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 17 | #address-cells = <1>; |
| 18 | #size-cells = <1>; |
| 19 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 20 | compatible = "ti,omap5"; |
| 21 | interrupt-parent = <&gic>; |
| 22 | |
| 23 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 24 | i2c0 = &i2c1; |
| 25 | i2c1 = &i2c2; |
| 26 | i2c2 = &i2c3; |
| 27 | i2c3 = &i2c4; |
| 28 | i2c4 = &i2c5; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 29 | serial0 = &uart1; |
| 30 | serial1 = &uart2; |
| 31 | serial2 = &uart3; |
| 32 | serial3 = &uart4; |
| 33 | serial4 = &uart5; |
| 34 | serial5 = &uart6; |
| 35 | }; |
| 36 | |
| 37 | cpus { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 38 | #address-cells = <1>; |
| 39 | #size-cells = <0>; |
| 40 | |
Nishanth Menon | b8981d7 | 2013-10-16 10:39:04 -0500 | [diff] [blame] | 41 | cpu0: cpu@0 { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 42 | device_type = "cpu"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 43 | compatible = "arm,cortex-a15"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 44 | reg = <0x0>; |
J Keerthy | 6c24894 | 2013-10-16 10:39:06 -0500 | [diff] [blame] | 45 | |
| 46 | operating-points = < |
| 47 | /* kHz uV */ |
J Keerthy | 6c24894 | 2013-10-16 10:39:06 -0500 | [diff] [blame] | 48 | 1000000 1060000 |
| 49 | 1500000 1250000 |
| 50 | >; |
Nishanth Menon | 8d766fa | 2014-01-29 12:19:17 -0600 | [diff] [blame] | 51 | |
| 52 | clocks = <&dpll_mpu_ck>; |
| 53 | clock-names = "cpu"; |
| 54 | |
| 55 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
| 56 | |
Eduardo Valentin | 2cd29f6 | 2013-08-16 11:30:47 -0400 | [diff] [blame] | 57 | /* cooling options */ |
| 58 | cooling-min-level = <0>; |
| 59 | cooling-max-level = <2>; |
| 60 | #cooling-cells = <2>; /* min followed by max */ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 61 | }; |
| 62 | cpu@1 { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 63 | device_type = "cpu"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 64 | compatible = "arm,cortex-a15"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 65 | reg = <0x1>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 66 | }; |
| 67 | }; |
| 68 | |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 69 | thermal-zones { |
| 70 | #include "omap4-cpu-thermal.dtsi" |
| 71 | #include "omap5-gpu-thermal.dtsi" |
| 72 | #include "omap5-core-thermal.dtsi" |
| 73 | }; |
| 74 | |
Santosh Shilimkar | b45ccc4 | 2013-02-10 21:40:19 +0530 | [diff] [blame] | 75 | timer { |
| 76 | compatible = "arm,armv7-timer"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 77 | /* PPI secure/nonsecure IRQ */ |
| 78 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 79 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 80 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 81 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; |
Santosh Shilimkar | b45ccc4 | 2013-02-10 21:40:19 +0530 | [diff] [blame] | 82 | }; |
| 83 | |
Nathan Lynch | 69a126c | 2014-03-19 10:45:53 -0500 | [diff] [blame] | 84 | pmu { |
| 85 | compatible = "arm,cortex-a15-pmu"; |
| 86 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 87 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; |
| 88 | }; |
| 89 | |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 90 | gic: interrupt-controller@48211000 { |
| 91 | compatible = "arm,cortex-a15-gic"; |
| 92 | interrupt-controller; |
| 93 | #interrupt-cells = <3>; |
| 94 | reg = <0x48211000 0x1000>, |
Santosh Shilimkar | 0129c16 | 2013-02-19 17:29:24 +0530 | [diff] [blame] | 95 | <0x48212000 0x1000>, |
| 96 | <0x48214000 0x2000>, |
| 97 | <0x48216000 0x2000>; |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 98 | }; |
| 99 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 100 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 101 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 102 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 103 | */ |
| 104 | soc { |
| 105 | compatible = "ti,omap-infra"; |
| 106 | mpu { |
Rajendra Nayak | 1306c08 | 2014-09-10 11:04:04 -0500 | [diff] [blame] | 107 | compatible = "ti,omap4-mpu"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 108 | ti,hwmods = "mpu"; |
Rajendra Nayak | 1306c08 | 2014-09-10 11:04:04 -0500 | [diff] [blame] | 109 | sram = <&ocmcram>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 110 | }; |
| 111 | }; |
| 112 | |
| 113 | /* |
| 114 | * XXX: Use a flat representation of the OMAP3 interconnect. |
| 115 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 116 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 117 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 118 | * hierarchy. |
| 119 | */ |
| 120 | ocp { |
| 121 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <1>; |
| 124 | ranges; |
| 125 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
Santosh Shilimkar | 20a60ea | 2013-02-26 17:36:14 +0530 | [diff] [blame] | 126 | reg = <0x44000000 0x2000>, |
| 127 | <0x44800000 0x3000>, |
| 128 | <0x45000000 0x4000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 129 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 130 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 131 | |
Tero Kristo | 85dc74e | 2013-07-18 17:09:29 +0300 | [diff] [blame] | 132 | prm: prm@4ae06000 { |
| 133 | compatible = "ti,omap5-prm"; |
| 134 | reg = <0x4ae06000 0x3000>; |
Nishanth Menon | 5081ce6 | 2014-08-22 09:03:50 -0500 | [diff] [blame] | 135 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
Tero Kristo | 85dc74e | 2013-07-18 17:09:29 +0300 | [diff] [blame] | 136 | |
| 137 | prm_clocks: clocks { |
| 138 | #address-cells = <1>; |
| 139 | #size-cells = <0>; |
| 140 | }; |
| 141 | |
| 142 | prm_clockdomains: clockdomains { |
| 143 | }; |
| 144 | }; |
| 145 | |
| 146 | cm_core_aon: cm_core_aon@4a004000 { |
| 147 | compatible = "ti,omap5-cm-core-aon"; |
| 148 | reg = <0x4a004000 0x2000>; |
| 149 | |
| 150 | cm_core_aon_clocks: clocks { |
| 151 | #address-cells = <1>; |
| 152 | #size-cells = <0>; |
| 153 | }; |
| 154 | |
| 155 | cm_core_aon_clockdomains: clockdomains { |
| 156 | }; |
| 157 | }; |
| 158 | |
| 159 | scrm: scrm@4ae0a000 { |
| 160 | compatible = "ti,omap5-scrm"; |
| 161 | reg = <0x4ae0a000 0x2000>; |
| 162 | |
| 163 | scrm_clocks: clocks { |
| 164 | #address-cells = <1>; |
| 165 | #size-cells = <0>; |
| 166 | }; |
| 167 | |
| 168 | scrm_clockdomains: clockdomains { |
| 169 | }; |
| 170 | }; |
| 171 | |
| 172 | cm_core: cm_core@4a008000 { |
| 173 | compatible = "ti,omap5-cm-core"; |
| 174 | reg = <0x4a008000 0x3000>; |
| 175 | |
| 176 | cm_core_clocks: clocks { |
| 177 | #address-cells = <1>; |
| 178 | #size-cells = <0>; |
| 179 | }; |
| 180 | |
| 181 | cm_core_clockdomains: clockdomains { |
| 182 | }; |
| 183 | }; |
| 184 | |
Jon Hunter | 3b3132f | 2012-11-01 09:12:23 -0500 | [diff] [blame] | 185 | counter32k: counter@4ae04000 { |
| 186 | compatible = "ti,omap-counter32k"; |
| 187 | reg = <0x4ae04000 0x40>; |
| 188 | ti,hwmods = "counter_32k"; |
| 189 | }; |
| 190 | |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 191 | omap5_pmx_core: pinmux@4a002840 { |
Nishanth Menon | 924c31c | 2014-05-23 00:58:08 -0500 | [diff] [blame] | 192 | compatible = "ti,omap5-padconf", "pinctrl-single"; |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 193 | reg = <0x4a002840 0x01b6>; |
| 194 | #address-cells = <1>; |
| 195 | #size-cells = <0>; |
Nishanth Menon | 924c31c | 2014-05-23 00:58:08 -0500 | [diff] [blame] | 196 | #interrupt-cells = <1>; |
| 197 | interrupt-controller; |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 198 | pinctrl-single,register-width = <16>; |
| 199 | pinctrl-single,function-mask = <0x7fff>; |
| 200 | }; |
| 201 | omap5_pmx_wkup: pinmux@4ae0c840 { |
Nishanth Menon | 924c31c | 2014-05-23 00:58:08 -0500 | [diff] [blame] | 202 | compatible = "ti,omap5-padconf", "pinctrl-single"; |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 203 | reg = <0x4ae0c840 0x0038>; |
| 204 | #address-cells = <1>; |
| 205 | #size-cells = <0>; |
Nishanth Menon | 924c31c | 2014-05-23 00:58:08 -0500 | [diff] [blame] | 206 | #interrupt-cells = <1>; |
| 207 | interrupt-controller; |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 208 | pinctrl-single,register-width = <16>; |
| 209 | pinctrl-single,function-mask = <0x7fff>; |
| 210 | }; |
| 211 | |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 212 | omap5_padconf_global: tisyscon@4a002da0 { |
| 213 | compatible = "syscon"; |
| 214 | reg = <0x4A002da0 0xec>; |
| 215 | }; |
| 216 | |
| 217 | pbias_regulator: pbias_regulator { |
| 218 | compatible = "ti,pbias-omap"; |
| 219 | reg = <0x60 0x4>; |
| 220 | syscon = <&omap5_padconf_global>; |
| 221 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 222 | regulator-name = "pbias_mmc_omap5"; |
| 223 | regulator-min-microvolt = <1800000>; |
| 224 | regulator-max-microvolt = <3000000>; |
| 225 | }; |
| 226 | }; |
| 227 | |
Rajendra Nayak | 8b9a281 | 2014-09-10 11:04:03 -0500 | [diff] [blame] | 228 | ocmcram: ocmcram@40300000 { |
| 229 | compatible = "mmio-sram"; |
| 230 | reg = <0x40300000 0x20000>; /* 128k */ |
| 231 | }; |
| 232 | |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 233 | sdma: dma-controller@4a056000 { |
| 234 | compatible = "ti,omap4430-sdma"; |
| 235 | reg = <0x4a056000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 236 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 237 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 238 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 239 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 240 | #dma-cells = <1>; |
| 241 | #dma-channels = <32>; |
| 242 | #dma-requests = <127>; |
| 243 | }; |
| 244 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 245 | gpio1: gpio@4ae10000 { |
| 246 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 247 | reg = <0x4ae10000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 248 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 249 | ti,hwmods = "gpio1"; |
Jon Hunter | e4b9b9f | 2013-04-04 15:16:16 -0500 | [diff] [blame] | 250 | ti,gpio-always-on; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 251 | gpio-controller; |
| 252 | #gpio-cells = <2>; |
| 253 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 254 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 255 | }; |
| 256 | |
| 257 | gpio2: gpio@48055000 { |
| 258 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 259 | reg = <0x48055000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 260 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 261 | ti,hwmods = "gpio2"; |
| 262 | gpio-controller; |
| 263 | #gpio-cells = <2>; |
| 264 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 265 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | gpio3: gpio@48057000 { |
| 269 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 270 | reg = <0x48057000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 271 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 272 | ti,hwmods = "gpio3"; |
| 273 | gpio-controller; |
| 274 | #gpio-cells = <2>; |
| 275 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 276 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 277 | }; |
| 278 | |
| 279 | gpio4: gpio@48059000 { |
| 280 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 281 | reg = <0x48059000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 282 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 283 | ti,hwmods = "gpio4"; |
| 284 | gpio-controller; |
| 285 | #gpio-cells = <2>; |
| 286 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 287 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 288 | }; |
| 289 | |
| 290 | gpio5: gpio@4805b000 { |
| 291 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 292 | reg = <0x4805b000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 293 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 294 | ti,hwmods = "gpio5"; |
| 295 | gpio-controller; |
| 296 | #gpio-cells = <2>; |
| 297 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 298 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 299 | }; |
| 300 | |
| 301 | gpio6: gpio@4805d000 { |
| 302 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 303 | reg = <0x4805d000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 304 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 305 | ti,hwmods = "gpio6"; |
| 306 | gpio-controller; |
| 307 | #gpio-cells = <2>; |
| 308 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 309 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 310 | }; |
| 311 | |
| 312 | gpio7: gpio@48051000 { |
| 313 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 314 | reg = <0x48051000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 315 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 316 | ti,hwmods = "gpio7"; |
| 317 | gpio-controller; |
| 318 | #gpio-cells = <2>; |
| 319 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 320 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 321 | }; |
| 322 | |
| 323 | gpio8: gpio@48053000 { |
| 324 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 325 | reg = <0x48053000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 326 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 327 | ti,hwmods = "gpio8"; |
| 328 | gpio-controller; |
| 329 | #gpio-cells = <2>; |
| 330 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 331 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 332 | }; |
| 333 | |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 334 | gpmc: gpmc@50000000 { |
| 335 | compatible = "ti,omap4430-gpmc"; |
| 336 | reg = <0x50000000 0x1000>; |
| 337 | #address-cells = <2>; |
| 338 | #size-cells = <1>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 339 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 340 | gpmc,num-cs = <8>; |
| 341 | gpmc,num-waitpins = <4>; |
| 342 | ti,hwmods = "gpmc"; |
Florian Vaussard | 7b8b6af | 2014-02-26 11:38:09 +0100 | [diff] [blame] | 343 | clocks = <&l3_iclk_div>; |
| 344 | clock-names = "fck"; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 345 | }; |
| 346 | |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 347 | i2c1: i2c@48070000 { |
| 348 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 349 | reg = <0x48070000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 350 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 351 | #address-cells = <1>; |
| 352 | #size-cells = <0>; |
| 353 | ti,hwmods = "i2c1"; |
| 354 | }; |
| 355 | |
| 356 | i2c2: i2c@48072000 { |
| 357 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 358 | reg = <0x48072000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 359 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 360 | #address-cells = <1>; |
| 361 | #size-cells = <0>; |
| 362 | ti,hwmods = "i2c2"; |
| 363 | }; |
| 364 | |
| 365 | i2c3: i2c@48060000 { |
| 366 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 367 | reg = <0x48060000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 368 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 369 | #address-cells = <1>; |
| 370 | #size-cells = <0>; |
| 371 | ti,hwmods = "i2c3"; |
| 372 | }; |
| 373 | |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 374 | i2c4: i2c@4807a000 { |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 375 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 376 | reg = <0x4807a000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 377 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 378 | #address-cells = <1>; |
| 379 | #size-cells = <0>; |
| 380 | ti,hwmods = "i2c4"; |
| 381 | }; |
| 382 | |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 383 | i2c5: i2c@4807c000 { |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 384 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 385 | reg = <0x4807c000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 386 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 387 | #address-cells = <1>; |
| 388 | #size-cells = <0>; |
| 389 | ti,hwmods = "i2c5"; |
| 390 | }; |
| 391 | |
Suman Anna | fe0e09e | 2013-10-10 16:15:34 -0500 | [diff] [blame] | 392 | hwspinlock: spinlock@4a0f6000 { |
| 393 | compatible = "ti,omap4-hwspinlock"; |
| 394 | reg = <0x4a0f6000 0x1000>; |
| 395 | ti,hwmods = "spinlock"; |
Suman Anna | 3405421 | 2014-01-13 18:26:45 -0600 | [diff] [blame] | 396 | #hwlock-cells = <1>; |
Suman Anna | fe0e09e | 2013-10-10 16:15:34 -0500 | [diff] [blame] | 397 | }; |
| 398 | |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 399 | mcspi1: spi@48098000 { |
| 400 | compatible = "ti,omap4-mcspi"; |
| 401 | reg = <0x48098000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 402 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 403 | #address-cells = <1>; |
| 404 | #size-cells = <0>; |
| 405 | ti,hwmods = "mcspi1"; |
| 406 | ti,spi-num-cs = <4>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 407 | dmas = <&sdma 35>, |
| 408 | <&sdma 36>, |
| 409 | <&sdma 37>, |
| 410 | <&sdma 38>, |
| 411 | <&sdma 39>, |
| 412 | <&sdma 40>, |
| 413 | <&sdma 41>, |
| 414 | <&sdma 42>; |
| 415 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 416 | "tx2", "rx2", "tx3", "rx3"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 417 | }; |
| 418 | |
| 419 | mcspi2: spi@4809a000 { |
| 420 | compatible = "ti,omap4-mcspi"; |
| 421 | reg = <0x4809a000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 422 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 423 | #address-cells = <1>; |
| 424 | #size-cells = <0>; |
| 425 | ti,hwmods = "mcspi2"; |
| 426 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 427 | dmas = <&sdma 43>, |
| 428 | <&sdma 44>, |
| 429 | <&sdma 45>, |
| 430 | <&sdma 46>; |
| 431 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 432 | }; |
| 433 | |
| 434 | mcspi3: spi@480b8000 { |
| 435 | compatible = "ti,omap4-mcspi"; |
| 436 | reg = <0x480b8000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 437 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 438 | #address-cells = <1>; |
| 439 | #size-cells = <0>; |
| 440 | ti,hwmods = "mcspi3"; |
| 441 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 442 | dmas = <&sdma 15>, <&sdma 16>; |
| 443 | dma-names = "tx0", "rx0"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 444 | }; |
| 445 | |
| 446 | mcspi4: spi@480ba000 { |
| 447 | compatible = "ti,omap4-mcspi"; |
| 448 | reg = <0x480ba000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 449 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 450 | #address-cells = <1>; |
| 451 | #size-cells = <0>; |
| 452 | ti,hwmods = "mcspi4"; |
| 453 | ti,spi-num-cs = <1>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 454 | dmas = <&sdma 70>, <&sdma 71>; |
| 455 | dma-names = "tx0", "rx0"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 456 | }; |
| 457 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 458 | uart1: serial@4806a000 { |
| 459 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 460 | reg = <0x4806a000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 461 | interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 462 | ti,hwmods = "uart1"; |
| 463 | clock-frequency = <48000000>; |
| 464 | }; |
| 465 | |
| 466 | uart2: serial@4806c000 { |
| 467 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 468 | reg = <0x4806c000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 469 | interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 470 | ti,hwmods = "uart2"; |
| 471 | clock-frequency = <48000000>; |
| 472 | }; |
| 473 | |
| 474 | uart3: serial@48020000 { |
| 475 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 476 | reg = <0x48020000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 477 | interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 478 | ti,hwmods = "uart3"; |
| 479 | clock-frequency = <48000000>; |
| 480 | }; |
| 481 | |
| 482 | uart4: serial@4806e000 { |
| 483 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 484 | reg = <0x4806e000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 485 | interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 486 | ti,hwmods = "uart4"; |
| 487 | clock-frequency = <48000000>; |
| 488 | }; |
| 489 | |
| 490 | uart5: serial@48066000 { |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 491 | compatible = "ti,omap4-uart"; |
| 492 | reg = <0x48066000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 493 | interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 494 | ti,hwmods = "uart5"; |
| 495 | clock-frequency = <48000000>; |
| 496 | }; |
| 497 | |
| 498 | uart6: serial@48068000 { |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 499 | compatible = "ti,omap4-uart"; |
| 500 | reg = <0x48068000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 501 | interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 502 | ti,hwmods = "uart6"; |
| 503 | clock-frequency = <48000000>; |
| 504 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 505 | |
| 506 | mmc1: mmc@4809c000 { |
| 507 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 508 | reg = <0x4809c000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 509 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 510 | ti,hwmods = "mmc1"; |
| 511 | ti,dual-volt; |
| 512 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 513 | dmas = <&sdma 61>, <&sdma 62>; |
| 514 | dma-names = "tx", "rx"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 515 | pbias-supply = <&pbias_mmc_reg>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 516 | }; |
| 517 | |
| 518 | mmc2: mmc@480b4000 { |
| 519 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 520 | reg = <0x480b4000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 521 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 522 | ti,hwmods = "mmc2"; |
| 523 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 524 | dmas = <&sdma 47>, <&sdma 48>; |
| 525 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 526 | }; |
| 527 | |
| 528 | mmc3: mmc@480ad000 { |
| 529 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 530 | reg = <0x480ad000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 531 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 532 | ti,hwmods = "mmc3"; |
| 533 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 534 | dmas = <&sdma 77>, <&sdma 78>; |
| 535 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 536 | }; |
| 537 | |
| 538 | mmc4: mmc@480d1000 { |
| 539 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 540 | reg = <0x480d1000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 541 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 542 | ti,hwmods = "mmc4"; |
| 543 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 544 | dmas = <&sdma 57>, <&sdma 58>; |
| 545 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 546 | }; |
| 547 | |
| 548 | mmc5: mmc@480d5000 { |
| 549 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 550 | reg = <0x480d5000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 551 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 552 | ti,hwmods = "mmc5"; |
| 553 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 554 | dmas = <&sdma 59>, <&sdma 60>; |
| 555 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 556 | }; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 557 | |
Suman Anna | 2dcfa56 | 2014-03-05 18:24:19 -0600 | [diff] [blame] | 558 | mmu_dsp: mmu@4a066000 { |
| 559 | compatible = "ti,omap4-iommu"; |
| 560 | reg = <0x4a066000 0x100>; |
| 561 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 562 | ti,hwmods = "mmu_dsp"; |
| 563 | }; |
| 564 | |
| 565 | mmu_ipu: mmu@55082000 { |
| 566 | compatible = "ti,omap4-iommu"; |
| 567 | reg = <0x55082000 0x100>; |
| 568 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 569 | ti,hwmods = "mmu_ipu"; |
| 570 | ti,iommu-bus-err-back; |
| 571 | }; |
| 572 | |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 573 | keypad: keypad@4ae1c000 { |
| 574 | compatible = "ti,omap4-keypad"; |
Santosh Shilimkar | 8cc8b89 | 2013-01-23 19:53:30 +0530 | [diff] [blame] | 575 | reg = <0x4ae1c000 0x400>; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 576 | ti,hwmods = "kbd"; |
| 577 | }; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 578 | |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 579 | mcpdm: mcpdm@40132000 { |
| 580 | compatible = "ti,omap4-mcpdm"; |
| 581 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 582 | <0x49032000 0x7f>; /* L3 Interconnect */ |
| 583 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 584 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 585 | ti,hwmods = "mcpdm"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 586 | dmas = <&sdma 65>, |
| 587 | <&sdma 66>; |
| 588 | dma-names = "up_link", "dn_link"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 589 | status = "disabled"; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 590 | }; |
| 591 | |
| 592 | dmic: dmic@4012e000 { |
| 593 | compatible = "ti,omap4-dmic"; |
| 594 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 595 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
| 596 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 597 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 598 | ti,hwmods = "dmic"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 599 | dmas = <&sdma 67>; |
| 600 | dma-names = "up_link"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 601 | status = "disabled"; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 602 | }; |
| 603 | |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 604 | mcbsp1: mcbsp@40122000 { |
| 605 | compatible = "ti,omap4-mcbsp"; |
| 606 | reg = <0x40122000 0xff>, /* MPU private access */ |
| 607 | <0x49022000 0xff>; /* L3 Interconnect */ |
| 608 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 609 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 610 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 611 | ti,buffer-size = <128>; |
| 612 | ti,hwmods = "mcbsp1"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 613 | dmas = <&sdma 33>, |
| 614 | <&sdma 34>; |
| 615 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 616 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 617 | }; |
| 618 | |
| 619 | mcbsp2: mcbsp@40124000 { |
| 620 | compatible = "ti,omap4-mcbsp"; |
| 621 | reg = <0x40124000 0xff>, /* MPU private access */ |
| 622 | <0x49024000 0xff>; /* L3 Interconnect */ |
| 623 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 624 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 625 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 626 | ti,buffer-size = <128>; |
| 627 | ti,hwmods = "mcbsp2"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 628 | dmas = <&sdma 17>, |
| 629 | <&sdma 18>; |
| 630 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 631 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 632 | }; |
| 633 | |
| 634 | mcbsp3: mcbsp@40126000 { |
| 635 | compatible = "ti,omap4-mcbsp"; |
| 636 | reg = <0x40126000 0xff>, /* MPU private access */ |
| 637 | <0x49026000 0xff>; /* L3 Interconnect */ |
| 638 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 639 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 640 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 641 | ti,buffer-size = <128>; |
| 642 | ti,hwmods = "mcbsp3"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 643 | dmas = <&sdma 19>, |
| 644 | <&sdma 20>; |
| 645 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 646 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 647 | }; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 648 | |
Suman Anna | 84d89c3 | 2014-04-22 17:23:35 -0500 | [diff] [blame] | 649 | mailbox: mailbox@4a0f4000 { |
| 650 | compatible = "ti,omap4-mailbox"; |
| 651 | reg = <0x4a0f4000 0x200>; |
| 652 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| 653 | ti,hwmods = "mailbox"; |
Suman Anna | 41ffada | 2014-07-11 16:44:34 -0500 | [diff] [blame] | 654 | ti,mbox-num-users = <3>; |
| 655 | ti,mbox-num-fifos = <8>; |
Suman Anna | d27704d | 2014-09-10 14:27:23 -0500 | [diff] [blame] | 656 | mbox_ipu: mbox_ipu { |
| 657 | ti,mbox-tx = <0 0 0>; |
| 658 | ti,mbox-rx = <1 0 0>; |
| 659 | }; |
| 660 | mbox_dsp: mbox_dsp { |
| 661 | ti,mbox-tx = <3 0 0>; |
| 662 | ti,mbox-rx = <2 0 0>; |
| 663 | }; |
Suman Anna | 84d89c3 | 2014-04-22 17:23:35 -0500 | [diff] [blame] | 664 | }; |
| 665 | |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 666 | timer1: timer@4ae18000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 667 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 668 | reg = <0x4ae18000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 669 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 670 | ti,hwmods = "timer1"; |
| 671 | ti,timer-alwon; |
| 672 | }; |
| 673 | |
| 674 | timer2: timer@48032000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 675 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 676 | reg = <0x48032000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 677 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 678 | ti,hwmods = "timer2"; |
| 679 | }; |
| 680 | |
| 681 | timer3: timer@48034000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 682 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 683 | reg = <0x48034000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 684 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 685 | ti,hwmods = "timer3"; |
| 686 | }; |
| 687 | |
| 688 | timer4: timer@48036000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 689 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 690 | reg = <0x48036000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 691 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 692 | ti,hwmods = "timer4"; |
| 693 | }; |
| 694 | |
| 695 | timer5: timer@40138000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 696 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 697 | reg = <0x40138000 0x80>, |
| 698 | <0x49038000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 699 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 700 | ti,hwmods = "timer5"; |
| 701 | ti,timer-dsp; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 702 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 703 | }; |
| 704 | |
| 705 | timer6: timer@4013a000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 706 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 707 | reg = <0x4013a000 0x80>, |
| 708 | <0x4903a000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 709 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 710 | ti,hwmods = "timer6"; |
| 711 | ti,timer-dsp; |
| 712 | ti,timer-pwm; |
| 713 | }; |
| 714 | |
| 715 | timer7: timer@4013c000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 716 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 717 | reg = <0x4013c000 0x80>, |
| 718 | <0x4903c000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 719 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 720 | ti,hwmods = "timer7"; |
| 721 | ti,timer-dsp; |
| 722 | }; |
| 723 | |
| 724 | timer8: timer@4013e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 725 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 726 | reg = <0x4013e000 0x80>, |
| 727 | <0x4903e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 728 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 729 | ti,hwmods = "timer8"; |
| 730 | ti,timer-dsp; |
| 731 | ti,timer-pwm; |
| 732 | }; |
| 733 | |
| 734 | timer9: timer@4803e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 735 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 736 | reg = <0x4803e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 737 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 738 | ti,hwmods = "timer9"; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 739 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 740 | }; |
| 741 | |
| 742 | timer10: timer@48086000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 743 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 744 | reg = <0x48086000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 745 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 746 | ti,hwmods = "timer10"; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 747 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 748 | }; |
| 749 | |
| 750 | timer11: timer@48088000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 751 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 752 | reg = <0x48088000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 753 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 754 | ti,hwmods = "timer11"; |
| 755 | ti,timer-pwm; |
| 756 | }; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 757 | |
Lokesh Vutla | 5545219 | 2013-02-27 11:54:45 +0530 | [diff] [blame] | 758 | wdt2: wdt@4ae14000 { |
| 759 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; |
| 760 | reg = <0x4ae14000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 761 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | 5545219 | 2013-02-27 11:54:45 +0530 | [diff] [blame] | 762 | ti,hwmods = "wd_timer2"; |
| 763 | }; |
| 764 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 765 | dmm@4e000000 { |
| 766 | compatible = "ti,omap5-dmm"; |
| 767 | reg = <0x4e000000 0x800>; |
| 768 | interrupts = <0 113 0x4>; |
| 769 | ti,hwmods = "dmm"; |
| 770 | }; |
| 771 | |
Lee Jones | 8906d65 | 2013-07-22 11:52:37 +0100 | [diff] [blame] | 772 | emif1: emif@4c000000 { |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 773 | compatible = "ti,emif-4d5"; |
| 774 | ti,hwmods = "emif1"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 775 | ti,no-idle-on-init; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 776 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 777 | reg = <0x4c000000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 778 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 779 | hw-caps-read-idle-ctrl; |
| 780 | hw-caps-ll-interface; |
| 781 | hw-caps-temp-alert; |
| 782 | }; |
| 783 | |
Lee Jones | 8906d65 | 2013-07-22 11:52:37 +0100 | [diff] [blame] | 784 | emif2: emif@4d000000 { |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 785 | compatible = "ti,emif-4d5"; |
| 786 | ti,hwmods = "emif2"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 787 | ti,no-idle-on-init; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 788 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 789 | reg = <0x4d000000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 790 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 791 | hw-caps-read-idle-ctrl; |
| 792 | hw-caps-ll-interface; |
| 793 | hw-caps-temp-alert; |
| 794 | }; |
Kishon Vijay Abraham I | fedc428 | 2013-03-07 19:05:17 +0530 | [diff] [blame] | 795 | |
Roger Quadros | b297c29 | 2013-10-03 18:12:37 +0300 | [diff] [blame] | 796 | omap_control_usb2phy: control-phy@4a002300 { |
| 797 | compatible = "ti,control-phy-usb2"; |
| 798 | reg = <0x4a002300 0x4>; |
| 799 | reg-names = "power"; |
| 800 | }; |
| 801 | |
| 802 | omap_control_usb3phy: control-phy@4a002370 { |
| 803 | compatible = "ti,control-phy-pipe3"; |
| 804 | reg = <0x4a002370 0x4>; |
| 805 | reg-names = "power"; |
Kishon Vijay Abraham I | fedc428 | 2013-03-07 19:05:17 +0530 | [diff] [blame] | 806 | }; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 807 | |
Felipe Balbi | e3a412c | 2013-08-21 20:01:32 +0530 | [diff] [blame] | 808 | usb3: omap_dwc3@4a020000 { |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 809 | compatible = "ti,dwc3"; |
| 810 | ti,hwmods = "usb_otg_ss"; |
Felipe Balbi | 6f61ee2 | 2013-08-21 20:01:30 +0530 | [diff] [blame] | 811 | reg = <0x4a020000 0x10000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 812 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 813 | #address-cells = <1>; |
| 814 | #size-cells = <1>; |
| 815 | utmi-mode = <2>; |
| 816 | ranges; |
| 817 | dwc3@4a030000 { |
Felipe Balbi | 22a5aa1 | 2013-07-02 21:20:24 +0300 | [diff] [blame] | 818 | compatible = "snps,dwc3"; |
Felipe Balbi | 6f61ee2 | 2013-08-21 20:01:30 +0530 | [diff] [blame] | 819 | reg = <0x4a030000 0x10000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 820 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 821 | phys = <&usb2_phy>, <&usb3_phy>; |
| 822 | phy-names = "usb2-phy", "usb3-phy"; |
George Cherian | c47ee6e | 2013-10-10 16:19:54 +0530 | [diff] [blame] | 823 | dr_mode = "peripheral"; |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 824 | tx-fifo-resize; |
| 825 | }; |
| 826 | }; |
| 827 | |
Felipe Balbi | b6731f7 | 2013-08-21 20:01:31 +0530 | [diff] [blame] | 828 | ocp2scp@4a080000 { |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 829 | compatible = "ti,omap-ocp2scp"; |
| 830 | #address-cells = <1>; |
| 831 | #size-cells = <1>; |
Felipe Balbi | b6731f7 | 2013-08-21 20:01:31 +0530 | [diff] [blame] | 832 | reg = <0x4a080000 0x20>; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 833 | ranges; |
| 834 | ti,hwmods = "ocp2scp1"; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 835 | usb2_phy: usb2phy@4a084000 { |
| 836 | compatible = "ti,omap-usb2"; |
| 837 | reg = <0x4a084000 0x7c>; |
Roger Quadros | b297c29 | 2013-10-03 18:12:37 +0300 | [diff] [blame] | 838 | ctrl-module = <&omap_control_usb2phy>; |
Roger Quadros | c65d0ad | 2014-05-05 12:54:42 +0300 | [diff] [blame] | 839 | clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; |
| 840 | clock-names = "wkupclk", "refclk"; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 841 | #phy-cells = <0>; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 842 | }; |
| 843 | |
| 844 | usb3_phy: usb3phy@4a084400 { |
| 845 | compatible = "ti,omap-usb3"; |
| 846 | reg = <0x4a084400 0x80>, |
| 847 | <0x4a084800 0x64>, |
| 848 | <0x4a084c00 0x40>; |
| 849 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
Roger Quadros | b297c29 | 2013-10-03 18:12:37 +0300 | [diff] [blame] | 850 | ctrl-module = <&omap_control_usb3phy>; |
Roger Quadros | ada7657 | 2014-04-01 13:37:27 +0300 | [diff] [blame] | 851 | clocks = <&usb_phy_cm_clk32k>, |
| 852 | <&sys_clkin>, |
| 853 | <&usb_otg_ss_refclk960m>; |
| 854 | clock-names = "wkupclk", |
| 855 | "sysclk", |
| 856 | "refclk"; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 857 | #phy-cells = <0>; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 858 | }; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 859 | }; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 860 | |
| 861 | usbhstll: usbhstll@4a062000 { |
| 862 | compatible = "ti,usbhs-tll"; |
| 863 | reg = <0x4a062000 0x1000>; |
| 864 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| 865 | ti,hwmods = "usb_tll_hs"; |
| 866 | }; |
| 867 | |
| 868 | usbhshost: usbhshost@4a064000 { |
| 869 | compatible = "ti,usbhs-host"; |
| 870 | reg = <0x4a064000 0x800>; |
| 871 | ti,hwmods = "usb_host_hs"; |
| 872 | #address-cells = <1>; |
| 873 | #size-cells = <1>; |
| 874 | ranges; |
Roger Quadros | 051fc06 | 2014-02-27 16:18:26 +0200 | [diff] [blame] | 875 | clocks = <&l3init_60m_fclk>, |
| 876 | <&xclk60mhsp1_ck>, |
| 877 | <&xclk60mhsp2_ck>; |
| 878 | clock-names = "refclk_60m_int", |
| 879 | "refclk_60m_ext_p1", |
| 880 | "refclk_60m_ext_p2"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 881 | |
| 882 | usbhsohci: ohci@4a064800 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 883 | compatible = "ti,ohci-omap3"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 884 | reg = <0x4a064800 0x400>; |
| 885 | interrupt-parent = <&gic>; |
| 886 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 887 | }; |
| 888 | |
| 889 | usbhsehci: ehci@4a064c00 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 890 | compatible = "ti,ehci-omap"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 891 | reg = <0x4a064c00 0x400>; |
| 892 | interrupt-parent = <&gic>; |
| 893 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 894 | }; |
| 895 | }; |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 896 | |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 897 | bandgap: bandgap@4a0021e0 { |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 898 | reg = <0x4a0021e0 0xc |
| 899 | 0x4a00232c 0xc |
| 900 | 0x4a002380 0x2c |
| 901 | 0x4a0023C0 0x3c>; |
| 902 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| 903 | compatible = "ti,omap5430-bandgap"; |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 904 | |
| 905 | #thermal-sensor-cells = <1>; |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 906 | }; |
Balaji T K | 4f82952 | 2014-04-23 20:35:33 +0300 | [diff] [blame] | 907 | |
| 908 | omap_control_sata: control-phy@4a002374 { |
| 909 | compatible = "ti,control-phy-pipe3"; |
| 910 | reg = <0x4a002374 0x4>; |
| 911 | reg-names = "power"; |
| 912 | clocks = <&sys_clkin>; |
| 913 | clock-names = "sysclk"; |
| 914 | }; |
| 915 | |
| 916 | /* OCP2SCP3 */ |
| 917 | ocp2scp@4a090000 { |
| 918 | compatible = "ti,omap-ocp2scp"; |
| 919 | #address-cells = <1>; |
| 920 | #size-cells = <1>; |
| 921 | reg = <0x4a090000 0x20>; |
| 922 | ranges; |
| 923 | ti,hwmods = "ocp2scp3"; |
| 924 | sata_phy: phy@4a096000 { |
| 925 | compatible = "ti,phy-pipe3-sata"; |
| 926 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 927 | <0x4A096400 0x64>, /* phy_tx */ |
| 928 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 929 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 930 | ctrl-module = <&omap_control_sata>; |
| 931 | clocks = <&sys_clkin>; |
| 932 | clock-names = "sysclk"; |
| 933 | #phy-cells = <0>; |
| 934 | }; |
| 935 | }; |
| 936 | |
| 937 | sata: sata@4a141100 { |
| 938 | compatible = "snps,dwc-ahci"; |
| 939 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
| 940 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| 941 | phys = <&sata_phy>; |
| 942 | phy-names = "sata-phy"; |
| 943 | clocks = <&sata_ref_clk>; |
| 944 | ti,hwmods = "sata"; |
| 945 | }; |
| 946 | |
Tomi Valkeinen | e7585c4 | 2014-03-07 12:45:54 +0200 | [diff] [blame] | 947 | dss: dss@58000000 { |
| 948 | compatible = "ti,omap5-dss"; |
| 949 | reg = <0x58000000 0x80>; |
| 950 | status = "disabled"; |
| 951 | ti,hwmods = "dss_core"; |
| 952 | clocks = <&dss_dss_clk>; |
| 953 | clock-names = "fck"; |
| 954 | #address-cells = <1>; |
| 955 | #size-cells = <1>; |
| 956 | ranges; |
| 957 | |
| 958 | dispc@58001000 { |
| 959 | compatible = "ti,omap5-dispc"; |
| 960 | reg = <0x58001000 0x1000>; |
| 961 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 962 | ti,hwmods = "dss_dispc"; |
| 963 | clocks = <&dss_dss_clk>; |
| 964 | clock-names = "fck"; |
| 965 | }; |
| 966 | |
Tomi Valkeinen | 84ace67 | 2014-09-04 09:28:32 +0300 | [diff] [blame] | 967 | rfbi: encoder@58002000 { |
| 968 | compatible = "ti,omap5-rfbi"; |
| 969 | reg = <0x58002000 0x100>; |
| 970 | status = "disabled"; |
| 971 | ti,hwmods = "dss_rfbi"; |
| 972 | clocks = <&dss_dss_clk>, <&l3_iclk_div>; |
| 973 | clock-names = "fck", "ick"; |
| 974 | }; |
| 975 | |
Tomi Valkeinen | e7585c4 | 2014-03-07 12:45:54 +0200 | [diff] [blame] | 976 | dsi1: encoder@58004000 { |
| 977 | compatible = "ti,omap5-dsi"; |
| 978 | reg = <0x58004000 0x200>, |
| 979 | <0x58004200 0x40>, |
| 980 | <0x58004300 0x40>; |
| 981 | reg-names = "proto", "phy", "pll"; |
| 982 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 983 | status = "disabled"; |
| 984 | ti,hwmods = "dss_dsi1"; |
| 985 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; |
| 986 | clock-names = "fck", "sys_clk"; |
| 987 | }; |
| 988 | |
| 989 | dsi2: encoder@58005000 { |
| 990 | compatible = "ti,omap5-dsi"; |
| 991 | reg = <0x58009000 0x200>, |
| 992 | <0x58009200 0x40>, |
| 993 | <0x58009300 0x40>; |
| 994 | reg-names = "proto", "phy", "pll"; |
| 995 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 996 | status = "disabled"; |
| 997 | ti,hwmods = "dss_dsi2"; |
| 998 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; |
| 999 | clock-names = "fck", "sys_clk"; |
| 1000 | }; |
| 1001 | |
| 1002 | hdmi: encoder@58060000 { |
| 1003 | compatible = "ti,omap5-hdmi"; |
| 1004 | reg = <0x58040000 0x200>, |
| 1005 | <0x58040200 0x80>, |
| 1006 | <0x58040300 0x80>, |
| 1007 | <0x58060000 0x19000>; |
| 1008 | reg-names = "wp", "pll", "phy", "core"; |
| 1009 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| 1010 | status = "disabled"; |
| 1011 | ti,hwmods = "dss_hdmi"; |
| 1012 | clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; |
| 1013 | clock-names = "fck", "sys_clk"; |
Jyri Sarha | 7d0fde3 | 2014-05-12 12:12:26 +0300 | [diff] [blame] | 1014 | dmas = <&sdma 76>; |
| 1015 | dma-names = "audio_tx"; |
Tomi Valkeinen | e7585c4 | 2014-03-07 12:45:54 +0200 | [diff] [blame] | 1016 | }; |
| 1017 | }; |
Andrii.Tseglytskyi | 07b9b3d | 2014-06-05 20:11:12 -0500 | [diff] [blame] | 1018 | |
| 1019 | abb_mpu: regulator-abb-mpu { |
| 1020 | compatible = "ti,abb-v2"; |
| 1021 | regulator-name = "abb_mpu"; |
| 1022 | #address-cells = <0>; |
| 1023 | #size-cells = <0>; |
| 1024 | clocks = <&sys_clkin>; |
| 1025 | ti,settling-time = <50>; |
| 1026 | ti,clock-cycles = <16>; |
| 1027 | |
| 1028 | reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, |
| 1029 | <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; |
| 1030 | reg-names = "base-address", "int-address", |
| 1031 | "efuse-address", "ldo-address"; |
| 1032 | ti,tranxdone-status-mask = <0x80>; |
| 1033 | /* LDOVBBMPU_MUX_CTRL */ |
| 1034 | ti,ldovbb-override-mask = <0x400>; |
| 1035 | /* LDOVBBMPU_VSET_OUT */ |
| 1036 | ti,ldovbb-vset-mask = <0x1F>; |
| 1037 | |
| 1038 | /* |
| 1039 | * NOTE: only FBB mode used but actual vset will |
| 1040 | * determine final biasing |
| 1041 | */ |
| 1042 | ti,abb_info = < |
| 1043 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1044 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 1045 | 1250000 0 0x4 0 0x02000000 0x01F00000 |
| 1046 | >; |
| 1047 | }; |
| 1048 | |
| 1049 | abb_mm: regulator-abb-mm { |
| 1050 | compatible = "ti,abb-v2"; |
| 1051 | regulator-name = "abb_mm"; |
| 1052 | #address-cells = <0>; |
| 1053 | #size-cells = <0>; |
| 1054 | clocks = <&sys_clkin>; |
| 1055 | ti,settling-time = <50>; |
| 1056 | ti,clock-cycles = <16>; |
| 1057 | |
| 1058 | reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, |
| 1059 | <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; |
| 1060 | reg-names = "base-address", "int-address", |
| 1061 | "efuse-address", "ldo-address"; |
| 1062 | ti,tranxdone-status-mask = <0x80000000>; |
| 1063 | /* LDOVBBMM_MUX_CTRL */ |
| 1064 | ti,ldovbb-override-mask = <0x400>; |
| 1065 | /* LDOVBBMM_VSET_OUT */ |
| 1066 | ti,ldovbb-vset-mask = <0x1F>; |
| 1067 | |
| 1068 | /* |
| 1069 | * NOTE: only FBB mode used but actual vset will |
| 1070 | * determine final biasing |
| 1071 | */ |
| 1072 | ti,abb_info = < |
| 1073 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1074 | 1025000 0 0x0 0 0x02000000 0x01F00000 |
| 1075 | 1120000 0 0x4 0 0x02000000 0x01F00000 |
| 1076 | >; |
| 1077 | }; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1078 | }; |
| 1079 | }; |
Tero Kristo | 85dc74e | 2013-07-18 17:09:29 +0300 | [diff] [blame] | 1080 | |
| 1081 | /include/ "omap54xx-clocks.dtsi" |