Kumar Gala | 68de308 | 2014-03-07 10:56:59 -0600 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
| 3 | #include "skeleton.dtsi" |
| 4 | #include <dt-bindings/clock/qcom,gcc-ipq806x.h> |
| 5 | #include <dt-bindings/soc/qcom,gsbi.h> |
| 6 | |
| 7 | / { |
| 8 | model = "Qualcomm IPQ8064"; |
| 9 | compatible = "qcom,ipq8064"; |
| 10 | interrupt-parent = <&intc>; |
| 11 | |
| 12 | cpus { |
| 13 | #address-cells = <1>; |
| 14 | #size-cells = <0>; |
| 15 | |
| 16 | cpu@0 { |
| 17 | compatible = "qcom,krait"; |
| 18 | enable-method = "qcom,kpss-acc-v1"; |
| 19 | device_type = "cpu"; |
| 20 | reg = <0>; |
| 21 | next-level-cache = <&L2>; |
| 22 | qcom,acc = <&acc0>; |
| 23 | qcom,saw = <&saw0>; |
| 24 | }; |
| 25 | |
| 26 | cpu@1 { |
| 27 | compatible = "qcom,krait"; |
| 28 | enable-method = "qcom,kpss-acc-v1"; |
| 29 | device_type = "cpu"; |
| 30 | reg = <1>; |
| 31 | next-level-cache = <&L2>; |
| 32 | qcom,acc = <&acc1>; |
| 33 | qcom,saw = <&saw1>; |
| 34 | }; |
| 35 | |
| 36 | L2: l2-cache { |
| 37 | compatible = "cache"; |
| 38 | cache-level = <2>; |
| 39 | }; |
| 40 | }; |
| 41 | |
| 42 | cpu-pmu { |
| 43 | compatible = "qcom,krait-pmu"; |
| 44 | interrupts = <1 10 0x304>; |
| 45 | }; |
| 46 | |
| 47 | reserved-memory { |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | ranges; |
| 51 | |
| 52 | nss@40000000 { |
| 53 | reg = <0x40000000 0x1000000>; |
| 54 | no-map; |
| 55 | }; |
| 56 | |
| 57 | smem@41000000 { |
| 58 | reg = <0x41000000 0x200000>; |
| 59 | no-map; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | soc: soc { |
| 64 | #address-cells = <1>; |
| 65 | #size-cells = <1>; |
| 66 | ranges; |
| 67 | compatible = "simple-bus"; |
| 68 | |
| 69 | qcom_pinmux: pinmux@800000 { |
| 70 | compatible = "qcom,ipq8064-pinctrl"; |
| 71 | reg = <0x800000 0x4000>; |
| 72 | |
| 73 | gpio-controller; |
| 74 | #gpio-cells = <2>; |
| 75 | interrupt-controller; |
| 76 | #interrupt-cells = <2>; |
| 77 | interrupts = <0 32 0x4>; |
| 78 | }; |
| 79 | |
| 80 | intc: interrupt-controller@2000000 { |
| 81 | compatible = "qcom,msm-qgic2"; |
| 82 | interrupt-controller; |
| 83 | #interrupt-cells = <3>; |
| 84 | reg = <0x02000000 0x1000>, |
| 85 | <0x02002000 0x1000>; |
| 86 | }; |
| 87 | |
| 88 | timer@200a000 { |
| 89 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; |
| 90 | interrupts = <1 1 0x301>, |
| 91 | <1 2 0x301>, |
| 92 | <1 3 0x301>; |
| 93 | reg = <0x0200a000 0x100>; |
| 94 | clock-frequency = <25000000>, |
| 95 | <32768>; |
| 96 | cpu-offset = <0x80000>; |
| 97 | }; |
| 98 | |
| 99 | acc0: clock-controller@2088000 { |
| 100 | compatible = "qcom,kpss-acc-v1"; |
| 101 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; |
| 102 | }; |
| 103 | |
| 104 | acc1: clock-controller@2098000 { |
| 105 | compatible = "qcom,kpss-acc-v1"; |
| 106 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; |
| 107 | }; |
| 108 | |
| 109 | saw0: regulator@2089000 { |
| 110 | compatible = "qcom,saw2"; |
| 111 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
| 112 | regulator; |
| 113 | }; |
| 114 | |
| 115 | saw1: regulator@2099000 { |
| 116 | compatible = "qcom,saw2"; |
| 117 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
| 118 | regulator; |
| 119 | }; |
| 120 | |
| 121 | gsbi2: gsbi@12480000 { |
| 122 | compatible = "qcom,gsbi-v1.0.0"; |
| 123 | reg = <0x12480000 0x100>; |
| 124 | clocks = <&gcc GSBI2_H_CLK>; |
| 125 | clock-names = "iface"; |
| 126 | #address-cells = <1>; |
| 127 | #size-cells = <1>; |
| 128 | ranges; |
| 129 | status = "disabled"; |
| 130 | |
| 131 | serial@12490000 { |
| 132 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| 133 | reg = <0x12490000 0x1000>, |
| 134 | <0x12480000 0x1000>; |
| 135 | interrupts = <0 195 0x0>; |
| 136 | clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; |
| 137 | clock-names = "core", "iface"; |
| 138 | status = "disabled"; |
| 139 | }; |
| 140 | |
| 141 | i2c@124a0000 { |
| 142 | compatible = "qcom,i2c-qup-v1.1.1"; |
| 143 | reg = <0x124a0000 0x1000>; |
| 144 | interrupts = <0 196 0>; |
| 145 | |
| 146 | clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; |
| 147 | clock-names = "core", "iface"; |
| 148 | status = "disabled"; |
| 149 | |
| 150 | #address-cells = <1>; |
| 151 | #size-cells = <0>; |
| 152 | }; |
| 153 | |
| 154 | }; |
| 155 | |
| 156 | gsbi4: gsbi@16300000 { |
| 157 | compatible = "qcom,gsbi-v1.0.0"; |
| 158 | reg = <0x16300000 0x100>; |
| 159 | clocks = <&gcc GSBI4_H_CLK>; |
| 160 | clock-names = "iface"; |
| 161 | #address-cells = <1>; |
| 162 | #size-cells = <1>; |
| 163 | ranges; |
| 164 | status = "disabled"; |
| 165 | |
| 166 | serial@16340000 { |
| 167 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| 168 | reg = <0x16340000 0x1000>, |
| 169 | <0x16300000 0x1000>; |
| 170 | interrupts = <0 152 0x0>; |
| 171 | clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; |
| 172 | clock-names = "core", "iface"; |
| 173 | status = "disabled"; |
| 174 | }; |
| 175 | |
| 176 | i2c@16380000 { |
| 177 | compatible = "qcom,i2c-qup-v1.1.1"; |
| 178 | reg = <0x16380000 0x1000>; |
| 179 | interrupts = <0 153 0>; |
| 180 | |
| 181 | clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; |
| 182 | clock-names = "core", "iface"; |
| 183 | status = "disabled"; |
| 184 | |
| 185 | #address-cells = <1>; |
| 186 | #size-cells = <0>; |
| 187 | }; |
| 188 | }; |
| 189 | |
| 190 | gsbi5: gsbi@1a200000 { |
| 191 | compatible = "qcom,gsbi-v1.0.0"; |
| 192 | reg = <0x1a200000 0x100>; |
| 193 | clocks = <&gcc GSBI5_H_CLK>; |
| 194 | clock-names = "iface"; |
| 195 | #address-cells = <1>; |
| 196 | #size-cells = <1>; |
| 197 | ranges; |
| 198 | status = "disabled"; |
| 199 | |
| 200 | serial@1a240000 { |
| 201 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| 202 | reg = <0x1a240000 0x1000>, |
| 203 | <0x1a200000 0x1000>; |
| 204 | interrupts = <0 154 0x0>; |
| 205 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; |
| 206 | clock-names = "core", "iface"; |
| 207 | status = "disabled"; |
| 208 | }; |
| 209 | |
| 210 | i2c@1a280000 { |
| 211 | compatible = "qcom,i2c-qup-v1.1.1"; |
| 212 | reg = <0x1a280000 0x1000>; |
| 213 | interrupts = <0 155 0>; |
| 214 | |
| 215 | clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; |
| 216 | clock-names = "core", "iface"; |
| 217 | status = "disabled"; |
| 218 | |
| 219 | #address-cells = <1>; |
| 220 | #size-cells = <0>; |
| 221 | }; |
| 222 | |
| 223 | spi@1a280000 { |
| 224 | compatible = "qcom,spi-qup-v1.1.1"; |
| 225 | reg = <0x1a280000 0x1000>; |
| 226 | interrupts = <0 155 0>; |
| 227 | |
| 228 | clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; |
| 229 | clock-names = "core", "iface"; |
| 230 | status = "disabled"; |
| 231 | |
| 232 | #address-cells = <1>; |
| 233 | #size-cells = <0>; |
| 234 | }; |
| 235 | }; |
| 236 | |
Kumar Gala | e512448 | 2014-09-23 13:21:41 -0500 | [diff] [blame] | 237 | sata_phy: sata-phy@1b400000 { |
| 238 | compatible = "qcom,ipq806x-sata-phy"; |
| 239 | reg = <0x1b400000 0x200>; |
| 240 | |
| 241 | clocks = <&gcc SATA_PHY_CFG_CLK>; |
| 242 | clock-names = "cfg"; |
| 243 | |
| 244 | #phy-cells = <0>; |
| 245 | status = "disabled"; |
| 246 | }; |
| 247 | |
| 248 | sata@29000000 { |
| 249 | compatible = "qcom,ipq806x-ahci", "generic-ahci"; |
| 250 | reg = <0x29000000 0x180>; |
| 251 | |
| 252 | interrupts = <0 209 0x0>; |
| 253 | |
| 254 | clocks = <&gcc SFAB_SATA_S_H_CLK>, |
| 255 | <&gcc SATA_H_CLK>, |
| 256 | <&gcc SATA_A_CLK>, |
| 257 | <&gcc SATA_RXOOB_CLK>, |
| 258 | <&gcc SATA_PMALIVE_CLK>; |
| 259 | clock-names = "slave_face", "iface", "core", |
| 260 | "rxoob", "pmalive"; |
| 261 | |
| 262 | assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; |
| 263 | assigned-clock-rates = <100000000>, <100000000>; |
| 264 | |
| 265 | phys = <&sata_phy>; |
| 266 | phy-names = "sata-phy"; |
| 267 | status = "disabled"; |
| 268 | }; |
| 269 | |
Kumar Gala | 68de308 | 2014-03-07 10:56:59 -0600 | [diff] [blame] | 270 | qcom,ssbi@500000 { |
| 271 | compatible = "qcom,ssbi"; |
| 272 | reg = <0x00500000 0x1000>; |
| 273 | qcom,controller-type = "pmic-arbiter"; |
| 274 | }; |
| 275 | |
| 276 | gcc: clock-controller@900000 { |
| 277 | compatible = "qcom,gcc-ipq8064"; |
| 278 | reg = <0x00900000 0x4000>; |
| 279 | #clock-cells = <1>; |
| 280 | #reset-cells = <1>; |
| 281 | }; |
| 282 | }; |
| 283 | }; |