Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 1 | /* |
| 2 | * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with |
| 3 | * Gigabit Ethernet. |
| 4 | * |
| 5 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> |
| 6 | * |
| 7 | * Licensed under GPLv2. |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/pinctrl/at91.h> |
| 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | |
| 13 | / { |
| 14 | ahb { |
| 15 | apb { |
| 16 | pinctrl@fffff200 { |
| 17 | macb0 { |
| 18 | pinctrl_macb0_data_rgmii: macb0_data_rgmii { |
| 19 | atmel,pins = |
| 20 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ |
| 21 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ |
| 22 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ |
| 23 | AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ |
| 24 | AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ |
| 25 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ |
| 26 | AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ |
| 27 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ |
| 28 | }; |
| 29 | pinctrl_macb0_data_gmii: macb0_data_gmii { |
| 30 | atmel,pins = |
| 31 | <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ |
| 32 | AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ |
| 33 | AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ |
| 34 | AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ |
| 35 | AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ |
| 36 | AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ |
| 37 | AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ |
| 38 | AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ |
| 39 | }; |
| 40 | pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { |
| 41 | atmel,pins = |
| 42 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ |
| 43 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ |
| 44 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ |
| 45 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ |
| 46 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ |
| 47 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ |
| 48 | AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ |
| 49 | }; |
| 50 | pinctrl_macb0_signal_gmii: macb0_signal_gmii { |
| 51 | atmel,pins = |
| 52 | <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ |
| 53 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ |
| 54 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ |
| 55 | AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ |
| 56 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ |
| 57 | AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ |
| 58 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ |
| 59 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ |
| 60 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ |
| 61 | AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ |
| 62 | }; |
| 63 | |
| 64 | }; |
| 65 | }; |
| 66 | |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 67 | pmc: pmc@fffffc00 { |
| 68 | periphck { |
| 69 | macb0_clk: macb0_clk { |
| 70 | #clock-cells = <0>; |
| 71 | reg = <34>; |
| 72 | }; |
| 73 | }; |
| 74 | }; |
| 75 | |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 76 | macb0: ethernet@f0028000 { |
Cyrille Pitchen | d58c86ec | 2014-07-24 13:51:02 +0200 | [diff] [blame] | 77 | compatible = "atmel,sama5d3-gem"; |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 78 | reg = <0xf0028000 0x100>; |
| 79 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; |
| 80 | pinctrl-names = "default"; |
| 81 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 82 | clocks = <&macb0_clk>, <&macb0_clk>; |
| 83 | clock-names = "hclk", "pclk"; |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 84 | status = "disabled"; |
| 85 | }; |
| 86 | }; |
| 87 | }; |
| 88 | }; |