Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
Maxime Ripard | 394c56c | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 6 | * This file is dual-licensed: you can use it either under the terms |
| 7 | * of the GPL or the X11 license, at your option. Note that this dual |
| 8 | * licensing only applies to this file, and not this project as a |
| 9 | * whole. |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 10 | * |
Maxime Ripard | 394c56c | 2014-09-02 19:25:26 +0200 | [diff] [blame] | 11 | * a) This library is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of the |
| 14 | * License, or (at your option) any later version. |
| 15 | * |
| 16 | * This library is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public |
| 22 | * License along with this library; if not, write to the Free |
| 23 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 24 | * MA 02110-1301 USA |
| 25 | * |
| 26 | * Or, alternatively, |
| 27 | * |
| 28 | * b) Permission is hereby granted, free of charge, to any person |
| 29 | * obtaining a copy of this software and associated documentation |
| 30 | * files (the "Software"), to deal in the Software without |
| 31 | * restriction, including without limitation the rights to use, |
| 32 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 33 | * sell copies of the Software, and to permit persons to whom the |
| 34 | * Software is furnished to do so, subject to the following |
| 35 | * conditions: |
| 36 | * |
| 37 | * The above copyright notice and this permission notice shall be |
| 38 | * included in all copies or substantial portions of the Software. |
| 39 | * |
| 40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 47 | * OTHER DEALINGS IN THE SOFTWARE. |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 48 | */ |
| 49 | |
| 50 | /include/ "skeleton.dtsi" |
| 51 | |
| 52 | / { |
| 53 | interrupt-parent = <&gic>; |
| 54 | |
Emilio López | e751cce | 2013-11-16 15:17:29 -0300 | [diff] [blame] | 55 | aliases { |
Chen-Yu Tsai | 18428f7 | 2014-02-10 18:35:54 +0800 | [diff] [blame] | 56 | ethernet0 = &gmac; |
Maxime Ripard | 4566b4b | 2014-01-02 22:05:04 +0100 | [diff] [blame] | 57 | serial0 = &uart0; |
| 58 | serial1 = &uart1; |
| 59 | serial2 = &uart2; |
| 60 | serial3 = &uart3; |
| 61 | serial4 = &uart4; |
| 62 | serial5 = &uart5; |
| 63 | serial6 = &uart6; |
| 64 | serial7 = &uart7; |
Emilio López | e751cce | 2013-11-16 15:17:29 -0300 | [diff] [blame] | 65 | }; |
| 66 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 67 | cpus { |
| 68 | #address-cells = <1>; |
| 69 | #size-cells = <0>; |
| 70 | |
| 71 | cpu@0 { |
| 72 | compatible = "arm,cortex-a7"; |
| 73 | device_type = "cpu"; |
| 74 | reg = <0>; |
| 75 | }; |
| 76 | |
| 77 | cpu@1 { |
| 78 | compatible = "arm,cortex-a7"; |
| 79 | device_type = "cpu"; |
| 80 | reg = <1>; |
| 81 | }; |
| 82 | }; |
| 83 | |
| 84 | memory { |
| 85 | reg = <0x40000000 0x80000000>; |
| 86 | }; |
| 87 | |
Marc Zyngier | 7902763 | 2014-02-18 14:04:44 +0000 | [diff] [blame] | 88 | timer { |
| 89 | compatible = "arm,armv7-timer"; |
| 90 | interrupts = <1 13 0xf08>, |
| 91 | <1 14 0xf08>, |
| 92 | <1 11 0xf08>, |
| 93 | <1 10 0xf08>; |
| 94 | }; |
| 95 | |
Maxime Ripard | e29ea4d | 2014-04-17 21:54:41 +0200 | [diff] [blame] | 96 | pmu { |
| 97 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; |
| 98 | interrupts = <0 120 4>, |
| 99 | <0 121 4>; |
| 100 | }; |
| 101 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 102 | clocks { |
| 103 | #address-cells = <1>; |
| 104 | #size-cells = <1>; |
| 105 | ranges; |
| 106 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 107 | osc24M: clk@01c20050 { |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 108 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 109 | compatible = "allwinner,sun4i-a10-osc-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 110 | reg = <0x01c20050 0x4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 111 | clock-frequency = <24000000>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 112 | clock-output-names = "osc24M"; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 113 | }; |
| 114 | |
Chen-Yu Tsai | 673fac7 | 2014-01-01 10:30:47 +0800 | [diff] [blame] | 115 | osc32k: clk@0 { |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 116 | #clock-cells = <0>; |
| 117 | compatible = "fixed-clock"; |
| 118 | clock-frequency = <32768>; |
Chen-Yu Tsai | 673fac7 | 2014-01-01 10:30:47 +0800 | [diff] [blame] | 119 | clock-output-names = "osc32k"; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 120 | }; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 121 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 122 | pll1: clk@01c20000 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 123 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 124 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 125 | reg = <0x01c20000 0x4>; |
| 126 | clocks = <&osc24M>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 127 | clock-output-names = "pll1"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 128 | }; |
| 129 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 130 | pll4: clk@01c20018 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 131 | #clock-cells = <0>; |
Emilio López | 04ebcb5 | 2014-03-19 15:19:31 -0300 | [diff] [blame] | 132 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 133 | reg = <0x01c20018 0x4>; |
| 134 | clocks = <&osc24M>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 135 | clock-output-names = "pll4"; |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 136 | }; |
| 137 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 138 | pll5: clk@01c20020 { |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 139 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 140 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 141 | reg = <0x01c20020 0x4>; |
| 142 | clocks = <&osc24M>; |
| 143 | clock-output-names = "pll5_ddr", "pll5_other"; |
| 144 | }; |
| 145 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 146 | pll6: clk@01c20028 { |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 147 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 148 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 149 | reg = <0x01c20028 0x4>; |
| 150 | clocks = <&osc24M>; |
| 151 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 152 | }; |
| 153 | |
Emilio López | 04ebcb5 | 2014-03-19 15:19:31 -0300 | [diff] [blame] | 154 | pll8: clk@01c20040 { |
| 155 | #clock-cells = <0>; |
| 156 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
| 157 | reg = <0x01c20040 0x4>; |
| 158 | clocks = <&osc24M>; |
| 159 | clock-output-names = "pll8"; |
| 160 | }; |
| 161 | |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 162 | cpu: cpu@01c20054 { |
| 163 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 164 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 165 | reg = <0x01c20054 0x4>; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 166 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 167 | clock-output-names = "cpu"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 168 | }; |
| 169 | |
| 170 | axi: axi@01c20054 { |
| 171 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 172 | compatible = "allwinner,sun4i-a10-axi-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 173 | reg = <0x01c20054 0x4>; |
| 174 | clocks = <&cpu>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 175 | clock-output-names = "axi"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | ahb: ahb@01c20054 { |
| 179 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 180 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 181 | reg = <0x01c20054 0x4>; |
| 182 | clocks = <&axi>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 183 | clock-output-names = "ahb"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 184 | }; |
| 185 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 186 | ahb_gates: clk@01c20060 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 187 | #clock-cells = <1>; |
| 188 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; |
| 189 | reg = <0x01c20060 0x8>; |
| 190 | clocks = <&ahb>; |
| 191 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
| 192 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", |
| 193 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", |
| 194 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", |
| 195 | "ahb_nand", "ahb_sdram", "ahb_ace", |
| 196 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", |
| 197 | "ahb_spi2", "ahb_spi3", "ahb_sata", |
| 198 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", |
| 199 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", |
| 200 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", |
| 201 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", |
| 202 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", |
| 203 | "ahb_mali"; |
| 204 | }; |
| 205 | |
| 206 | apb0: apb0@01c20054 { |
| 207 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 208 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 209 | reg = <0x01c20054 0x4>; |
| 210 | clocks = <&ahb>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 211 | clock-output-names = "apb0"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 212 | }; |
| 213 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 214 | apb0_gates: clk@01c20068 { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 215 | #clock-cells = <1>; |
| 216 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; |
| 217 | reg = <0x01c20068 0x4>; |
| 218 | clocks = <&apb0>; |
| 219 | clock-output-names = "apb0_codec", "apb0_spdif", |
| 220 | "apb0_ac97", "apb0_iis0", "apb0_iis1", |
| 221 | "apb0_pio", "apb0_ir0", "apb0_ir1", |
| 222 | "apb0_iis2", "apb0_keypad"; |
| 223 | }; |
| 224 | |
| 225 | apb1_mux: apb1_mux@01c20058 { |
| 226 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 227 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 228 | reg = <0x01c20058 0x4>; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 229 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 230 | clock-output-names = "apb1_mux"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 231 | }; |
| 232 | |
| 233 | apb1: apb1@01c20058 { |
| 234 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 235 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 236 | reg = <0x01c20058 0x4>; |
| 237 | clocks = <&apb1_mux>; |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 238 | clock-output-names = "apb1"; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 239 | }; |
| 240 | |
Chen-Yu Tsai | 06067a2 | 2014-02-03 09:51:44 +0800 | [diff] [blame] | 241 | apb1_gates: clk@01c2006c { |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 242 | #clock-cells = <1>; |
| 243 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; |
| 244 | reg = <0x01c2006c 0x4>; |
| 245 | clocks = <&apb1>; |
| 246 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
| 247 | "apb1_i2c2", "apb1_i2c3", "apb1_can", |
| 248 | "apb1_scr", "apb1_ps20", "apb1_ps21", |
| 249 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", |
| 250 | "apb1_uart2", "apb1_uart3", "apb1_uart4", |
| 251 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; |
| 252 | }; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 253 | |
| 254 | nand_clk: clk@01c20080 { |
| 255 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 256 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 257 | reg = <0x01c20080 0x4>; |
| 258 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 259 | clock-output-names = "nand"; |
| 260 | }; |
| 261 | |
| 262 | ms_clk: clk@01c20084 { |
| 263 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 264 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 265 | reg = <0x01c20084 0x4>; |
| 266 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 267 | clock-output-names = "ms"; |
| 268 | }; |
| 269 | |
| 270 | mmc0_clk: clk@01c20088 { |
| 271 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 272 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 273 | reg = <0x01c20088 0x4>; |
| 274 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 275 | clock-output-names = "mmc0"; |
| 276 | }; |
| 277 | |
| 278 | mmc1_clk: clk@01c2008c { |
| 279 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 280 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 281 | reg = <0x01c2008c 0x4>; |
| 282 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 283 | clock-output-names = "mmc1"; |
| 284 | }; |
| 285 | |
| 286 | mmc2_clk: clk@01c20090 { |
| 287 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 288 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 289 | reg = <0x01c20090 0x4>; |
| 290 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 291 | clock-output-names = "mmc2"; |
| 292 | }; |
| 293 | |
| 294 | mmc3_clk: clk@01c20094 { |
| 295 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 296 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 297 | reg = <0x01c20094 0x4>; |
| 298 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 299 | clock-output-names = "mmc3"; |
| 300 | }; |
| 301 | |
| 302 | ts_clk: clk@01c20098 { |
| 303 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 304 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 305 | reg = <0x01c20098 0x4>; |
| 306 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 307 | clock-output-names = "ts"; |
| 308 | }; |
| 309 | |
| 310 | ss_clk: clk@01c2009c { |
| 311 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 312 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 313 | reg = <0x01c2009c 0x4>; |
| 314 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 315 | clock-output-names = "ss"; |
| 316 | }; |
| 317 | |
| 318 | spi0_clk: clk@01c200a0 { |
| 319 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 320 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 321 | reg = <0x01c200a0 0x4>; |
| 322 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 323 | clock-output-names = "spi0"; |
| 324 | }; |
| 325 | |
| 326 | spi1_clk: clk@01c200a4 { |
| 327 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 328 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 329 | reg = <0x01c200a4 0x4>; |
| 330 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 331 | clock-output-names = "spi1"; |
| 332 | }; |
| 333 | |
| 334 | spi2_clk: clk@01c200a8 { |
| 335 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 336 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 337 | reg = <0x01c200a8 0x4>; |
| 338 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 339 | clock-output-names = "spi2"; |
| 340 | }; |
| 341 | |
| 342 | pata_clk: clk@01c200ac { |
| 343 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 344 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 345 | reg = <0x01c200ac 0x4>; |
| 346 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 347 | clock-output-names = "pata"; |
| 348 | }; |
| 349 | |
| 350 | ir0_clk: clk@01c200b0 { |
| 351 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 352 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 353 | reg = <0x01c200b0 0x4>; |
| 354 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 355 | clock-output-names = "ir0"; |
| 356 | }; |
| 357 | |
| 358 | ir1_clk: clk@01c200b4 { |
| 359 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 360 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 361 | reg = <0x01c200b4 0x4>; |
| 362 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 363 | clock-output-names = "ir1"; |
| 364 | }; |
| 365 | |
Roman Byshko | 434e41b | 2014-02-07 16:21:53 +0100 | [diff] [blame] | 366 | usb_clk: clk@01c200cc { |
| 367 | #clock-cells = <1>; |
| 368 | #reset-cells = <1>; |
| 369 | compatible = "allwinner,sun4i-a10-usb-clk"; |
| 370 | reg = <0x01c200cc 0x4>; |
| 371 | clocks = <&pll6 1>; |
| 372 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; |
| 373 | }; |
| 374 | |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 375 | spi3_clk: clk@01c200d4 { |
| 376 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 377 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 1c92b95 | 2013-12-23 00:32:43 -0300 | [diff] [blame] | 378 | reg = <0x01c200d4 0x4>; |
| 379 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 380 | clock-output-names = "spi3"; |
| 381 | }; |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 382 | |
| 383 | mbus_clk: clk@01c2015c { |
| 384 | #clock-cells = <0>; |
Maxime Ripard | 7868c5e | 2014-07-16 23:45:48 +0200 | [diff] [blame] | 385 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 386 | reg = <0x01c2015c 0x4>; |
| 387 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; |
| 388 | clock-output-names = "mbus"; |
| 389 | }; |
Chen-Yu Tsai | 0aff037 | 2014-01-01 10:30:48 +0800 | [diff] [blame] | 390 | |
| 391 | /* |
Chen-Yu Tsai | daed5a8 | 2014-02-10 18:35:48 +0800 | [diff] [blame] | 392 | * The following two are dummy clocks, placeholders used in the gmac_tx |
| 393 | * clock. The gmac driver will choose one parent depending on the PHY |
| 394 | * interface mode, using clk_set_rate auto-reparenting. |
| 395 | * The actual TX clock rate is not controlled by the gmac_tx clock. |
| 396 | */ |
| 397 | mii_phy_tx_clk: clk@2 { |
| 398 | #clock-cells = <0>; |
| 399 | compatible = "fixed-clock"; |
| 400 | clock-frequency = <25000000>; |
| 401 | clock-output-names = "mii_phy_tx"; |
| 402 | }; |
| 403 | |
| 404 | gmac_int_tx_clk: clk@3 { |
| 405 | #clock-cells = <0>; |
| 406 | compatible = "fixed-clock"; |
| 407 | clock-frequency = <125000000>; |
| 408 | clock-output-names = "gmac_int_tx"; |
| 409 | }; |
| 410 | |
| 411 | gmac_tx_clk: clk@01c20164 { |
| 412 | #clock-cells = <0>; |
| 413 | compatible = "allwinner,sun7i-a20-gmac-clk"; |
| 414 | reg = <0x01c20164 0x4>; |
| 415 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; |
| 416 | clock-output-names = "gmac_tx"; |
| 417 | }; |
| 418 | |
| 419 | /* |
Chen-Yu Tsai | 0aff037 | 2014-01-01 10:30:48 +0800 | [diff] [blame] | 420 | * Dummy clock used by output clocks |
| 421 | */ |
| 422 | osc24M_32k: clk@1 { |
| 423 | #clock-cells = <0>; |
| 424 | compatible = "fixed-factor-clock"; |
| 425 | clock-div = <750>; |
| 426 | clock-mult = <1>; |
| 427 | clocks = <&osc24M>; |
| 428 | clock-output-names = "osc24M_32k"; |
| 429 | }; |
| 430 | |
| 431 | clk_out_a: clk@01c201f0 { |
| 432 | #clock-cells = <0>; |
| 433 | compatible = "allwinner,sun7i-a20-out-clk"; |
| 434 | reg = <0x01c201f0 0x4>; |
| 435 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; |
| 436 | clock-output-names = "clk_out_a"; |
| 437 | }; |
| 438 | |
| 439 | clk_out_b: clk@01c201f4 { |
| 440 | #clock-cells = <0>; |
| 441 | compatible = "allwinner,sun7i-a20-out-clk"; |
| 442 | reg = <0x01c201f4 0x4>; |
| 443 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; |
| 444 | clock-output-names = "clk_out_b"; |
| 445 | }; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 446 | }; |
| 447 | |
| 448 | soc@01c00000 { |
| 449 | compatible = "simple-bus"; |
| 450 | #address-cells = <1>; |
| 451 | #size-cells = <1>; |
| 452 | ranges; |
| 453 | |
Carlo Caione | 8ff973a | 2014-03-19 20:21:18 +0100 | [diff] [blame] | 454 | nmi_intc: interrupt-controller@01c00030 { |
| 455 | compatible = "allwinner,sun7i-a20-sc-nmi"; |
| 456 | interrupt-controller; |
| 457 | #interrupt-cells = <2>; |
| 458 | reg = <0x01c00030 0x0c>; |
| 459 | interrupts = <0 0 4>; |
| 460 | }; |
| 461 | |
Emilio López | 316e0b0 | 2014-08-04 17:09:59 -0300 | [diff] [blame] | 462 | dma: dma-controller@01c02000 { |
| 463 | compatible = "allwinner,sun4i-a10-dma"; |
| 464 | reg = <0x01c02000 0x1000>; |
| 465 | interrupts = <0 27 4>; |
| 466 | clocks = <&ahb_gates 6>; |
| 467 | #dma-cells = <2>; |
| 468 | }; |
| 469 | |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 470 | spi0: spi@01c05000 { |
| 471 | compatible = "allwinner,sun4i-a10-spi"; |
| 472 | reg = <0x01c05000 0x1000>; |
| 473 | interrupts = <0 10 4>; |
| 474 | clocks = <&ahb_gates 20>, <&spi0_clk>; |
| 475 | clock-names = "ahb", "mod"; |
Emilio López | ffec721 | 2014-08-04 17:10:02 -0300 | [diff] [blame] | 476 | dmas = <&dma 1 27>, <&dma 1 26>; |
| 477 | dma-names = "rx", "tx"; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 478 | status = "disabled"; |
| 479 | #address-cells = <1>; |
| 480 | #size-cells = <0>; |
| 481 | }; |
| 482 | |
| 483 | spi1: spi@01c06000 { |
| 484 | compatible = "allwinner,sun4i-a10-spi"; |
| 485 | reg = <0x01c06000 0x1000>; |
| 486 | interrupts = <0 11 4>; |
| 487 | clocks = <&ahb_gates 21>, <&spi1_clk>; |
| 488 | clock-names = "ahb", "mod"; |
Emilio López | ffec721 | 2014-08-04 17:10:02 -0300 | [diff] [blame] | 489 | dmas = <&dma 1 9>, <&dma 1 8>; |
| 490 | dma-names = "rx", "tx"; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 491 | status = "disabled"; |
| 492 | #address-cells = <1>; |
| 493 | #size-cells = <0>; |
| 494 | }; |
| 495 | |
Maxime Ripard | 2e804d0 | 2013-09-11 11:10:06 +0200 | [diff] [blame] | 496 | emac: ethernet@01c0b000 { |
Maxime Ripard | 1c70e09 | 2014-02-02 14:49:13 +0100 | [diff] [blame] | 497 | compatible = "allwinner,sun4i-a10-emac"; |
Maxime Ripard | 2e804d0 | 2013-09-11 11:10:06 +0200 | [diff] [blame] | 498 | reg = <0x01c0b000 0x1000>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 499 | interrupts = <0 55 4>; |
Maxime Ripard | 2e804d0 | 2013-09-11 11:10:06 +0200 | [diff] [blame] | 500 | clocks = <&ahb_gates 17>; |
| 501 | status = "disabled"; |
| 502 | }; |
| 503 | |
| 504 | mdio@01c0b080 { |
Maxime Ripard | 1c70e09 | 2014-02-02 14:49:13 +0100 | [diff] [blame] | 505 | compatible = "allwinner,sun4i-a10-mdio"; |
Maxime Ripard | 2e804d0 | 2013-09-11 11:10:06 +0200 | [diff] [blame] | 506 | reg = <0x01c0b080 0x14>; |
| 507 | status = "disabled"; |
| 508 | #address-cells = <1>; |
| 509 | #size-cells = <0>; |
| 510 | }; |
| 511 | |
Hans de Goede | dd29ce5 | 2014-05-02 17:57:26 +0200 | [diff] [blame] | 512 | mmc0: mmc@01c0f000 { |
| 513 | compatible = "allwinner,sun5i-a13-mmc"; |
| 514 | reg = <0x01c0f000 0x1000>; |
| 515 | clocks = <&ahb_gates 8>, <&mmc0_clk>; |
| 516 | clock-names = "ahb", "mmc"; |
| 517 | interrupts = <0 32 4>; |
| 518 | status = "disabled"; |
| 519 | }; |
| 520 | |
| 521 | mmc1: mmc@01c10000 { |
| 522 | compatible = "allwinner,sun5i-a13-mmc"; |
| 523 | reg = <0x01c10000 0x1000>; |
| 524 | clocks = <&ahb_gates 9>, <&mmc1_clk>; |
| 525 | clock-names = "ahb", "mmc"; |
| 526 | interrupts = <0 33 4>; |
| 527 | status = "disabled"; |
| 528 | }; |
| 529 | |
| 530 | mmc2: mmc@01c11000 { |
| 531 | compatible = "allwinner,sun5i-a13-mmc"; |
| 532 | reg = <0x01c11000 0x1000>; |
| 533 | clocks = <&ahb_gates 10>, <&mmc2_clk>; |
| 534 | clock-names = "ahb", "mmc"; |
| 535 | interrupts = <0 34 4>; |
| 536 | status = "disabled"; |
| 537 | }; |
| 538 | |
| 539 | mmc3: mmc@01c12000 { |
| 540 | compatible = "allwinner,sun5i-a13-mmc"; |
| 541 | reg = <0x01c12000 0x1000>; |
| 542 | clocks = <&ahb_gates 11>, <&mmc3_clk>; |
| 543 | clock-names = "ahb", "mmc"; |
| 544 | interrupts = <0 35 4>; |
| 545 | status = "disabled"; |
| 546 | }; |
| 547 | |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 548 | usbphy: phy@01c13400 { |
| 549 | #phy-cells = <1>; |
| 550 | compatible = "allwinner,sun7i-a20-usb-phy"; |
| 551 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; |
| 552 | reg-names = "phy_ctrl", "pmu1", "pmu2"; |
| 553 | clocks = <&usb_clk 8>; |
| 554 | clock-names = "usb_phy"; |
| 555 | resets = <&usb_clk 1>, <&usb_clk 2>; |
| 556 | reset-names = "usb1_reset", "usb2_reset"; |
| 557 | status = "disabled"; |
| 558 | }; |
| 559 | |
| 560 | ehci0: usb@01c14000 { |
| 561 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; |
| 562 | reg = <0x01c14000 0x100>; |
| 563 | interrupts = <0 39 4>; |
| 564 | clocks = <&ahb_gates 1>; |
| 565 | phys = <&usbphy 1>; |
| 566 | phy-names = "usb"; |
| 567 | status = "disabled"; |
| 568 | }; |
| 569 | |
| 570 | ohci0: usb@01c14400 { |
| 571 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; |
| 572 | reg = <0x01c14400 0x100>; |
| 573 | interrupts = <0 64 4>; |
| 574 | clocks = <&usb_clk 6>, <&ahb_gates 2>; |
| 575 | phys = <&usbphy 1>; |
| 576 | phy-names = "usb"; |
| 577 | status = "disabled"; |
| 578 | }; |
| 579 | |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 580 | spi2: spi@01c17000 { |
| 581 | compatible = "allwinner,sun4i-a10-spi"; |
| 582 | reg = <0x01c17000 0x1000>; |
| 583 | interrupts = <0 12 4>; |
| 584 | clocks = <&ahb_gates 22>, <&spi2_clk>; |
| 585 | clock-names = "ahb", "mod"; |
Emilio López | ffec721 | 2014-08-04 17:10:02 -0300 | [diff] [blame] | 586 | dmas = <&dma 1 29>, <&dma 1 28>; |
| 587 | dma-names = "rx", "tx"; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 588 | status = "disabled"; |
| 589 | #address-cells = <1>; |
| 590 | #size-cells = <0>; |
| 591 | }; |
| 592 | |
Hans de Goede | 902febf | 2014-03-01 20:26:22 +0100 | [diff] [blame] | 593 | ahci: sata@01c18000 { |
| 594 | compatible = "allwinner,sun4i-a10-ahci"; |
| 595 | reg = <0x01c18000 0x1000>; |
| 596 | interrupts = <0 56 4>; |
| 597 | clocks = <&pll6 0>, <&ahb_gates 25>; |
| 598 | status = "disabled"; |
| 599 | }; |
| 600 | |
Roman Byshko | 9debd0a | 2014-03-01 20:26:25 +0100 | [diff] [blame] | 601 | ehci1: usb@01c1c000 { |
| 602 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; |
| 603 | reg = <0x01c1c000 0x100>; |
| 604 | interrupts = <0 40 4>; |
| 605 | clocks = <&ahb_gates 3>; |
| 606 | phys = <&usbphy 2>; |
| 607 | phy-names = "usb"; |
| 608 | status = "disabled"; |
| 609 | }; |
| 610 | |
| 611 | ohci1: usb@01c1c400 { |
| 612 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; |
| 613 | reg = <0x01c1c400 0x100>; |
| 614 | interrupts = <0 65 4>; |
| 615 | clocks = <&usb_clk 7>, <&ahb_gates 4>; |
| 616 | phys = <&usbphy 2>; |
| 617 | phy-names = "usb"; |
| 618 | status = "disabled"; |
| 619 | }; |
| 620 | |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 621 | spi3: spi@01c1f000 { |
| 622 | compatible = "allwinner,sun4i-a10-spi"; |
| 623 | reg = <0x01c1f000 0x1000>; |
| 624 | interrupts = <0 50 4>; |
| 625 | clocks = <&ahb_gates 23>, <&spi3_clk>; |
| 626 | clock-names = "ahb", "mod"; |
Emilio López | ffec721 | 2014-08-04 17:10:02 -0300 | [diff] [blame] | 627 | dmas = <&dma 1 31>, <&dma 1 30>; |
| 628 | dma-names = "rx", "tx"; |
Maxime Ripard | 36ab3e7 | 2014-02-22 22:35:54 +0100 | [diff] [blame] | 629 | status = "disabled"; |
| 630 | #address-cells = <1>; |
| 631 | #size-cells = <0>; |
| 632 | }; |
| 633 | |
Maxime Ripard | 17eac03 | 2013-07-24 23:46:11 +0200 | [diff] [blame] | 634 | pio: pinctrl@01c20800 { |
| 635 | compatible = "allwinner,sun7i-a20-pinctrl"; |
| 636 | reg = <0x01c20800 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 637 | interrupts = <0 28 4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 638 | clocks = <&apb0_gates 5>; |
Maxime Ripard | 17eac03 | 2013-07-24 23:46:11 +0200 | [diff] [blame] | 639 | gpio-controller; |
| 640 | interrupt-controller; |
Chen-Yu Tsai | 7d4ff96 | 2014-06-30 23:57:51 +0200 | [diff] [blame] | 641 | #interrupt-cells = <2>; |
Maxime Ripard | 17eac03 | 2013-07-24 23:46:11 +0200 | [diff] [blame] | 642 | #size-cells = <0>; |
| 643 | #gpio-cells = <3>; |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 644 | |
Alexandre Belloni | fd7898a | 2014-04-28 18:17:12 +0200 | [diff] [blame] | 645 | pwm0_pins_a: pwm0@0 { |
| 646 | allwinner,pins = "PB2"; |
| 647 | allwinner,function = "pwm"; |
| 648 | allwinner,drive = <0>; |
| 649 | allwinner,pull = <0>; |
| 650 | }; |
| 651 | |
| 652 | pwm1_pins_a: pwm1@0 { |
| 653 | allwinner,pins = "PI3"; |
| 654 | allwinner,function = "pwm"; |
| 655 | allwinner,drive = <0>; |
| 656 | allwinner,pull = <0>; |
| 657 | }; |
| 658 | |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 659 | uart0_pins_a: uart0@0 { |
| 660 | allwinner,pins = "PB22", "PB23"; |
| 661 | allwinner,function = "uart0"; |
| 662 | allwinner,drive = <0>; |
| 663 | allwinner,pull = <0>; |
| 664 | }; |
| 665 | |
Chen-Yu Tsai | 4261ec4 | 2014-01-14 22:49:50 +0800 | [diff] [blame] | 666 | uart2_pins_a: uart2@0 { |
| 667 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; |
| 668 | allwinner,function = "uart2"; |
| 669 | allwinner,drive = <0>; |
| 670 | allwinner,pull = <0>; |
| 671 | }; |
| 672 | |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 673 | uart3_pins_a: uart3@0 { |
| 674 | allwinner,pins = "PG6", "PG7", "PG8", "PG9"; |
| 675 | allwinner,function = "uart3"; |
| 676 | allwinner,drive = <0>; |
| 677 | allwinner,pull = <0>; |
| 678 | }; |
| 679 | |
| 680 | uart4_pins_a: uart4@0 { |
| 681 | allwinner,pins = "PG10", "PG11"; |
| 682 | allwinner,function = "uart4"; |
| 683 | allwinner,drive = <0>; |
| 684 | allwinner,pull = <0>; |
| 685 | }; |
| 686 | |
| 687 | uart5_pins_a: uart5@0 { |
| 688 | allwinner,pins = "PI10", "PI11"; |
| 689 | allwinner,function = "uart5"; |
| 690 | allwinner,drive = <0>; |
| 691 | allwinner,pull = <0>; |
| 692 | }; |
| 693 | |
Maxime Ripard | 9f229ba | 2013-07-25 00:09:47 +0200 | [diff] [blame] | 694 | uart6_pins_a: uart6@0 { |
| 695 | allwinner,pins = "PI12", "PI13"; |
| 696 | allwinner,function = "uart6"; |
| 697 | allwinner,drive = <0>; |
| 698 | allwinner,pull = <0>; |
| 699 | }; |
| 700 | |
| 701 | uart7_pins_a: uart7@0 { |
| 702 | allwinner,pins = "PI20", "PI21"; |
| 703 | allwinner,function = "uart7"; |
| 704 | allwinner,drive = <0>; |
| 705 | allwinner,pull = <0>; |
| 706 | }; |
Maxime Ripard | 756084c | 2013-09-11 11:10:07 +0200 | [diff] [blame] | 707 | |
Maxime Ripard | e5496a3 | 2013-08-31 23:08:49 +0200 | [diff] [blame] | 708 | i2c0_pins_a: i2c0@0 { |
| 709 | allwinner,pins = "PB0", "PB1"; |
| 710 | allwinner,function = "i2c0"; |
| 711 | allwinner,drive = <0>; |
| 712 | allwinner,pull = <0>; |
| 713 | }; |
| 714 | |
| 715 | i2c1_pins_a: i2c1@0 { |
| 716 | allwinner,pins = "PB18", "PB19"; |
| 717 | allwinner,function = "i2c1"; |
| 718 | allwinner,drive = <0>; |
| 719 | allwinner,pull = <0>; |
| 720 | }; |
| 721 | |
| 722 | i2c2_pins_a: i2c2@0 { |
| 723 | allwinner,pins = "PB20", "PB21"; |
| 724 | allwinner,function = "i2c2"; |
| 725 | allwinner,drive = <0>; |
| 726 | allwinner,pull = <0>; |
| 727 | }; |
| 728 | |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 729 | i2c3_pins_a: i2c3@0 { |
| 730 | allwinner,pins = "PI0", "PI1"; |
| 731 | allwinner,function = "i2c3"; |
| 732 | allwinner,drive = <0>; |
| 733 | allwinner,pull = <0>; |
| 734 | }; |
| 735 | |
Maxime Ripard | 756084c | 2013-09-11 11:10:07 +0200 | [diff] [blame] | 736 | emac_pins_a: emac0@0 { |
| 737 | allwinner,pins = "PA0", "PA1", "PA2", |
| 738 | "PA3", "PA4", "PA5", "PA6", |
| 739 | "PA7", "PA8", "PA9", "PA10", |
| 740 | "PA11", "PA12", "PA13", "PA14", |
| 741 | "PA15", "PA16"; |
| 742 | allwinner,function = "emac"; |
| 743 | allwinner,drive = <0>; |
| 744 | allwinner,pull = <0>; |
| 745 | }; |
Chen-Yu Tsai | f2e0759 | 2014-01-01 10:30:50 +0800 | [diff] [blame] | 746 | |
| 747 | clk_out_a_pins_a: clk_out_a@0 { |
| 748 | allwinner,pins = "PI12"; |
| 749 | allwinner,function = "clk_out_a"; |
| 750 | allwinner,drive = <0>; |
| 751 | allwinner,pull = <0>; |
| 752 | }; |
| 753 | |
| 754 | clk_out_b_pins_a: clk_out_b@0 { |
| 755 | allwinner,pins = "PI13"; |
| 756 | allwinner,function = "clk_out_b"; |
| 757 | allwinner,drive = <0>; |
| 758 | allwinner,pull = <0>; |
| 759 | }; |
Chen-Yu Tsai | 129ccbc | 2014-02-10 18:35:50 +0800 | [diff] [blame] | 760 | |
| 761 | gmac_pins_mii_a: gmac_mii@0 { |
| 762 | allwinner,pins = "PA0", "PA1", "PA2", |
| 763 | "PA3", "PA4", "PA5", "PA6", |
| 764 | "PA7", "PA8", "PA9", "PA10", |
| 765 | "PA11", "PA12", "PA13", "PA14", |
| 766 | "PA15", "PA16"; |
| 767 | allwinner,function = "gmac"; |
| 768 | allwinner,drive = <0>; |
| 769 | allwinner,pull = <0>; |
| 770 | }; |
| 771 | |
| 772 | gmac_pins_rgmii_a: gmac_rgmii@0 { |
| 773 | allwinner,pins = "PA0", "PA1", "PA2", |
| 774 | "PA3", "PA4", "PA5", "PA6", |
| 775 | "PA7", "PA8", "PA10", |
| 776 | "PA11", "PA12", "PA13", |
| 777 | "PA15", "PA16"; |
| 778 | allwinner,function = "gmac"; |
| 779 | /* |
| 780 | * data lines in RGMII mode use DDR mode |
| 781 | * and need a higher signal drive strength |
| 782 | */ |
| 783 | allwinner,drive = <3>; |
| 784 | allwinner,pull = <0>; |
| 785 | }; |
Maxime Ripard | 412f2c6 | 2014-02-22 22:35:58 +0100 | [diff] [blame] | 786 | |
| 787 | spi1_pins_a: spi1@0 { |
| 788 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; |
| 789 | allwinner,function = "spi1"; |
| 790 | allwinner,drive = <0>; |
| 791 | allwinner,pull = <0>; |
| 792 | }; |
| 793 | |
| 794 | spi2_pins_a: spi2@0 { |
| 795 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; |
| 796 | allwinner,function = "spi2"; |
| 797 | allwinner,drive = <0>; |
| 798 | allwinner,pull = <0>; |
| 799 | }; |
Hans de Goede | 11fbedf | 2014-05-02 17:57:27 +0200 | [diff] [blame] | 800 | |
Wills Wang | 7b5bace | 2014-08-19 15:33:00 +0800 | [diff] [blame] | 801 | spi2_pins_b: spi2@1 { |
| 802 | allwinner,pins = "PB14", "PB15", "PB16", "PB17"; |
| 803 | allwinner,function = "spi2"; |
| 804 | allwinner,drive = <0>; |
| 805 | allwinner,pull = <0>; |
| 806 | }; |
| 807 | |
Hans de Goede | 11fbedf | 2014-05-02 17:57:27 +0200 | [diff] [blame] | 808 | mmc0_pins_a: mmc0@0 { |
| 809 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; |
| 810 | allwinner,function = "mmc0"; |
| 811 | allwinner,drive = <2>; |
| 812 | allwinner,pull = <0>; |
| 813 | }; |
| 814 | |
| 815 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { |
| 816 | allwinner,pins = "PH1"; |
| 817 | allwinner,function = "gpio_in"; |
| 818 | allwinner,drive = <0>; |
| 819 | allwinner,pull = <1>; |
| 820 | }; |
| 821 | |
| 822 | mmc3_pins_a: mmc3@0 { |
| 823 | allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; |
| 824 | allwinner,function = "mmc3"; |
| 825 | allwinner,drive = <2>; |
| 826 | allwinner,pull = <0>; |
| 827 | }; |
Alexander Bersenev | 0fc2b7a | 2014-06-09 00:08:11 +0600 | [diff] [blame] | 828 | |
| 829 | ir0_pins_a: ir0@0 { |
| 830 | allwinner,pins = "PB3","PB4"; |
| 831 | allwinner,function = "ir0"; |
| 832 | allwinner,drive = <0>; |
| 833 | allwinner,pull = <0>; |
| 834 | }; |
| 835 | |
| 836 | ir1_pins_a: ir1@0 { |
| 837 | allwinner,pins = "PB22","PB23"; |
| 838 | allwinner,function = "ir1"; |
| 839 | allwinner,drive = <0>; |
| 840 | allwinner,pull = <0>; |
| 841 | }; |
Maxime Ripard | 17eac03 | 2013-07-24 23:46:11 +0200 | [diff] [blame] | 842 | }; |
| 843 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 844 | timer@01c20c00 { |
Maxime Ripard | b4f2644 | 2014-02-06 10:40:32 +0100 | [diff] [blame] | 845 | compatible = "allwinner,sun4i-a10-timer"; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 846 | reg = <0x01c20c00 0x90>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 847 | interrupts = <0 22 4>, |
| 848 | <0 23 4>, |
| 849 | <0 24 4>, |
| 850 | <0 25 4>, |
| 851 | <0 67 4>, |
| 852 | <0 68 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 853 | clocks = <&osc24M>; |
| 854 | }; |
| 855 | |
| 856 | wdt: watchdog@01c20c90 { |
Maxime Ripard | ca5d04d | 2014-02-07 22:29:26 +0100 | [diff] [blame] | 857 | compatible = "allwinner,sun4i-a10-wdt"; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 858 | reg = <0x01c20c90 0x10>; |
| 859 | }; |
| 860 | |
Carlo Caione | b5d905c | 2013-10-16 20:30:26 +0200 | [diff] [blame] | 861 | rtc: rtc@01c20d00 { |
| 862 | compatible = "allwinner,sun7i-a20-rtc"; |
| 863 | reg = <0x01c20d00 0x20>; |
Maxime Ripard | 2f41898 | 2014-02-01 16:46:16 +0100 | [diff] [blame] | 864 | interrupts = <0 24 4>; |
Carlo Caione | b5d905c | 2013-10-16 20:30:26 +0200 | [diff] [blame] | 865 | }; |
| 866 | |
Alexandre Belloni | 8ec40c2 | 2014-04-28 18:17:13 +0200 | [diff] [blame] | 867 | pwm: pwm@01c20e00 { |
| 868 | compatible = "allwinner,sun7i-a20-pwm"; |
| 869 | reg = <0x01c20e00 0xc>; |
| 870 | clocks = <&osc24M>; |
| 871 | #pwm-cells = <3>; |
| 872 | status = "disabled"; |
| 873 | }; |
| 874 | |
Alexander Bersenev | c1a0ee3 | 2014-06-21 17:04:05 +0600 | [diff] [blame] | 875 | ir0: ir@01c21800 { |
Hans de Goede | 1715a38 | 2014-06-30 23:57:54 +0200 | [diff] [blame] | 876 | compatible = "allwinner,sun4i-a10-ir"; |
Alexander Bersenev | c1a0ee3 | 2014-06-21 17:04:05 +0600 | [diff] [blame] | 877 | clocks = <&apb0_gates 6>, <&ir0_clk>; |
| 878 | clock-names = "apb", "ir"; |
| 879 | interrupts = <0 5 4>; |
| 880 | reg = <0x01c21800 0x40>; |
| 881 | status = "disabled"; |
| 882 | }; |
| 883 | |
| 884 | ir1: ir@01c21c00 { |
Hans de Goede | 1715a38 | 2014-06-30 23:57:54 +0200 | [diff] [blame] | 885 | compatible = "allwinner,sun4i-a10-ir"; |
Alexander Bersenev | c1a0ee3 | 2014-06-21 17:04:05 +0600 | [diff] [blame] | 886 | clocks = <&apb0_gates 7>, <&ir1_clk>; |
| 887 | clock-names = "apb", "ir"; |
| 888 | interrupts = <0 6 4>; |
| 889 | reg = <0x01c21c00 0x40>; |
| 890 | status = "disabled"; |
| 891 | }; |
| 892 | |
Oliver Schinagl | 2bad969 | 2013-09-03 12:33:28 +0200 | [diff] [blame] | 893 | sid: eeprom@01c23800 { |
| 894 | compatible = "allwinner,sun7i-a20-sid"; |
| 895 | reg = <0x01c23800 0x200>; |
| 896 | }; |
| 897 | |
Hans de Goede | 00f7ed8 | 2013-12-31 17:20:52 +0100 | [diff] [blame] | 898 | rtp: rtp@01c25000 { |
Maxime Ripard | 40dd8f3 | 2014-02-02 14:52:40 +0100 | [diff] [blame] | 899 | compatible = "allwinner,sun4i-a10-ts"; |
Hans de Goede | 00f7ed8 | 2013-12-31 17:20:52 +0100 | [diff] [blame] | 900 | reg = <0x01c25000 0x100>; |
| 901 | interrupts = <0 29 4>; |
| 902 | }; |
| 903 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 904 | uart0: serial@01c28000 { |
| 905 | compatible = "snps,dw-apb-uart"; |
| 906 | reg = <0x01c28000 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 907 | interrupts = <0 1 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 908 | reg-shift = <2>; |
| 909 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 910 | clocks = <&apb1_gates 16>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 911 | status = "disabled"; |
| 912 | }; |
| 913 | |
| 914 | uart1: serial@01c28400 { |
| 915 | compatible = "snps,dw-apb-uart"; |
| 916 | reg = <0x01c28400 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 917 | interrupts = <0 2 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 918 | reg-shift = <2>; |
| 919 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 920 | clocks = <&apb1_gates 17>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 921 | status = "disabled"; |
| 922 | }; |
| 923 | |
| 924 | uart2: serial@01c28800 { |
| 925 | compatible = "snps,dw-apb-uart"; |
| 926 | reg = <0x01c28800 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 927 | interrupts = <0 3 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 928 | reg-shift = <2>; |
| 929 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 930 | clocks = <&apb1_gates 18>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 931 | status = "disabled"; |
| 932 | }; |
| 933 | |
| 934 | uart3: serial@01c28c00 { |
| 935 | compatible = "snps,dw-apb-uart"; |
| 936 | reg = <0x01c28c00 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 937 | interrupts = <0 4 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 938 | reg-shift = <2>; |
| 939 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 940 | clocks = <&apb1_gates 19>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 941 | status = "disabled"; |
| 942 | }; |
| 943 | |
| 944 | uart4: serial@01c29000 { |
| 945 | compatible = "snps,dw-apb-uart"; |
| 946 | reg = <0x01c29000 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 947 | interrupts = <0 17 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 948 | reg-shift = <2>; |
| 949 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 950 | clocks = <&apb1_gates 20>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 951 | status = "disabled"; |
| 952 | }; |
| 953 | |
| 954 | uart5: serial@01c29400 { |
| 955 | compatible = "snps,dw-apb-uart"; |
| 956 | reg = <0x01c29400 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 957 | interrupts = <0 18 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 958 | reg-shift = <2>; |
| 959 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 960 | clocks = <&apb1_gates 21>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 961 | status = "disabled"; |
| 962 | }; |
| 963 | |
| 964 | uart6: serial@01c29800 { |
| 965 | compatible = "snps,dw-apb-uart"; |
| 966 | reg = <0x01c29800 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 967 | interrupts = <0 19 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 968 | reg-shift = <2>; |
| 969 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 970 | clocks = <&apb1_gates 22>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 971 | status = "disabled"; |
| 972 | }; |
| 973 | |
| 974 | uart7: serial@01c29c00 { |
| 975 | compatible = "snps,dw-apb-uart"; |
| 976 | reg = <0x01c29c00 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 977 | interrupts = <0 20 4>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 978 | reg-shift = <2>; |
| 979 | reg-io-width = <4>; |
Maxime Ripard | de7dc93 | 2013-07-25 21:12:52 +0200 | [diff] [blame] | 980 | clocks = <&apb1_gates 23>; |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 981 | status = "disabled"; |
| 982 | }; |
| 983 | |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 984 | i2c0: i2c@01c2ac00 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 985 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 986 | reg = <0x01c2ac00 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 987 | interrupts = <0 7 4>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 988 | clocks = <&apb1_gates 0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 989 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 990 | #address-cells = <1>; |
| 991 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 992 | }; |
| 993 | |
| 994 | i2c1: i2c@01c2b000 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 995 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 996 | reg = <0x01c2b000 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 997 | interrupts = <0 8 4>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 998 | clocks = <&apb1_gates 1>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 999 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1000 | #address-cells = <1>; |
| 1001 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1002 | }; |
| 1003 | |
| 1004 | i2c2: i2c@01c2b400 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 1005 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1006 | reg = <0x01c2b400 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 1007 | interrupts = <0 9 4>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1008 | clocks = <&apb1_gates 2>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1009 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1010 | #address-cells = <1>; |
| 1011 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1012 | }; |
| 1013 | |
| 1014 | i2c3: i2c@01c2b800 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 1015 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1016 | reg = <0x01c2b800 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 1017 | interrupts = <0 88 4>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1018 | clocks = <&apb1_gates 3>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1019 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1020 | #address-cells = <1>; |
| 1021 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1022 | }; |
| 1023 | |
Maxime Ripard | a386704 | 2014-04-18 21:13:08 +0200 | [diff] [blame] | 1024 | i2c4: i2c@01c2c000 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame] | 1025 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | a386704 | 2014-04-18 21:13:08 +0200 | [diff] [blame] | 1026 | reg = <0x01c2c000 0x400>; |
Maxime Ripard | 378d0ae | 2013-12-10 19:37:21 +0100 | [diff] [blame] | 1027 | interrupts = <0 89 4>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1028 | clocks = <&apb1_gates 15>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1029 | status = "disabled"; |
Hans de Goede | d1412ae | 2014-04-13 13:41:05 +0200 | [diff] [blame] | 1030 | #address-cells = <1>; |
| 1031 | #size-cells = <0>; |
Maxime Ripard | 428abbb | 2013-08-31 23:07:24 +0200 | [diff] [blame] | 1032 | }; |
| 1033 | |
Chen-Yu Tsai | c40b8d5 | 2014-02-10 18:35:49 +0800 | [diff] [blame] | 1034 | gmac: ethernet@01c50000 { |
| 1035 | compatible = "allwinner,sun7i-a20-gmac"; |
| 1036 | reg = <0x01c50000 0x10000>; |
| 1037 | interrupts = <0 85 4>; |
| 1038 | interrupt-names = "macirq"; |
| 1039 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; |
| 1040 | clock-names = "stmmaceth", "allwinner_gmac_tx"; |
| 1041 | snps,pbl = <2>; |
| 1042 | snps,fixed-burst; |
| 1043 | snps,force_sf_dma_mode; |
| 1044 | status = "disabled"; |
| 1045 | #address-cells = <1>; |
| 1046 | #size-cells = <0>; |
| 1047 | }; |
| 1048 | |
Maxime Ripard | 31f8ad3 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 1049 | hstimer@01c60000 { |
| 1050 | compatible = "allwinner,sun7i-a20-hstimer"; |
| 1051 | reg = <0x01c60000 0x1000>; |
Maxime Ripard | 2f41898 | 2014-02-01 16:46:16 +0100 | [diff] [blame] | 1052 | interrupts = <0 81 4>, |
| 1053 | <0 82 4>, |
| 1054 | <0 83 4>, |
| 1055 | <0 84 4>; |
Maxime Ripard | 31f8ad3 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 1056 | clocks = <&ahb_gates 28>; |
| 1057 | }; |
| 1058 | |
Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1059 | gic: interrupt-controller@01c81000 { |
| 1060 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 1061 | reg = <0x01c81000 0x1000>, |
| 1062 | <0x01c82000 0x1000>, |
| 1063 | <0x01c84000 0x2000>, |
| 1064 | <0x01c86000 0x2000>; |
| 1065 | interrupt-controller; |
| 1066 | #interrupt-cells = <3>; |
| 1067 | interrupts = <1 9 0xf04>; |
| 1068 | }; |
| 1069 | }; |
| 1070 | }; |