Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/proc-v7.S |
| 3 | * |
| 4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This is the "shell" of the ARMv7 processor support. |
| 11 | */ |
Tim Abbott | 991da17 | 2009-04-27 14:02:22 -0400 | [diff] [blame] | 12 | #include <linux/init.h> |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 13 | #include <linux/linkage.h> |
| 14 | #include <asm/assembler.h> |
| 15 | #include <asm/asm-offsets.h> |
Russell King | 5ec9407 | 2008-09-07 19:15:31 +0100 | [diff] [blame] | 16 | #include <asm/hwcap.h> |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 17 | #include <asm/pgtable-hwdef.h> |
| 18 | #include <asm/pgtable.h> |
| 19 | |
| 20 | #include "proc-macros.S" |
| 21 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 22 | #ifdef CONFIG_ARM_LPAE |
| 23 | #include "proc-v7-3level.S" |
| 24 | #else |
Catalin Marinas | 8d2cd3a | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 25 | #include "proc-v7-2level.S" |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 26 | #endif |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 27 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 28 | ENTRY(cpu_v7_proc_init) |
| 29 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 30 | ENDPROC(cpu_v7_proc_init) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 31 | |
| 32 | ENTRY(cpu_v7_proc_fin) |
Tony Lindgren | 1f667c6 | 2010-01-19 17:01:33 +0100 | [diff] [blame] | 33 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
| 34 | bic r0, r0, #0x1000 @ ...i............ |
| 35 | bic r0, r0, #0x0006 @ .............ca. |
| 36 | mcr p15, 0, r0, c1, c0, 0 @ disable caches |
Russell King | 9ca03a2 | 2010-07-26 12:22:12 +0100 | [diff] [blame] | 37 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 38 | ENDPROC(cpu_v7_proc_fin) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * cpu_v7_reset(loc) |
| 42 | * |
| 43 | * Perform a soft reset of the system. Put the CPU into the |
| 44 | * same state as it would be if it had been reset, and branch |
| 45 | * to what would be the reset vector. |
| 46 | * |
| 47 | * - loc - location to jump to for soft reset |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 48 | * |
| 49 | * This code must be executed using a flat identity mapping with |
| 50 | * caches disabled. |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 51 | */ |
| 52 | .align 5 |
Will Deacon | 1a4baaf | 2011-11-15 13:25:04 +0000 | [diff] [blame] | 53 | .pushsection .idmap.text, "ax" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 54 | ENTRY(cpu_v7_reset) |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 55 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
| 56 | bic r1, r1, #0x1 @ ...............m |
Will Deacon | 0f81bb6 | 2011-08-26 16:34:51 +0100 | [diff] [blame] | 57 | THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 58 | mcr p15, 0, r1, c1, c0, 0 @ disable MMU |
| 59 | isb |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 60 | mov pc, r0 |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 61 | ENDPROC(cpu_v7_reset) |
Will Deacon | 1a4baaf | 2011-11-15 13:25:04 +0000 | [diff] [blame] | 62 | .popsection |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * cpu_v7_do_idle() |
| 66 | * |
| 67 | * Idle the processor (eg, wait for interrupt). |
| 68 | * |
| 69 | * IRQs are already disabled. |
| 70 | */ |
| 71 | ENTRY(cpu_v7_do_idle) |
Catalin Marinas | 8553cb6 | 2008-11-10 14:14:11 +0000 | [diff] [blame] | 72 | dsb @ WFI may enter a low-power mode |
Catalin Marinas | 000b502 | 2008-10-03 11:09:10 +0100 | [diff] [blame] | 73 | wfi |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 74 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 75 | ENDPROC(cpu_v7_do_idle) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 76 | |
| 77 | ENTRY(cpu_v7_dcache_clean_area) |
| 78 | #ifndef TLB_CAN_READ_FROM_L1_CACHE |
| 79 | dcache_line_size r2, r3 |
| 80 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 81 | add r0, r0, r2 |
| 82 | subs r1, r1, r2 |
| 83 | bhi 1b |
| 84 | dsb |
| 85 | #endif |
| 86 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 87 | ENDPROC(cpu_v7_dcache_clean_area) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 88 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 89 | string cpu_v7_name, "ARMv7 Processor" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 90 | .align |
| 91 | |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 92 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ |
| 93 | .globl cpu_v7_suspend_size |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 94 | .equ cpu_v7_suspend_size, 4 * 8 |
Arnd Bergmann | 15e0d9e | 2011-10-01 21:09:39 +0200 | [diff] [blame] | 95 | #ifdef CONFIG_ARM_CPU_SUSPEND |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 96 | ENTRY(cpu_v7_do_suspend) |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 97 | stmfd sp!, {r4 - r10, lr} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 98 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 99 | mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
| 100 | stmia r0!, {r4 - r5} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 101 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 102 | mrc p15, 0, r7, c2, c0, 1 @ TTB 1 |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 103 | mrc p15, 0, r11, c2, c0, 2 @ TTB control register |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 104 | mrc p15, 0, r8, c1, c0, 0 @ Control register |
| 105 | mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register |
| 106 | mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 107 | stmia r0, {r6 - r11} |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 108 | ldmfd sp!, {r4 - r10, pc} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 109 | ENDPROC(cpu_v7_do_suspend) |
| 110 | |
| 111 | ENTRY(cpu_v7_do_resume) |
| 112 | mov ip, #0 |
| 113 | mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs |
| 114 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 115 | mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID |
| 116 | ldmia r0!, {r4 - r5} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 117 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 118 | mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 119 | ldmia r0, {r6 - r11} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 120 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 121 | #ifndef CONFIG_ARM_LPAE |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 122 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) |
| 123 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 124 | #endif |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 125 | mcr p15, 0, r1, c2, c0, 0 @ TTB 0 |
| 126 | mcr p15, 0, r7, c2, c0, 1 @ TTB 1 |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 127 | mcr p15, 0, r11, c2, c0, 2 @ TTB control register |
Russell King | 2590415 | 2011-08-26 22:44:59 +0100 | [diff] [blame] | 128 | mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 129 | teq r4, r9 @ Is it already set? |
| 130 | mcrne p15, 0, r9, c1, c0, 1 @ No, so write it |
| 131 | mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 132 | ldr r4, =PRRR @ PRRR |
| 133 | ldr r5, =NMRR @ NMRR |
| 134 | mcr p15, 0, r4, c10, c2, 0 @ write PRRR |
| 135 | mcr p15, 0, r5, c10, c2, 1 @ write NMRR |
| 136 | isb |
Russell King | f35235a | 2011-08-27 00:37:38 +0100 | [diff] [blame] | 137 | dsb |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 138 | mov r0, r8 @ control register |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 139 | b cpu_resume_mmu |
| 140 | ENDPROC(cpu_v7_do_resume) |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 141 | #endif |
| 142 | |
Russell King | 5085f3f | 2010-10-01 15:37:05 +0100 | [diff] [blame] | 143 | __CPUINIT |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * __v7_setup |
| 147 | * |
| 148 | * Initialise TLB, Caches, and MMU state ready to switch the MMU |
| 149 | * on. Return in r0 the new CP15 C1 control register setting. |
| 150 | * |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 151 | * This should be able to cover all ARMv7 cores. |
| 152 | * |
| 153 | * It is assumed that: |
| 154 | * - cache type register is implemented |
| 155 | */ |
Pawel Moll | 15eb169 | 2011-05-20 14:39:29 +0100 | [diff] [blame] | 156 | __v7_ca5mp_setup: |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 157 | __v7_ca9mp_setup: |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 158 | mov r10, #(1 << 0) @ TLB ops broadcasting |
| 159 | b 1f |
Pawel Moll | b424473 | 2011-12-09 20:00:39 +0100 | [diff] [blame] | 160 | __v7_ca7mp_setup: |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 161 | __v7_ca15mp_setup: |
| 162 | mov r10, #0 |
| 163 | 1: |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 164 | #ifdef CONFIG_SMP |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 165 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) |
| 166 | ALT_UP(mov r0, #(1 << 6)) @ fake it for UP |
Tony Thompson | 1b3a02eb | 2009-11-04 12:16:38 +0000 | [diff] [blame] | 167 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 168 | orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode |
| 169 | orreq r0, r0, r10 @ Enable CPU-specific SMP bits |
| 170 | mcreq p15, 0, r0, c1, c0, 1 |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 171 | #endif |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 172 | __v7_setup: |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 173 | adr r12, __v7_setup_stack @ the local stack |
| 174 | stmia r12, {r0-r5, r7, r9, r11, lr} |
| 175 | bl v7_flush_dcache_all |
| 176 | ldmia r12, {r0-r5, r7, r9, r11, lr} |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 177 | |
| 178 | mrc p15, 0, r0, c0, c0, 0 @ read main ID register |
| 179 | and r10, r0, #0xff000000 @ ARM? |
| 180 | teq r10, #0x41000000 |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 181 | bne 3f |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 182 | and r5, r0, #0x00f00000 @ variant |
| 183 | and r6, r0, #0x0000000f @ revision |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 184 | orr r6, r6, r5, lsr #20-4 @ combine variant and revision |
| 185 | ubfx r0, r0, #4, #12 @ primary part number |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 186 | |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 187 | /* Cortex-A8 Errata */ |
| 188 | ldr r10, =0x00000c08 @ Cortex-A8 primary part number |
| 189 | teq r0, r10 |
| 190 | bne 2f |
Catalin Marinas | 7ce236f | 2009-04-30 17:06:09 +0100 | [diff] [blame] | 191 | #ifdef CONFIG_ARM_ERRATA_430973 |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 192 | teq r5, #0x00100000 @ only present in r1p* |
| 193 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
| 194 | orreq r10, r10, #(1 << 6) @ set IBE to 1 |
| 195 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register |
Catalin Marinas | 7ce236f | 2009-04-30 17:06:09 +0100 | [diff] [blame] | 196 | #endif |
Catalin Marinas | 855c551 | 2009-04-30 17:06:15 +0100 | [diff] [blame] | 197 | #ifdef CONFIG_ARM_ERRATA_458693 |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 198 | teq r6, #0x20 @ only present in r2p0 |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 199 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
| 200 | orreq r10, r10, #(1 << 5) @ set L1NEON to 1 |
| 201 | orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 |
| 202 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register |
Catalin Marinas | 855c551 | 2009-04-30 17:06:15 +0100 | [diff] [blame] | 203 | #endif |
Catalin Marinas | 0516e46 | 2009-04-30 17:06:20 +0100 | [diff] [blame] | 204 | #ifdef CONFIG_ARM_ERRATA_460075 |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 205 | teq r6, #0x20 @ only present in r2p0 |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 206 | mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register |
| 207 | tsteq r10, #1 << 22 |
| 208 | orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit |
| 209 | mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register |
Catalin Marinas | 0516e46 | 2009-04-30 17:06:20 +0100 | [diff] [blame] | 210 | #endif |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 211 | b 3f |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 212 | |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 213 | /* Cortex-A9 Errata */ |
| 214 | 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number |
| 215 | teq r0, r10 |
| 216 | bne 3f |
| 217 | #ifdef CONFIG_ARM_ERRATA_742230 |
| 218 | cmp r6, #0x22 @ only present up to r2p2 |
| 219 | mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 220 | orrle r10, r10, #1 << 4 @ set bit #4 |
| 221 | mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 222 | #endif |
Will Deacon | a672e99 | 2010-09-14 09:53:02 +0100 | [diff] [blame] | 223 | #ifdef CONFIG_ARM_ERRATA_742231 |
| 224 | teq r6, #0x20 @ present in r2p0 |
| 225 | teqne r6, #0x21 @ present in r2p1 |
| 226 | teqne r6, #0x22 @ present in r2p2 |
| 227 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 228 | orreq r10, r10, #1 << 12 @ set bit #12 |
| 229 | orreq r10, r10, #1 << 22 @ set bit #22 |
| 230 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 231 | #endif |
Will Deacon | 475d92f | 2010-09-28 14:02:02 +0100 | [diff] [blame] | 232 | #ifdef CONFIG_ARM_ERRATA_743622 |
Will Deacon | efbc74a | 2012-02-24 12:12:38 +0100 | [diff] [blame^] | 233 | teq r5, #0x00200000 @ only present in r2p* |
Will Deacon | 475d92f | 2010-09-28 14:02:02 +0100 | [diff] [blame] | 234 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 235 | orreq r10, r10, #1 << 6 @ set bit #6 |
| 236 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 237 | #endif |
Dave Martin | ba90c51 | 2011-12-08 13:41:06 +0100 | [diff] [blame] | 238 | #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) |
| 239 | ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 |
| 240 | ALT_UP_B(1f) |
Will Deacon | 9a27c27 | 2011-02-18 16:36:35 +0100 | [diff] [blame] | 241 | mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 242 | orrlt r10, r10, #1 << 11 @ set bit #11 |
| 243 | mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register |
Dave Martin | ba90c51 | 2011-12-08 13:41:06 +0100 | [diff] [blame] | 244 | 1: |
Will Deacon | 9a27c27 | 2011-02-18 16:36:35 +0100 | [diff] [blame] | 245 | #endif |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 246 | |
| 247 | 3: mov r10, #0 |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 248 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 249 | dsb |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 250 | #ifdef CONFIG_MMU |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 251 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
Catalin Marinas | 8d2cd3a | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 252 | v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 253 | ldr r5, =PRRR @ PRRR |
| 254 | ldr r6, =NMRR @ NMRR |
Russell King | 3f69c0c | 2008-09-15 17:23:10 +0100 | [diff] [blame] | 255 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR |
| 256 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR |
Catalin Marinas | bdaaaec | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 257 | #endif |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 258 | adr r5, v7_crval |
| 259 | ldmia r5, {r5, r6} |
Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 260 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| 261 | orr r6, r6, #1 << 25 @ big-endian page tables |
| 262 | #endif |
Leif Lindholm | 64d2dc3 | 2010-09-16 18:00:47 +0100 | [diff] [blame] | 263 | #ifdef CONFIG_SWP_EMULATE |
| 264 | orr r5, r5, #(1 << 10) @ set SW bit in "clear" |
| 265 | bic r6, r6, #(1 << 10) @ clear it in "mmuset" |
| 266 | #endif |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 267 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
| 268 | bic r0, r0, r5 @ clear bits them |
| 269 | orr r0, r0, r6 @ set them |
Catalin Marinas | 347c8b7 | 2009-07-24 12:32:56 +0100 | [diff] [blame] | 270 | THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 271 | mov pc, lr @ return to head.S:__ret |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 272 | ENDPROC(__v7_setup) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 273 | |
Catalin Marinas | 8d2cd3a | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 274 | .align 2 |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 275 | __v7_setup_stack: |
| 276 | .space 4 * 11 @ 11 registers |
| 277 | |
Russell King | 5085f3f | 2010-10-01 15:37:05 +0100 | [diff] [blame] | 278 | __INITDATA |
| 279 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 280 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
| 281 | define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 282 | |
Russell King | 5085f3f | 2010-10-01 15:37:05 +0100 | [diff] [blame] | 283 | .section ".rodata" |
| 284 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 285 | string cpu_arch_name, "armv7" |
| 286 | string cpu_elf_name, "v7" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 287 | .align |
| 288 | |
| 289 | .section ".proc.info.init", #alloc, #execinstr |
| 290 | |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 291 | /* |
| 292 | * Standard v7 proc info content |
| 293 | */ |
| 294 | .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 |
| 295 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 296 | PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 297 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 298 | PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) |
| 299 | .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ |
| 300 | PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 301 | W(b) \initfunc |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 302 | .long cpu_arch_name |
| 303 | .long cpu_elf_name |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 304 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ |
| 305 | HWCAP_EDSP | HWCAP_TLS | \hwcaps |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 306 | .long cpu_v7_name |
| 307 | .long v7_processor_functions |
| 308 | .long v7wbi_tlb_fns |
| 309 | .long v6_user_fns |
| 310 | .long v7_cache_fns |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 311 | .endm |
| 312 | |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 313 | #ifndef CONFIG_ARM_LPAE |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 314 | /* |
Pawel Moll | 15eb169 | 2011-05-20 14:39:29 +0100 | [diff] [blame] | 315 | * ARM Ltd. Cortex A5 processor. |
| 316 | */ |
| 317 | .type __v7_ca5mp_proc_info, #object |
| 318 | __v7_ca5mp_proc_info: |
| 319 | .long 0x410fc050 |
| 320 | .long 0xff0ffff0 |
| 321 | __v7_proc __v7_ca5mp_setup |
| 322 | .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info |
| 323 | |
| 324 | /* |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 325 | * ARM Ltd. Cortex A9 processor. |
| 326 | */ |
| 327 | .type __v7_ca9mp_proc_info, #object |
| 328 | __v7_ca9mp_proc_info: |
| 329 | .long 0x410fc090 |
| 330 | .long 0xff0ffff0 |
| 331 | __v7_proc __v7_ca9mp_setup |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 332 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
Catalin Marinas | 1b6ba46 | 2011-11-22 17:30:29 +0000 | [diff] [blame] | 333 | #endif /* CONFIG_ARM_LPAE */ |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 334 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 335 | /* |
Will Deacon | 868dbf9 | 2012-01-20 12:01:14 +0100 | [diff] [blame] | 336 | * ARM Ltd. Cortex A7 processor. |
| 337 | */ |
| 338 | .type __v7_ca7mp_proc_info, #object |
| 339 | __v7_ca7mp_proc_info: |
| 340 | .long 0x410fc070 |
| 341 | .long 0xff0ffff0 |
| 342 | __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV |
| 343 | .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info |
| 344 | |
| 345 | /* |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 346 | * ARM Ltd. Cortex A15 processor. |
| 347 | */ |
| 348 | .type __v7_ca15mp_proc_info, #object |
| 349 | __v7_ca15mp_proc_info: |
| 350 | .long 0x410fc0f0 |
| 351 | .long 0xff0ffff0 |
| 352 | __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV |
| 353 | .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info |
| 354 | |
| 355 | /* |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 356 | * Match any ARMv7 processor core. |
| 357 | */ |
| 358 | .type __v7_proc_info, #object |
| 359 | __v7_proc_info: |
| 360 | .long 0x000f0000 @ Required ID value |
| 361 | .long 0x000f0000 @ Mask for ID |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 362 | __v7_proc __v7_setup |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 363 | .size __v7_proc_info, . - __v7_proc_info |