blob: fffae7b4f6e98cc790552560f336db8c59644170 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/video/w100fb.h
3 *
4 * Frame Buffer Device for ATI w100 (Wallaby)
5 *
6 * Copyright (C) 2002, ATI Corp.
7 * Copyright (C) 2004-2005 Richard Purdie
Richard Purdieaac51f02005-09-06 15:19:03 -07008 * Copyright (c) 2005 Ian Molton <spyro@f2s.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * Modified to work with 2.6 by Richard Purdie <rpurdie@rpsys.net>
11 *
Richard Purdieaac51f02005-09-06 15:19:03 -070012 * w32xx support by Ian Molton
13 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#if !defined (_W100FB_H)
21#define _W100FB_H
22
23/* Block CIF Start: */
24#define mmCHIP_ID 0x0000
Richard Purdieaac51f02005-09-06 15:19:03 -070025#define mmREVISION_ID 0x0004
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#define mmWRAP_BUF_A 0x0008
27#define mmWRAP_BUF_B 0x000C
28#define mmWRAP_TOP_DIR 0x0010
29#define mmWRAP_START_DIR 0x0014
30#define mmCIF_CNTL 0x0018
31#define mmCFGREG_BASE 0x001C
32#define mmCIF_IO 0x0020
33#define mmCIF_READ_DBG 0x0024
34#define mmCIF_WRITE_DBG 0x0028
35#define cfgIND_ADDR_A_0 0x0000
36#define cfgIND_ADDR_A_1 0x0001
37#define cfgIND_ADDR_A_2 0x0002
38#define cfgIND_DATA_A 0x0003
39#define cfgREG_BASE 0x0004
40#define cfgINTF_CNTL 0x0005
41#define cfgSTATUS 0x0006
42#define cfgCPU_DEFAULTS 0x0007
43#define cfgIND_ADDR_B_0 0x0008
44#define cfgIND_ADDR_B_1 0x0009
45#define cfgIND_ADDR_B_2 0x000A
46#define cfgIND_DATA_B 0x000B
47#define cfgPM4_RPTR 0x000C
48#define cfgSCRATCH 0x000D
49#define cfgPM4_WRPTR_0 0x000E
50#define cfgPM4_WRPTR_1 0x000F
51/* Block CIF End: */
52
53/* Block CP Start: */
54#define mmSCRATCH_UMSK 0x0280
55#define mmSCRATCH_ADDR 0x0284
56#define mmGEN_INT_CNTL 0x0200
57#define mmGEN_INT_STATUS 0x0204
58/* Block CP End: */
59
60/* Block DISPLAY Start: */
61#define mmLCD_FORMAT 0x0410
62#define mmGRAPHIC_CTRL 0x0414
63#define mmGRAPHIC_OFFSET 0x0418
64#define mmGRAPHIC_PITCH 0x041C
65#define mmCRTC_TOTAL 0x0420
66#define mmACTIVE_H_DISP 0x0424
67#define mmACTIVE_V_DISP 0x0428
68#define mmGRAPHIC_H_DISP 0x042C
69#define mmGRAPHIC_V_DISP 0x0430
70#define mmVIDEO_CTRL 0x0434
71#define mmGRAPHIC_KEY 0x0438
72#define mmBRIGHTNESS_CNTL 0x045C
73#define mmDISP_INT_CNTL 0x0488
74#define mmCRTC_SS 0x048C
75#define mmCRTC_LS 0x0490
76#define mmCRTC_REV 0x0494
77#define mmCRTC_DCLK 0x049C
78#define mmCRTC_GS 0x04A0
79#define mmCRTC_VPOS_GS 0x04A4
80#define mmCRTC_GCLK 0x04A8
81#define mmCRTC_GOE 0x04AC
82#define mmCRTC_FRAME 0x04B0
83#define mmCRTC_FRAME_VPOS 0x04B4
84#define mmGPIO_DATA 0x04B8
85#define mmGPIO_CNTL1 0x04BC
86#define mmGPIO_CNTL2 0x04C0
87#define mmLCDD_CNTL1 0x04C4
88#define mmLCDD_CNTL2 0x04C8
89#define mmGENLCD_CNTL1 0x04CC
90#define mmGENLCD_CNTL2 0x04D0
91#define mmDISP_DEBUG 0x04D4
92#define mmDISP_DB_BUF_CNTL 0x04D8
93#define mmDISP_CRC_SIG 0x04DC
Richard Purdieaac51f02005-09-06 15:19:03 -070094#define mmCRTC_DEFAULT_COUNT 0x04E0
Linus Torvalds1da177e2005-04-16 15:20:36 -070095#define mmLCD_BACKGROUND_COLOR 0x04E4
96#define mmCRTC_PS2 0x04E8
97#define mmCRTC_PS2_VPOS 0x04EC
98#define mmCRTC_PS1_ACTIVE 0x04F0
99#define mmCRTC_PS1_NACTIVE 0x04F4
100#define mmCRTC_GCLK_EXT 0x04F8
101#define mmCRTC_ALW 0x04FC
102#define mmCRTC_ALW_VPOS 0x0500
103#define mmCRTC_PSK 0x0504
104#define mmCRTC_PSK_HPOS 0x0508
105#define mmCRTC_CV4_START 0x050C
106#define mmCRTC_CV4_END 0x0510
107#define mmCRTC_CV4_HPOS 0x0514
108#define mmCRTC_ECK 0x051C
109#define mmREFRESH_CNTL 0x0520
110#define mmGENLCD_CNTL3 0x0524
111#define mmGPIO_DATA2 0x0528
112#define mmGPIO_CNTL3 0x052C
113#define mmGPIO_CNTL4 0x0530
114#define mmCHIP_STRAP 0x0534
115#define mmDISP_DEBUG2 0x0538
116#define mmDEBUG_BUS_CNTL 0x053C
117#define mmGAMMA_VALUE1 0x0540
118#define mmGAMMA_VALUE2 0x0544
119#define mmGAMMA_SLOPE 0x0548
120#define mmGEN_STATUS 0x054C
121#define mmHW_INT 0x0550
122/* Block DISPLAY End: */
123
124/* Block GFX Start: */
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800125#define mmDST_OFFSET 0x1004
126#define mmDST_PITCH 0x1008
127#define mmDST_Y_X 0x1038
128#define mmDST_WIDTH_HEIGHT 0x1198
129#define mmDP_GUI_MASTER_CNTL 0x106C
Richard Purdieaac51f02005-09-06 15:19:03 -0700130#define mmBRUSH_OFFSET 0x108C
131#define mmBRUSH_Y_X 0x1074
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800132#define mmDP_BRUSH_FRGD_CLR 0x107C
133#define mmSRC_OFFSET 0x11AC
134#define mmSRC_PITCH 0x11B0
135#define mmSRC_Y_X 0x1034
Richard Purdieaac51f02005-09-06 15:19:03 -0700136#define mmDEFAULT_PITCH_OFFSET 0x10A0
137#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
138#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800139#define mmSC_TOP_LEFT 0x11BC
140#define mmSC_BOTTOM_RIGHT 0x11C0
141#define mmSRC_SC_BOTTOM_RIGHT 0x11C4
Richard Purdieaac51f02005-09-06 15:19:03 -0700142#define mmGLOBAL_ALPHA 0x1210
143#define mmFILTER_COEF 0x1214
144#define mmMVC_CNTL_START 0x11E0
145#define mmE2_ARITHMETIC_CNTL 0x1220
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800146#define mmDP_CNTL 0x11C8
147#define mmDP_CNTL_DST_DIR 0x11CC
148#define mmDP_DATATYPE 0x12C4
149#define mmDP_MIX 0x12C8
150#define mmDP_WRITE_MSK 0x12CC
Richard Purdieaac51f02005-09-06 15:19:03 -0700151#define mmENG_CNTL 0x13E8
152#define mmENG_PERF_CNT 0x13F0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153/* Block GFX End: */
154
155/* Block IDCT Start: */
156#define mmIDCT_RUNS 0x0C00
157#define mmIDCT_LEVELS 0x0C04
158#define mmIDCT_CONTROL 0x0C3C
159#define mmIDCT_AUTH_CONTROL 0x0C08
160#define mmIDCT_AUTH 0x0C0C
161/* Block IDCT End: */
162
163/* Block MC Start: */
Richard Purdieaac51f02005-09-06 15:19:03 -0700164#define mmMEM_CNTL 0x0180
165#define mmMEM_ARB 0x0184
166#define mmMC_FB_LOCATION 0x0188
167#define mmMEM_EXT_CNTL 0x018C
168#define mmMC_EXT_MEM_LOCATION 0x0190
169#define mmMEM_EXT_TIMING_CNTL 0x0194
170#define mmMEM_SDRAM_MODE_REG 0x0198
171#define mmMEM_IO_CNTL 0x019C
172#define mmMC_DEBUG 0x01A0
173#define mmMC_BIST_CTRL 0x01A4
174#define mmMC_BIST_COLLAR_READ 0x01A8
175#define mmTC_MISMATCH 0x01AC
176#define mmMC_PERF_MON_CNTL 0x01B0
177#define mmMC_PERF_COUNTERS 0x01B4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178/* Block MC End: */
179
Richard Purdieaac51f02005-09-06 15:19:03 -0700180/* Block BM Start: */
181#define mmBM_EXT_MEM_BANDWIDTH 0x0A00
182#define mmBM_OFFSET 0x0A04
183#define mmBM_MEM_EXT_TIMING_CNTL 0x0A08
184#define mmBM_MEM_EXT_CNTL 0x0A0C
185#define mmBM_MEM_MODE_REG 0x0A10
186#define mmBM_MEM_IO_CNTL 0x0A18
187#define mmBM_CONFIG 0x0A1C
188#define mmBM_STATUS 0x0A20
189#define mmBM_DEBUG 0x0A24
190#define mmBM_PERF_MON_CNTL 0x0A28
191#define mmBM_PERF_COUNTERS 0x0A2C
192#define mmBM_PERF2_MON_CNTL 0x0A30
193#define mmBM_PERF2_COUNTERS 0x0A34
194/* Block BM End: */
195
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196/* Block RBBM Start: */
197#define mmWAIT_UNTIL 0x1400
198#define mmISYNC_CNTL 0x1404
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800199#define mmRBBM_STATUS 0x0140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200#define mmRBBM_CNTL 0x0144
201#define mmNQWAIT_UNTIL 0x0150
202/* Block RBBM End: */
203
204/* Block CG Start: */
205#define mmCLK_PIN_CNTL 0x0080
206#define mmPLL_REF_FB_DIV 0x0084
207#define mmPLL_CNTL 0x0088
208#define mmSCLK_CNTL 0x008C
209#define mmPCLK_CNTL 0x0090
210#define mmCLK_TEST_CNTL 0x0094
211#define mmPWRMGT_CNTL 0x0098
212#define mmPWRMGT_STATUS 0x009C
213/* Block CG End: */
214
215/* default value definitions */
Richard Purdieaac51f02005-09-06 15:19:03 -0700216#define defWRAP_TOP_DIR 0x00000000
217#define defWRAP_START_DIR 0x00000000
218#define defCFGREG_BASE 0x00000000
219#define defCIF_IO 0x000C0902
220#define defINTF_CNTL 0x00000011
221#define defCPU_DEFAULTS 0x00000006
222#define defHW_INT 0x00000000
223#define defMC_EXT_MEM_LOCATION 0x07ff0000
224#define defTC_MISMATCH 0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225
226#define W100_CFG_BASE 0x0
227#define W100_CFG_LEN 0x10
228#define W100_REG_BASE 0x10000
229#define W100_REG_LEN 0x2000
230#define MEM_INT_BASE_VALUE 0x100000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231#define MEM_EXT_BASE_VALUE 0x800000
Richard Purdieaac51f02005-09-06 15:19:03 -0700232#define MEM_INT_SIZE 0x05ffff
233#define MEM_WINDOW_BASE 0x100000
234#define MEM_WINDOW_SIZE 0xf00000
235
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236#define WRAP_BUF_BASE_VALUE 0x80000
237#define WRAP_BUF_TOP_VALUE 0xbffff
238
Richard Purdieaac51f02005-09-06 15:19:03 -0700239#define CHIP_ID_W100 0x57411002
240#define CHIP_ID_W3200 0x56441002
241#define CHIP_ID_W3220 0x57441002
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242
Richard Purdieaac51f02005-09-06 15:19:03 -0700243/* Register structure definitions */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244
245struct wrap_top_dir_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800246 u32 top_addr : 23;
247 u32 : 9;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248} __attribute__((packed));
249
250union wrap_top_dir_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800251 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700252 struct wrap_top_dir_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253} __attribute__((packed));
254
255struct wrap_start_dir_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800256 u32 start_addr : 23;
257 u32 : 9;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258} __attribute__((packed));
259
260union wrap_start_dir_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800261 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700262 struct wrap_start_dir_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263} __attribute__((packed));
264
265struct cif_cntl_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800266 u32 swap_reg : 2;
267 u32 swap_fbuf_1 : 2;
268 u32 swap_fbuf_2 : 2;
269 u32 swap_fbuf_3 : 2;
270 u32 pmi_int_disable : 1;
271 u32 pmi_schmen_disable : 1;
272 u32 intb_oe : 1;
273 u32 en_wait_to_compensate_dq_prop_dly : 1;
274 u32 compensate_wait_rd_size : 2;
275 u32 wait_asserted_timeout_val : 2;
276 u32 wait_masked_val : 2;
277 u32 en_wait_timeout : 1;
278 u32 en_one_clk_setup_before_wait : 1;
279 u32 interrupt_active_high : 1;
280 u32 en_overwrite_straps : 1;
281 u32 strap_wait_active_hi : 1;
282 u32 lat_busy_count : 2;
283 u32 lat_rd_pm4_sclk_busy : 1;
284 u32 dis_system_bits : 1;
285 u32 dis_mr : 1;
286 u32 cif_spare_1 : 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287} __attribute__((packed));
288
289union cif_cntl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800290 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700291 struct cif_cntl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292} __attribute__((packed));
293
294struct cfgreg_base_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800295 u32 cfgreg_base : 24;
296 u32 : 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297} __attribute__((packed));
298
299union cfgreg_base_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800300 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700301 struct cfgreg_base_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302} __attribute__((packed));
303
304struct cif_io_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800305 u32 dq_srp : 1;
306 u32 dq_srn : 1;
307 u32 dq_sp : 4;
308 u32 dq_sn : 4;
309 u32 waitb_srp : 1;
310 u32 waitb_srn : 1;
311 u32 waitb_sp : 4;
312 u32 waitb_sn : 4;
313 u32 intb_srp : 1;
314 u32 intb_srn : 1;
315 u32 intb_sp : 4;
316 u32 intb_sn : 4;
317 u32 : 2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318} __attribute__((packed));
319
320union cif_io_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800321 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700322 struct cif_io_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323} __attribute__((packed));
324
325struct cif_read_dbg_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800326 u32 unpacker_pre_fetch_trig_gen : 2;
327 u32 dly_second_rd_fetch_trig : 1;
328 u32 rst_rd_burst_id : 1;
329 u32 dis_rd_burst_id : 1;
330 u32 en_block_rd_when_packer_is_not_emp : 1;
331 u32 dis_pre_fetch_cntl_sm : 1;
332 u32 rbbm_chrncy_dis : 1;
333 u32 rbbm_rd_after_wr_lat : 2;
334 u32 dis_be_during_rd : 1;
335 u32 one_clk_invalidate_pulse : 1;
336 u32 dis_chnl_priority : 1;
337 u32 rst_read_path_a_pls : 1;
338 u32 rst_read_path_b_pls : 1;
339 u32 dis_reg_rd_fetch_trig : 1;
340 u32 dis_rd_fetch_trig_from_ind_addr : 1;
341 u32 dis_rd_same_byte_to_trig_fetch : 1;
342 u32 dis_dir_wrap : 1;
343 u32 dis_ring_buf_to_force_dec : 1;
344 u32 dis_addr_comp_in_16bit : 1;
345 u32 clr_w : 1;
346 u32 err_rd_tag_is_3 : 1;
347 u32 err_load_when_ful_a : 1;
348 u32 err_load_when_ful_b : 1;
349 u32 : 7;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350} __attribute__((packed));
351
352union cif_read_dbg_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800353 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700354 struct cif_read_dbg_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355} __attribute__((packed));
356
357struct cif_write_dbg_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800358 u32 packer_timeout_count : 2;
359 u32 en_upper_load_cond : 1;
360 u32 en_chnl_change_cond : 1;
361 u32 dis_addr_comp_cond : 1;
362 u32 dis_load_same_byte_addr_cond : 1;
363 u32 dis_timeout_cond : 1;
364 u32 dis_timeout_during_rbbm : 1;
365 u32 dis_packer_ful_during_rbbm_timeout : 1;
366 u32 en_dword_split_to_rbbm : 1;
367 u32 en_dummy_val : 1;
368 u32 dummy_val_sel : 1;
369 u32 mask_pm4_wrptr_dec : 1;
370 u32 dis_mc_clean_cond : 1;
371 u32 err_two_reqi_during_ful : 1;
372 u32 err_reqi_during_idle_clk : 1;
373 u32 err_global : 1;
374 u32 en_wr_buf_dbg_load : 1;
375 u32 en_wr_buf_dbg_path : 1;
376 u32 sel_wr_buf_byte : 3;
377 u32 dis_rd_flush_wr : 1;
378 u32 dis_packer_ful_cond : 1;
379 u32 dis_invalidate_by_ops_chnl : 1;
380 u32 en_halt_when_reqi_err : 1;
381 u32 cif_spare_2 : 5;
382 u32 : 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383} __attribute__((packed));
384
385union cif_write_dbg_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800386 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700387 struct cif_write_dbg_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388} __attribute__((packed));
389
390
391struct intf_cntl_t {
Richard Purdieaac51f02005-09-06 15:19:03 -0700392 unsigned char ad_inc_a : 1;
393 unsigned char ring_buf_a : 1;
394 unsigned char rd_fetch_trigger_a : 1;
395 unsigned char rd_data_rdy_a : 1;
396 unsigned char ad_inc_b : 1;
397 unsigned char ring_buf_b : 1;
398 unsigned char rd_fetch_trigger_b : 1;
399 unsigned char rd_data_rdy_b : 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400} __attribute__((packed));
401
402union intf_cntl_u {
Richard Purdieaac51f02005-09-06 15:19:03 -0700403 unsigned char val : 8;
404 struct intf_cntl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405} __attribute__((packed));
406
407struct cpu_defaults_t {
Richard Purdieaac51f02005-09-06 15:19:03 -0700408 unsigned char unpack_rd_data : 1;
409 unsigned char access_ind_addr_a : 1;
410 unsigned char access_ind_addr_b : 1;
411 unsigned char access_scratch_reg : 1;
412 unsigned char pack_wr_data : 1;
413 unsigned char transition_size : 1;
414 unsigned char en_read_buf_mode : 1;
415 unsigned char rd_fetch_scratch : 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416} __attribute__((packed));
417
418union cpu_defaults_u {
Richard Purdieaac51f02005-09-06 15:19:03 -0700419 unsigned char val : 8;
420 struct cpu_defaults_t f;
421} __attribute__((packed));
422
423struct crtc_total_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800424 u32 crtc_h_total : 10;
425 u32 : 6;
426 u32 crtc_v_total : 10;
427 u32 : 6;
Richard Purdieaac51f02005-09-06 15:19:03 -0700428} __attribute__((packed));
429
430union crtc_total_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800431 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700432 struct crtc_total_t f;
433} __attribute__((packed));
434
435struct crtc_ss_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800436 u32 ss_start : 10;
437 u32 : 6;
438 u32 ss_end : 10;
439 u32 : 2;
440 u32 ss_align : 1;
441 u32 ss_pol : 1;
442 u32 ss_run_mode : 1;
443 u32 ss_en : 1;
Richard Purdieaac51f02005-09-06 15:19:03 -0700444} __attribute__((packed));
445
446union crtc_ss_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800447 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700448 struct crtc_ss_t f;
449} __attribute__((packed));
450
451struct active_h_disp_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800452 u32 active_h_start : 10;
453 u32 : 6;
454 u32 active_h_end : 10;
455 u32 : 6;
Richard Purdieaac51f02005-09-06 15:19:03 -0700456} __attribute__((packed));
457
458union active_h_disp_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800459 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700460 struct active_h_disp_t f;
461} __attribute__((packed));
462
463struct active_v_disp_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800464 u32 active_v_start : 10;
465 u32 : 6;
466 u32 active_v_end : 10;
467 u32 : 6;
Richard Purdieaac51f02005-09-06 15:19:03 -0700468} __attribute__((packed));
469
470union active_v_disp_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800471 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700472 struct active_v_disp_t f;
473} __attribute__((packed));
474
475struct graphic_h_disp_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800476 u32 graphic_h_start : 10;
477 u32 : 6;
478 u32 graphic_h_end : 10;
479 u32 : 6;
Richard Purdieaac51f02005-09-06 15:19:03 -0700480} __attribute__((packed));
481
482union graphic_h_disp_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800483 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700484 struct graphic_h_disp_t f;
485} __attribute__((packed));
486
487struct graphic_v_disp_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800488 u32 graphic_v_start : 10;
489 u32 : 6;
490 u32 graphic_v_end : 10;
491 u32 : 6;
Richard Purdieaac51f02005-09-06 15:19:03 -0700492} __attribute__((packed));
493
494union graphic_v_disp_u{
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800495 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700496 struct graphic_v_disp_t f;
497} __attribute__((packed));
498
499struct graphic_ctrl_t_w100 {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800500 u32 color_depth : 3;
501 u32 portrait_mode : 2;
502 u32 low_power_on : 1;
503 u32 req_freq : 4;
504 u32 en_crtc : 1;
505 u32 en_graphic_req : 1;
506 u32 en_graphic_crtc : 1;
507 u32 total_req_graphic : 9;
508 u32 lcd_pclk_on : 1;
509 u32 lcd_sclk_on : 1;
510 u32 pclk_running : 1;
511 u32 sclk_running : 1;
512 u32 : 6;
Richard Purdieaac51f02005-09-06 15:19:03 -0700513} __attribute__((packed));
514
515struct graphic_ctrl_t_w32xx {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800516 u32 color_depth : 3;
517 u32 portrait_mode : 2;
518 u32 low_power_on : 1;
519 u32 req_freq : 4;
520 u32 en_crtc : 1;
521 u32 en_graphic_req : 1;
522 u32 en_graphic_crtc : 1;
523 u32 total_req_graphic : 10;
524 u32 lcd_pclk_on : 1;
525 u32 lcd_sclk_on : 1;
526 u32 pclk_running : 1;
527 u32 sclk_running : 1;
528 u32 : 5;
Richard Purdieaac51f02005-09-06 15:19:03 -0700529} __attribute__((packed));
530
531union graphic_ctrl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800532 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700533 struct graphic_ctrl_t_w100 f_w100;
534 struct graphic_ctrl_t_w32xx f_w32xx;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535} __attribute__((packed));
536
537struct video_ctrl_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800538 u32 video_mode : 1;
539 u32 keyer_en : 1;
540 u32 en_video_req : 1;
541 u32 en_graphic_req_video : 1;
542 u32 en_video_crtc : 1;
543 u32 video_hor_exp : 2;
544 u32 video_ver_exp : 2;
545 u32 uv_combine : 1;
546 u32 total_req_video : 9;
547 u32 video_ch_sel : 1;
548 u32 video_portrait : 2;
549 u32 yuv2rgb_en : 1;
550 u32 yuv2rgb_option : 1;
551 u32 video_inv_hor : 1;
552 u32 video_inv_ver : 1;
553 u32 gamma_sel : 2;
554 u32 dis_limit : 1;
555 u32 en_uv_hblend : 1;
556 u32 rgb_gamma_sel : 2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557} __attribute__((packed));
558
559union video_ctrl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800560 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700561 struct video_ctrl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562} __attribute__((packed));
563
564struct disp_db_buf_cntl_rd_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800565 u32 en_db_buf : 1;
566 u32 update_db_buf_done : 1;
567 u32 db_buf_cntl : 6;
568 u32 : 24;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569} __attribute__((packed));
570
571union disp_db_buf_cntl_rd_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800572 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700573 struct disp_db_buf_cntl_rd_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574} __attribute__((packed));
575
576struct disp_db_buf_cntl_wr_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800577 u32 en_db_buf : 1;
578 u32 update_db_buf : 1;
579 u32 db_buf_cntl : 6;
580 u32 : 24;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581} __attribute__((packed));
582
583union disp_db_buf_cntl_wr_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800584 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700585 struct disp_db_buf_cntl_wr_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586} __attribute__((packed));
587
588struct gamma_value1_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800589 u32 gamma1 : 8;
590 u32 gamma2 : 8;
591 u32 gamma3 : 8;
592 u32 gamma4 : 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593} __attribute__((packed));
594
595union gamma_value1_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800596 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700597 struct gamma_value1_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598} __attribute__((packed));
599
600struct gamma_value2_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800601 u32 gamma5 : 8;
602 u32 gamma6 : 8;
603 u32 gamma7 : 8;
604 u32 gamma8 : 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605} __attribute__((packed));
606
607union gamma_value2_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800608 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700609 struct gamma_value2_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610} __attribute__((packed));
611
612struct gamma_slope_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800613 u32 slope1 : 3;
614 u32 slope2 : 3;
615 u32 slope3 : 3;
616 u32 slope4 : 3;
617 u32 slope5 : 3;
618 u32 slope6 : 3;
619 u32 slope7 : 3;
620 u32 slope8 : 3;
621 u32 : 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622} __attribute__((packed));
623
624union gamma_slope_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800625 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700626 struct gamma_slope_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627} __attribute__((packed));
628
629struct mc_ext_mem_location_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800630 u32 mc_ext_mem_start : 16;
631 u32 mc_ext_mem_top : 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632} __attribute__((packed));
633
634union mc_ext_mem_location_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800635 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700636 struct mc_ext_mem_location_t f;
637} __attribute__((packed));
638
639struct mc_fb_location_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800640 u32 mc_fb_start : 16;
641 u32 mc_fb_top : 16;
Richard Purdieaac51f02005-09-06 15:19:03 -0700642} __attribute__((packed));
643
644union mc_fb_location_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800645 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700646 struct mc_fb_location_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647} __attribute__((packed));
648
649struct clk_pin_cntl_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800650 u32 osc_en : 1;
651 u32 osc_gain : 5;
652 u32 dont_use_xtalin : 1;
653 u32 xtalin_pm_en : 1;
654 u32 xtalin_dbl_en : 1;
655 u32 : 7;
656 u32 cg_debug : 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657} __attribute__((packed));
658
659union clk_pin_cntl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800660 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700661 struct clk_pin_cntl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662} __attribute__((packed));
663
664struct pll_ref_fb_div_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800665 u32 pll_ref_div : 4;
666 u32 : 4;
667 u32 pll_fb_div_int : 6;
668 u32 : 2;
669 u32 pll_fb_div_frac : 3;
670 u32 : 1;
671 u32 pll_reset_time : 4;
672 u32 pll_lock_time : 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673} __attribute__((packed));
674
675union pll_ref_fb_div_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800676 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700677 struct pll_ref_fb_div_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678} __attribute__((packed));
679
680struct pll_cntl_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800681 u32 pll_pwdn : 1;
682 u32 pll_reset : 1;
683 u32 pll_pm_en : 1;
684 u32 pll_mode : 1;
685 u32 pll_refclk_sel : 1;
686 u32 pll_fbclk_sel : 1;
687 u32 pll_tcpoff : 1;
688 u32 pll_pcp : 3;
689 u32 pll_pvg : 3;
690 u32 pll_vcofr : 1;
691 u32 pll_ioffset : 2;
692 u32 pll_pecc_mode : 2;
693 u32 pll_pecc_scon : 2;
694 u32 pll_dactal : 4;
695 u32 pll_cp_clip : 2;
696 u32 pll_conf : 3;
697 u32 pll_mbctrl : 2;
698 u32 pll_ring_off : 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699} __attribute__((packed));
700
701union pll_cntl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800702 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700703 struct pll_cntl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704} __attribute__((packed));
705
706struct sclk_cntl_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800707 u32 sclk_src_sel : 2;
708 u32 : 2;
709 u32 sclk_post_div_fast : 4;
710 u32 sclk_clkon_hys : 3;
711 u32 sclk_post_div_slow : 4;
712 u32 disp_cg_ok2switch_en : 1;
713 u32 sclk_force_reg : 1;
714 u32 sclk_force_disp : 1;
715 u32 sclk_force_mc : 1;
716 u32 sclk_force_extmc : 1;
717 u32 sclk_force_cp : 1;
718 u32 sclk_force_e2 : 1;
719 u32 sclk_force_e3 : 1;
720 u32 sclk_force_idct : 1;
721 u32 sclk_force_bist : 1;
722 u32 busy_extend_cp : 1;
723 u32 busy_extend_e2 : 1;
724 u32 busy_extend_e3 : 1;
725 u32 busy_extend_idct : 1;
726 u32 : 3;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727} __attribute__((packed));
728
729union sclk_cntl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800730 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700731 struct sclk_cntl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732} __attribute__((packed));
733
734struct pclk_cntl_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800735 u32 pclk_src_sel : 2;
736 u32 : 2;
737 u32 pclk_post_div : 4;
738 u32 : 8;
739 u32 pclk_force_disp : 1;
740 u32 : 15;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741} __attribute__((packed));
742
743union pclk_cntl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800744 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700745 struct pclk_cntl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746} __attribute__((packed));
747
Richard Purdieaac51f02005-09-06 15:19:03 -0700748
749#define TESTCLK_SRC_PLL 0x01
750#define TESTCLK_SRC_SCLK 0x02
751#define TESTCLK_SRC_PCLK 0x03
752/* 4 and 5 seem to by XTAL/M */
753#define TESTCLK_SRC_XTAL 0x06
754
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755struct clk_test_cntl_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800756 u32 testclk_sel : 4;
757 u32 : 3;
758 u32 start_check_freq : 1;
759 u32 tstcount_rst : 1;
760 u32 : 15;
761 u32 test_count : 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762} __attribute__((packed));
763
764union clk_test_cntl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800765 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700766 struct clk_test_cntl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767} __attribute__((packed));
768
769struct pwrmgt_cntl_t {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800770 u32 pwm_enable : 1;
771 u32 : 1;
772 u32 pwm_mode_req : 2;
773 u32 pwm_wakeup_cond : 2;
774 u32 pwm_fast_noml_hw_en : 1;
775 u32 pwm_noml_fast_hw_en : 1;
776 u32 pwm_fast_noml_cond : 4;
777 u32 pwm_noml_fast_cond : 4;
778 u32 pwm_idle_timer : 8;
779 u32 pwm_busy_timer : 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780} __attribute__((packed));
781
782union pwrmgt_cntl_u {
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800783 u32 val : 32;
Richard Purdieaac51f02005-09-06 15:19:03 -0700784 struct pwrmgt_cntl_t f;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785} __attribute__((packed));
786
Alberto Mardegan9b0e1c52006-03-31 02:31:46 -0800787#define SRC_DATATYPE_EQU_DST 3
788
789#define ROP3_SRCCOPY 0xcc
790#define ROP3_PATCOPY 0xf0
791
792#define GMC_BRUSH_SOLID_COLOR 13
793#define GMC_BRUSH_NONE 15
794
795#define DP_SRC_MEM_RECTANGULAR 2
796
797#define DP_OP_ROP 0
798
799struct dp_gui_master_cntl_t {
800 u32 gmc_src_pitch_offset_cntl : 1;
801 u32 gmc_dst_pitch_offset_cntl : 1;
802 u32 gmc_src_clipping : 1;
803 u32 gmc_dst_clipping : 1;
804 u32 gmc_brush_datatype : 4;
805 u32 gmc_dst_datatype : 4;
806 u32 gmc_src_datatype : 3;
807 u32 gmc_byte_pix_order : 1;
808 u32 gmc_default_sel : 1;
809 u32 gmc_rop3 : 8;
810 u32 gmc_dp_src_source : 3;
811 u32 gmc_clr_cmp_fcn_dis : 1;
812 u32 : 1;
813 u32 gmc_wr_msk_dis : 1;
814 u32 gmc_dp_op : 1;
815} __attribute__((packed));
816
817union dp_gui_master_cntl_u {
818 u32 val : 32;
819 struct dp_gui_master_cntl_t f;
820} __attribute__((packed));
821
822struct rbbm_status_t {
823 u32 cmdfifo_avail : 7;
824 u32 : 1;
825 u32 hirq_on_rbb : 1;
826 u32 cprq_on_rbb : 1;
827 u32 cfrq_on_rbb : 1;
828 u32 hirq_in_rtbuf : 1;
829 u32 cprq_in_rtbuf : 1;
830 u32 cfrq_in_rtbuf : 1;
831 u32 cf_pipe_busy : 1;
832 u32 eng_ev_busy : 1;
833 u32 cp_cmdstrm_busy : 1;
834 u32 e2_busy : 1;
835 u32 rb2d_busy : 1;
836 u32 rb3d_busy : 1;
837 u32 se_busy : 1;
838 u32 re_busy : 1;
839 u32 tam_busy : 1;
840 u32 tdm_busy : 1;
841 u32 pb_busy : 1;
842 u32 : 6;
843 u32 gui_active : 1;
844} __attribute__((packed));
845
846union rbbm_status_u {
847 u32 val : 32;
848 struct rbbm_status_t f;
849} __attribute__((packed));
850
851struct dp_datatype_t {
852 u32 dp_dst_datatype : 4;
853 u32 : 4;
854 u32 dp_brush_datatype : 4;
855 u32 dp_src2_type : 1;
856 u32 dp_src2_datatype : 3;
857 u32 dp_src_datatype : 3;
858 u32 : 11;
859 u32 dp_byte_pix_order : 1;
860 u32 : 1;
861} __attribute__((packed));
862
863union dp_datatype_u {
864 u32 val : 32;
865 struct dp_datatype_t f;
866} __attribute__((packed));
867
868struct dp_mix_t {
869 u32 : 8;
870 u32 dp_src_source : 3;
871 u32 dp_src2_source : 3;
872 u32 : 2;
873 u32 dp_rop3 : 8;
874 u32 dp_op : 1;
875 u32 : 7;
876} __attribute__((packed));
877
878union dp_mix_u {
879 u32 val : 32;
880 struct dp_mix_t f;
881} __attribute__((packed));
882
883struct eng_cntl_t {
884 u32 erc_reg_rd_ws : 1;
885 u32 erc_reg_wr_ws : 1;
886 u32 erc_idle_reg_wr : 1;
887 u32 dis_engine_triggers : 1;
888 u32 dis_rop_src_uses_dst_w_h : 1;
889 u32 dis_src_uses_dst_dirmaj : 1;
890 u32 : 6;
891 u32 force_3dclk_when_2dclk : 1;
892 u32 : 19;
893} __attribute__((packed));
894
895union eng_cntl_u {
896 u32 val : 32;
897 struct eng_cntl_t f;
898} __attribute__((packed));
899
900struct dp_cntl_t {
901 u32 dst_x_dir : 1;
902 u32 dst_y_dir : 1;
903 u32 src_x_dir : 1;
904 u32 src_y_dir : 1;
905 u32 dst_major_x : 1;
906 u32 src_major_x : 1;
907 u32 : 26;
908} __attribute__((packed));
909
910union dp_cntl_u {
911 u32 val : 32;
912 struct dp_cntl_t f;
913} __attribute__((packed));
914
915struct dp_cntl_dst_dir_t {
916 u32 : 15;
917 u32 dst_y_dir : 1;
918 u32 : 15;
919 u32 dst_x_dir : 1;
920} __attribute__((packed));
921
922union dp_cntl_dst_dir_u {
923 u32 val : 32;
924 struct dp_cntl_dst_dir_t f;
925} __attribute__((packed));
926
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927#endif
928