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Mike Turquette9d9f78e2012-03-15 23:11:20 -07001/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adjustable divider clock implementation
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <linux/string.h>
19
20/*
21 * DOC: basic adjustable divider clock that cannot gate
22 *
23 * Traits of this clock:
24 * prepare - clk_prepare only ensures that parents are prepared
25 * enable - clk_enable only ensures that parents are enabled
26 * rate - rate is adjustable. clk->rate = parent->rate / divisor
27 * parent - fixed parent. No clk_set_parent support
28 */
29
30#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
31
32#define div_mask(d) ((1 << (d->width)) - 1)
Rajendra Nayak6d9252b2012-05-17 15:52:13 +053033#define is_power_of_two(i) !(i & ~i)
34
Rajendra Nayak357c3f02012-06-29 19:06:32 +053035static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
36{
37 unsigned int maxdiv = 0;
38 const struct clk_div_table *clkt;
39
40 for (clkt = table; clkt->div; clkt++)
41 if (clkt->div > maxdiv)
42 maxdiv = clkt->div;
43 return maxdiv;
44}
45
Rajendra Nayak6d9252b2012-05-17 15:52:13 +053046static unsigned int _get_maxdiv(struct clk_divider *divider)
47{
48 if (divider->flags & CLK_DIVIDER_ONE_BASED)
49 return div_mask(divider);
50 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
51 return 1 << div_mask(divider);
Rajendra Nayak357c3f02012-06-29 19:06:32 +053052 if (divider->table)
53 return _get_table_maxdiv(divider->table);
Rajendra Nayak6d9252b2012-05-17 15:52:13 +053054 return div_mask(divider) + 1;
55}
56
Rajendra Nayak357c3f02012-06-29 19:06:32 +053057static unsigned int _get_table_div(const struct clk_div_table *table,
58 unsigned int val)
59{
60 const struct clk_div_table *clkt;
61
62 for (clkt = table; clkt->div; clkt++)
63 if (clkt->val == val)
64 return clkt->div;
65 return 0;
66}
67
Rajendra Nayak6d9252b2012-05-17 15:52:13 +053068static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
69{
70 if (divider->flags & CLK_DIVIDER_ONE_BASED)
71 return val;
72 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
73 return 1 << val;
Rajendra Nayak357c3f02012-06-29 19:06:32 +053074 if (divider->table)
75 return _get_table_div(divider->table, val);
Rajendra Nayak6d9252b2012-05-17 15:52:13 +053076 return val + 1;
77}
78
Rajendra Nayak357c3f02012-06-29 19:06:32 +053079static unsigned int _get_table_val(const struct clk_div_table *table,
80 unsigned int div)
81{
82 const struct clk_div_table *clkt;
83
84 for (clkt = table; clkt->div; clkt++)
85 if (clkt->div == div)
86 return clkt->val;
87 return 0;
88}
89
Rajendra Nayak6d9252b2012-05-17 15:52:13 +053090static unsigned int _get_val(struct clk_divider *divider, u8 div)
91{
92 if (divider->flags & CLK_DIVIDER_ONE_BASED)
93 return div;
94 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
95 return __ffs(div);
Rajendra Nayak357c3f02012-06-29 19:06:32 +053096 if (divider->table)
97 return _get_table_val(divider->table, div);
Rajendra Nayak6d9252b2012-05-17 15:52:13 +053098 return div - 1;
99}
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700100
101static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
102 unsigned long parent_rate)
103{
104 struct clk_divider *divider = to_clk_divider(hw);
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530105 unsigned int div, val;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700106
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530107 val = readl(divider->reg) >> divider->shift;
108 val &= div_mask(divider);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700109
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530110 div = _get_div(divider, val);
111 if (!div) {
112 WARN(1, "%s: Invalid divisor for clock %s\n", __func__,
113 __clk_get_name(hw->clk));
114 return parent_rate;
115 }
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700116
117 return parent_rate / div;
118}
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700119
120/*
121 * The reverse of DIV_ROUND_UP: The maximum number which
122 * divided by m is r
123 */
124#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
125
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530126static bool _is_valid_table_div(const struct clk_div_table *table,
127 unsigned int div)
128{
129 const struct clk_div_table *clkt;
130
131 for (clkt = table; clkt->div; clkt++)
132 if (clkt->div == div)
133 return true;
134 return false;
135}
136
137static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
138{
139 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
140 return is_power_of_two(div);
141 if (divider->table)
142 return _is_valid_table_div(divider->table, div);
143 return true;
144}
145
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700146static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
147 unsigned long *best_parent_rate)
148{
149 struct clk_divider *divider = to_clk_divider(hw);
150 int i, bestdiv = 0;
151 unsigned long parent_rate, best = 0, now, maxdiv;
152
153 if (!rate)
154 rate = 1;
155
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530156 maxdiv = _get_maxdiv(divider);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700157
Shawn Guo81536e02012-04-12 20:50:17 +0800158 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
159 parent_rate = *best_parent_rate;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700160 bestdiv = DIV_ROUND_UP(parent_rate, rate);
161 bestdiv = bestdiv == 0 ? 1 : bestdiv;
162 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
163 return bestdiv;
164 }
165
166 /*
167 * The maximum divider we can use without overflowing
168 * unsigned long in rate * i below
169 */
170 maxdiv = min(ULONG_MAX / rate, maxdiv);
171
172 for (i = 1; i <= maxdiv; i++) {
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530173 if (!_is_valid_div(divider, i))
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530174 continue;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700175 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
176 MULT_ROUND_UP(rate, i));
177 now = parent_rate / i;
178 if (now <= rate && now > best) {
179 bestdiv = i;
180 best = now;
181 *best_parent_rate = parent_rate;
182 }
183 }
184
185 if (!bestdiv) {
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530186 bestdiv = _get_maxdiv(divider);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700187 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
188 }
189
190 return bestdiv;
191}
192
193static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
194 unsigned long *prate)
195{
196 int div;
197 div = clk_divider_bestdiv(hw, rate, prate);
198
Shawn Guo81536e02012-04-12 20:50:17 +0800199 return *prate / div;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700200}
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700201
Shawn Guo1c0035d2012-04-12 20:50:18 +0800202static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
203 unsigned long parent_rate)
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700204{
205 struct clk_divider *divider = to_clk_divider(hw);
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530206 unsigned int div, value;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700207 unsigned long flags = 0;
208 u32 val;
209
Shawn Guo1c0035d2012-04-12 20:50:18 +0800210 div = parent_rate / rate;
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530211 value = _get_val(divider, div);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700212
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530213 if (value > div_mask(divider))
214 value = div_mask(divider);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700215
216 if (divider->lock)
217 spin_lock_irqsave(divider->lock, flags);
218
219 val = readl(divider->reg);
220 val &= ~(div_mask(divider) << divider->shift);
Rajendra Nayak6d9252b2012-05-17 15:52:13 +0530221 val |= value << divider->shift;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700222 writel(val, divider->reg);
223
224 if (divider->lock)
225 spin_unlock_irqrestore(divider->lock, flags);
226
227 return 0;
228}
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700229
Shawn Guo822c2502012-03-27 15:23:22 +0800230const struct clk_ops clk_divider_ops = {
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700231 .recalc_rate = clk_divider_recalc_rate,
232 .round_rate = clk_divider_round_rate,
233 .set_rate = clk_divider_set_rate,
234};
235EXPORT_SYMBOL_GPL(clk_divider_ops);
236
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530237static struct clk *_register_divider(struct device *dev, const char *name,
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700238 const char *parent_name, unsigned long flags,
239 void __iomem *reg, u8 shift, u8 width,
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530240 u8 clk_divider_flags, const struct clk_div_table *table,
241 spinlock_t *lock)
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700242{
243 struct clk_divider *div;
244 struct clk *clk;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700245 struct clk_init_data init;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700246
Mike Turquette27d54592012-03-26 17:51:03 -0700247 /* allocate the divider */
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700248 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700249 if (!div) {
250 pr_err("%s: could not allocate divider clk\n", __func__);
Mike Turquette27d54592012-03-26 17:51:03 -0700251 return ERR_PTR(-ENOMEM);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700252 }
253
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700254 init.name = name;
255 init.ops = &clk_divider_ops;
Rajendra Nayakf7d8caa2012-06-01 14:02:47 +0530256 init.flags = flags | CLK_IS_BASIC;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700257 init.parent_names = (parent_name ? &parent_name: NULL);
258 init.num_parents = (parent_name ? 1 : 0);
259
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700260 /* struct clk_divider assignments */
261 div->reg = reg;
262 div->shift = shift;
263 div->width = width;
264 div->flags = clk_divider_flags;
265 div->lock = lock;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700266 div->hw.init = &init;
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530267 div->table = table;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700268
Mike Turquette27d54592012-03-26 17:51:03 -0700269 /* register the clock */
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700270 clk = clk_register(dev, &div->hw);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700271
Mike Turquette27d54592012-03-26 17:51:03 -0700272 if (IS_ERR(clk))
273 kfree(div);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700274
Mike Turquette27d54592012-03-26 17:51:03 -0700275 return clk;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700276}
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530277
278/**
279 * clk_register_divider - register a divider clock with the clock framework
280 * @dev: device registering this clock
281 * @name: name of this clock
282 * @parent_name: name of clock's parent
283 * @flags: framework-specific flags
284 * @reg: register address to adjust divider
285 * @shift: number of bits to shift the bitfield
286 * @width: width of the bitfield
287 * @clk_divider_flags: divider-specific flags for this clock
288 * @lock: shared register lock for this clock
289 */
290struct clk *clk_register_divider(struct device *dev, const char *name,
291 const char *parent_name, unsigned long flags,
292 void __iomem *reg, u8 shift, u8 width,
293 u8 clk_divider_flags, spinlock_t *lock)
294{
295 return _register_divider(dev, name, parent_name, flags, reg, shift,
296 width, clk_divider_flags, NULL, lock);
297}
298
299/**
300 * clk_register_divider_table - register a table based divider clock with
301 * the clock framework
302 * @dev: device registering this clock
303 * @name: name of this clock
304 * @parent_name: name of clock's parent
305 * @flags: framework-specific flags
306 * @reg: register address to adjust divider
307 * @shift: number of bits to shift the bitfield
308 * @width: width of the bitfield
309 * @clk_divider_flags: divider-specific flags for this clock
310 * @table: array of divider/value pairs ending with a div set to 0
311 * @lock: shared register lock for this clock
312 */
313struct clk *clk_register_divider_table(struct device *dev, const char *name,
314 const char *parent_name, unsigned long flags,
315 void __iomem *reg, u8 shift, u8 width,
316 u8 clk_divider_flags, const struct clk_div_table *table,
317 spinlock_t *lock)
318{
319 return _register_divider(dev, name, parent_name, flags, reg, shift,
320 width, clk_divider_flags, table, lock);
321}