Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame^] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/fs.h> |
| 19 | #include <linux/file.h> |
| 20 | #include <linux/sync.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/debugfs.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/dma-mapping.h> |
| 25 | #include <linux/dma-buf.h> |
| 26 | #include <linux/msm_ion.h> |
| 27 | |
| 28 | #include "sde_rotator_core.h" |
| 29 | #include "sde_rotator_util.h" |
| 30 | #include "sde_rotator_smmu.h" |
| 31 | #include "sde_rotator_r3.h" |
| 32 | #include "sde_rotator_r3_internal.h" |
| 33 | #include "sde_rotator_r3_hwio.h" |
| 34 | #include "sde_rotator_r3_debug.h" |
| 35 | #include "sde_rotator_trace.h" |
| 36 | |
| 37 | /* XIN mapping */ |
| 38 | #define XIN_SSPP 0 |
| 39 | #define XIN_WRITEBACK 1 |
| 40 | |
| 41 | /* wait for at most 2 vsync for lowest refresh rate (24hz) */ |
| 42 | #define KOFF_TIMEOUT msecs_to_jiffies(42 * 32) |
| 43 | |
| 44 | /* Macro for constructing the REGDMA command */ |
| 45 | #define SDE_REGDMA_WRITE(p, off, data) \ |
| 46 | do { \ |
| 47 | *p++ = REGDMA_OP_REGWRITE | \ |
| 48 | ((off) & REGDMA_ADDR_OFFSET_MASK); \ |
| 49 | *p++ = (data); \ |
| 50 | } while (0) |
| 51 | |
| 52 | #define SDE_REGDMA_MODIFY(p, off, mask, data) \ |
| 53 | do { \ |
| 54 | *p++ = REGDMA_OP_REGMODIFY | \ |
| 55 | ((off) & REGDMA_ADDR_OFFSET_MASK); \ |
| 56 | *p++ = (mask); \ |
| 57 | *p++ = (data); \ |
| 58 | } while (0) |
| 59 | |
| 60 | #define SDE_REGDMA_BLKWRITE_INC(p, off, len) \ |
| 61 | do { \ |
| 62 | *p++ = REGDMA_OP_BLKWRITE_INC | \ |
| 63 | ((off) & REGDMA_ADDR_OFFSET_MASK); \ |
| 64 | *p++ = (len); \ |
| 65 | } while (0) |
| 66 | |
| 67 | #define SDE_REGDMA_BLKWRITE_DATA(p, data) \ |
| 68 | do { \ |
| 69 | *(p) = (data); \ |
| 70 | (p)++; \ |
| 71 | } while (0) |
| 72 | |
| 73 | /* Macro for directly accessing mapped registers */ |
| 74 | #define SDE_ROTREG_WRITE(base, off, data) \ |
| 75 | writel_relaxed(data, (base + (off))) |
| 76 | |
| 77 | #define SDE_ROTREG_READ(base, off) \ |
| 78 | readl_relaxed(base + (off)) |
| 79 | |
| 80 | /** |
| 81 | * sde_hw_rotator_get_ctx(): Retrieve rotator context from rotator HW based |
| 82 | * on provided session_id. Each rotator has a different session_id. |
| 83 | */ |
| 84 | static struct sde_hw_rotator_context *sde_hw_rotator_get_ctx( |
| 85 | struct sde_hw_rotator *rot, u32 session_id, |
| 86 | enum sde_rot_queue_prio q_id) |
| 87 | { |
| 88 | int i; |
| 89 | struct sde_hw_rotator_context *ctx = NULL; |
| 90 | |
| 91 | for (i = 0; i < SDE_HW_ROT_REGDMA_TOTAL_CTX; i++) { |
| 92 | ctx = rot->rotCtx[q_id][i]; |
| 93 | |
| 94 | if (ctx && (ctx->session_id == session_id)) { |
| 95 | SDEROT_DBG( |
| 96 | "rotCtx sloti[%d][%d] ==> ctx:%p | session-id:%d\n", |
| 97 | q_id, i, ctx, ctx->session_id); |
| 98 | return ctx; |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | return NULL; |
| 103 | } |
| 104 | |
| 105 | /* |
| 106 | * sde_hw_rotator_map_vaddr - map the debug buffer to kernel space |
| 107 | * @dbgbuf: Pointer to debug buffer |
| 108 | * @buf: Pointer to layer buffer structure |
| 109 | * @data: Pointer to h/w mapped buffer structure |
| 110 | */ |
| 111 | static void sde_hw_rotator_map_vaddr(struct sde_dbg_buf *dbgbuf, |
| 112 | struct sde_layer_buffer *buf, struct sde_mdp_data *data) |
| 113 | { |
| 114 | dbgbuf->dmabuf = data->p[0].srcp_dma_buf; |
| 115 | dbgbuf->buflen = data->p[0].srcp_dma_buf->size; |
| 116 | |
| 117 | dbgbuf->vaddr = NULL; |
| 118 | dbgbuf->width = buf->width; |
| 119 | dbgbuf->height = buf->height; |
| 120 | |
| 121 | if (dbgbuf->dmabuf && (dbgbuf->buflen > 0)) { |
| 122 | dma_buf_begin_cpu_access(dbgbuf->dmabuf, 0, dbgbuf->buflen, |
| 123 | DMA_FROM_DEVICE); |
| 124 | dbgbuf->vaddr = dma_buf_kmap(dbgbuf->dmabuf, 0); |
| 125 | SDEROT_DBG("vaddr mapping: 0x%p/%ld w:%d/h:%d\n", |
| 126 | dbgbuf->vaddr, dbgbuf->buflen, |
| 127 | dbgbuf->width, dbgbuf->height); |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * sde_hw_rotator_unmap_vaddr - unmap the debug buffer from kernel space |
| 133 | * @dbgbuf: Pointer to debug buffer |
| 134 | */ |
| 135 | static void sde_hw_rotator_unmap_vaddr(struct sde_dbg_buf *dbgbuf) |
| 136 | { |
| 137 | if (dbgbuf->vaddr) { |
| 138 | dma_buf_kunmap(dbgbuf->dmabuf, 0, dbgbuf->vaddr); |
| 139 | dma_buf_end_cpu_access(dbgbuf->dmabuf, 0, dbgbuf->buflen, |
| 140 | DMA_FROM_DEVICE); |
| 141 | } |
| 142 | |
| 143 | dbgbuf->vaddr = NULL; |
| 144 | dbgbuf->dmabuf = NULL; |
| 145 | dbgbuf->buflen = 0; |
| 146 | dbgbuf->width = 0; |
| 147 | dbgbuf->height = 0; |
| 148 | } |
| 149 | |
| 150 | /* |
| 151 | * sde_hw_rotator_setup_timestamp_packet - setup timestamp writeback command |
| 152 | * @ctx: Pointer to rotator context |
| 153 | * @mask: Bit mask location of the timestamp |
| 154 | * @swts: Software timestamp |
| 155 | */ |
| 156 | static void sde_hw_rotator_setup_timestamp_packet( |
| 157 | struct sde_hw_rotator_context *ctx, u32 mask, u32 swts) |
| 158 | { |
| 159 | u32 *wrptr; |
| 160 | |
| 161 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 162 | |
| 163 | /* |
| 164 | * Create a dummy packet write out to 1 location for timestamp |
| 165 | * generation. |
| 166 | */ |
| 167 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_SSPP_SRC_SIZE, 6); |
| 168 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x00010001); |
| 169 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 170 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 171 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x00010001); |
| 172 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 173 | SDE_REGDMA_BLKWRITE_DATA(wrptr, ctx->ts_addr); |
| 174 | SDE_REGDMA_WRITE(wrptr, ROT_SSPP_SRC_YSTRIDE0, 4); |
| 175 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_SSPP_SRC_FORMAT, 4); |
| 176 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x004037FF); |
| 177 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x03020100); |
| 178 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x80000000); |
| 179 | SDE_REGDMA_BLKWRITE_DATA(wrptr, ctx->timestamp); |
| 180 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_WB_DST_FORMAT, 4); |
| 181 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x000037FF); |
| 182 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 183 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x03020100); |
| 184 | SDE_REGDMA_BLKWRITE_DATA(wrptr, ctx->ts_addr); |
| 185 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_YSTRIDE0, 4); |
| 186 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_SIZE, 0x00010001); |
| 187 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_IMG_SIZE, 0x00010001); |
| 188 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_XY, 0); |
| 189 | SDE_REGDMA_WRITE(wrptr, ROTTOP_DNSC, 0); |
| 190 | SDE_REGDMA_WRITE(wrptr, ROTTOP_OP_MODE, 1); |
| 191 | SDE_REGDMA_MODIFY(wrptr, REGDMA_TIMESTAMP_REG, mask, swts); |
| 192 | SDE_REGDMA_WRITE(wrptr, ROTTOP_START_CTRL, 1); |
| 193 | |
| 194 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 195 | } |
| 196 | |
| 197 | /* |
| 198 | * sde_hw_rotator_setup_fetchengine - setup fetch engine |
| 199 | * @ctx: Pointer to rotator context |
| 200 | * @queue_id: Priority queue identifier |
| 201 | * @cfg: Fetch configuration |
| 202 | * @danger_lut: real-time QoS LUT for danger setting (not used) |
| 203 | * @safe_lut: real-time QoS LUT for safe setting (not used) |
| 204 | * @flags: Control flag |
| 205 | */ |
| 206 | static void sde_hw_rotator_setup_fetchengine(struct sde_hw_rotator_context *ctx, |
| 207 | enum sde_rot_queue_prio queue_id, |
| 208 | struct sde_hw_rot_sspp_cfg *cfg, u32 danger_lut, u32 safe_lut, |
| 209 | u32 flags) |
| 210 | { |
| 211 | struct sde_hw_rotator *rot = ctx->rot; |
| 212 | struct sde_mdp_format_params *fmt; |
| 213 | struct sde_mdp_data *data; |
| 214 | u32 *wrptr; |
| 215 | u32 opmode = 0; |
| 216 | u32 chroma_samp = 0; |
| 217 | u32 src_format = 0; |
| 218 | u32 unpack = 0; |
| 219 | u32 width = cfg->img_width; |
| 220 | u32 height = cfg->img_height; |
| 221 | u32 fetch_blocksize = 0; |
| 222 | int i; |
| 223 | |
| 224 | if (ctx->rot->mode == ROT_REGDMA_ON) { |
| 225 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_INT_EN, |
| 226 | REGDMA_INT_MASK); |
| 227 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_OP_MODE, |
| 228 | REGDMA_EN); |
| 229 | } |
| 230 | |
| 231 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 232 | |
| 233 | /* source image setup */ |
| 234 | if ((flags & SDE_ROT_FLAG_DEINTERLACE) |
| 235 | && !(flags & SDE_ROT_FLAG_SOURCE_ROTATED_90)) { |
| 236 | for (i = 0; i < cfg->src_plane.num_planes; i++) |
| 237 | cfg->src_plane.ystride[i] *= 2; |
| 238 | width *= 2; |
| 239 | height /= 2; |
| 240 | } |
| 241 | |
| 242 | /* |
| 243 | * REGDMA BLK write from SRC_SIZE to OP_MODE, total 15 registers |
| 244 | */ |
| 245 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_SSPP_SRC_SIZE, 15); |
| 246 | |
| 247 | /* SRC_SIZE, SRC_IMG_SIZE, SRC_XY, OUT_SIZE, OUT_XY */ |
| 248 | SDE_REGDMA_BLKWRITE_DATA(wrptr, |
| 249 | cfg->src_rect->w | (cfg->src_rect->h << 16)); |
| 250 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); /* SRC_IMG_SIZE unused */ |
| 251 | SDE_REGDMA_BLKWRITE_DATA(wrptr, |
| 252 | cfg->src_rect->x | (cfg->src_rect->y << 16)); |
| 253 | SDE_REGDMA_BLKWRITE_DATA(wrptr, |
| 254 | cfg->src_rect->w | (cfg->src_rect->h << 16)); |
| 255 | SDE_REGDMA_BLKWRITE_DATA(wrptr, |
| 256 | cfg->src_rect->x | (cfg->src_rect->y << 16)); |
| 257 | |
| 258 | /* SRC_ADDR [0-3], SRC_YSTRIDE [0-1] */ |
| 259 | data = cfg->data; |
| 260 | for (i = 0; i < SDE_ROT_MAX_PLANES; i++) |
| 261 | SDE_REGDMA_BLKWRITE_DATA(wrptr, data->p[i].addr); |
| 262 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->src_plane.ystride[0] | |
| 263 | (cfg->src_plane.ystride[1] << 16)); |
| 264 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->src_plane.ystride[2] | |
| 265 | (cfg->src_plane.ystride[3] << 16)); |
| 266 | |
| 267 | /* UNUSED, write 0 */ |
| 268 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 269 | |
| 270 | /* setup source format */ |
| 271 | fmt = cfg->fmt; |
| 272 | |
| 273 | chroma_samp = fmt->chroma_sample; |
| 274 | if (flags & SDE_ROT_FLAG_SOURCE_ROTATED_90) { |
| 275 | if (chroma_samp == SDE_MDP_CHROMA_H2V1) |
| 276 | chroma_samp = SDE_MDP_CHROMA_H1V2; |
| 277 | else if (chroma_samp == SDE_MDP_CHROMA_H1V2) |
| 278 | chroma_samp = SDE_MDP_CHROMA_H2V1; |
| 279 | } |
| 280 | |
| 281 | src_format = (chroma_samp << 23) | |
| 282 | (fmt->fetch_planes << 19) | |
| 283 | (fmt->bits[C3_ALPHA] << 6) | |
| 284 | (fmt->bits[C2_R_Cr] << 4) | |
| 285 | (fmt->bits[C1_B_Cb] << 2) | |
| 286 | (fmt->bits[C0_G_Y] << 0); |
| 287 | |
| 288 | if (fmt->alpha_enable && |
| 289 | (fmt->fetch_planes == SDE_MDP_PLANE_INTERLEAVED)) |
| 290 | src_format |= BIT(8); /* SRCC3_EN */ |
| 291 | |
| 292 | src_format |= ((fmt->unpack_count - 1) << 12) | |
| 293 | (fmt->unpack_tight << 17) | |
| 294 | (fmt->unpack_align_msb << 18) | |
| 295 | ((fmt->bpp - 1) << 9) | |
| 296 | ((fmt->frame_format & 3) << 30); |
| 297 | |
| 298 | if (flags & SDE_ROT_FLAG_ROT_90) |
| 299 | src_format |= BIT(11); /* ROT90 */ |
| 300 | |
| 301 | if (sde_mdp_is_ubwc_format(fmt)) |
| 302 | opmode |= BIT(0); /* BWC_DEC_EN */ |
| 303 | |
| 304 | /* if this is YUV pixel format, enable CSC */ |
| 305 | if (sde_mdp_is_yuv_format(fmt)) |
| 306 | src_format |= BIT(15); /* SRC_COLOR_SPACE */ |
| 307 | |
| 308 | if (fmt->pixel_mode == SDE_MDP_PIXEL_10BIT) |
| 309 | src_format |= BIT(14); /* UNPACK_DX_FORMAT */ |
| 310 | |
| 311 | /* SRC_FORMAT */ |
| 312 | SDE_REGDMA_BLKWRITE_DATA(wrptr, src_format); |
| 313 | |
| 314 | /* setup source unpack pattern */ |
| 315 | unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | |
| 316 | (fmt->element[1] << 8) | (fmt->element[0] << 0); |
| 317 | |
| 318 | /* SRC_UNPACK_PATTERN */ |
| 319 | SDE_REGDMA_BLKWRITE_DATA(wrptr, unpack); |
| 320 | |
| 321 | /* setup source op mode */ |
| 322 | if (flags & SDE_ROT_FLAG_FLIP_LR) |
| 323 | opmode |= BIT(13); /* FLIP_MODE L/R horizontal flip */ |
| 324 | if (flags & SDE_ROT_FLAG_FLIP_UD) |
| 325 | opmode |= BIT(14); /* FLIP_MODE U/D vertical flip */ |
| 326 | opmode |= BIT(31); /* MDSS_MDP_OP_PE_OVERRIDE */ |
| 327 | |
| 328 | /* SRC_OP_MODE */ |
| 329 | SDE_REGDMA_BLKWRITE_DATA(wrptr, opmode); |
| 330 | |
| 331 | /* setup source fetch config, TP10 uses different block size */ |
| 332 | if (sde_mdp_is_tp10_format(fmt)) |
| 333 | fetch_blocksize = SDE_ROT_SSPP_FETCH_BLOCKSIZE_96; |
| 334 | else |
| 335 | fetch_blocksize = SDE_ROT_SSPP_FETCH_BLOCKSIZE_128; |
| 336 | SDE_REGDMA_WRITE(wrptr, ROT_SSPP_FETCH_CONFIG, |
| 337 | fetch_blocksize | |
| 338 | SDE_ROT_SSPP_FETCH_CONFIG_RESET_VALUE | |
| 339 | ((rot->highest_bank & 0x3) << 18)); |
| 340 | |
| 341 | /* setup source buffer plane security status */ |
| 342 | if (flags & SDE_ROT_FLAG_SECURE_OVERLAY_SESSION) { |
| 343 | SDE_REGDMA_WRITE(wrptr, ROT_SSPP_SRC_ADDR_SW_STATUS, 0xF); |
| 344 | ctx->is_secure = true; |
| 345 | } |
| 346 | |
| 347 | /* Update command queue write ptr */ |
| 348 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 349 | } |
| 350 | |
| 351 | /* |
| 352 | * sde_hw_rotator_setup_wbengine - setup writeback engine |
| 353 | * @ctx: Pointer to rotator context |
| 354 | * @queue_id: Priority queue identifier |
| 355 | * @cfg: Writeback configuration |
| 356 | * @flags: Control flag |
| 357 | */ |
| 358 | static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx, |
| 359 | enum sde_rot_queue_prio queue_id, |
| 360 | struct sde_hw_rot_wb_cfg *cfg, |
| 361 | u32 flags) |
| 362 | { |
| 363 | struct sde_mdp_format_params *fmt; |
| 364 | u32 *wrptr; |
| 365 | u32 pack = 0; |
| 366 | u32 dst_format = 0; |
| 367 | int i; |
| 368 | |
| 369 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 370 | |
| 371 | fmt = cfg->fmt; |
| 372 | |
| 373 | /* setup WB DST format */ |
| 374 | dst_format |= (fmt->chroma_sample << 23) | |
| 375 | (fmt->fetch_planes << 19) | |
| 376 | (fmt->bits[C3_ALPHA] << 6) | |
| 377 | (fmt->bits[C2_R_Cr] << 4) | |
| 378 | (fmt->bits[C1_B_Cb] << 2) | |
| 379 | (fmt->bits[C0_G_Y] << 0); |
| 380 | |
| 381 | /* alpha control */ |
| 382 | if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) { |
| 383 | dst_format |= BIT(8); |
| 384 | if (!fmt->alpha_enable) { |
| 385 | dst_format |= BIT(14); |
| 386 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_ALPHA_X_VALUE, 0); |
| 387 | } |
| 388 | } |
| 389 | |
| 390 | dst_format |= ((fmt->unpack_count - 1) << 12) | |
| 391 | (fmt->unpack_tight << 17) | |
| 392 | (fmt->unpack_align_msb << 18) | |
| 393 | ((fmt->bpp - 1) << 9) | |
| 394 | ((fmt->frame_format & 3) << 30); |
| 395 | |
| 396 | if (sde_mdp_is_yuv_format(fmt)) |
| 397 | dst_format |= BIT(15); |
| 398 | |
| 399 | if (fmt->pixel_mode == SDE_MDP_PIXEL_10BIT) |
| 400 | dst_format |= BIT(21); /* PACK_DX_FORMAT */ |
| 401 | |
| 402 | /* |
| 403 | * REGDMA BLK write, from DST_FORMAT to DST_YSTRIDE 1, total 9 regs |
| 404 | */ |
| 405 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_WB_DST_FORMAT, 9); |
| 406 | |
| 407 | /* DST_FORMAT */ |
| 408 | SDE_REGDMA_BLKWRITE_DATA(wrptr, dst_format); |
| 409 | |
| 410 | /* DST_OP_MODE */ |
| 411 | if (sde_mdp_is_ubwc_format(fmt)) |
| 412 | SDE_REGDMA_BLKWRITE_DATA(wrptr, BIT(0)); |
| 413 | else |
| 414 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 415 | |
| 416 | /* DST_PACK_PATTERN */ |
| 417 | pack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | |
| 418 | (fmt->element[1] << 8) | (fmt->element[0] << 0); |
| 419 | SDE_REGDMA_BLKWRITE_DATA(wrptr, pack); |
| 420 | |
| 421 | /* DST_ADDR [0-3], DST_YSTRIDE [0-1] */ |
| 422 | for (i = 0; i < SDE_ROT_MAX_PLANES; i++) |
| 423 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->data->p[i].addr); |
| 424 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->dst_plane.ystride[0] | |
| 425 | (cfg->dst_plane.ystride[1] << 16)); |
| 426 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->dst_plane.ystride[2] | |
| 427 | (cfg->dst_plane.ystride[3] << 16)); |
| 428 | |
| 429 | /* setup WB out image size and ROI */ |
| 430 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_IMG_SIZE, |
| 431 | cfg->img_width | (cfg->img_height << 16)); |
| 432 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_SIZE, |
| 433 | cfg->dst_rect->w | (cfg->dst_rect->h << 16)); |
| 434 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_XY, |
| 435 | cfg->dst_rect->x | (cfg->dst_rect->y << 16)); |
| 436 | |
| 437 | /* |
| 438 | * setup Downscale factor |
| 439 | */ |
| 440 | SDE_REGDMA_WRITE(wrptr, ROTTOP_DNSC, |
| 441 | cfg->v_downscale_factor | |
| 442 | (cfg->h_downscale_factor << 16)); |
| 443 | |
| 444 | /* write config setup for bank configration */ |
| 445 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG, |
| 446 | (ctx->rot->highest_bank & 0x3) << 8); |
| 447 | |
| 448 | if (flags & SDE_ROT_FLAG_ROT_90) |
| 449 | SDE_REGDMA_WRITE(wrptr, ROTTOP_OP_MODE, 0x3); |
| 450 | else |
| 451 | SDE_REGDMA_WRITE(wrptr, ROTTOP_OP_MODE, 0x1); |
| 452 | |
| 453 | /* Update command queue write ptr */ |
| 454 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 455 | } |
| 456 | |
| 457 | /* |
| 458 | * sde_hw_rotator_start_no_regdma - start non-regdma operation |
| 459 | * @ctx: Pointer to rotator context |
| 460 | * @queue_id: Priority queue identifier |
| 461 | */ |
| 462 | static u32 sde_hw_rotator_start_no_regdma(struct sde_hw_rotator_context *ctx, |
| 463 | enum sde_rot_queue_prio queue_id) |
| 464 | { |
| 465 | struct sde_hw_rotator *rot = ctx->rot; |
| 466 | u32 *wrptr; |
| 467 | u32 *rdptr; |
| 468 | u8 *addr; |
| 469 | u32 mask; |
| 470 | u32 blksize; |
| 471 | |
| 472 | rdptr = sde_hw_rotator_get_regdma_segment_base(ctx); |
| 473 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 474 | |
| 475 | if (rot->irq_num >= 0) { |
| 476 | SDE_REGDMA_WRITE(wrptr, ROTTOP_INTR_EN, 1); |
| 477 | SDE_REGDMA_WRITE(wrptr, ROTTOP_INTR_CLEAR, 1); |
| 478 | reinit_completion(&ctx->rot_comp); |
| 479 | enable_irq(rot->irq_num); |
| 480 | } |
| 481 | |
| 482 | SDE_REGDMA_WRITE(wrptr, ROTTOP_START_CTRL, 1); |
| 483 | |
| 484 | /* Update command queue write ptr */ |
| 485 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 486 | |
| 487 | SDEROT_DBG("BEGIN %d\n", ctx->timestamp); |
| 488 | /* Write all command stream to Rotator blocks */ |
| 489 | /* Rotator will start right away after command stream finish writing */ |
| 490 | while (rdptr < wrptr) { |
| 491 | u32 op = REGDMA_OP_MASK & *rdptr; |
| 492 | |
| 493 | switch (op) { |
| 494 | case REGDMA_OP_NOP: |
| 495 | SDEROT_DBG("NOP\n"); |
| 496 | rdptr++; |
| 497 | break; |
| 498 | case REGDMA_OP_REGWRITE: |
| 499 | SDEROT_DBG("REGW %6.6x %8.8x\n", |
| 500 | rdptr[0] & REGDMA_ADDR_OFFSET_MASK, |
| 501 | rdptr[1]); |
| 502 | addr = rot->mdss_base + |
| 503 | (*rdptr++ & REGDMA_ADDR_OFFSET_MASK); |
| 504 | writel_relaxed(*rdptr++, addr); |
| 505 | break; |
| 506 | case REGDMA_OP_REGMODIFY: |
| 507 | SDEROT_DBG("REGM %6.6x %8.8x %8.8x\n", |
| 508 | rdptr[0] & REGDMA_ADDR_OFFSET_MASK, |
| 509 | rdptr[1], rdptr[2]); |
| 510 | addr = rot->mdss_base + |
| 511 | (*rdptr++ & REGDMA_ADDR_OFFSET_MASK); |
| 512 | mask = *rdptr++; |
| 513 | writel_relaxed((readl_relaxed(addr) & mask) | *rdptr++, |
| 514 | addr); |
| 515 | break; |
| 516 | case REGDMA_OP_BLKWRITE_SINGLE: |
| 517 | SDEROT_DBG("BLKWS %6.6x %6.6x\n", |
| 518 | rdptr[0] & REGDMA_ADDR_OFFSET_MASK, |
| 519 | rdptr[1]); |
| 520 | addr = rot->mdss_base + |
| 521 | (*rdptr++ & REGDMA_ADDR_OFFSET_MASK); |
| 522 | blksize = *rdptr++; |
| 523 | while (blksize--) { |
| 524 | SDEROT_DBG("DATA %8.8x\n", rdptr[0]); |
| 525 | writel_relaxed(*rdptr++, addr); |
| 526 | } |
| 527 | break; |
| 528 | case REGDMA_OP_BLKWRITE_INC: |
| 529 | SDEROT_DBG("BLKWI %6.6x %6.6x\n", |
| 530 | rdptr[0] & REGDMA_ADDR_OFFSET_MASK, |
| 531 | rdptr[1]); |
| 532 | addr = rot->mdss_base + |
| 533 | (*rdptr++ & REGDMA_ADDR_OFFSET_MASK); |
| 534 | blksize = *rdptr++; |
| 535 | while (blksize--) { |
| 536 | SDEROT_DBG("DATA %8.8x\n", rdptr[0]); |
| 537 | writel_relaxed(*rdptr++, addr); |
| 538 | addr += 4; |
| 539 | } |
| 540 | break; |
| 541 | default: |
| 542 | /* Other not supported OP mode |
| 543 | * Skip data for now for unregonized OP mode |
| 544 | */ |
| 545 | SDEROT_DBG("UNDEFINED\n"); |
| 546 | rdptr++; |
| 547 | break; |
| 548 | } |
| 549 | } |
| 550 | SDEROT_DBG("END %d\n", ctx->timestamp); |
| 551 | |
| 552 | return ctx->timestamp; |
| 553 | } |
| 554 | |
| 555 | /* |
| 556 | * sde_hw_rotator_start_regdma - start regdma operation |
| 557 | * @ctx: Pointer to rotator context |
| 558 | * @queue_id: Priority queue identifier |
| 559 | */ |
| 560 | static u32 sde_hw_rotator_start_regdma(struct sde_hw_rotator_context *ctx, |
| 561 | enum sde_rot_queue_prio queue_id) |
| 562 | { |
| 563 | struct sde_hw_rotator *rot = ctx->rot; |
| 564 | u32 *wrptr; |
| 565 | u32 regdmaSlot; |
| 566 | u32 offset; |
| 567 | long length; |
| 568 | long ts_length; |
| 569 | u32 enableInt; |
| 570 | u32 swts = 0; |
| 571 | u32 mask = 0; |
| 572 | |
| 573 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 574 | |
| 575 | if (rot->irq_num >= 0) |
| 576 | reinit_completion(&ctx->regdma_comp); |
| 577 | |
| 578 | /* enable IRQ for first regdma submission from idle */ |
| 579 | if (atomic_read(&rot->regdma_submit_count) == |
| 580 | atomic_read(&rot->regdma_done_count)) { |
| 581 | SDEROT_DBG("Enable IRQ! regdma submitcnt==donecnt -> %d\n", |
| 582 | atomic_read(&rot->regdma_submit_count)); |
| 583 | enable_irq(rot->irq_num); |
| 584 | } |
| 585 | |
| 586 | /* |
| 587 | * Last ROT command must be ROT_START before REGDMA start |
| 588 | */ |
| 589 | SDE_REGDMA_WRITE(wrptr, ROTTOP_START_CTRL, 1); |
| 590 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 591 | |
| 592 | /* |
| 593 | * Start REGDMA with command offset and size |
| 594 | */ |
| 595 | regdmaSlot = sde_hw_rotator_get_regdma_ctxidx(ctx); |
| 596 | length = ((long)wrptr - (long)ctx->regdma_base) / 4; |
| 597 | offset = (u32)(ctx->regdma_base - (u32 *)(rot->mdss_base + |
| 598 | REGDMA_RAM_REGDMA_CMD_RAM)); |
| 599 | enableInt = ((ctx->timestamp & 1) + 1) << 30; |
| 600 | |
| 601 | SDEROT_DBG( |
| 602 | "regdma(%d)[%d] <== INT:0x%X|length:%ld|offset:0x%X, ts:%X\n", |
| 603 | queue_id, regdmaSlot, enableInt, length, offset, |
| 604 | ctx->timestamp); |
| 605 | |
| 606 | /* ensure the command packet is issued before the submit command */ |
| 607 | wmb(); |
| 608 | |
| 609 | /* REGDMA submission for current context */ |
| 610 | if (queue_id == ROT_QUEUE_HIGH_PRIORITY) { |
| 611 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 612 | REGDMA_CSR_REGDMA_QUEUE_0_SUBMIT, |
| 613 | (length << 14) | offset); |
| 614 | swts = ctx->timestamp; |
| 615 | mask = ~SDE_REGDMA_SWTS_MASK; |
| 616 | } else { |
| 617 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 618 | REGDMA_CSR_REGDMA_QUEUE_1_SUBMIT, |
| 619 | (length << 14) | offset); |
| 620 | swts = ctx->timestamp << SDE_REGDMA_SWTS_SHIFT; |
| 621 | mask = ~(SDE_REGDMA_SWTS_MASK << SDE_REGDMA_SWTS_SHIFT); |
| 622 | } |
| 623 | |
| 624 | /* Write timestamp after previous rotator job finished */ |
| 625 | sde_hw_rotator_setup_timestamp_packet(ctx, mask, swts); |
| 626 | offset += length; |
| 627 | ts_length = sde_hw_rotator_get_regdma_segment(ctx) - wrptr; |
| 628 | WARN_ON((length + ts_length) > SDE_HW_ROT_REGDMA_SEG_SIZE); |
| 629 | |
| 630 | /* ensure command packet is issue before the submit command */ |
| 631 | wmb(); |
| 632 | |
| 633 | if (queue_id == ROT_QUEUE_HIGH_PRIORITY) { |
| 634 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 635 | REGDMA_CSR_REGDMA_QUEUE_0_SUBMIT, |
| 636 | enableInt | (ts_length << 14) | offset); |
| 637 | } else { |
| 638 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 639 | REGDMA_CSR_REGDMA_QUEUE_1_SUBMIT, |
| 640 | enableInt | (ts_length << 14) | offset); |
| 641 | } |
| 642 | |
| 643 | /* Update REGDMA submit count */ |
| 644 | atomic_inc(&rot->regdma_submit_count); |
| 645 | |
| 646 | /* Update command queue write ptr */ |
| 647 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 648 | |
| 649 | return ctx->timestamp; |
| 650 | } |
| 651 | |
| 652 | /* |
| 653 | * sde_hw_rotator_wait_done_no_regdma - wait for non-regdma completion |
| 654 | * @ctx: Pointer to rotator context |
| 655 | * @queue_id: Priority queue identifier |
| 656 | * @flags: Option flag |
| 657 | */ |
| 658 | static u32 sde_hw_rotator_wait_done_no_regdma( |
| 659 | struct sde_hw_rotator_context *ctx, |
| 660 | enum sde_rot_queue_prio queue_id, u32 flag) |
| 661 | { |
| 662 | struct sde_hw_rotator *rot = ctx->rot; |
| 663 | int rc = 0; |
| 664 | u32 sts = 0; |
| 665 | u32 status; |
| 666 | unsigned long flags; |
| 667 | |
| 668 | if (rot->irq_num >= 0) { |
| 669 | SDEROT_DBG("Wait for Rotator completion\n"); |
| 670 | rc = wait_for_completion_timeout(&ctx->rot_comp, |
| 671 | KOFF_TIMEOUT); |
| 672 | |
| 673 | spin_lock_irqsave(&rot->rotisr_lock, flags); |
| 674 | status = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_STATUS); |
| 675 | if (rc == 0) { |
| 676 | /* |
| 677 | * Timeout, there might be error, |
| 678 | * or rotator still busy |
| 679 | */ |
| 680 | if (status & ROT_BUSY_BIT) |
| 681 | SDEROT_ERR( |
| 682 | "Timeout waiting for rotator done\n"); |
| 683 | else if (status & ROT_ERROR_BIT) |
| 684 | SDEROT_ERR( |
| 685 | "Rotator report error status\n"); |
| 686 | else |
| 687 | SDEROT_WARN( |
| 688 | "Timeout waiting, but rotator job is done!!\n"); |
| 689 | |
| 690 | disable_irq_nosync(rot->irq_num); |
| 691 | } |
| 692 | spin_unlock_irqrestore(&rot->rotisr_lock, flags); |
| 693 | } else { |
| 694 | int cnt = 200; |
| 695 | |
| 696 | do { |
| 697 | udelay(500); |
| 698 | status = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_STATUS); |
| 699 | cnt--; |
| 700 | } while ((cnt > 0) && (status & ROT_BUSY_BIT) |
| 701 | && ((status & ROT_ERROR_BIT) == 0)); |
| 702 | |
| 703 | if (status & ROT_ERROR_BIT) |
| 704 | SDEROT_ERR("Rotator error\n"); |
| 705 | else if (status & ROT_BUSY_BIT) |
| 706 | SDEROT_ERR("Rotator busy\n"); |
| 707 | |
| 708 | SDE_ROTREG_WRITE(rot->mdss_base, ROTTOP_INTR_CLEAR, |
| 709 | ROT_DONE_CLEAR); |
| 710 | } |
| 711 | |
| 712 | sts = (status & ROT_ERROR_BIT) ? -ENODEV : 0; |
| 713 | |
| 714 | return sts; |
| 715 | } |
| 716 | |
| 717 | /* |
| 718 | * sde_hw_rotator_wait_done_regdma - wait for regdma completion |
| 719 | * @ctx: Pointer to rotator context |
| 720 | * @queue_id: Priority queue identifier |
| 721 | * @flags: Option flag |
| 722 | */ |
| 723 | static u32 sde_hw_rotator_wait_done_regdma( |
| 724 | struct sde_hw_rotator_context *ctx, |
| 725 | enum sde_rot_queue_prio queue_id, u32 flag) |
| 726 | { |
| 727 | struct sde_hw_rotator *rot = ctx->rot; |
| 728 | int rc = 0; |
| 729 | u32 status; |
| 730 | u32 last_isr; |
| 731 | u32 last_ts; |
| 732 | u32 int_id; |
| 733 | u32 sts = 0; |
| 734 | u32 d_count; |
| 735 | unsigned long flags; |
| 736 | |
| 737 | if (rot->irq_num >= 0) { |
| 738 | SDEROT_DBG("Wait for REGDMA completion, ctx:%p, ts:%X\n", |
| 739 | ctx, ctx->timestamp); |
| 740 | rc = wait_for_completion_timeout(&ctx->regdma_comp, |
| 741 | KOFF_TIMEOUT); |
| 742 | |
| 743 | spin_lock_irqsave(&rot->rotisr_lock, flags); |
| 744 | |
| 745 | last_isr = ctx->last_regdma_isr_status; |
| 746 | last_ts = ctx->last_regdma_timestamp; |
| 747 | status = last_isr & REGDMA_INT_MASK; |
| 748 | int_id = last_ts & 1; |
| 749 | SDEROT_DBG("INT status:0x%X, INT id:%d, timestamp:0x%X\n", |
| 750 | status, int_id, last_ts); |
| 751 | |
| 752 | if (rc == 0 || (status & REGDMA_INT_ERR_MASK)) { |
| 753 | SDEROT_ERR( |
| 754 | "Timeout wait for regdma interrupt status, ts:%X\n", |
| 755 | ctx->timestamp); |
| 756 | |
| 757 | if (status & REGDMA_WATCHDOG_INT) |
| 758 | SDEROT_ERR("REGDMA watchdog interrupt\n"); |
| 759 | else if (status & REGDMA_INVALID_DESCRIPTOR) |
| 760 | SDEROT_ERR("REGDMA invalid descriptor\n"); |
| 761 | else if (status & REGDMA_INCOMPLETE_CMD) |
| 762 | SDEROT_ERR("REGDMA incomplete command\n"); |
| 763 | else if (status & REGDMA_INVALID_CMD) |
| 764 | SDEROT_ERR("REGDMA invalid command\n"); |
| 765 | |
| 766 | status = ROT_ERROR_BIT; |
| 767 | } else if (queue_id == ROT_QUEUE_HIGH_PRIORITY) { |
| 768 | /* Got to match exactly with interrupt ID */ |
| 769 | int_id = REGDMA_QUEUE0_INT0 << int_id; |
| 770 | |
| 771 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 772 | REGDMA_CSR_REGDMA_INT_CLEAR, |
| 773 | int_id); |
| 774 | |
| 775 | status = 0; |
| 776 | } else if (queue_id == ROT_QUEUE_LOW_PRIORITY) { |
| 777 | /* Matching interrupt ID */ |
| 778 | int_id = REGDMA_QUEUE1_INT0 << int_id; |
| 779 | |
| 780 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 781 | REGDMA_CSR_REGDMA_INT_CLEAR, |
| 782 | int_id); |
| 783 | |
| 784 | status = 0; |
| 785 | } |
| 786 | |
| 787 | /* regardless success or timeout, update done count */ |
| 788 | d_count = atomic_inc_return(&rot->regdma_done_count); |
| 789 | |
| 790 | /* disable IRQ if no more regdma submission in queue */ |
| 791 | if (d_count == atomic_read(&rot->regdma_submit_count)) { |
| 792 | SDEROT_DBG( |
| 793 | "Disable IRQ!! regdma donecnt==submitcnt -> %d\n", |
| 794 | d_count); |
| 795 | disable_irq_nosync(rot->irq_num); |
| 796 | } |
| 797 | |
| 798 | spin_unlock_irqrestore(&rot->rotisr_lock, flags); |
| 799 | } else { |
| 800 | int cnt = 200; |
| 801 | |
| 802 | do { |
| 803 | udelay(500); |
| 804 | status = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_STATUS); |
| 805 | cnt--; |
| 806 | } while ((cnt > 0) && (status & ROT_BUSY_BIT) |
| 807 | && ((status & ROT_ERROR_BIT) == 0)); |
| 808 | |
| 809 | if (status & ROT_ERROR_BIT) |
| 810 | SDEROT_ERR("Rotator error\n"); |
| 811 | else if (status & ROT_BUSY_BIT) |
| 812 | SDEROT_ERR("Rotator busy\n"); |
| 813 | |
| 814 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_INT_CLEAR, |
| 815 | 0xFFFF); |
| 816 | } |
| 817 | |
| 818 | sts = (status & ROT_ERROR_BIT) ? -ENODEV : 0; |
| 819 | |
| 820 | return sts; |
| 821 | } |
| 822 | |
| 823 | /* |
| 824 | * setup_rotator_ops - setup callback functions for the low-level HAL |
| 825 | * @ops: Pointer to low-level ops callback |
| 826 | * @mode: Operation mode (non-regdma or regdma) |
| 827 | */ |
| 828 | static void setup_rotator_ops(struct sde_hw_rotator_ops *ops, |
| 829 | enum sde_rotator_regdma_mode mode) |
| 830 | { |
| 831 | ops->setup_rotator_fetchengine = sde_hw_rotator_setup_fetchengine; |
| 832 | ops->setup_rotator_wbengine = sde_hw_rotator_setup_wbengine; |
| 833 | if (mode == ROT_REGDMA_ON) { |
| 834 | ops->start_rotator = sde_hw_rotator_start_regdma; |
| 835 | ops->wait_rotator_done = sde_hw_rotator_wait_done_regdma; |
| 836 | } else { |
| 837 | ops->start_rotator = sde_hw_rotator_start_no_regdma; |
| 838 | ops->wait_rotator_done = sde_hw_rotator_wait_done_no_regdma; |
| 839 | } |
| 840 | } |
| 841 | |
| 842 | /* |
| 843 | * sde_hw_rotator_swts_create - create software timestamp buffer |
| 844 | * @rot: Pointer to rotator hw |
| 845 | * |
| 846 | * This buffer is used by regdma to keep track of last completed command. |
| 847 | */ |
| 848 | static int sde_hw_rotator_swts_create(struct sde_hw_rotator *rot) |
| 849 | { |
| 850 | int rc = 0; |
| 851 | struct ion_handle *handle; |
| 852 | struct sde_mdp_img_data *data; |
| 853 | u32 bufsize = sizeof(int) * SDE_HW_ROT_REGDMA_TOTAL_CTX * 2; |
| 854 | |
| 855 | rot->iclient = msm_ion_client_create(rot->pdev->name); |
| 856 | if (IS_ERR_OR_NULL(rot->iclient)) { |
| 857 | SDEROT_ERR("msm_ion_client_create() return error (%p)\n", |
| 858 | rot->iclient); |
| 859 | return -EINVAL; |
| 860 | } |
| 861 | |
| 862 | handle = ion_alloc(rot->iclient, bufsize, SZ_4K, |
| 863 | ION_HEAP(ION_SYSTEM_HEAP_ID), 0); |
| 864 | if (IS_ERR_OR_NULL(handle)) { |
| 865 | SDEROT_ERR("ion memory allocation failed\n"); |
| 866 | return -ENOMEM; |
| 867 | } |
| 868 | |
| 869 | data = &rot->swts_buf; |
| 870 | data->len = bufsize; |
| 871 | data->srcp_dma_buf = ion_share_dma_buf(rot->iclient, handle); |
| 872 | if (IS_ERR(data->srcp_dma_buf)) { |
| 873 | SDEROT_ERR("ion_dma_buf setup failed\n"); |
| 874 | rc = -ENOMEM; |
| 875 | goto imap_err; |
| 876 | } |
| 877 | |
| 878 | sde_smmu_ctrl(1); |
| 879 | |
| 880 | data->srcp_attachment = sde_smmu_dma_buf_attach(data->srcp_dma_buf, |
| 881 | &rot->pdev->dev, SDE_IOMMU_DOMAIN_ROT_UNSECURE); |
| 882 | if (IS_ERR_OR_NULL(data->srcp_attachment)) { |
| 883 | SDEROT_ERR("sde_smmu_dma_buf_attach error\n"); |
| 884 | rc = -ENOMEM; |
| 885 | goto err_put; |
| 886 | } |
| 887 | |
| 888 | data->srcp_table = dma_buf_map_attachment(data->srcp_attachment, |
| 889 | DMA_BIDIRECTIONAL); |
| 890 | if (IS_ERR_OR_NULL(data->srcp_table)) { |
| 891 | SDEROT_ERR("dma_buf_map_attachment error\n"); |
| 892 | rc = -ENOMEM; |
| 893 | goto err_detach; |
| 894 | } |
| 895 | |
| 896 | rc = sde_smmu_map_dma_buf(data->srcp_dma_buf, data->srcp_table, |
| 897 | SDE_IOMMU_DOMAIN_ROT_UNSECURE, &data->addr, |
| 898 | &data->len, DMA_BIDIRECTIONAL); |
| 899 | if (IS_ERR_VALUE(rc)) { |
| 900 | SDEROT_ERR("smmu_map_dma_buf failed: (%d)\n", rc); |
| 901 | goto err_unmap; |
| 902 | } |
| 903 | |
| 904 | dma_buf_begin_cpu_access(data->srcp_dma_buf, 0, data->len, |
| 905 | DMA_FROM_DEVICE); |
| 906 | rot->swts_buffer = dma_buf_kmap(data->srcp_dma_buf, 0); |
| 907 | if (IS_ERR_OR_NULL(rot->swts_buffer)) { |
| 908 | SDEROT_ERR("ion kernel memory mapping failed\n"); |
| 909 | rc = IS_ERR(rot->swts_buffer); |
| 910 | goto kmap_err; |
| 911 | } |
| 912 | |
| 913 | data->mapped = true; |
| 914 | SDEROT_DBG("swts buffer mapped: %pad/%lx va:%p\n", &data->addr, |
| 915 | data->len, rot->swts_buffer); |
| 916 | |
| 917 | ion_free(rot->iclient, handle); |
| 918 | |
| 919 | sde_smmu_ctrl(0); |
| 920 | |
| 921 | return rc; |
| 922 | kmap_err: |
| 923 | sde_smmu_unmap_dma_buf(data->srcp_table, SDE_IOMMU_DOMAIN_ROT_UNSECURE, |
| 924 | DMA_FROM_DEVICE, data->srcp_dma_buf); |
| 925 | err_unmap: |
| 926 | dma_buf_unmap_attachment(data->srcp_attachment, data->srcp_table, |
| 927 | DMA_FROM_DEVICE); |
| 928 | err_detach: |
| 929 | dma_buf_detach(data->srcp_dma_buf, data->srcp_attachment); |
| 930 | err_put: |
| 931 | dma_buf_put(data->srcp_dma_buf); |
| 932 | data->srcp_dma_buf = NULL; |
| 933 | imap_err: |
| 934 | ion_free(rot->iclient, handle); |
| 935 | |
| 936 | return rc; |
| 937 | } |
| 938 | |
| 939 | /* |
| 940 | * sde_hw_rotator_swtc_destroy - destroy software timestamp buffer |
| 941 | * @rot: Pointer to rotator hw |
| 942 | */ |
| 943 | static void sde_hw_rotator_swtc_destroy(struct sde_hw_rotator *rot) |
| 944 | { |
| 945 | struct sde_mdp_img_data *data; |
| 946 | |
| 947 | data = &rot->swts_buf; |
| 948 | |
| 949 | dma_buf_end_cpu_access(data->srcp_dma_buf, 0, data->len, |
| 950 | DMA_FROM_DEVICE); |
| 951 | dma_buf_kunmap(data->srcp_dma_buf, 0, rot->swts_buffer); |
| 952 | |
| 953 | sde_smmu_unmap_dma_buf(data->srcp_table, SDE_IOMMU_DOMAIN_ROT_UNSECURE, |
| 954 | DMA_FROM_DEVICE, data->srcp_dma_buf); |
| 955 | dma_buf_unmap_attachment(data->srcp_attachment, data->srcp_table, |
| 956 | DMA_FROM_DEVICE); |
| 957 | dma_buf_detach(data->srcp_dma_buf, data->srcp_attachment); |
| 958 | dma_buf_put(data->srcp_dma_buf); |
| 959 | data->srcp_dma_buf = NULL; |
| 960 | } |
| 961 | |
| 962 | /* |
| 963 | * sde_hw_rotator_destroy - Destroy hw rotator and free allocated resources |
| 964 | * @mgr: Pointer to rotator manager |
| 965 | */ |
| 966 | static void sde_hw_rotator_destroy(struct sde_rot_mgr *mgr) |
| 967 | { |
| 968 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
| 969 | struct sde_hw_rotator *rot; |
| 970 | |
| 971 | if (!mgr || !mgr->pdev || !mgr->hw_data) { |
| 972 | SDEROT_ERR("null parameters\n"); |
| 973 | return; |
| 974 | } |
| 975 | |
| 976 | rot = mgr->hw_data; |
| 977 | if (rot->irq_num >= 0) |
| 978 | devm_free_irq(&mgr->pdev->dev, rot->irq_num, mdata); |
| 979 | |
| 980 | if (rot->mode == ROT_REGDMA_ON) |
| 981 | sde_hw_rotator_swtc_destroy(rot); |
| 982 | |
| 983 | devm_kfree(&mgr->pdev->dev, mgr->hw_data); |
| 984 | mgr->hw_data = NULL; |
| 985 | } |
| 986 | |
| 987 | /* |
| 988 | * sde_hw_rotator_alloc_ext - allocate rotator resource from rotator hw |
| 989 | * @mgr: Pointer to rotator manager |
| 990 | * @pipe_id: pipe identifier (not used) |
| 991 | * @wb_id: writeback identifier/priority queue identifier |
| 992 | * |
| 993 | * This function allocates a new hw rotator resource for the given priority. |
| 994 | */ |
| 995 | static struct sde_rot_hw_resource *sde_hw_rotator_alloc_ext( |
| 996 | struct sde_rot_mgr *mgr, u32 pipe_id, u32 wb_id) |
| 997 | { |
| 998 | struct sde_hw_rotator_resource_info *resinfo; |
| 999 | |
| 1000 | if (!mgr || !mgr->hw_data) { |
| 1001 | SDEROT_ERR("null parameters\n"); |
| 1002 | return NULL; |
| 1003 | } |
| 1004 | |
| 1005 | /* |
| 1006 | * Allocate rotator resource info. Each allocation is per |
| 1007 | * HW priority queue |
| 1008 | */ |
| 1009 | resinfo = devm_kzalloc(&mgr->pdev->dev, sizeof(*resinfo), GFP_KERNEL); |
| 1010 | if (!resinfo) { |
| 1011 | SDEROT_ERR("Failed allocation HW rotator resource info\n"); |
| 1012 | return NULL; |
| 1013 | } |
| 1014 | |
| 1015 | resinfo->rot = mgr->hw_data; |
| 1016 | resinfo->hw.wb_id = wb_id; |
| 1017 | atomic_set(&resinfo->hw.num_active, 0); |
| 1018 | init_waitqueue_head(&resinfo->hw.wait_queue); |
| 1019 | |
| 1020 | /* For non-regdma, only support one active session */ |
| 1021 | if (resinfo->rot->mode == ROT_REGDMA_OFF) |
| 1022 | resinfo->hw.max_active = 1; |
| 1023 | else { |
| 1024 | resinfo->hw.max_active = SDE_HW_ROT_REGDMA_TOTAL_CTX - 1; |
| 1025 | |
| 1026 | if (resinfo->rot->iclient == NULL) |
| 1027 | sde_hw_rotator_swts_create(resinfo->rot); |
| 1028 | } |
| 1029 | |
| 1030 | SDEROT_DBG("New rotator resource:%p, priority:%d\n", |
| 1031 | resinfo, wb_id); |
| 1032 | |
| 1033 | return &resinfo->hw; |
| 1034 | } |
| 1035 | |
| 1036 | /* |
| 1037 | * sde_hw_rotator_free_ext - free the given rotator resource |
| 1038 | * @mgr: Pointer to rotator manager |
| 1039 | * @hw: Pointer to rotator resource |
| 1040 | */ |
| 1041 | static void sde_hw_rotator_free_ext(struct sde_rot_mgr *mgr, |
| 1042 | struct sde_rot_hw_resource *hw) |
| 1043 | { |
| 1044 | struct sde_hw_rotator_resource_info *resinfo; |
| 1045 | |
| 1046 | if (!mgr || !mgr->hw_data) |
| 1047 | return; |
| 1048 | |
| 1049 | resinfo = container_of(hw, struct sde_hw_rotator_resource_info, hw); |
| 1050 | |
| 1051 | SDEROT_DBG( |
| 1052 | "Free rotator resource:%p, priority:%d, active:%d, pending:%d\n", |
| 1053 | resinfo, hw->wb_id, atomic_read(&hw->num_active), |
| 1054 | hw->pending_count); |
| 1055 | |
| 1056 | devm_kfree(&mgr->pdev->dev, resinfo); |
| 1057 | } |
| 1058 | |
| 1059 | /* |
| 1060 | * sde_hw_rotator_alloc_rotctx - allocate rotator context |
| 1061 | * @rot: Pointer to rotator hw |
| 1062 | * @hw: Pointer to rotator resource |
| 1063 | * @session_id: Session identifier of this context |
| 1064 | * |
| 1065 | * This function allocates a new rotator context for the given session id. |
| 1066 | */ |
| 1067 | static struct sde_hw_rotator_context *sde_hw_rotator_alloc_rotctx( |
| 1068 | struct sde_hw_rotator *rot, |
| 1069 | struct sde_rot_hw_resource *hw, |
| 1070 | u32 session_id) |
| 1071 | { |
| 1072 | struct sde_hw_rotator_context *ctx; |
| 1073 | |
| 1074 | /* Allocate rotator context */ |
| 1075 | ctx = devm_kzalloc(&rot->pdev->dev, sizeof(*ctx), GFP_KERNEL); |
| 1076 | if (!ctx) { |
| 1077 | SDEROT_ERR("Failed allocation HW rotator context\n"); |
| 1078 | return NULL; |
| 1079 | } |
| 1080 | |
| 1081 | ctx->rot = rot; |
| 1082 | ctx->q_id = hw->wb_id; |
| 1083 | ctx->session_id = session_id; |
| 1084 | ctx->hwres = hw; |
| 1085 | ctx->timestamp = atomic_add_return(1, &rot->timestamp[ctx->q_id]); |
| 1086 | ctx->timestamp &= SDE_REGDMA_SWTS_MASK; |
| 1087 | ctx->is_secure = false; |
| 1088 | |
| 1089 | ctx->regdma_base = rot->cmd_wr_ptr[ctx->q_id] |
| 1090 | [sde_hw_rotator_get_regdma_ctxidx(ctx)]; |
| 1091 | ctx->regdma_wrptr = ctx->regdma_base; |
| 1092 | ctx->ts_addr = (dma_addr_t)((u32 *)rot->swts_buf.addr + |
| 1093 | ctx->q_id * SDE_HW_ROT_REGDMA_TOTAL_CTX + |
| 1094 | sde_hw_rotator_get_regdma_ctxidx(ctx)); |
| 1095 | |
| 1096 | init_completion(&ctx->rot_comp); |
| 1097 | init_completion(&ctx->regdma_comp); |
| 1098 | |
| 1099 | /* Store rotator context for lookup purpose */ |
| 1100 | sde_hw_rotator_put_ctx(ctx); |
| 1101 | |
| 1102 | SDEROT_DBG( |
| 1103 | "New rot CTX:%p, ctxidx:%d, session-id:%d, prio:%d, timestamp:%X, active:%d\n", |
| 1104 | ctx, sde_hw_rotator_get_regdma_ctxidx(ctx), ctx->session_id, |
| 1105 | ctx->q_id, ctx->timestamp, |
| 1106 | atomic_read(&ctx->hwres->num_active)); |
| 1107 | |
| 1108 | return ctx; |
| 1109 | } |
| 1110 | |
| 1111 | /* |
| 1112 | * sde_hw_rotator_free_rotctx - free the given rotator context |
| 1113 | * @rot: Pointer to rotator hw |
| 1114 | * @ctx: Pointer to rotator context |
| 1115 | */ |
| 1116 | static void sde_hw_rotator_free_rotctx(struct sde_hw_rotator *rot, |
| 1117 | struct sde_hw_rotator_context *ctx) |
| 1118 | { |
| 1119 | if (!rot || !ctx) |
| 1120 | return; |
| 1121 | |
| 1122 | SDEROT_DBG( |
| 1123 | "Free rot CTX:%p, ctxidx:%d, session-id:%d, prio:%d, timestamp:%X, active:%d\n", |
| 1124 | ctx, sde_hw_rotator_get_regdma_ctxidx(ctx), ctx->session_id, |
| 1125 | ctx->q_id, ctx->timestamp, |
| 1126 | atomic_read(&ctx->hwres->num_active)); |
| 1127 | |
| 1128 | rot->rotCtx[ctx->q_id][sde_hw_rotator_get_regdma_ctxidx(ctx)] = NULL; |
| 1129 | |
| 1130 | devm_kfree(&rot->pdev->dev, ctx); |
| 1131 | } |
| 1132 | |
| 1133 | /* |
| 1134 | * sde_hw_rotator_config - configure hw for the given rotation entry |
| 1135 | * @hw: Pointer to rotator resource |
| 1136 | * @entry: Pointer to rotation entry |
| 1137 | * |
| 1138 | * This function setup the fetch/writeback/rotator blocks, as well as VBIF |
| 1139 | * based on the given rotation entry. |
| 1140 | */ |
| 1141 | static int sde_hw_rotator_config(struct sde_rot_hw_resource *hw, |
| 1142 | struct sde_rot_entry *entry) |
| 1143 | { |
| 1144 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
| 1145 | struct sde_hw_rotator *rot; |
| 1146 | struct sde_hw_rotator_resource_info *resinfo; |
| 1147 | struct sde_hw_rotator_context *ctx; |
| 1148 | struct sde_hw_rot_sspp_cfg sspp_cfg; |
| 1149 | struct sde_hw_rot_wb_cfg wb_cfg; |
| 1150 | u32 danger_lut = 0; /* applicable for realtime client only */ |
| 1151 | u32 safe_lut = 0; /* applicable for realtime client only */ |
| 1152 | u32 flags = 0; |
| 1153 | struct sde_rotation_item *item; |
| 1154 | |
| 1155 | if (!hw || !entry) { |
| 1156 | SDEROT_ERR("null hw resource/entry\n"); |
| 1157 | return -EINVAL; |
| 1158 | } |
| 1159 | |
| 1160 | resinfo = container_of(hw, struct sde_hw_rotator_resource_info, hw); |
| 1161 | rot = resinfo->rot; |
| 1162 | item = &entry->item; |
| 1163 | |
| 1164 | ctx = sde_hw_rotator_alloc_rotctx(rot, hw, item->session_id); |
| 1165 | if (!ctx) { |
| 1166 | SDEROT_ERR("Failed allocating rotator context!!\n"); |
| 1167 | return -EINVAL; |
| 1168 | } |
| 1169 | |
| 1170 | flags = (item->flags & SDE_ROTATION_FLIP_LR) ? |
| 1171 | SDE_ROT_FLAG_FLIP_LR : 0; |
| 1172 | flags |= (item->flags & SDE_ROTATION_FLIP_UD) ? |
| 1173 | SDE_ROT_FLAG_FLIP_UD : 0; |
| 1174 | flags |= (item->flags & SDE_ROTATION_90) ? |
| 1175 | SDE_ROT_FLAG_ROT_90 : 0; |
| 1176 | flags |= (item->flags & SDE_ROTATION_DEINTERLACE) ? |
| 1177 | SDE_ROT_FLAG_DEINTERLACE : 0; |
| 1178 | flags |= (item->flags & SDE_ROTATION_SECURE) ? |
| 1179 | SDE_ROT_FLAG_SECURE_OVERLAY_SESSION : 0; |
| 1180 | |
| 1181 | sspp_cfg.img_width = item->input.width; |
| 1182 | sspp_cfg.img_height = item->input.height; |
| 1183 | sspp_cfg.fmt = sde_get_format_params(item->input.format); |
| 1184 | if (!sspp_cfg.fmt) { |
| 1185 | SDEROT_ERR("null format\n"); |
| 1186 | return -EINVAL; |
| 1187 | } |
| 1188 | sspp_cfg.src_rect = &item->src_rect; |
| 1189 | sspp_cfg.data = &entry->src_buf; |
| 1190 | sde_mdp_get_plane_sizes(sspp_cfg.fmt, item->input.width, |
| 1191 | item->input.height, &sspp_cfg.src_plane, |
| 1192 | 0, /* No bwc_mode */ |
| 1193 | (flags & SDE_ROT_FLAG_SOURCE_ROTATED_90) ? |
| 1194 | true : false); |
| 1195 | |
| 1196 | rot->ops.setup_rotator_fetchengine(ctx, ctx->q_id, |
| 1197 | &sspp_cfg, danger_lut, safe_lut, flags); |
| 1198 | |
| 1199 | wb_cfg.img_width = item->output.width; |
| 1200 | wb_cfg.img_height = item->output.height; |
| 1201 | wb_cfg.fmt = sde_get_format_params(item->output.format); |
| 1202 | wb_cfg.dst_rect = &item->dst_rect; |
| 1203 | wb_cfg.data = &entry->dst_buf; |
| 1204 | sde_mdp_get_plane_sizes(wb_cfg.fmt, item->output.width, |
| 1205 | item->output.height, &wb_cfg.dst_plane, |
| 1206 | 0, /* No bwc_mode */ |
| 1207 | (flags & SDE_ROT_FLAG_ROT_90) ? true : false); |
| 1208 | |
| 1209 | wb_cfg.v_downscale_factor = entry->dnsc_factor_h; |
| 1210 | wb_cfg.h_downscale_factor = entry->dnsc_factor_w; |
| 1211 | |
| 1212 | rot->ops.setup_rotator_wbengine(ctx, ctx->q_id, &wb_cfg, flags); |
| 1213 | |
| 1214 | /* setup VA mapping for debugfs */ |
| 1215 | if (rot->dbgmem) { |
| 1216 | sde_hw_rotator_map_vaddr(&ctx->src_dbgbuf, |
| 1217 | &item->input, |
| 1218 | &entry->src_buf); |
| 1219 | |
| 1220 | sde_hw_rotator_map_vaddr(&ctx->dst_dbgbuf, |
| 1221 | &item->output, |
| 1222 | &entry->dst_buf); |
| 1223 | } |
| 1224 | |
| 1225 | if (mdata->default_ot_rd_limit) { |
| 1226 | struct sde_mdp_set_ot_params ot_params; |
| 1227 | |
| 1228 | memset(&ot_params, 0, sizeof(struct sde_mdp_set_ot_params)); |
| 1229 | ot_params.xin_id = XIN_SSPP; |
| 1230 | ot_params.num = 0; /* not used */ |
| 1231 | ot_params.width = sspp_cfg.img_width; |
| 1232 | ot_params.height = sspp_cfg.img_height; |
| 1233 | ot_params.reg_off_vbif_lim_conf = MMSS_VBIF_RD_LIM_CONF; |
| 1234 | ot_params.reg_off_mdp_clk_ctrl = |
| 1235 | MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0; |
| 1236 | ot_params.bit_off_mdp_clk_ctrl = |
| 1237 | MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0_XIN0; |
| 1238 | ot_params.is_rot = true; |
| 1239 | ot_params.is_wb = true; |
| 1240 | ot_params.is_yuv = sde_mdp_is_yuv_format(sspp_cfg.fmt); |
| 1241 | sde_mdp_set_ot_limit(&ot_params); |
| 1242 | } |
| 1243 | |
| 1244 | if (mdata->default_ot_wr_limit) { |
| 1245 | struct sde_mdp_set_ot_params ot_params; |
| 1246 | |
| 1247 | memset(&ot_params, 0, sizeof(struct sde_mdp_set_ot_params)); |
| 1248 | ot_params.xin_id = XIN_WRITEBACK; |
| 1249 | ot_params.num = 0; /* not used */ |
| 1250 | ot_params.width = wb_cfg.img_width; |
| 1251 | ot_params.height = wb_cfg.img_height; |
| 1252 | ot_params.reg_off_vbif_lim_conf = MMSS_VBIF_WR_LIM_CONF; |
| 1253 | ot_params.reg_off_mdp_clk_ctrl = |
| 1254 | MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0; |
| 1255 | ot_params.bit_off_mdp_clk_ctrl = |
| 1256 | MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0_XIN1; |
| 1257 | ot_params.is_rot = true; |
| 1258 | ot_params.is_wb = true; |
| 1259 | ot_params.is_yuv = sde_mdp_is_yuv_format(wb_cfg.fmt); |
| 1260 | sde_mdp_set_ot_limit(&ot_params); |
| 1261 | } |
| 1262 | |
| 1263 | if (test_bit(SDE_QOS_PER_PIPE_LUT, mdata->sde_qos_map)) { |
| 1264 | u32 qos_lut = 0; /* low priority for nrt read client */ |
| 1265 | |
| 1266 | trace_rot_perf_set_qos_luts(XIN_SSPP, sspp_cfg.fmt->format, |
| 1267 | qos_lut, sde_mdp_is_linear_format(sspp_cfg.fmt)); |
| 1268 | |
| 1269 | SDE_ROTREG_WRITE(rot->mdss_base, ROT_SSPP_CREQ_LUT, qos_lut); |
| 1270 | } |
| 1271 | |
| 1272 | if (mdata->npriority_lvl > 0) { |
| 1273 | u32 mask, reg_val, i, vbif_qos; |
| 1274 | |
| 1275 | for (i = 0; i < mdata->npriority_lvl; i++) { |
| 1276 | reg_val = SDE_VBIF_READ(mdata, |
| 1277 | MMSS_VBIF_NRT_VBIF_QOS_REMAP_00 + i*4); |
| 1278 | mask = 0x3 << (XIN_SSPP * 2); |
| 1279 | reg_val &= ~(mask); |
| 1280 | vbif_qos = mdata->vbif_nrt_qos[i]; |
| 1281 | reg_val |= vbif_qos << (XIN_SSPP * 2); |
| 1282 | /* ensure write is issued after the read operation */ |
| 1283 | mb(); |
| 1284 | SDE_VBIF_WRITE(mdata, |
| 1285 | MMSS_VBIF_NRT_VBIF_QOS_REMAP_00 + i*4, |
| 1286 | reg_val); |
| 1287 | } |
| 1288 | } |
| 1289 | |
| 1290 | /* Enable write gather for writeback to remove write gaps, which |
| 1291 | * may hang AXI/BIMC/SDE. |
| 1292 | */ |
| 1293 | SDE_VBIF_WRITE(mdata, MMSS_VBIF_NRT_VBIF_WRITE_GATHTER_EN, |
| 1294 | BIT(XIN_WRITEBACK)); |
| 1295 | |
| 1296 | return 0; |
| 1297 | } |
| 1298 | |
| 1299 | /* |
| 1300 | * sde_hw_rotator_kickoff - kickoff processing on the given entry |
| 1301 | * @hw: Pointer to rotator resource |
| 1302 | * @entry: Pointer to rotation entry |
| 1303 | */ |
| 1304 | static int sde_hw_rotator_kickoff(struct sde_rot_hw_resource *hw, |
| 1305 | struct sde_rot_entry *entry) |
| 1306 | { |
| 1307 | struct sde_hw_rotator *rot; |
| 1308 | struct sde_hw_rotator_resource_info *resinfo; |
| 1309 | struct sde_hw_rotator_context *ctx; |
| 1310 | int ret = 0; |
| 1311 | |
| 1312 | if (!hw || !entry) { |
| 1313 | SDEROT_ERR("null hw resource/entry\n"); |
| 1314 | return -EINVAL; |
| 1315 | } |
| 1316 | |
| 1317 | resinfo = container_of(hw, struct sde_hw_rotator_resource_info, hw); |
| 1318 | rot = resinfo->rot; |
| 1319 | |
| 1320 | /* Lookup rotator context from session-id */ |
| 1321 | ctx = sde_hw_rotator_get_ctx(rot, entry->item.session_id, hw->wb_id); |
| 1322 | if (!ctx) { |
| 1323 | SDEROT_ERR("Cannot locate rotator ctx from sesison id:%d\n", |
| 1324 | entry->item.session_id); |
| 1325 | } |
| 1326 | WARN_ON(ctx == NULL); |
| 1327 | |
| 1328 | ret = sde_smmu_ctrl(1); |
| 1329 | if (IS_ERR_VALUE(ret)) { |
| 1330 | SDEROT_ERR("IOMMU attach failed\n"); |
| 1331 | return ret; |
| 1332 | } |
| 1333 | |
| 1334 | rot->ops.start_rotator(ctx, ctx->q_id); |
| 1335 | |
| 1336 | return 0; |
| 1337 | } |
| 1338 | |
| 1339 | /* |
| 1340 | * sde_hw_rotator_wait4done - wait for completion notification |
| 1341 | * @hw: Pointer to rotator resource |
| 1342 | * @entry: Pointer to rotation entry |
| 1343 | * |
| 1344 | * This function blocks until the given entry is complete, error |
| 1345 | * is detected, or timeout. |
| 1346 | */ |
| 1347 | static int sde_hw_rotator_wait4done(struct sde_rot_hw_resource *hw, |
| 1348 | struct sde_rot_entry *entry) |
| 1349 | { |
| 1350 | struct sde_hw_rotator *rot; |
| 1351 | struct sde_hw_rotator_resource_info *resinfo; |
| 1352 | struct sde_hw_rotator_context *ctx; |
| 1353 | int ret; |
| 1354 | |
| 1355 | if (!hw || !entry) { |
| 1356 | SDEROT_ERR("null hw resource/entry\n"); |
| 1357 | return -EINVAL; |
| 1358 | } |
| 1359 | |
| 1360 | resinfo = container_of(hw, struct sde_hw_rotator_resource_info, hw); |
| 1361 | rot = resinfo->rot; |
| 1362 | |
| 1363 | /* Lookup rotator context from session-id */ |
| 1364 | ctx = sde_hw_rotator_get_ctx(rot, entry->item.session_id, hw->wb_id); |
| 1365 | if (!ctx) { |
| 1366 | SDEROT_ERR("Cannot locate rotator ctx from sesison id:%d\n", |
| 1367 | entry->item.session_id); |
| 1368 | } |
| 1369 | WARN_ON(ctx == NULL); |
| 1370 | |
| 1371 | ret = rot->ops.wait_rotator_done(ctx, ctx->q_id, 0); |
| 1372 | |
| 1373 | sde_smmu_ctrl(0); |
| 1374 | |
| 1375 | if (rot->dbgmem) { |
| 1376 | sde_hw_rotator_unmap_vaddr(&ctx->src_dbgbuf); |
| 1377 | sde_hw_rotator_unmap_vaddr(&ctx->dst_dbgbuf); |
| 1378 | } |
| 1379 | |
| 1380 | /* Current rotator context job is finished, time to free up*/ |
| 1381 | sde_hw_rotator_free_rotctx(rot, ctx); |
| 1382 | |
| 1383 | return ret; |
| 1384 | } |
| 1385 | |
| 1386 | /* |
| 1387 | * sde_rotator_hw_rev_init - setup feature and/or capability bitmask |
| 1388 | * @rot: Pointer to hw rotator |
| 1389 | * |
| 1390 | * This function initializes feature and/or capability bitmask based on |
| 1391 | * h/w version read from the device. |
| 1392 | */ |
| 1393 | static int sde_rotator_hw_rev_init(struct sde_hw_rotator *rot) |
| 1394 | { |
| 1395 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
| 1396 | u32 hw_version; |
| 1397 | |
| 1398 | if (!mdata) { |
| 1399 | SDEROT_ERR("null rotator data\n"); |
| 1400 | return -EINVAL; |
| 1401 | } |
| 1402 | |
| 1403 | hw_version = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_HW_VERSION); |
| 1404 | SDEROT_DBG("hw version %8.8x\n", hw_version); |
| 1405 | |
| 1406 | clear_bit(SDE_QOS_PER_PIPE_IB, mdata->sde_qos_map); |
| 1407 | set_bit(SDE_QOS_OVERHEAD_FACTOR, mdata->sde_qos_map); |
| 1408 | clear_bit(SDE_QOS_CDP, mdata->sde_qos_map); |
| 1409 | set_bit(SDE_QOS_OTLIM, mdata->sde_qos_map); |
| 1410 | set_bit(SDE_QOS_PER_PIPE_LUT, mdata->sde_qos_map); |
| 1411 | clear_bit(SDE_QOS_SIMPLIFIED_PREFILL, mdata->sde_qos_map); |
| 1412 | |
| 1413 | set_bit(SDE_CAPS_R3_WB, mdata->sde_caps_map); |
| 1414 | |
| 1415 | return 0; |
| 1416 | } |
| 1417 | |
| 1418 | /* |
| 1419 | * sde_hw_rotator_rotirq_handler - non-regdma interrupt handler |
| 1420 | * @irq: Interrupt number |
| 1421 | * @ptr: Pointer to private handle provided during registration |
| 1422 | * |
| 1423 | * This function services rotator interrupt and wakes up waiting client |
| 1424 | * with pending rotation requests already submitted to h/w. |
| 1425 | */ |
| 1426 | static irqreturn_t sde_hw_rotator_rotirq_handler(int irq, void *ptr) |
| 1427 | { |
| 1428 | struct sde_hw_rotator *rot = ptr; |
| 1429 | struct sde_hw_rotator_context *ctx; |
| 1430 | irqreturn_t ret = IRQ_NONE; |
| 1431 | u32 isr; |
| 1432 | |
| 1433 | isr = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_INTR_STATUS); |
| 1434 | |
| 1435 | SDEROT_DBG("intr_status = %8.8x\n", isr); |
| 1436 | |
| 1437 | if (isr & ROT_DONE_MASK) { |
| 1438 | if (rot->irq_num >= 0) |
| 1439 | disable_irq_nosync(rot->irq_num); |
| 1440 | SDEROT_DBG("Notify rotator complete\n"); |
| 1441 | |
| 1442 | /* Normal rotator only 1 session, no need to lookup */ |
| 1443 | ctx = rot->rotCtx[0][0]; |
| 1444 | WARN_ON(ctx == NULL); |
| 1445 | complete_all(&ctx->rot_comp); |
| 1446 | |
| 1447 | spin_lock(&rot->rotisr_lock); |
| 1448 | SDE_ROTREG_WRITE(rot->mdss_base, ROTTOP_INTR_CLEAR, |
| 1449 | ROT_DONE_CLEAR); |
| 1450 | spin_unlock(&rot->rotisr_lock); |
| 1451 | ret = IRQ_HANDLED; |
| 1452 | } |
| 1453 | |
| 1454 | return ret; |
| 1455 | } |
| 1456 | |
| 1457 | /* |
| 1458 | * sde_hw_rotator_regdmairq_handler - regdma interrupt handler |
| 1459 | * @irq: Interrupt number |
| 1460 | * @ptr: Pointer to private handle provided during registration |
| 1461 | * |
| 1462 | * This function services rotator interrupt, decoding the source of |
| 1463 | * events (high/low priority queue), and wakes up all waiting clients |
| 1464 | * with pending rotation requests already submitted to h/w. |
| 1465 | */ |
| 1466 | static irqreturn_t sde_hw_rotator_regdmairq_handler(int irq, void *ptr) |
| 1467 | { |
| 1468 | struct sde_hw_rotator *rot = ptr; |
| 1469 | struct sde_hw_rotator_context *ctx; |
| 1470 | irqreturn_t ret = IRQ_NONE; |
| 1471 | u32 isr; |
| 1472 | u32 ts; |
| 1473 | u32 q_id; |
| 1474 | |
| 1475 | isr = SDE_ROTREG_READ(rot->mdss_base, REGDMA_CSR_REGDMA_INT_STATUS); |
| 1476 | ts = SDE_ROTREG_READ(rot->mdss_base, REGDMA_TIMESTAMP_REG); |
| 1477 | |
| 1478 | SDEROT_DBG("intr_status = %8.8x, sw_TS:%X\n", isr, ts); |
| 1479 | |
| 1480 | /* Any REGDMA status, including error and watchdog timer, should |
| 1481 | * trigger and wake up waiting thread |
| 1482 | */ |
| 1483 | if (isr & (REGDMA_INT_HIGH_MASK | REGDMA_INT_LOW_MASK)) { |
| 1484 | spin_lock(&rot->rotisr_lock); |
| 1485 | |
| 1486 | /* |
| 1487 | * Obtain rotator context based on timestamp from regdma |
| 1488 | * and low/high interrupt status |
| 1489 | */ |
| 1490 | if (isr & REGDMA_INT_HIGH_MASK) { |
| 1491 | q_id = ROT_QUEUE_HIGH_PRIORITY; |
| 1492 | ts = ts & SDE_REGDMA_SWTS_MASK; |
| 1493 | } else if (isr & REGDMA_INT_LOW_MASK) { |
| 1494 | q_id = ROT_QUEUE_LOW_PRIORITY; |
| 1495 | ts = (ts >> SDE_REGDMA_SWTS_SHIFT) & |
| 1496 | SDE_REGDMA_SWTS_MASK; |
| 1497 | } |
| 1498 | |
| 1499 | ctx = rot->rotCtx[q_id][ts & SDE_HW_ROT_REGDMA_SEG_MASK]; |
| 1500 | WARN_ON(ctx == NULL); |
| 1501 | |
| 1502 | /* |
| 1503 | * Wake up all waiting context from the current and previous |
| 1504 | * SW Timestamp. |
| 1505 | */ |
| 1506 | do { |
| 1507 | ctx->last_regdma_isr_status = isr; |
| 1508 | ctx->last_regdma_timestamp = ts; |
| 1509 | SDEROT_DBG( |
| 1510 | "regdma complete: ctx:%p, ts:%X, dcount:%X\n", |
| 1511 | ctx, ts, atomic_read(&rot->regdma_done_count)); |
| 1512 | complete_all(&ctx->regdma_comp); |
| 1513 | |
| 1514 | ts = (ts - 1) & SDE_REGDMA_SWTS_MASK; |
| 1515 | ctx = rot->rotCtx[q_id] |
| 1516 | [ts & SDE_HW_ROT_REGDMA_SEG_MASK]; |
| 1517 | } while (ctx && (ctx->last_regdma_timestamp == 0)); |
| 1518 | |
| 1519 | /* |
| 1520 | * Clear corresponding regdma interrupt because it is a level |
| 1521 | * interrupt |
| 1522 | */ |
| 1523 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_INT_CLEAR, |
| 1524 | isr); |
| 1525 | |
| 1526 | spin_unlock(&rot->rotisr_lock); |
| 1527 | ret = IRQ_HANDLED; |
| 1528 | } else if (isr & REGDMA_INT_ERR_MASK) { |
| 1529 | /* |
| 1530 | * For REGDMA Err, we save the isr info and wake up |
| 1531 | * all waiting contexts |
| 1532 | */ |
| 1533 | int i, j; |
| 1534 | |
| 1535 | SDEROT_ERR( |
| 1536 | "regdma err isr:%X, wake up all waiting contexts\n", |
| 1537 | isr); |
| 1538 | |
| 1539 | spin_lock(&rot->rotisr_lock); |
| 1540 | |
| 1541 | for (i = 0; i < ROT_QUEUE_MAX; i++) { |
| 1542 | for (j = 0; j < SDE_HW_ROT_REGDMA_TOTAL_CTX; j++) { |
| 1543 | ctx = rot->rotCtx[i][j]; |
| 1544 | if (ctx && ctx->last_regdma_isr_status == 0) { |
| 1545 | ctx->last_regdma_isr_status = isr; |
| 1546 | ctx->last_regdma_timestamp = ts; |
| 1547 | complete_all(&ctx->regdma_comp); |
| 1548 | SDEROT_DBG("Wakeup rotctx[%d][%d]:%p\n", |
| 1549 | i, j, ctx); |
| 1550 | } |
| 1551 | } |
| 1552 | } |
| 1553 | |
| 1554 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_INT_CLEAR, |
| 1555 | isr); |
| 1556 | |
| 1557 | spin_unlock(&rot->rotisr_lock); |
| 1558 | ret = IRQ_HANDLED; |
| 1559 | } |
| 1560 | |
| 1561 | return ret; |
| 1562 | } |
| 1563 | |
| 1564 | /* |
| 1565 | * sde_hw_rotator_validate_entry - validate rotation entry |
| 1566 | * @mgr: Pointer to rotator manager |
| 1567 | * @entry: Pointer to rotation entry |
| 1568 | * |
| 1569 | * This function validates the given rotation entry and provides possible |
| 1570 | * fixup (future improvement) if available. This function returns 0 if |
| 1571 | * the entry is valid, and returns error code otherwise. |
| 1572 | */ |
| 1573 | static int sde_hw_rotator_validate_entry(struct sde_rot_mgr *mgr, |
| 1574 | struct sde_rot_entry *entry) |
| 1575 | { |
| 1576 | int ret = 0; |
| 1577 | u16 src_w, src_h, dst_w, dst_h; |
| 1578 | struct sde_rotation_item *item = &entry->item; |
| 1579 | struct sde_mdp_format_params *fmt; |
| 1580 | |
| 1581 | src_w = item->src_rect.w; |
| 1582 | src_h = item->src_rect.h; |
| 1583 | |
| 1584 | if (item->flags & SDE_ROTATION_90) { |
| 1585 | dst_w = item->dst_rect.h; |
| 1586 | dst_h = item->dst_rect.w; |
| 1587 | } else { |
| 1588 | dst_w = item->dst_rect.w; |
| 1589 | dst_h = item->dst_rect.h; |
| 1590 | } |
| 1591 | |
| 1592 | entry->dnsc_factor_w = 0; |
| 1593 | entry->dnsc_factor_h = 0; |
| 1594 | |
| 1595 | if ((src_w != dst_w) || (src_h != dst_h)) { |
| 1596 | if ((src_w % dst_w) || (src_h % dst_h)) { |
| 1597 | SDEROT_DBG("non integral scale not support\n"); |
| 1598 | ret = -EINVAL; |
| 1599 | goto dnsc_err; |
| 1600 | } |
| 1601 | entry->dnsc_factor_w = src_w / dst_w; |
| 1602 | if ((entry->dnsc_factor_w & (entry->dnsc_factor_w - 1)) || |
| 1603 | (entry->dnsc_factor_w > 64)) { |
| 1604 | SDEROT_DBG("non power-of-2 w_scale not support\n"); |
| 1605 | ret = -EINVAL; |
| 1606 | goto dnsc_err; |
| 1607 | } |
| 1608 | entry->dnsc_factor_h = src_h / dst_h; |
| 1609 | if ((entry->dnsc_factor_h & (entry->dnsc_factor_h - 1)) || |
| 1610 | (entry->dnsc_factor_h > 64)) { |
| 1611 | SDEROT_DBG("non power-of-2 h_scale not support\n"); |
| 1612 | ret = -EINVAL; |
| 1613 | goto dnsc_err; |
| 1614 | } |
| 1615 | } |
| 1616 | |
| 1617 | fmt = sde_get_format_params(item->output.format); |
| 1618 | /* Tiled format downscale support not applied to AYUV tiled */ |
| 1619 | if (sde_mdp_is_tilea5x_format(fmt) && (entry->dnsc_factor_h > 4)) { |
| 1620 | SDEROT_DBG("max downscale for tiled format is 4\n"); |
| 1621 | ret = -EINVAL; |
| 1622 | goto dnsc_err; |
| 1623 | } |
| 1624 | if (sde_mdp_is_ubwc_format(fmt) && (entry->dnsc_factor_h > 2)) { |
| 1625 | SDEROT_DBG("downscale with ubwc cannot be more than 2\n"); |
| 1626 | ret = -EINVAL; |
| 1627 | } |
| 1628 | |
| 1629 | dnsc_err: |
| 1630 | /* Downscaler does not support asymmetrical dnsc */ |
| 1631 | if (entry->dnsc_factor_w != entry->dnsc_factor_h) { |
| 1632 | SDEROT_DBG("asymmetric downscale not support\n"); |
| 1633 | ret = -EINVAL; |
| 1634 | } |
| 1635 | |
| 1636 | if (ret) { |
| 1637 | entry->dnsc_factor_w = 0; |
| 1638 | entry->dnsc_factor_h = 0; |
| 1639 | } |
| 1640 | return ret; |
| 1641 | } |
| 1642 | |
| 1643 | /* |
| 1644 | * sde_hw_rotator_show_caps - output capability info to sysfs 'caps' file |
| 1645 | * @mgr: Pointer to rotator manager |
| 1646 | * @attr: Pointer to device attribute interface |
| 1647 | * @buf: Pointer to output buffer |
| 1648 | * @len: Length of output buffer |
| 1649 | */ |
| 1650 | static ssize_t sde_hw_rotator_show_caps(struct sde_rot_mgr *mgr, |
| 1651 | struct device_attribute *attr, char *buf, ssize_t len) |
| 1652 | { |
| 1653 | struct sde_hw_rotator *hw_data; |
| 1654 | int cnt = 0; |
| 1655 | |
| 1656 | if (!mgr || !buf) |
| 1657 | return 0; |
| 1658 | |
| 1659 | hw_data = mgr->hw_data; |
| 1660 | |
| 1661 | #define SPRINT(fmt, ...) \ |
| 1662 | (cnt += scnprintf(buf + cnt, len - cnt, fmt, ##__VA_ARGS__)) |
| 1663 | |
| 1664 | /* insert capabilities here */ |
| 1665 | |
| 1666 | #undef SPRINT |
| 1667 | return cnt; |
| 1668 | } |
| 1669 | |
| 1670 | /* |
| 1671 | * sde_hw_rotator_show_state - output state info to sysfs 'state' file |
| 1672 | * @mgr: Pointer to rotator manager |
| 1673 | * @attr: Pointer to device attribute interface |
| 1674 | * @buf: Pointer to output buffer |
| 1675 | * @len: Length of output buffer |
| 1676 | */ |
| 1677 | static ssize_t sde_hw_rotator_show_state(struct sde_rot_mgr *mgr, |
| 1678 | struct device_attribute *attr, char *buf, ssize_t len) |
| 1679 | { |
| 1680 | struct sde_hw_rotator *rot; |
| 1681 | struct sde_hw_rotator_context *ctx; |
| 1682 | int cnt = 0; |
| 1683 | int num_active = 0; |
| 1684 | int i, j; |
| 1685 | |
| 1686 | if (!mgr || !buf) { |
| 1687 | SDEROT_ERR("null parameters\n"); |
| 1688 | return 0; |
| 1689 | } |
| 1690 | |
| 1691 | rot = mgr->hw_data; |
| 1692 | |
| 1693 | #define SPRINT(fmt, ...) \ |
| 1694 | (cnt += scnprintf(buf + cnt, len - cnt, fmt, ##__VA_ARGS__)) |
| 1695 | |
| 1696 | if (rot) { |
| 1697 | SPRINT("rot_mode=%d\n", rot->mode); |
| 1698 | SPRINT("irq_num=%d\n", rot->irq_num); |
| 1699 | |
| 1700 | if (rot->mode == ROT_REGDMA_OFF) { |
| 1701 | SPRINT("max_active=1\n"); |
| 1702 | SPRINT("num_active=%d\n", rot->rotCtx[0][0] ? 1 : 0); |
| 1703 | } else { |
| 1704 | for (i = 0; i < ROT_QUEUE_MAX; i++) { |
| 1705 | for (j = 0; j < SDE_HW_ROT_REGDMA_TOTAL_CTX; |
| 1706 | j++) { |
| 1707 | ctx = rot->rotCtx[i][j]; |
| 1708 | |
| 1709 | if (ctx) { |
| 1710 | SPRINT( |
| 1711 | "rotCtx[%d][%d]:%p\n", |
| 1712 | i, j, ctx); |
| 1713 | ++num_active; |
| 1714 | } |
| 1715 | } |
| 1716 | } |
| 1717 | |
| 1718 | SPRINT("max_active=%d\n", SDE_HW_ROT_REGDMA_TOTAL_CTX); |
| 1719 | SPRINT("num_active=%d\n", num_active); |
| 1720 | } |
| 1721 | } |
| 1722 | |
| 1723 | #undef SPRINT |
| 1724 | return cnt; |
| 1725 | } |
| 1726 | |
| 1727 | /* |
| 1728 | * sde_hw_rotator_parse_dt - parse r3 specific device tree settings |
| 1729 | * @hw_data: Pointer to rotator hw |
| 1730 | * @dev: Pointer to platform device |
| 1731 | */ |
| 1732 | static int sde_hw_rotator_parse_dt(struct sde_hw_rotator *hw_data, |
| 1733 | struct platform_device *dev) |
| 1734 | { |
| 1735 | int ret = 0; |
| 1736 | u32 data; |
| 1737 | |
| 1738 | if (!hw_data || !dev) |
| 1739 | return -EINVAL; |
| 1740 | |
| 1741 | ret = of_property_read_u32(dev->dev.of_node, "qcom,mdss-rot-mode", |
| 1742 | &data); |
| 1743 | if (ret) { |
| 1744 | SDEROT_DBG("default to regdma off\n"); |
| 1745 | ret = 0; |
| 1746 | hw_data->mode = ROT_REGDMA_OFF; |
| 1747 | } else if (data < ROT_REGDMA_MAX) { |
| 1748 | SDEROT_DBG("set to regdma mode %d\n", data); |
| 1749 | hw_data->mode = data; |
| 1750 | } else { |
| 1751 | SDEROT_ERR("regdma mode out of range. default to regdma off\n"); |
| 1752 | hw_data->mode = ROT_REGDMA_OFF; |
| 1753 | } |
| 1754 | |
| 1755 | ret = of_property_read_u32(dev->dev.of_node, |
| 1756 | "qcom,mdss-highest-bank-bit", &data); |
| 1757 | if (ret) { |
| 1758 | SDEROT_DBG("default to A5X bank\n"); |
| 1759 | ret = 0; |
| 1760 | hw_data->highest_bank = 2; |
| 1761 | } else { |
| 1762 | SDEROT_DBG("set highest bank bit to %d\n", data); |
| 1763 | hw_data->highest_bank = data; |
| 1764 | } |
| 1765 | |
| 1766 | return ret; |
| 1767 | } |
| 1768 | |
| 1769 | /* |
| 1770 | * sde_rotator_r3_init - initialize the r3 module |
| 1771 | * @mgr: Pointer to rotator manager |
| 1772 | * |
| 1773 | * This function setup r3 callback functions, parses r3 specific |
| 1774 | * device tree settings, installs r3 specific interrupt handler, |
| 1775 | * as well as initializes r3 internal data structure. |
| 1776 | */ |
| 1777 | int sde_rotator_r3_init(struct sde_rot_mgr *mgr) |
| 1778 | { |
| 1779 | struct sde_hw_rotator *rot; |
| 1780 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
| 1781 | int i; |
| 1782 | int ret; |
| 1783 | |
| 1784 | rot = devm_kzalloc(&mgr->pdev->dev, sizeof(*rot), GFP_KERNEL); |
| 1785 | if (!rot) |
| 1786 | return -ENOMEM; |
| 1787 | |
| 1788 | mgr->hw_data = rot; |
| 1789 | mgr->queue_count = ROT_QUEUE_MAX; |
| 1790 | |
| 1791 | rot->mdss_base = mdata->sde_io.base; |
| 1792 | rot->pdev = mgr->pdev; |
| 1793 | |
| 1794 | /* Assign ops */ |
| 1795 | mgr->ops_hw_destroy = sde_hw_rotator_destroy; |
| 1796 | mgr->ops_hw_alloc = sde_hw_rotator_alloc_ext; |
| 1797 | mgr->ops_hw_free = sde_hw_rotator_free_ext; |
| 1798 | mgr->ops_config_hw = sde_hw_rotator_config; |
| 1799 | mgr->ops_kickoff_entry = sde_hw_rotator_kickoff; |
| 1800 | mgr->ops_wait_for_entry = sde_hw_rotator_wait4done; |
| 1801 | mgr->ops_hw_validate_entry = sde_hw_rotator_validate_entry; |
| 1802 | mgr->ops_hw_show_caps = sde_hw_rotator_show_caps; |
| 1803 | mgr->ops_hw_show_state = sde_hw_rotator_show_state; |
| 1804 | mgr->ops_hw_create_debugfs = sde_rotator_r3_create_debugfs; |
| 1805 | |
| 1806 | ret = sde_hw_rotator_parse_dt(mgr->hw_data, mgr->pdev); |
| 1807 | if (ret) |
| 1808 | goto error_parse_dt; |
| 1809 | |
| 1810 | rot->irq_num = platform_get_irq(mgr->pdev, 0); |
| 1811 | if (rot->irq_num < 0) { |
| 1812 | SDEROT_ERR("fail to get rotator irq\n"); |
| 1813 | } else { |
| 1814 | if (rot->mode == ROT_REGDMA_OFF) |
| 1815 | ret = devm_request_threaded_irq(&mgr->pdev->dev, |
| 1816 | rot->irq_num, |
| 1817 | sde_hw_rotator_rotirq_handler, |
| 1818 | NULL, 0, "sde_rotator_r3", rot); |
| 1819 | else |
| 1820 | ret = devm_request_threaded_irq(&mgr->pdev->dev, |
| 1821 | rot->irq_num, |
| 1822 | sde_hw_rotator_regdmairq_handler, |
| 1823 | NULL, 0, "sde_rotator_r3", rot); |
| 1824 | if (ret) { |
| 1825 | SDEROT_ERR("fail to request irq r:%d\n", ret); |
| 1826 | rot->irq_num = -1; |
| 1827 | } else { |
| 1828 | disable_irq(rot->irq_num); |
| 1829 | } |
| 1830 | } |
| 1831 | |
| 1832 | setup_rotator_ops(&rot->ops, rot->mode); |
| 1833 | |
| 1834 | spin_lock_init(&rot->rotctx_lock); |
| 1835 | spin_lock_init(&rot->rotisr_lock); |
| 1836 | |
| 1837 | /* REGDMA initialization */ |
| 1838 | if (rot->mode == ROT_REGDMA_OFF) { |
| 1839 | for (i = 0; i < SDE_HW_ROT_REGDMA_TOTAL_CTX; i++) |
| 1840 | rot->cmd_wr_ptr[0][i] = &rot->cmd_queue[ |
| 1841 | SDE_HW_ROT_REGDMA_SEG_SIZE * i]; |
| 1842 | } else { |
| 1843 | for (i = 0; i < SDE_HW_ROT_REGDMA_TOTAL_CTX; i++) |
| 1844 | rot->cmd_wr_ptr[ROT_QUEUE_HIGH_PRIORITY][i] = |
| 1845 | (u32 *)(rot->mdss_base + |
| 1846 | REGDMA_RAM_REGDMA_CMD_RAM + |
| 1847 | SDE_HW_ROT_REGDMA_SEG_SIZE * 4 * i); |
| 1848 | |
| 1849 | for (i = 0; i < SDE_HW_ROT_REGDMA_TOTAL_CTX; i++) |
| 1850 | rot->cmd_wr_ptr[ROT_QUEUE_LOW_PRIORITY][i] = |
| 1851 | (u32 *)(rot->mdss_base + |
| 1852 | REGDMA_RAM_REGDMA_CMD_RAM + |
| 1853 | SDE_HW_ROT_REGDMA_SEG_SIZE * 4 * |
| 1854 | (i + SDE_HW_ROT_REGDMA_TOTAL_CTX)); |
| 1855 | } |
| 1856 | |
| 1857 | atomic_set(&rot->timestamp[0], 0); |
| 1858 | atomic_set(&rot->timestamp[1], 0); |
| 1859 | atomic_set(&rot->regdma_submit_count, 0); |
| 1860 | atomic_set(&rot->regdma_done_count, 0); |
| 1861 | |
| 1862 | ret = sde_rotator_hw_rev_init(rot); |
| 1863 | if (ret) |
| 1864 | goto error_hw_rev_init; |
| 1865 | |
| 1866 | return 0; |
| 1867 | error_hw_rev_init: |
| 1868 | if (rot->irq_num >= 0) |
| 1869 | devm_free_irq(&mgr->pdev->dev, rot->irq_num, mdata); |
| 1870 | devm_kfree(&mgr->pdev->dev, mgr->hw_data); |
| 1871 | error_parse_dt: |
| 1872 | return ret; |
| 1873 | } |