blob: d522b47e30b5a82322da83f6fed63d7d110dab5a [file] [log] [blame]
Andrew Victor62c16602006-11-30 12:27:38 +01001/*
Andrew Victor9d041262007-02-05 11:42:07 +01002 * arch/arm/mach-at91/at91sam9261.c
Andrew Victor62c16602006-11-30 12:27:38 +01003 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
Andrew Victor3ef2fb42008-04-02 21:36:06 +010014#include <linux/pm.h>
Andrew Victor62c16602006-11-30 12:27:38 +010015
Russell King80b02c12009-01-08 10:01:47 +000016#include <asm/irq.h>
Andrew Victor62c16602006-11-30 12:27:38 +010017#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
Nicolas Ferreb319ff82009-06-26 15:37:01 +010019#include <mach/cpu.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010020#include <mach/at91sam9261.h>
21#include <mach/at91_pmc.h>
22#include <mach/at91_rstc.h>
23#include <mach/at91_shdwc.h>
Andrew Victor62c16602006-11-30 12:27:38 +010024
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +080025#include "soc.h"
Andrew Victor62c16602006-11-30 12:27:38 +010026#include "generic.h"
27#include "clock.h"
28
Andrew Victor62c16602006-11-30 12:27:38 +010029/* --------------------------------------------------------------------
30 * Clocks
31 * -------------------------------------------------------------------- */
32
33/*
34 * The peripheral clocks.
35 */
36static struct clk pioA_clk = {
37 .name = "pioA_clk",
38 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
39 .type = CLK_TYPE_PERIPHERAL,
40};
41static struct clk pioB_clk = {
42 .name = "pioB_clk",
43 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioC_clk = {
47 .name = "pioC_clk",
48 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk usart0_clk = {
52 .name = "usart0_clk",
53 .pmc_mask = 1 << AT91SAM9261_ID_US0,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk usart1_clk = {
57 .name = "usart1_clk",
58 .pmc_mask = 1 << AT91SAM9261_ID_US1,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk usart2_clk = {
62 .name = "usart2_clk",
63 .pmc_mask = 1 << AT91SAM9261_ID_US2,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk mmc_clk = {
67 .name = "mci_clk",
68 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk udc_clk = {
72 .name = "udc_clk",
73 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk twi_clk = {
77 .name = "twi_clk",
78 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk spi0_clk = {
82 .name = "spi0_clk",
83 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk spi1_clk = {
87 .name = "spi1_clk",
88 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
89 .type = CLK_TYPE_PERIPHERAL,
90};
Andrew Victore8788ba2007-05-02 17:14:57 +010091static struct clk ssc0_clk = {
92 .name = "ssc0_clk",
93 .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk ssc1_clk = {
97 .name = "ssc1_clk",
98 .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk ssc2_clk = {
102 .name = "ssc2_clk",
103 .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
104 .type = CLK_TYPE_PERIPHERAL,
105};
Andrew Victorc177a1e2007-02-08 10:25:38 +0100106static struct clk tc0_clk = {
107 .name = "tc0_clk",
108 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk tc1_clk = {
112 .name = "tc1_clk",
113 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk tc2_clk = {
117 .name = "tc2_clk",
118 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
119 .type = CLK_TYPE_PERIPHERAL,
120};
Andrew Victor62c16602006-11-30 12:27:38 +0100121static struct clk ohci_clk = {
122 .name = "ohci_clk",
123 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk lcdc_clk = {
127 .name = "lcdc_clk",
128 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131
132static struct clk *periph_clocks[] __initdata = {
133 &pioA_clk,
134 &pioB_clk,
135 &pioC_clk,
136 &usart0_clk,
137 &usart1_clk,
138 &usart2_clk,
139 &mmc_clk,
140 &udc_clk,
141 &twi_clk,
142 &spi0_clk,
143 &spi1_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100144 &ssc0_clk,
145 &ssc1_clk,
146 &ssc2_clk,
Andrew Victorc177a1e2007-02-08 10:25:38 +0100147 &tc0_clk,
148 &tc1_clk,
149 &tc2_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100150 &ohci_clk,
151 &lcdc_clk,
152 // irq0 .. irq2
153};
154
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100155static struct clk_lookup periph_clocks_lookups[] = {
156 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
157 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
158 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
159 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
160 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
161 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
162 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
163 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
164};
165
166static struct clk_lookup usart_clocks_lookups[] = {
167 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
168 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
169 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
170 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
171};
172
Andrew Victor62c16602006-11-30 12:27:38 +0100173/*
174 * The four programmable clocks.
175 * You must configure pin multiplexing to bring these signals out.
176 */
177static struct clk pck0 = {
178 .name = "pck0",
179 .pmc_mask = AT91_PMC_PCK0,
180 .type = CLK_TYPE_PROGRAMMABLE,
181 .id = 0,
182};
183static struct clk pck1 = {
184 .name = "pck1",
185 .pmc_mask = AT91_PMC_PCK1,
186 .type = CLK_TYPE_PROGRAMMABLE,
187 .id = 1,
188};
189static struct clk pck2 = {
190 .name = "pck2",
191 .pmc_mask = AT91_PMC_PCK2,
192 .type = CLK_TYPE_PROGRAMMABLE,
193 .id = 2,
194};
195static struct clk pck3 = {
196 .name = "pck3",
197 .pmc_mask = AT91_PMC_PCK3,
198 .type = CLK_TYPE_PROGRAMMABLE,
199 .id = 3,
200};
201
202/* HClocks */
203static struct clk hck0 = {
204 .name = "hck0",
205 .pmc_mask = AT91_PMC_HCK0,
206 .type = CLK_TYPE_SYSTEM,
207 .id = 0,
208};
209static struct clk hck1 = {
210 .name = "hck1",
211 .pmc_mask = AT91_PMC_HCK1,
212 .type = CLK_TYPE_SYSTEM,
213 .id = 1,
214};
215
216static void __init at91sam9261_register_clocks(void)
217{
218 int i;
219
220 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
221 clk_register(periph_clocks[i]);
222
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100223 clkdev_add_table(periph_clocks_lookups,
224 ARRAY_SIZE(periph_clocks_lookups));
225 clkdev_add_table(usart_clocks_lookups,
226 ARRAY_SIZE(usart_clocks_lookups));
227
Andrew Victor62c16602006-11-30 12:27:38 +0100228 clk_register(&pck0);
229 clk_register(&pck1);
230 clk_register(&pck2);
231 clk_register(&pck3);
232
233 clk_register(&hck0);
234 clk_register(&hck1);
235}
236
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100237static struct clk_lookup console_clock_lookup;
238
239void __init at91sam9261_set_console_clock(int id)
240{
241 if (id >= ARRAY_SIZE(usart_clocks_lookups))
242 return;
243
244 console_clock_lookup.con_id = "usart";
245 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
246 clkdev_add(&console_clock_lookup);
247}
248
Andrew Victor62c16602006-11-30 12:27:38 +0100249/* --------------------------------------------------------------------
250 * GPIO
251 * -------------------------------------------------------------------- */
252
253static struct at91_gpio_bank at91sam9261_gpio[] = {
254 {
255 .id = AT91SAM9261_ID_PIOA,
256 .offset = AT91_PIOA,
257 .clock = &pioA_clk,
258 }, {
259 .id = AT91SAM9261_ID_PIOB,
260 .offset = AT91_PIOB,
261 .clock = &pioB_clk,
262 }, {
263 .id = AT91SAM9261_ID_PIOC,
264 .offset = AT91_PIOC,
265 .clock = &pioC_clk,
266 }
267};
268
Andrew Victor3ef2fb42008-04-02 21:36:06 +0100269static void at91sam9261_poweroff(void)
270{
271 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
272}
273
Andrew Victor62c16602006-11-30 12:27:38 +0100274
275/* --------------------------------------------------------------------
276 * AT91SAM9261 processor initialization
277 * -------------------------------------------------------------------- */
278
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800279static void __init at91sam9261_map_io(void)
Andrew Victor62c16602006-11-30 12:27:38 +0100280{
Nicolas Ferreb319ff82009-06-26 15:37:01 +0100281 if (cpu_is_at91sam9g10())
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800282 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
Nicolas Ferreb319ff82009-06-26 15:37:01 +0100283 else
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800284 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800285}
Nicolas Ferreb319ff82009-06-26 15:37:01 +0100286
Jean-Christophe PLAGNIOL-VILLARD46539372011-04-24 18:20:28 +0800287static void __init at91sam9261_initialize(void)
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800288{
Nicolas Ferrebb413db2010-10-14 19:14:00 +0200289 at91_arch_reset = at91sam9_alt_reset;
Andrew Victor3ef2fb42008-04-02 21:36:06 +0100290 pm_power_off = at91sam9261_poweroff;
Andrew Victor62c16602006-11-30 12:27:38 +0100291 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
292 | (1 << AT91SAM9261_ID_IRQ2);
293
Andrew Victor62c16602006-11-30 12:27:38 +0100294 /* Register GPIO subsystem */
295 at91_gpio_init(at91sam9261_gpio, 3);
296}
297
298/* --------------------------------------------------------------------
299 * Interrupt initialization
300 * -------------------------------------------------------------------- */
301
302/*
303 * The default interrupt priority levels (0 = lowest, 7 = highest).
304 */
305static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
306 7, /* Advanced Interrupt Controller */
307 7, /* System Peripherals */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100308 1, /* Parallel IO Controller A */
309 1, /* Parallel IO Controller B */
310 1, /* Parallel IO Controller C */
Andrew Victor62c16602006-11-30 12:27:38 +0100311 0,
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100312 5, /* USART 0 */
313 5, /* USART 1 */
314 5, /* USART 2 */
Andrew Victor62c16602006-11-30 12:27:38 +0100315 0, /* Multimedia Card Interface */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100316 2, /* USB Device Port */
317 6, /* Two-Wire Interface */
318 5, /* Serial Peripheral Interface 0 */
319 5, /* Serial Peripheral Interface 1 */
320 4, /* Serial Synchronous Controller 0 */
321 4, /* Serial Synchronous Controller 1 */
322 4, /* Serial Synchronous Controller 2 */
Andrew Victor62c16602006-11-30 12:27:38 +0100323 0, /* Timer Counter 0 */
324 0, /* Timer Counter 1 */
325 0, /* Timer Counter 2 */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100326 2, /* USB Host port */
Andrew Victor62c16602006-11-30 12:27:38 +0100327 3, /* LCD Controller */
328 0,
329 0,
330 0,
331 0,
332 0,
333 0,
334 0,
335 0, /* Advanced Interrupt Controller */
336 0, /* Advanced Interrupt Controller */
337 0, /* Advanced Interrupt Controller */
338};
339
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800340struct at91_init_soc __initdata at91sam9261_soc = {
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800341 .map_io = at91sam9261_map_io,
Jean-Christophe PLAGNIOL-VILLARD92100c12011-04-23 15:28:34 +0800342 .default_irq_priority = at91sam9261_default_irq_priority,
Jean-Christophe PLAGNIOL-VILLARD51ddec72011-04-24 18:15:34 +0800343 .register_clocks = at91sam9261_register_clocks,
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800344 .init = at91sam9261_initialize,
345};