blob: f1fd3f2b9813c322115b55a5368ee57155a1c5c1 [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001/*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm.h"
29#include "nouveau_drv.h"
30#include "nouveau_dma.h"
31
32int
33nouveau_dma_init(struct nouveau_channel *chan)
34{
35 struct drm_device *dev = chan->dev;
36 struct drm_nouveau_private *dev_priv = dev->dev_private;
37 struct nouveau_gpuobj *m2mf = NULL;
Francisco Jerezf03a3142009-12-26 02:42:45 +010038 struct nouveau_gpuobj *nvsw = NULL;
Ben Skeggs6ee73862009-12-11 19:24:15 +100039 int ret, i;
40
41 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
42 ret = nouveau_gpuobj_gr_new(chan, dev_priv->card_type < NV_50 ?
43 0x0039 : 0x5039, &m2mf);
44 if (ret)
45 return ret;
46
47 ret = nouveau_gpuobj_ref_add(dev, chan, NvM2MF, m2mf, NULL);
48 if (ret)
49 return ret;
50
Francisco Jerezf03a3142009-12-26 02:42:45 +010051 /* Create an NV_SW object for various sync purposes */
52 ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
53 if (ret)
54 return ret;
55
56 ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
57 if (ret)
58 return ret;
59
Ben Skeggs6ee73862009-12-11 19:24:15 +100060 /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
61 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
62 if (ret)
63 return ret;
64
65 /* Map push buffer */
66 ret = nouveau_bo_map(chan->pushbuf_bo);
67 if (ret)
68 return ret;
69
70 /* Map M2MF notifier object - fbcon. */
71 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
72 ret = nouveau_bo_map(chan->notifier_bo);
73 if (ret)
74 return ret;
75 }
76
77 /* Initialise DMA vars */
78 chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2;
79 chan->dma.put = 0;
80 chan->dma.cur = chan->dma.put;
81 chan->dma.free = chan->dma.max - chan->dma.cur;
82
83 /* Insert NOPS for NOUVEAU_DMA_SKIPS */
84 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
85 if (ret)
86 return ret;
87
88 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
89 OUT_RING(chan, 0);
90
91 /* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
92 ret = RING_SPACE(chan, 4);
93 if (ret)
94 return ret;
95 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
96 OUT_RING(chan, NvM2MF);
97 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
98 OUT_RING(chan, NvNotify0);
99
Francisco Jerezf03a3142009-12-26 02:42:45 +0100100 /* Initialise NV_SW */
101 ret = RING_SPACE(chan, 2);
102 if (ret)
103 return ret;
104 BEGIN_RING(chan, NvSubSw, 0, 1);
105 OUT_RING(chan, NvSw);
106
Ben Skeggs6ee73862009-12-11 19:24:15 +1000107 /* Sit back and pray the channel works.. */
108 FIRE_RING(chan);
109
110 return 0;
111}
112
113void
114OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
115{
116 bool is_iomem;
117 u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
118 mem = &mem[chan->dma.cur];
119 if (is_iomem)
120 memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
121 else
122 memcpy(mem, data, nr_dwords * 4);
123 chan->dma.cur += nr_dwords;
124}
125
126static inline bool
127READ_GET(struct nouveau_channel *chan, uint32_t *get)
128{
129 uint32_t val;
130
131 val = nvchan_rd32(chan, chan->user_get);
132 if (val < chan->pushbuf_base ||
133 val >= chan->pushbuf_base + chan->pushbuf_bo->bo.mem.size) {
134 /* meaningless to dma_wait() except to know whether the
135 * GPU has stalled or not
136 */
137 *get = val;
138 return false;
139 }
140
141 *get = (val - chan->pushbuf_base) >> 2;
142 return true;
143}
144
145int
146nouveau_dma_wait(struct nouveau_channel *chan, int size)
147{
148 uint32_t get, prev_get = 0, cnt = 0;
149 bool get_valid;
150
151 while (chan->dma.free < size) {
152 /* reset counter as long as GET is still advancing, this is
153 * to avoid misdetecting a GPU lockup if the GPU happens to
154 * just be processing an operation that takes a long time
155 */
156 get_valid = READ_GET(chan, &get);
157 if (get != prev_get) {
158 prev_get = get;
159 cnt = 0;
160 }
161
162 if ((++cnt & 0xff) == 0) {
163 DRM_UDELAY(1);
164 if (cnt > 100000)
165 return -EBUSY;
166 }
167
168 /* loop until we have a usable GET pointer. the value
169 * we read from the GPU may be outside the main ring if
170 * PFIFO is processing a buffer called from the main ring,
171 * discard these values until something sensible is seen.
172 *
173 * the other case we discard GET is while the GPU is fetching
174 * from the SKIPS area, so the code below doesn't have to deal
175 * with some fun corner cases.
176 */
177 if (!get_valid || get < NOUVEAU_DMA_SKIPS)
178 continue;
179
180 if (get <= chan->dma.cur) {
181 /* engine is fetching behind us, or is completely
182 * idle (GET == PUT) so we have free space up until
183 * the end of the push buffer
184 *
185 * we can only hit that path once per call due to
186 * looping back to the beginning of the push buffer,
187 * we'll hit the fetching-ahead-of-us path from that
188 * point on.
189 *
190 * the *one* exception to that rule is if we read
191 * GET==PUT, in which case the below conditional will
192 * always succeed and break us out of the wait loop.
193 */
194 chan->dma.free = chan->dma.max - chan->dma.cur;
195 if (chan->dma.free >= size)
196 break;
197
198 /* not enough space left at the end of the push buffer,
199 * instruct the GPU to jump back to the start right
200 * after processing the currently pending commands.
201 */
202 OUT_RING(chan, chan->pushbuf_base | 0x20000000);
203 WRITE_PUT(NOUVEAU_DMA_SKIPS);
204
205 /* we're now submitting commands at the start of
206 * the push buffer.
207 */
208 chan->dma.cur =
209 chan->dma.put = NOUVEAU_DMA_SKIPS;
210 }
211
212 /* engine fetching ahead of us, we have space up until the
213 * current GET pointer. the "- 1" is to ensure there's
214 * space left to emit a jump back to the beginning of the
215 * push buffer if we require it. we can never get GET == PUT
216 * here, so this is safe.
217 */
218 chan->dma.free = get - chan->dma.cur - 1;
219 }
220
221 return 0;
222}
223