blob: a79da8dd206455dc35b92e84e62893c262d18a5c [file] [log] [blame]
David Somayajuluafaf5a22006-09-19 10:28:00 -07001/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
27
28#include <net/tcp.h>
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
33#include <scsi/scsi_transport.h>
34#include <scsi/scsi_transport_iscsi.h>
35
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053036#include "ql4_dbg.h"
37#include "ql4_nx.h"
David Somayajuluafaf5a22006-09-19 10:28:00 -070038
39#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
40#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
41#endif
42
43#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
44#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
David C Somayajulud9150582006-11-15 17:38:40 -080045#endif
46
47#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
48#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
49#endif
David Somayajuluafaf5a22006-09-19 10:28:00 -070050
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053051#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
52#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
53#endif
54
David Somayajuluafaf5a22006-09-19 10:28:00 -070055#define QLA_SUCCESS 0
56#define QLA_ERROR 1
57
58/*
59 * Data bit definitions
60 */
61#define BIT_0 0x1
62#define BIT_1 0x2
63#define BIT_2 0x4
64#define BIT_3 0x8
65#define BIT_4 0x10
66#define BIT_5 0x20
67#define BIT_6 0x40
68#define BIT_7 0x80
69#define BIT_8 0x100
70#define BIT_9 0x200
71#define BIT_10 0x400
72#define BIT_11 0x800
73#define BIT_12 0x1000
74#define BIT_13 0x2000
75#define BIT_14 0x4000
76#define BIT_15 0x8000
77#define BIT_16 0x10000
78#define BIT_17 0x20000
79#define BIT_18 0x40000
80#define BIT_19 0x80000
81#define BIT_20 0x100000
82#define BIT_21 0x200000
83#define BIT_22 0x400000
84#define BIT_23 0x800000
85#define BIT_24 0x1000000
86#define BIT_25 0x2000000
87#define BIT_26 0x4000000
88#define BIT_27 0x8000000
89#define BIT_28 0x10000000
90#define BIT_29 0x20000000
91#define BIT_30 0x40000000
92#define BIT_31 0x80000000
93
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +053094/**
95 * Macros to help code, maintain, etc.
96 **/
97#define ql4_printk(level, ha, format, arg...) \
98 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
99
100
David Somayajuluafaf5a22006-09-19 10:28:00 -0700101/*
102 * Host adapter default definitions
103 ***********************************/
104#define MAX_HBAS 16
105#define MAX_BUSES 1
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530106#define MAX_TARGETS MAX_DEV_DB_ENTRIES
David Somayajuluafaf5a22006-09-19 10:28:00 -0700107#define MAX_LUNS 0xffff
108#define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530109#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
David Somayajuluafaf5a22006-09-19 10:28:00 -0700110#define MAX_PDU_ENTRIES 32
111#define INVALID_ENTRY 0xFFFF
112#define MAX_CMDS_TO_RISC 1024
113#define MAX_SRBS MAX_CMDS_TO_RISC
114#define MBOX_AEN_REG_COUNT 5
115#define MAX_INIT_RETRIES 5
David Somayajuluafaf5a22006-09-19 10:28:00 -0700116
117/*
118 * Buffer sizes
119 */
120#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
121#define RESPONSE_QUEUE_DEPTH 64
122#define QUEUE_SIZE 64
123#define DMA_BUFFER_SIZE 512
124
125/*
126 * Misc
127 */
128#define MAC_ADDR_LEN 6 /* in bytes */
129#define IP_ADDR_LEN 4 /* in bytes */
Vikas Chaudhary2a49a782010-04-28 11:37:07 +0530130#define IPv6_ADDR_LEN 16 /* IPv6 address size */
David Somayajuluafaf5a22006-09-19 10:28:00 -0700131#define DRIVER_NAME "qla4xxx"
132
133#define MAX_LINKED_CMDS_PER_LUN 3
Ravi Ananddbaf82e2010-07-10 14:50:32 +0530134#define MAX_REQS_SERVICED_PER_INTR 1
David Somayajuluafaf5a22006-09-19 10:28:00 -0700135
136#define ISCSI_IPADDR_SIZE 4 /* IP address size */
Joe Perchesb1c11812008-02-03 17:28:22 +0200137#define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700138#define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
David Somayajuluafaf5a22006-09-19 10:28:00 -0700139
140#define LSDW(x) ((u32)((u64)(x)))
141#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
142
143/*
144 * Retry & Timeout Values
145 */
146#define MBOX_TOV 60
147#define SOFT_RESET_TOV 30
148#define RESET_INTR_TOV 3
149#define SEMAPHORE_TOV 10
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530150#define ADAPTER_INIT_TOV 30
David Somayajuluafaf5a22006-09-19 10:28:00 -0700151#define ADAPTER_RESET_TOV 180
152#define EXTEND_CMD_TOV 60
153#define WAIT_CMD_TOV 30
154#define EH_WAIT_CMD_TOV 120
155#define FIRMWARE_UP_TOV 60
156#define RESET_FIRMWARE_TOV 30
157#define LOGOUT_TOV 10
158#define IOCB_TOV_MARGIN 10
159#define RELOGIN_TOV 18
160#define ISNS_DEREG_TOV 5
161
162#define MAX_RESET_HA_RETRIES 2
163
Vikas Chaudhary53698872010-04-28 11:41:59 +0530164#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
165
David Somayajuluafaf5a22006-09-19 10:28:00 -0700166/*
167 * SCSI Request Block structure (srb) that is placed
168 * on cmd->SCp location of every I/O [We have 22 bytes available]
169 */
170struct srb {
171 struct list_head list; /* (8) */
172 struct scsi_qla_host *ha; /* HA the SP is queued on */
173 struct ddb_entry *ddb;
174 uint16_t flags; /* (1) Status flags. */
175
176#define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
177#define SRB_GOT_SENSE BIT_4 /* sense data recieved. */
178 uint8_t state; /* (1) Status flags. */
179
180#define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
181#define SRB_FREE_STATE 1
182#define SRB_ACTIVE_STATE 3
183#define SRB_ACTIVE_TIMEOUT_STATE 4
184#define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
185
186 struct scsi_cmnd *cmd; /* (4) SCSI command block */
187 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
Vikas Chaudhary09a0f712010-04-28 11:42:24 +0530188 struct kref srb_ref; /* reference count for this srb */
David Somayajuluafaf5a22006-09-19 10:28:00 -0700189 uint32_t fw_ddb_index;
190 uint8_t err_id; /* error id */
191#define SRB_ERR_PORT 1 /* Request failed because "port down" */
192#define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
193#define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
194#define SRB_ERR_OTHER 4
195
196 uint16_t reserved;
197 uint16_t iocb_tov;
198 uint16_t iocb_cnt; /* Number of used iocbs */
199 uint16_t cc_stat;
Karen Higgins94bced32009-07-15 15:02:58 -0500200
201 /* Used for extended sense / status continuation */
202 uint8_t *req_sense_ptr;
203 uint16_t req_sense_len;
204 uint16_t reserved2;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700205};
206
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700207/*
208 * Asynchronous Event Queue structure
209 */
210struct aen {
211 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
212};
213
214struct ql4_aen_log {
215 int count;
216 struct aen entry[MAX_AEN_ENTRIES];
217};
218
219/*
220 * Device Database (DDB) structure
221 */
David Somayajuluafaf5a22006-09-19 10:28:00 -0700222struct ddb_entry {
223 struct list_head list; /* ddb list */
224 struct scsi_qla_host *ha;
225 struct iscsi_cls_session *sess;
226 struct iscsi_cls_conn *conn;
227
228 atomic_t state; /* DDB State */
229
230 unsigned long flags; /* DDB Flags */
231
232 unsigned long dev_scan_wait_to_start_relogin;
233 unsigned long dev_scan_wait_to_complete_relogin;
234
David Somayajuluafaf5a22006-09-19 10:28:00 -0700235 uint16_t fw_ddb_index; /* DDB firmware index */
Vikas Chaudhary2a49a782010-04-28 11:37:07 +0530236 uint16_t options;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700237 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
238
239 uint32_t CmdSn;
240 uint16_t target_session_id;
241 uint16_t connection_id;
242 uint16_t exe_throttle; /* Max mumber of cmds outstanding
243 * simultaneously */
244 uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to
245 * complete */
246 uint16_t default_relogin_timeout; /* Max time to wait for
247 * relogin to complete */
248 uint16_t tcp_source_port_num;
249 uint32_t default_time2wait; /* Default Min time between
250 * relogins (+aens) */
251
252 atomic_t port_down_timer; /* Device connection timer */
253 atomic_t retry_relogin_timer; /* Min Time between relogins
254 * (4000 only) */
255 atomic_t relogin_timer; /* Max Time to wait for relogin to complete */
256 atomic_t relogin_retry_count; /* Num of times relogin has been
257 * retried */
258
259 uint16_t port;
260 uint32_t tpgt;
Vikas Chaudhary2a49a782010-04-28 11:37:07 +0530261 uint8_t ip_addr[IP_ADDR_LEN];
David Somayajuluafaf5a22006-09-19 10:28:00 -0700262 uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */
263 uint8_t iscsi_alias[0x20];
Mike Christie41bbdbe2009-01-16 12:36:52 -0600264 uint8_t isid[6];
Vikas Chaudhary2a49a782010-04-28 11:37:07 +0530265 uint16_t iscsi_max_burst_len;
266 uint16_t iscsi_max_outsnd_r2t;
267 uint16_t iscsi_first_burst_len;
268 uint16_t iscsi_max_rcv_data_seg_len;
269 uint16_t iscsi_max_snd_data_seg_len;
270
271 struct in6_addr remote_ipv6_addr;
272 struct in6_addr link_local_ipv6_addr;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700273};
274
275/*
276 * DDB states.
277 */
278#define DDB_STATE_DEAD 0 /* We can no longer talk to
279 * this device */
280#define DDB_STATE_ONLINE 1 /* Device ready to accept
281 * commands */
282#define DDB_STATE_MISSING 2 /* Device logged off, trying
283 * to re-login */
284
285/*
286 * DDB flags.
287 */
288#define DF_RELOGIN 0 /* Relogin to device */
289#define DF_NO_RELOGIN 1 /* Do not relogin if IOCTL
290 * logged it out */
291#define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
292#define DF_FO_MASKED 3
293
David Somayajuluafaf5a22006-09-19 10:28:00 -0700294
295#include "ql4_fw.h"
296#include "ql4_nvram.h"
297
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530298struct ql82xx_hw_data {
299 /* Offsets for flash/nvram access (set to ~0 if not used). */
300 uint32_t flash_conf_off;
301 uint32_t flash_data_off;
302
303 uint32_t fdt_wrt_disable;
304 uint32_t fdt_erase_cmd;
305 uint32_t fdt_block_size;
306 uint32_t fdt_unprotect_sec_cmd;
307 uint32_t fdt_protect_sec_cmd;
308
309 uint32_t flt_region_flt;
310 uint32_t flt_region_fdt;
311 uint32_t flt_region_boot;
312 uint32_t flt_region_bootload;
313 uint32_t flt_region_fw;
314 uint32_t reserved;
315};
316
317struct qla4_8xxx_legacy_intr_set {
318 uint32_t int_vec_bit;
319 uint32_t tgt_status_reg;
320 uint32_t tgt_mask_reg;
321 uint32_t pci_int_reg;
322};
323
324/* MSI-X Support */
325
326#define QLA_MSIX_DEFAULT 0x00
327#define QLA_MSIX_RSP_Q 0x01
328
329#define QLA_MSIX_ENTRIES 2
330#define QLA_MIDX_DEFAULT 0
331#define QLA_MIDX_RSP_Q 1
332
333struct ql4_msix_entry {
334 int have_irq;
335 uint16_t msix_vector;
336 uint16_t msix_entry;
337};
338
339/*
340 * ISP Operations
341 */
342struct isp_operations {
343 int (*iospace_config) (struct scsi_qla_host *ha);
344 void (*pci_config) (struct scsi_qla_host *);
345 void (*disable_intrs) (struct scsi_qla_host *);
346 void (*enable_intrs) (struct scsi_qla_host *);
347 int (*start_firmware) (struct scsi_qla_host *);
348 irqreturn_t (*intr_handler) (int , void *);
349 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
350 int (*reset_chip) (struct scsi_qla_host *);
351 int (*reset_firmware) (struct scsi_qla_host *);
352 void (*queue_iocb) (struct scsi_qla_host *);
353 void (*complete_iocb) (struct scsi_qla_host *);
354 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
355 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
356 int (*get_sys_info) (struct scsi_qla_host *);
357};
358
David Somayajuluafaf5a22006-09-19 10:28:00 -0700359/*
360 * Linux Host Adapter structure
361 */
362struct scsi_qla_host {
363 /* Linux adapter configuration data */
David Somayajuluafaf5a22006-09-19 10:28:00 -0700364 unsigned long flags;
365
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700366#define AF_ONLINE 0 /* 0x00000001 */
367#define AF_INIT_DONE 1 /* 0x00000002 */
368#define AF_MBOX_COMMAND 2 /* 0x00000004 */
369#define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530370#define AF_DPC_SCHEDULED 5 /* 0x00000020 */
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700371#define AF_INTERRUPTS_ON 6 /* 0x00000040 */
372#define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
373#define AF_LINK_UP 8 /* 0x00000100 */
374#define AF_IRQ_ATTACHED 10 /* 0x00000400 */
375#define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530376#define AF_HBA_GOING_AWAY 12 /* 0x00001000 */
377#define AF_INTx_ENABLED 15 /* 0x00008000 */
378#define AF_MSI_ENABLED 16 /* 0x00010000 */
379#define AF_MSIX_ENABLED 17 /* 0x00020000 */
380#define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
381
David Somayajuluafaf5a22006-09-19 10:28:00 -0700382
383 unsigned long dpc_flags;
384
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700385#define DPC_RESET_HA 1 /* 0x00000002 */
386#define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
387#define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530388#define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700389#define DPC_RESET_HA_INTR 5 /* 0x00000020 */
390#define DPC_ISNS_RESTART 7 /* 0x00000080 */
391#define DPC_AEN 9 /* 0x00000200 */
392#define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
Vikas Chaudhary065aa1b2010-04-28 11:38:11 +0530393#define DPC_LINK_CHANGED 18 /* 0x00040000 */
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530394#define DPC_RESET_ACTIVE 20 /* 0x00040000 */
395#define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
396#define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
397
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700398
399 struct Scsi_Host *host; /* pointer to host data */
400 uint32_t tot_ddbs;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700401
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530402 uint16_t iocb_cnt;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700403
404 /* SRB cache. */
405#define SRB_MIN_REQ 128
406 mempool_t *srb_mempool;
407
408 /* pci information */
409 struct pci_dev *pdev;
410
411 struct isp_reg __iomem *reg; /* Base I/O address */
412 unsigned long pio_address;
413 unsigned long pio_length;
414#define MIN_IOBASE_LEN 0x100
415
416 uint16_t req_q_count;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700417
418 unsigned long host_no;
419
420 /* NVRAM registers */
421 struct eeprom_data *nvram;
422 spinlock_t hardware_lock ____cacheline_aligned;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530423 uint32_t eeprom_cmd_data;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700424
425 /* Counters for general statistics */
David C Somayajulud9150582006-11-15 17:38:40 -0800426 uint64_t isr_count;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700427 uint64_t adapter_error_count;
428 uint64_t device_error_count;
429 uint64_t total_io_count;
430 uint64_t total_mbytes_xferred;
431 uint64_t link_failure_count;
432 uint64_t invalid_crc_count;
David C Somayajulud9150582006-11-15 17:38:40 -0800433 uint32_t bytes_xfered;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700434 uint32_t spurious_int_count;
435 uint32_t aborted_io_count;
436 uint32_t io_timeout_count;
437 uint32_t mailbox_timeout_count;
438 uint32_t seconds_since_last_intr;
439 uint32_t seconds_since_last_heartbeat;
440 uint32_t mac_index;
441
442 /* Info Needed for Management App */
443 /* --- From GetFwVersion --- */
444 uint32_t firmware_version[2];
445 uint32_t patch_number;
446 uint32_t build_number;
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700447 uint32_t board_id;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700448
449 /* --- From Init_FW --- */
450 /* init_cb_t *init_cb; */
451 uint16_t firmware_options;
452 uint16_t tcp_options;
453 uint8_t ip_address[IP_ADDR_LEN];
454 uint8_t subnet_mask[IP_ADDR_LEN];
455 uint8_t gateway[IP_ADDR_LEN];
456 uint8_t alias[32];
457 uint8_t name_string[256];
458 uint8_t heartbeat_interval;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700459
460 /* --- From FlashSysInfo --- */
461 uint8_t my_mac[MAC_ADDR_LEN];
462 uint8_t serial_number[16];
463
464 /* --- From GetFwState --- */
465 uint32_t firmware_state;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700466 uint32_t addl_fw_state;
467
468 /* Linux kernel thread */
469 struct workqueue_struct *dpc_thread;
470 struct work_struct dpc_work;
471
472 /* Linux timer thread */
473 struct timer_list timer;
474 uint32_t timer_active;
475
476 /* Recovery Timers */
477 uint32_t port_down_retry_count;
478 uint32_t discovery_wait;
479 atomic_t check_relogin_timeouts;
480 uint32_t retry_reset_ha_cnt;
481 uint32_t isp_reset_timer; /* reset test timer */
482 uint32_t nic_reset_timer; /* simulated nic reset test timer */
483 int eh_start;
484 struct list_head free_srb_q;
485 uint16_t free_srb_q_count;
486 uint16_t num_srbs_allocated;
487
488 /* DMA Memory Block */
489 void *queues;
490 dma_addr_t queues_dma;
491 unsigned long queues_len;
492
493#define MEM_ALIGN_VALUE \
494 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
495 sizeof(struct queue_entry))
496 /* request and response queue variables */
497 dma_addr_t request_dma;
498 struct queue_entry *request_ring;
499 struct queue_entry *request_ptr;
500 dma_addr_t response_dma;
501 struct queue_entry *response_ring;
502 struct queue_entry *response_ptr;
503 dma_addr_t shadow_regs_dma;
504 struct shadow_regs *shadow_regs;
505 uint16_t request_in; /* Current indexes. */
506 uint16_t request_out;
507 uint16_t response_in;
508 uint16_t response_out;
509
510 /* aen queue variables */
511 uint16_t aen_q_count; /* Number of available aen_q entries */
512 uint16_t aen_in; /* Current indexes */
513 uint16_t aen_out;
514 struct aen aen_q[MAX_AEN_ENTRIES];
515
David C Somayajulu5c8bfc92007-05-23 17:50:55 -0700516 struct ql4_aen_log aen_log;/* tracks all aens */
517
David Somayajuluafaf5a22006-09-19 10:28:00 -0700518 /* This mutex protects several threads to do mailbox commands
519 * concurrently.
520 */
521 struct mutex mbox_sem;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700522
523 /* temporary mailbox status registers */
524 volatile uint8_t mbox_status_count;
525 volatile uint32_t mbox_status[MBOX_REG_COUNT];
526
527 /* local device database list (contains internal ddb entries) */
528 struct list_head ddb_list;
529
530 /* Map ddb_list entry by FW ddb index */
531 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
532
Karen Higgins94bced32009-07-15 15:02:58 -0500533 /* Saved srb for status continuation entry processing */
534 struct srb *status_srb;
Vikas Chaudhary2a49a782010-04-28 11:37:07 +0530535
536 /* IPv6 support info from InitFW */
537 uint8_t acb_version;
538 uint8_t ipv4_addr_state;
539 uint16_t ipv4_options;
540
541 uint32_t resvd2;
542 uint32_t ipv6_options;
543 uint32_t ipv6_addl_options;
544 uint8_t ipv6_link_local_state;
545 uint8_t ipv6_addr0_state;
546 uint8_t ipv6_addr1_state;
547 uint8_t ipv6_default_router_state;
548 struct in6_addr ipv6_link_local_addr;
549 struct in6_addr ipv6_addr0;
550 struct in6_addr ipv6_addr1;
551 struct in6_addr ipv6_default_router_addr;
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530552
553 /* qla82xx specific fields */
554 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */
555 unsigned long nx_pcibase; /* Base I/O address */
556 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
557 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
558 unsigned long first_page_group_start;
559 unsigned long first_page_group_end;
560
561 uint32_t crb_win;
562 uint32_t curr_window;
563 uint32_t ddr_mn_window;
564 unsigned long mn_win_crb;
565 unsigned long ms_win_crb;
566 int qdr_sn_window;
567 rwlock_t hw_lock;
568 uint16_t func_num;
569 int link_width;
570
571 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
572 u32 nx_crb_mask;
573
574 uint8_t revision_id;
575 uint32_t fw_heartbeat_counter;
576
577 struct isp_operations *isp_ops;
578 struct ql82xx_hw_data hw;
579
580 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
581
582 uint32_t nx_dev_init_timeout;
583 uint32_t nx_reset_timeout;
584
585 struct completion mbx_intr_comp;
David Somayajuluafaf5a22006-09-19 10:28:00 -0700586};
587
Vikas Chaudhary2a49a782010-04-28 11:37:07 +0530588static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
589{
590 return ((ha->ipv4_options & IPOPT_IPv4_PROTOCOL_ENABLE) != 0);
591}
592
593static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
594{
595 return ((ha->ipv6_options & IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
596}
597
David Somayajuluafaf5a22006-09-19 10:28:00 -0700598static inline int is_qla4010(struct scsi_qla_host *ha)
599{
600 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
601}
602
603static inline int is_qla4022(struct scsi_qla_host *ha)
604{
605 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
606}
607
David C Somayajulud9150582006-11-15 17:38:40 -0800608static inline int is_qla4032(struct scsi_qla_host *ha)
609{
610 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
611}
612
Vikas Chaudharyf4f5df232010-07-28 15:53:44 +0530613static inline int is_qla8022(struct scsi_qla_host *ha)
614{
615 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
616}
617
David Somayajuluafaf5a22006-09-19 10:28:00 -0700618static inline int adapter_up(struct scsi_qla_host *ha)
619{
620 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
621 (test_bit(AF_LINK_UP, &ha->flags) != 0);
622}
623
624static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
625{
626 return (struct scsi_qla_host *)shost->hostdata;
627}
628
629static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
630{
David C Somayajulud9150582006-11-15 17:38:40 -0800631 return (is_qla4010(ha) ?
632 &ha->reg->u1.isp4010.nvram :
633 &ha->reg->u1.isp4022.semaphore);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700634}
635
636static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
637{
David C Somayajulud9150582006-11-15 17:38:40 -0800638 return (is_qla4010(ha) ?
639 &ha->reg->u1.isp4010.nvram :
640 &ha->reg->u1.isp4022.nvram);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700641}
642
643static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
644{
David C Somayajulud9150582006-11-15 17:38:40 -0800645 return (is_qla4010(ha) ?
646 &ha->reg->u2.isp4010.ext_hw_conf :
647 &ha->reg->u2.isp4022.p0.ext_hw_conf);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700648}
649
650static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
651{
David C Somayajulud9150582006-11-15 17:38:40 -0800652 return (is_qla4010(ha) ?
653 &ha->reg->u2.isp4010.port_status :
654 &ha->reg->u2.isp4022.p0.port_status);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700655}
656
657static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
658{
David C Somayajulud9150582006-11-15 17:38:40 -0800659 return (is_qla4010(ha) ?
660 &ha->reg->u2.isp4010.port_ctrl :
661 &ha->reg->u2.isp4022.p0.port_ctrl);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700662}
663
664static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
665{
David C Somayajulud9150582006-11-15 17:38:40 -0800666 return (is_qla4010(ha) ?
667 &ha->reg->u2.isp4010.port_err_status :
668 &ha->reg->u2.isp4022.p0.port_err_status);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700669}
670
671static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
672{
David C Somayajulud9150582006-11-15 17:38:40 -0800673 return (is_qla4010(ha) ?
674 &ha->reg->u2.isp4010.gp_out :
675 &ha->reg->u2.isp4022.p0.gp_out);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700676}
677
678static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
679{
David C Somayajulud9150582006-11-15 17:38:40 -0800680 return (is_qla4010(ha) ?
681 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
682 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700683}
684
685int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
686void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
687int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
688
689static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
690{
David C Somayajulud9150582006-11-15 17:38:40 -0800691 if (is_qla4010(a))
692 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
693 QL4010_FLASH_SEM_BITS);
694 else
David Somayajuluafaf5a22006-09-19 10:28:00 -0700695 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
696 (QL4022_RESOURCE_BITS_BASE_CODE |
697 (a->mac_index)) << 13);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700698}
699
700static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
701{
David C Somayajulud9150582006-11-15 17:38:40 -0800702 if (is_qla4010(a))
David Somayajuluafaf5a22006-09-19 10:28:00 -0700703 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
David C Somayajulud9150582006-11-15 17:38:40 -0800704 else
705 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700706}
707
708static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
709{
David C Somayajulud9150582006-11-15 17:38:40 -0800710 if (is_qla4010(a))
711 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
712 QL4010_NVRAM_SEM_BITS);
713 else
David Somayajuluafaf5a22006-09-19 10:28:00 -0700714 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
715 (QL4022_RESOURCE_BITS_BASE_CODE |
716 (a->mac_index)) << 10);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700717}
718
719static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
720{
David C Somayajulud9150582006-11-15 17:38:40 -0800721 if (is_qla4010(a))
David Somayajuluafaf5a22006-09-19 10:28:00 -0700722 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
David C Somayajulud9150582006-11-15 17:38:40 -0800723 else
724 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700725}
726
727static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
728{
David C Somayajulud9150582006-11-15 17:38:40 -0800729 if (is_qla4010(a))
730 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
731 QL4010_DRVR_SEM_BITS);
732 else
David Somayajuluafaf5a22006-09-19 10:28:00 -0700733 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
734 (QL4022_RESOURCE_BITS_BASE_CODE |
735 (a->mac_index)) << 1);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700736}
737
738static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
739{
David C Somayajulud9150582006-11-15 17:38:40 -0800740 if (is_qla4010(a))
David Somayajuluafaf5a22006-09-19 10:28:00 -0700741 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
David C Somayajulud9150582006-11-15 17:38:40 -0800742 else
743 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
David Somayajuluafaf5a22006-09-19 10:28:00 -0700744}
745
746/*---------------------------------------------------------------------------*/
747
748/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
749#define PRESERVE_DDB_LIST 0
750#define REBUILD_DDB_LIST 1
751
752/* Defines for process_aen() */
753#define PROCESS_ALL_AENS 0
754#define FLUSH_DDB_CHANGED_AENS 1
755#define RELOGIN_DDB_CHANGED_AENS 2
756
David Somayajuluafaf5a22006-09-19 10:28:00 -0700757#endif /*_QLA4XXX_H */