| Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1 | # |
| 2 | # Memory devices |
| 3 | # |
| 4 | |
| 5 | menuconfig MEMORY |
| 6 | bool "Memory Controller drivers" |
| 7 | |
| 8 | if MEMORY |
| 9 | |
| 10 | config TI_EMIF |
| 11 | tristate "Texas Instruments EMIF driver" |
| Santosh Shilimkar | 18e9a97 | 2012-05-04 11:38:11 +0530 | [diff] [blame] | 12 | depends on ARCH_OMAP2PLUS |
| Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 13 | select DDR |
| 14 | help |
| 15 | This driver is for the EMIF module available in Texas Instruments |
| 16 | SoCs. EMIF is an SDRAM controller that, based on its revision, |
| 17 | supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. |
| 18 | This driver takes care of only LPDDR2 memories presently. The |
| 19 | functions of the driver includes re-configuring AC timing |
| 20 | parameters and other settings during frequency, voltage and |
| 21 | temperature changes |
| 22 | |
| Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 23 | config TEGRA20_MC |
| Hiroshi DOYU | f0e33f9 | 2012-05-11 09:56:24 +0300 | [diff] [blame^] | 24 | bool "Tegra20 Memory Controller(MC) driver" |
| 25 | default y |
| Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 26 | depends on ARCH_TEGRA_2x_SOC |
| Hiroshi DOYU | f0e33f9 | 2012-05-11 09:56:24 +0300 | [diff] [blame^] | 27 | help |
| 28 | This driver is for the Memory Controller(MC) module available |
| 29 | in Tegra20 SoCs, mainly for a address translation fault |
| 30 | analysis, especially for IOMMU/GART(Graphics Address |
| 31 | Relocation Table) module. |
| Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 32 | |
| Hiroshi DOYU | af46810 | 2012-05-10 10:42:32 +0300 | [diff] [blame] | 33 | config TEGRA30_MC |
| 34 | bool |
| 35 | depends on ARCH_TEGRA_3x_SOC |
| 36 | |
| Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 37 | endif |