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Jamie Iles06c3df42011-06-06 12:43:07 +01001/*
2 * (C) Copyright 2009 Intel Corporation
3 * Author: Jacob Pan (jacob.jun.pan@intel.com)
4 *
5 * Shared with ARM platforms, Jamie Iles, Picochip 2011
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Support for the Synopsys DesignWare APB Timers.
12 */
13#include <linux/dw_apb_timer.h>
14#include <linux/delay.h>
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19#include <linux/slab.h>
20
21#define APBT_MIN_PERIOD 4
22#define APBT_MIN_DELTA_USEC 200
23
John Stultzd3d8fee2013-06-17 19:34:57 -070024#define APBTMR_N_LOAD_COUNT 0x00
25#define APBTMR_N_CURRENT_VALUE 0x04
26#define APBTMR_N_CONTROL 0x08
27#define APBTMR_N_EOI 0x0c
28#define APBTMR_N_INT_STATUS 0x10
29
Jamie Iles06c3df42011-06-06 12:43:07 +010030#define APBTMRS_INT_STATUS 0xa0
31#define APBTMRS_EOI 0xa4
32#define APBTMRS_RAW_INT_STATUS 0xa8
33#define APBTMRS_COMP_VERSION 0xac
34
35#define APBTMR_CONTROL_ENABLE (1 << 0)
36/* 1: periodic, 0:free running. */
37#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1)
38#define APBTMR_CONTROL_INT (1 << 2)
39
40static inline struct dw_apb_clock_event_device *
41ced_to_dw_apb_ced(struct clock_event_device *evt)
42{
43 return container_of(evt, struct dw_apb_clock_event_device, ced);
44}
45
46static inline struct dw_apb_clocksource *
47clocksource_to_dw_apb_clocksource(struct clocksource *cs)
48{
49 return container_of(cs, struct dw_apb_clocksource, cs);
50}
51
52static unsigned long apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
53{
54 return readl(timer->base + offs);
55}
56
57static void apbt_writel(struct dw_apb_timer *timer, unsigned long val,
58 unsigned long offs)
59{
60 writel(val, timer->base + offs);
61}
62
63static void apbt_disable_int(struct dw_apb_timer *timer)
64{
65 unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
66
67 ctrl |= APBTMR_CONTROL_INT;
68 apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
69}
70
71/**
72 * dw_apb_clockevent_pause() - stop the clock_event_device from running
73 *
74 * @dw_ced: The APB clock to stop generating events.
75 */
76void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
77{
78 disable_irq(dw_ced->timer.irq);
79 apbt_disable_int(&dw_ced->timer);
80}
81
82static void apbt_eoi(struct dw_apb_timer *timer)
83{
84 apbt_readl(timer, APBTMR_N_EOI);
85}
86
87static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
88{
89 struct clock_event_device *evt = data;
90 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
91
92 if (!evt->event_handler) {
93 pr_info("Spurious APBT timer interrupt %d", irq);
94 return IRQ_NONE;
95 }
96
97 if (dw_ced->eoi)
98 dw_ced->eoi(&dw_ced->timer);
99
100 evt->event_handler(evt);
101 return IRQ_HANDLED;
102}
103
104static void apbt_enable_int(struct dw_apb_timer *timer)
105{
106 unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
107 /* clear pending intr */
108 apbt_readl(timer, APBTMR_N_EOI);
109 ctrl &= ~APBTMR_CONTROL_INT;
110 apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
111}
112
Viresh Kumar226be922015-06-18 16:24:19 +0530113static int apbt_shutdown(struct clock_event_device *evt)
Jamie Iles06c3df42011-06-06 12:43:07 +0100114{
Viresh Kumar226be922015-06-18 16:24:19 +0530115 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
Jamie Iles06c3df42011-06-06 12:43:07 +0100116 unsigned long ctrl;
Viresh Kumar226be922015-06-18 16:24:19 +0530117
118 pr_debug("%s CPU %d state=shutdown\n", __func__,
119 cpumask_first(evt->cpumask));
120
121 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
122 ctrl &= ~APBTMR_CONTROL_ENABLE;
123 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
124 return 0;
125}
126
127static int apbt_set_oneshot(struct clock_event_device *evt)
128{
129 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
130 unsigned long ctrl;
131
132 pr_debug("%s CPU %d state=oneshot\n", __func__,
133 cpumask_first(evt->cpumask));
134
135 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
136 /*
137 * set free running mode, this mode will let timer reload max
138 * timeout which will give time (3min on 25MHz clock) to rearm
139 * the next event, therefore emulate the one-shot mode.
140 */
141 ctrl &= ~APBTMR_CONTROL_ENABLE;
142 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
143
144 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
145 /* write again to set free running mode */
146 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
147
148 /*
149 * DW APB p. 46, load counter with all 1s before starting free
150 * running mode.
151 */
152 apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
153 ctrl &= ~APBTMR_CONTROL_INT;
154 ctrl |= APBTMR_CONTROL_ENABLE;
155 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
156 return 0;
157}
158
159static int apbt_set_periodic(struct clock_event_device *evt)
160{
161 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
162 unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
163 unsigned long ctrl;
164
165 pr_debug("%s CPU %d state=periodic\n", __func__,
166 cpumask_first(evt->cpumask));
167
168 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
169 ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
170 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
171 /*
172 * DW APB p. 46, have to disable timer before load counter,
173 * may cause sync problem.
174 */
175 ctrl &= ~APBTMR_CONTROL_ENABLE;
176 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
177 udelay(1);
178 pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
179 apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
180 ctrl |= APBTMR_CONTROL_ENABLE;
181 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
182 return 0;
183}
184
185static int apbt_resume(struct clock_event_device *evt)
186{
Jamie Iles06c3df42011-06-06 12:43:07 +0100187 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
188
Viresh Kumar226be922015-06-18 16:24:19 +0530189 pr_debug("%s CPU %d state=resume\n", __func__,
190 cpumask_first(evt->cpumask));
Jamie Iles06c3df42011-06-06 12:43:07 +0100191
Viresh Kumar226be922015-06-18 16:24:19 +0530192 apbt_enable_int(&dw_ced->timer);
193 return 0;
Jamie Iles06c3df42011-06-06 12:43:07 +0100194}
195
196static int apbt_next_event(unsigned long delta,
197 struct clock_event_device *evt)
198{
199 unsigned long ctrl;
200 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
201
202 /* Disable timer */
203 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
204 ctrl &= ~APBTMR_CONTROL_ENABLE;
205 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
206 /* write new count */
207 apbt_writel(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
208 ctrl |= APBTMR_CONTROL_ENABLE;
209 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
210
211 return 0;
212}
213
214/**
215 * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
216 *
217 * @cpu: The CPU the events will be targeted at.
218 * @name: The name used for the timer and the IRQ for it.
219 * @rating: The rating to give the timer.
220 * @base: I/O base for the timer registers.
221 * @irq: The interrupt number to use for the timer.
222 * @freq: The frequency that the timer counts at.
223 *
224 * This creates a clock_event_device for using with the generic clock layer
225 * but does not start and register it. This should be done with
226 * dw_apb_clockevent_register() as the next step. If this is the first time
227 * it has been called for a timer then the IRQ will be requested, if not it
228 * just be enabled to allow CPU hotplug to avoid repeatedly requesting and
229 * releasing the IRQ.
230 */
231struct dw_apb_clock_event_device *
232dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
233 void __iomem *base, int irq, unsigned long freq)
234{
235 struct dw_apb_clock_event_device *dw_ced =
236 kzalloc(sizeof(*dw_ced), GFP_KERNEL);
237 int err;
238
239 if (!dw_ced)
240 return NULL;
241
242 dw_ced->timer.base = base;
243 dw_ced->timer.irq = irq;
244 dw_ced->timer.freq = freq;
245
246 clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
247 dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
248 &dw_ced->ced);
249 dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
250 dw_ced->ced.cpumask = cpumask_of(cpu);
Jisheng Zhang8b5f0012015-07-04 13:06:43 +0800251 dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
252 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
Viresh Kumar226be922015-06-18 16:24:19 +0530253 dw_ced->ced.set_state_shutdown = apbt_shutdown;
254 dw_ced->ced.set_state_periodic = apbt_set_periodic;
255 dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
256 dw_ced->ced.tick_resume = apbt_resume;
Jamie Iles06c3df42011-06-06 12:43:07 +0100257 dw_ced->ced.set_next_event = apbt_next_event;
258 dw_ced->ced.irq = dw_ced->timer.irq;
259 dw_ced->ced.rating = rating;
260 dw_ced->ced.name = name;
261
262 dw_ced->irqaction.name = dw_ced->ced.name;
263 dw_ced->irqaction.handler = dw_apb_clockevent_irq;
264 dw_ced->irqaction.dev_id = &dw_ced->ced;
265 dw_ced->irqaction.irq = irq;
266 dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL |
Michael Opdenacker38c30a82013-12-09 10:12:10 +0100267 IRQF_NOBALANCING;
Jamie Iles06c3df42011-06-06 12:43:07 +0100268
269 dw_ced->eoi = apbt_eoi;
270 err = setup_irq(irq, &dw_ced->irqaction);
271 if (err) {
272 pr_err("failed to request timer irq\n");
273 kfree(dw_ced);
274 dw_ced = NULL;
275 }
276
277 return dw_ced;
278}
279
280/**
281 * dw_apb_clockevent_resume() - resume a clock that has been paused.
282 *
283 * @dw_ced: The APB clock to resume.
284 */
285void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
286{
287 enable_irq(dw_ced->timer.irq);
288}
289
290/**
291 * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
292 *
293 * @dw_ced: The APB clock to stop generating the events.
294 */
295void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
296{
297 free_irq(dw_ced->timer.irq, &dw_ced->ced);
298}
299
300/**
301 * dw_apb_clockevent_register() - register the clock with the generic layer
302 *
303 * @dw_ced: The APB clock to register as a clock_event_device.
304 */
305void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
306{
307 apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
308 clockevents_register_device(&dw_ced->ced);
309 apbt_enable_int(&dw_ced->timer);
310}
311
312/**
313 * dw_apb_clocksource_start() - start the clocksource counting.
314 *
315 * @dw_cs: The clocksource to start.
316 *
317 * This is used to start the clocksource before registration and can be used
318 * to enable calibration of timers.
319 */
320void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
321{
322 /*
323 * start count down from 0xffff_ffff. this is done by toggling the
324 * enable bit then load initial load count to ~0.
325 */
326 unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
327
328 ctrl &= ~APBTMR_CONTROL_ENABLE;
329 apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
330 apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
331 /* enable, mask interrupt */
332 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
333 ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
334 apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
335 /* read it once to get cached counter value initialized */
336 dw_apb_clocksource_read(dw_cs);
337}
338
339static cycle_t __apbt_read_clocksource(struct clocksource *cs)
340{
341 unsigned long current_count;
342 struct dw_apb_clocksource *dw_cs =
343 clocksource_to_dw_apb_clocksource(cs);
344
345 current_count = apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
346
347 return (cycle_t)~current_count;
348}
349
350static void apbt_restart_clocksource(struct clocksource *cs)
351{
352 struct dw_apb_clocksource *dw_cs =
353 clocksource_to_dw_apb_clocksource(cs);
354
355 dw_apb_clocksource_start(dw_cs);
356}
357
358/**
359 * dw_apb_clocksource_init() - use an APB timer as a clocksource.
360 *
361 * @rating: The rating to give the clocksource.
362 * @name: The name for the clocksource.
363 * @base: The I/O base for the timer registers.
364 * @freq: The frequency that the timer counts at.
365 *
366 * This creates a clocksource using an APB timer but does not yet register it
367 * with the clocksource system. This should be done with
368 * dw_apb_clocksource_register() as the next step.
369 */
370struct dw_apb_clocksource *
Jamie Ilesa1330222011-07-25 16:34:37 +0100371dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
Jamie Iles06c3df42011-06-06 12:43:07 +0100372 unsigned long freq)
373{
374 struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);
375
376 if (!dw_cs)
377 return NULL;
378
379 dw_cs->timer.base = base;
380 dw_cs->timer.freq = freq;
381 dw_cs->cs.name = name;
382 dw_cs->cs.rating = rating;
383 dw_cs->cs.read = __apbt_read_clocksource;
384 dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
385 dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
386 dw_cs->cs.resume = apbt_restart_clocksource;
387
388 return dw_cs;
389}
390
391/**
392 * dw_apb_clocksource_register() - register the APB clocksource.
393 *
394 * @dw_cs: The clocksource to register.
395 */
396void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
397{
398 clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
399}
400
401/**
402 * dw_apb_clocksource_read() - read the current value of a clocksource.
403 *
404 * @dw_cs: The clocksource to read.
405 */
406cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
407{
408 return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
409}