blob: 3abebb75fc57c729ee7f615276862e60a6d51171 [file] [log] [blame]
Roland Stiggee04920d2012-04-22 12:01:19 +02001/*
2 * NXP LPC32xx SoC
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 compatible = "nxp,lpc3220";
18 interrupt-parent = <&mic>;
19
20 cpus {
Lorenzo Pieralisi73158b72013-04-18 18:34:51 +010021 #address-cells = <0>;
22 #size-cells = <0>;
23
24 cpu {
25 compatible = "arm,arm926ej-s";
26 device_type = "cpu";
Roland Stiggee04920d2012-04-22 12:01:19 +020027 };
28 };
29
30 ahb {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 ranges = <0x20000000 0x20000000 0x30000000>;
35
36 /*
37 * Enable either SLC or MLC
38 */
39 slc: flash@20020000 {
40 compatible = "nxp,lpc3220-slc";
41 reg = <0x20020000 0x1000>;
Roland Stiggecb85a9e2012-06-14 16:16:18 +020042 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +020043 };
44
Roland Stigge6d1c3e92012-06-14 16:16:17 +020045 mlc: flash@200a8000 {
Roland Stiggee04920d2012-04-22 12:01:19 +020046 compatible = "nxp,lpc3220-mlc";
Roland Stigge6d1c3e92012-06-14 16:16:17 +020047 reg = <0x200a8000 0x11000>;
48 interrupts = <11 0>;
Roland Stiggecb85a9e2012-06-14 16:16:18 +020049 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +020050 };
51
52 dma@31000000 {
53 compatible = "arm,pl080", "arm,primecell";
54 reg = <0x31000000 0x1000>;
55 interrupts = <0x1c 0>;
56 };
57
58 /*
59 * Enable either ohci or usbd (gadget)!
60 */
61 ohci@31020000 {
62 compatible = "nxp,ohci-nxp", "usb-ohci";
63 reg = <0x31020000 0x300>;
64 interrupts = <0x3b 0>;
Roland Stiggecb85a9e2012-06-14 16:16:18 +020065 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +020066 };
67
68 usbd@31020000 {
69 compatible = "nxp,lpc3220-udc";
70 reg = <0x31020000 0x300>;
71 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
Roland Stiggecb85a9e2012-06-14 16:16:18 +020072 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +020073 };
74
75 clcd@31040000 {
76 compatible = "arm,pl110", "arm,primecell";
77 reg = <0x31040000 0x1000>;
78 interrupts = <0x0e 0>;
Roland Stiggecb85a9e2012-06-14 16:16:18 +020079 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +020080 };
81
82 mac: ethernet@31060000 {
83 compatible = "nxp,lpc-eth";
84 reg = <0x31060000 0x1000>;
85 interrupts = <0x1d 0>;
86 };
87
88 apb {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "simple-bus";
92 ranges = <0x20000000 0x20000000 0x30000000>;
93
94 ssp0: ssp@20084000 {
95 compatible = "arm,pl022", "arm,primecell";
96 reg = <0x20084000 0x1000>;
97 interrupts = <0x14 0>;
98 };
99
100 spi1: spi@20088000 {
101 compatible = "nxp,lpc3220-spi";
102 reg = <0x20088000 0x1000>;
103 };
104
105 ssp1: ssp@2008c000 {
106 compatible = "arm,pl022", "arm,primecell";
107 reg = <0x2008c000 0x1000>;
108 interrupts = <0x15 0>;
109 };
110
111 spi2: spi@20090000 {
112 compatible = "nxp,lpc3220-spi";
113 reg = <0x20090000 0x1000>;
114 };
115
116 i2s0: i2s@20094000 {
117 compatible = "nxp,lpc3220-i2s";
118 reg = <0x20094000 0x1000>;
119 };
120
121 sd@20098000 {
Roland Stigge2c7fa282012-06-14 16:16:18 +0200122 compatible = "arm,pl18x", "arm,primecell";
Roland Stiggee04920d2012-04-22 12:01:19 +0200123 reg = <0x20098000 0x1000>;
124 interrupts = <0x0f 0>, <0x0d 0>;
Roland Stigge2c7fa282012-06-14 16:16:18 +0200125 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200126 };
127
128 i2s1: i2s@2009C000 {
129 compatible = "nxp,lpc3220-i2s";
130 reg = <0x2009C000 0x1000>;
131 };
132
Roland Stiggec70426f2012-06-14 16:16:18 +0200133 /* UART5 first since it is the default console, ttyS0 */
134 uart5: serial@40090000 {
135 /* actually, ns16550a w/ 64 byte fifos! */
136 compatible = "nxp,lpc3220-uart";
137 reg = <0x40090000 0x1000>;
138 interrupts = <9 0>;
139 clock-frequency = <13000000>;
140 reg-shift = <2>;
141 status = "disabled";
142 };
143
Roland Stiggee04920d2012-04-22 12:01:19 +0200144 uart3: serial@40080000 {
Roland Stiggec70426f2012-06-14 16:16:18 +0200145 compatible = "nxp,lpc3220-uart";
Roland Stiggee04920d2012-04-22 12:01:19 +0200146 reg = <0x40080000 0x1000>;
Roland Stiggec70426f2012-06-14 16:16:18 +0200147 interrupts = <7 0>;
148 clock-frequency = <13000000>;
149 reg-shift = <2>;
150 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200151 };
152
153 uart4: serial@40088000 {
Roland Stiggec70426f2012-06-14 16:16:18 +0200154 compatible = "nxp,lpc3220-uart";
Roland Stiggee04920d2012-04-22 12:01:19 +0200155 reg = <0x40088000 0x1000>;
Roland Stiggec70426f2012-06-14 16:16:18 +0200156 interrupts = <8 0>;
157 clock-frequency = <13000000>;
158 reg-shift = <2>;
159 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200160 };
161
162 uart6: serial@40098000 {
Roland Stiggec70426f2012-06-14 16:16:18 +0200163 compatible = "nxp,lpc3220-uart";
Roland Stiggee04920d2012-04-22 12:01:19 +0200164 reg = <0x40098000 0x1000>;
Roland Stiggec70426f2012-06-14 16:16:18 +0200165 interrupts = <10 0>;
166 clock-frequency = <13000000>;
167 reg-shift = <2>;
168 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200169 };
170
171 i2c1: i2c@400A0000 {
172 compatible = "nxp,pnx-i2c";
173 reg = <0x400A0000 0x100>;
174 interrupts = <0x33 0>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 pnx,timeout = <0x64>;
178 };
179
180 i2c2: i2c@400A8000 {
181 compatible = "nxp,pnx-i2c";
182 reg = <0x400A8000 0x100>;
183 interrupts = <0x32 0>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 pnx,timeout = <0x64>;
187 };
188
Alban Bedelb7d41c92012-11-14 13:59:45 +0100189 mpwm: mpwm@400E8000 {
190 compatible = "nxp,lpc3220-motor-pwm";
191 reg = <0x400E8000 0x78>;
192 status = "disabled";
193 #pwm-cells = <2>;
194 };
195
Roland Stiggee04920d2012-04-22 12:01:19 +0200196 i2cusb: i2c@31020300 {
197 compatible = "nxp,pnx-i2c";
198 reg = <0x31020300 0x100>;
199 interrupts = <0x3f 0>;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 pnx,timeout = <0x64>;
203 };
204 };
205
206 fab {
207 #address-cells = <1>;
208 #size-cells = <1>;
209 compatible = "simple-bus";
210 ranges = <0x20000000 0x20000000 0x30000000>;
211
212 /*
213 * MIC Interrupt controller includes:
214 * MIC @40008000
215 * SIC1 @4000C000
216 * SIC2 @40010000
217 */
218 mic: interrupt-controller@40008000 {
219 compatible = "nxp,lpc3220-mic";
220 interrupt-controller;
221 reg = <0x40008000 0xC000>;
222 #interrupt-cells = <2>;
223 };
224
225 uart1: serial@40014000 {
Roland Stiggeac5ced92012-06-14 16:16:18 +0200226 compatible = "nxp,lpc3220-hsuart";
Roland Stiggee04920d2012-04-22 12:01:19 +0200227 reg = <0x40014000 0x1000>;
Roland Stiggeac5ced92012-06-14 16:16:18 +0200228 interrupts = <26 0>;
229 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200230 };
231
232 uart2: serial@40018000 {
Roland Stiggeac5ced92012-06-14 16:16:18 +0200233 compatible = "nxp,lpc3220-hsuart";
Roland Stiggee04920d2012-04-22 12:01:19 +0200234 reg = <0x40018000 0x1000>;
Roland Stiggeac5ced92012-06-14 16:16:18 +0200235 interrupts = <25 0>;
236 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200237 };
238
Roland Stiggeac5ced92012-06-14 16:16:18 +0200239 uart7: serial@4001c000 {
240 compatible = "nxp,lpc3220-hsuart";
241 reg = <0x4001c000 0x1000>;
242 interrupts = <24 0>;
243 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200244 };
245
246 rtc@40024000 {
247 compatible = "nxp,lpc3220-rtc";
248 reg = <0x40024000 0x1000>;
249 interrupts = <0x34 0>;
250 };
251
252 gpio: gpio@40028000 {
253 compatible = "nxp,lpc3220-gpio";
254 reg = <0x40028000 0x1000>;
Roland Stiggea0352542012-05-19 12:28:53 +0200255 gpio-controller;
256 #gpio-cells = <3>; /* bank, pin, flags */
Roland Stiggee04920d2012-04-22 12:01:19 +0200257 };
258
259 watchdog@4003C000 {
260 compatible = "nxp,pnx4008-wdt";
261 reg = <0x4003C000 0x1000>;
262 };
263
264 /*
265 * TSC vs. ADC: Since those two share the same
266 * hardware, you need to choose from one of the
267 * following two and do 'status = "okay";' for one of
268 * them
269 */
270
271 adc@40048000 {
272 compatible = "nxp,lpc3220-adc";
273 reg = <0x40048000 0x1000>;
274 interrupts = <0x27 0>;
Roland Stiggecb85a9e2012-06-14 16:16:18 +0200275 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200276 };
277
278 tsc@40048000 {
279 compatible = "nxp,lpc3220-tsc";
280 reg = <0x40048000 0x1000>;
281 interrupts = <0x27 0>;
Roland Stiggecb85a9e2012-06-14 16:16:18 +0200282 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200283 };
284
285 key@40050000 {
286 compatible = "nxp,lpc3220-key";
287 reg = <0x40050000 0x1000>;
Roland Stiggea6d1be02012-06-14 16:16:17 +0200288 interrupts = <54 0>;
289 status = "disabled";
Roland Stiggee04920d2012-04-22 12:01:19 +0200290 };
291
Alexandre Pereira da Silvade639852012-07-20 13:33:09 +0200292 pwm: pwm@4005C000 {
293 compatible = "nxp,lpc3220-pwm";
294 reg = <0x4005C000 0x8>;
295 status = "disabled";
296 };
Roland Stiggee04920d2012-04-22 12:01:19 +0200297 };
298 };
299};