blob: d0bc123c7975200a204a6b2608b5620ed5ec71b8 [file] [log] [blame]
Thomas Petazzonifefe7b02012-09-19 22:52:58 +02001/*
2 * GPIO driver for Marvell SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
21 * block:
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
28 * registers.
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
33 * interrupts.
34 */
35
Thierry Reding641d0342013-01-21 11:09:01 +010036#include <linux/err.h>
Thomas Petazzonifefe7b02012-09-19 22:52:58 +020037#include <linux/module.h>
38#include <linux/gpio.h>
39#include <linux/irq.h>
40#include <linux/slab.h>
41#include <linux/irqdomain.h>
42#include <linux/io.h>
43#include <linux/of_irq.h>
44#include <linux/of_device.h>
Andrew Lunnde887472013-02-03 11:34:26 +010045#include <linux/clk.h>
Thomas Petazzonifefe7b02012-09-19 22:52:58 +020046#include <linux/pinctrl/consumer.h>
Thomas Petazzoni01ca59f2014-02-07 12:29:19 +010047#include <linux/irqchip/chained_irq.h>
Thomas Petazzonifefe7b02012-09-19 22:52:58 +020048
49/*
50 * GPIO unit register offsets.
51 */
52#define GPIO_OUT_OFF 0x0000
53#define GPIO_IO_CONF_OFF 0x0004
54#define GPIO_BLINK_EN_OFF 0x0008
55#define GPIO_IN_POL_OFF 0x000c
56#define GPIO_DATA_IN_OFF 0x0010
57#define GPIO_EDGE_CAUSE_OFF 0x0014
58#define GPIO_EDGE_MASK_OFF 0x0018
59#define GPIO_LEVEL_MASK_OFF 0x001c
60
61/* The MV78200 has per-CPU registers for edge mask and level mask */
Andrew Lunna4319a62015-01-10 00:34:47 +010062#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +020063#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
64
65/* The Armada XP has per-CPU registers for interrupt cause, interrupt
66 * mask and interrupt level mask. Those are relative to the
67 * percpu_membase. */
68#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
69#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
70#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
71
Andrew Lunna4319a62015-01-10 00:34:47 +010072#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
73#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
Thomas Petazzonifefe7b02012-09-19 22:52:58 +020074#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
75
Andrew Lunna4319a62015-01-10 00:34:47 +010076#define MVEBU_MAX_GPIO_PER_BANK 32
Thomas Petazzonifefe7b02012-09-19 22:52:58 +020077
78struct mvebu_gpio_chip {
79 struct gpio_chip chip;
80 spinlock_t lock;
81 void __iomem *membase;
82 void __iomem *percpu_membase;
Dan Carpenterd5359222013-11-07 10:50:19 +030083 int irqbase;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +020084 struct irq_domain *domain;
Andrew Lunna4319a62015-01-10 00:34:47 +010085 int soc_variant;
Thomas Petazzonib5b7b482014-10-24 13:59:19 +020086
Andrew Lunna4319a62015-01-10 00:34:47 +010087 /* Used to preserve GPIO registers across suspend/resume */
Thomas Petazzonib5b7b482014-10-24 13:59:19 +020088 u32 out_reg;
89 u32 io_conf_reg;
90 u32 blink_en_reg;
91 u32 in_pol_reg;
92 u32 edge_mask_regs[4];
93 u32 level_mask_regs[4];
Thomas Petazzonifefe7b02012-09-19 22:52:58 +020094};
95
96/*
97 * Functions returning addresses of individual registers for a given
98 * GPIO controller.
99 */
100static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
101{
102 return mvchip->membase + GPIO_OUT_OFF;
103}
104
Jamie Lentine9133762012-10-28 12:23:24 +0000105static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
106{
107 return mvchip->membase + GPIO_BLINK_EN_OFF;
108}
109
Andrew Lunna4319a62015-01-10 00:34:47 +0100110static inline void __iomem *
111mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200112{
113 return mvchip->membase + GPIO_IO_CONF_OFF;
114}
115
116static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
117{
118 return mvchip->membase + GPIO_IN_POL_OFF;
119}
120
Andrew Lunna4319a62015-01-10 00:34:47 +0100121static inline void __iomem *
122mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200123{
124 return mvchip->membase + GPIO_DATA_IN_OFF;
125}
126
Andrew Lunna4319a62015-01-10 00:34:47 +0100127static inline void __iomem *
128mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200129{
130 int cpu;
131
Laurent Navetf4dcd2d2013-03-20 13:15:56 +0100132 switch (mvchip->soc_variant) {
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200133 case MVEBU_GPIO_SOC_VARIANT_ORION:
134 case MVEBU_GPIO_SOC_VARIANT_MV78200:
135 return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
136 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
137 cpu = smp_processor_id();
Andrew Lunna4319a62015-01-10 00:34:47 +0100138 return mvchip->percpu_membase +
139 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200140 default:
141 BUG();
142 }
143}
144
Andrew Lunna4319a62015-01-10 00:34:47 +0100145static inline void __iomem *
146mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200147{
148 int cpu;
149
Laurent Navetf4dcd2d2013-03-20 13:15:56 +0100150 switch (mvchip->soc_variant) {
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200151 case MVEBU_GPIO_SOC_VARIANT_ORION:
152 return mvchip->membase + GPIO_EDGE_MASK_OFF;
153 case MVEBU_GPIO_SOC_VARIANT_MV78200:
154 cpu = smp_processor_id();
155 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
156 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
157 cpu = smp_processor_id();
Andrew Lunna4319a62015-01-10 00:34:47 +0100158 return mvchip->percpu_membase +
159 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200160 default:
161 BUG();
162 }
163}
164
165static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
166{
167 int cpu;
168
Laurent Navetf4dcd2d2013-03-20 13:15:56 +0100169 switch (mvchip->soc_variant) {
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200170 case MVEBU_GPIO_SOC_VARIANT_ORION:
171 return mvchip->membase + GPIO_LEVEL_MASK_OFF;
172 case MVEBU_GPIO_SOC_VARIANT_MV78200:
173 cpu = smp_processor_id();
174 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
175 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
176 cpu = smp_processor_id();
Andrew Lunna4319a62015-01-10 00:34:47 +0100177 return mvchip->percpu_membase +
178 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200179 default:
180 BUG();
181 }
182}
183
184/*
185 * Functions implementing the gpio_chip methods
186 */
187
Axel Lin3764bdd2012-11-08 10:27:29 +0800188static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200189{
190 return pinctrl_request_gpio(chip->base + pin);
191}
192
Axel Lin3764bdd2012-11-08 10:27:29 +0800193static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200194{
195 pinctrl_free_gpio(chip->base + pin);
196}
197
198static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
199{
200 struct mvebu_gpio_chip *mvchip =
201 container_of(chip, struct mvebu_gpio_chip, chip);
202 unsigned long flags;
203 u32 u;
204
205 spin_lock_irqsave(&mvchip->lock, flags);
206 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
207 if (value)
208 u |= 1 << pin;
209 else
210 u &= ~(1 << pin);
211 writel_relaxed(u, mvebu_gpioreg_out(mvchip));
212 spin_unlock_irqrestore(&mvchip->lock, flags);
213}
214
215static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
216{
217 struct mvebu_gpio_chip *mvchip =
218 container_of(chip, struct mvebu_gpio_chip, chip);
219 u32 u;
220
221 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
222 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
223 readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
224 } else {
225 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
226 }
227
228 return (u >> pin) & 1;
229}
230
Jamie Lentine9133762012-10-28 12:23:24 +0000231static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
232{
233 struct mvebu_gpio_chip *mvchip =
234 container_of(chip, struct mvebu_gpio_chip, chip);
235 unsigned long flags;
236 u32 u;
237
238 spin_lock_irqsave(&mvchip->lock, flags);
239 u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
240 if (value)
241 u |= 1 << pin;
242 else
243 u &= ~(1 << pin);
244 writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
245 spin_unlock_irqrestore(&mvchip->lock, flags);
246}
247
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200248static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
249{
250 struct mvebu_gpio_chip *mvchip =
251 container_of(chip, struct mvebu_gpio_chip, chip);
252 unsigned long flags;
253 int ret;
254 u32 u;
255
256 /* Check with the pinctrl driver whether this pin is usable as
257 * an input GPIO */
258 ret = pinctrl_gpio_direction_input(chip->base + pin);
259 if (ret)
260 return ret;
261
262 spin_lock_irqsave(&mvchip->lock, flags);
263 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
264 u |= 1 << pin;
265 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
266 spin_unlock_irqrestore(&mvchip->lock, flags);
267
268 return 0;
269}
270
271static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
272 int value)
273{
274 struct mvebu_gpio_chip *mvchip =
275 container_of(chip, struct mvebu_gpio_chip, chip);
276 unsigned long flags;
277 int ret;
278 u32 u;
279
280 /* Check with the pinctrl driver whether this pin is usable as
281 * an output GPIO */
282 ret = pinctrl_gpio_direction_output(chip->base + pin);
283 if (ret)
284 return ret;
285
Jamie Lentine9133762012-10-28 12:23:24 +0000286 mvebu_gpio_blink(chip, pin, 0);
Thomas Petazzonic57d75c2012-10-23 10:17:05 +0200287 mvebu_gpio_set(chip, pin, value);
288
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200289 spin_lock_irqsave(&mvchip->lock, flags);
290 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
291 u &= ~(1 << pin);
292 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
293 spin_unlock_irqrestore(&mvchip->lock, flags);
294
295 return 0;
296}
297
298static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
299{
300 struct mvebu_gpio_chip *mvchip =
301 container_of(chip, struct mvebu_gpio_chip, chip);
302 return irq_create_mapping(mvchip->domain, pin);
303}
304
305/*
306 * Functions implementing the irq_chip methods
307 */
308static void mvebu_gpio_irq_ack(struct irq_data *d)
309{
310 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
311 struct mvebu_gpio_chip *mvchip = gc->private;
312 u32 mask = ~(1 << (d->irq - gc->irq_base));
313
314 irq_gc_lock(gc);
315 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
316 irq_gc_unlock(gc);
317}
318
319static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
320{
321 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
322 struct mvebu_gpio_chip *mvchip = gc->private;
323 u32 mask = 1 << (d->irq - gc->irq_base);
324
325 irq_gc_lock(gc);
326 gc->mask_cache &= ~mask;
327 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
328 irq_gc_unlock(gc);
329}
330
331static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
332{
333 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
334 struct mvebu_gpio_chip *mvchip = gc->private;
335 u32 mask = 1 << (d->irq - gc->irq_base);
336
337 irq_gc_lock(gc);
338 gc->mask_cache |= mask;
339 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
340 irq_gc_unlock(gc);
341}
342
343static void mvebu_gpio_level_irq_mask(struct irq_data *d)
344{
345 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
346 struct mvebu_gpio_chip *mvchip = gc->private;
347 u32 mask = 1 << (d->irq - gc->irq_base);
348
349 irq_gc_lock(gc);
350 gc->mask_cache &= ~mask;
351 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
352 irq_gc_unlock(gc);
353}
354
355static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
356{
357 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
358 struct mvebu_gpio_chip *mvchip = gc->private;
359 u32 mask = 1 << (d->irq - gc->irq_base);
360
361 irq_gc_lock(gc);
362 gc->mask_cache |= mask;
363 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
364 irq_gc_unlock(gc);
365}
366
367/*****************************************************************************
368 * MVEBU GPIO IRQ
369 *
370 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
371 * value of the line or the opposite value.
372 *
373 * Level IRQ handlers: DATA_IN is used directly as cause register.
Andrew Lunna4319a62015-01-10 00:34:47 +0100374 * Interrupt are masked by LEVEL_MASK registers.
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200375 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
Andrew Lunna4319a62015-01-10 00:34:47 +0100376 * Interrupt are masked by EDGE_MASK registers.
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200377 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
Andrew Lunna4319a62015-01-10 00:34:47 +0100378 * the polarity to catch the next line transaction.
379 * This is a race condition that might not perfectly
380 * work on some use cases.
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200381 *
382 * Every eight GPIO lines are grouped (OR'ed) before going up to main
383 * cause register.
384 *
Andrew Lunna4319a62015-01-10 00:34:47 +0100385 * EDGE cause mask
386 * data-in /--------| |-----| |----\
387 * -----| |----- ---- to main cause reg
388 * X \----------------| |----/
389 * polarity LEVEL mask
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200390 *
391 ****************************************************************************/
392
393static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
394{
395 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
396 struct irq_chip_type *ct = irq_data_get_chip_type(d);
397 struct mvebu_gpio_chip *mvchip = gc->private;
398 int pin;
399 u32 u;
400
401 pin = d->hwirq;
402
403 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
Andrew Lunna4319a62015-01-10 00:34:47 +0100404 if (!u)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200405 return -EINVAL;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200406
407 type &= IRQ_TYPE_SENSE_MASK;
408 if (type == IRQ_TYPE_NONE)
409 return -EINVAL;
410
411 /* Check if we need to change chip and handler */
412 if (!(ct->type & type))
413 if (irq_setup_alt_chip(d, type))
414 return -EINVAL;
415
416 /*
417 * Configure interrupt polarity.
418 */
Laurent Navetf4dcd2d2013-03-20 13:15:56 +0100419 switch (type) {
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200420 case IRQ_TYPE_EDGE_RISING:
421 case IRQ_TYPE_LEVEL_HIGH:
422 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
423 u &= ~(1 << pin);
424 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
Axel Lin7cf8c9f2012-09-30 16:23:27 +0800425 break;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200426 case IRQ_TYPE_EDGE_FALLING:
427 case IRQ_TYPE_LEVEL_LOW:
428 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
429 u |= 1 << pin;
430 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
Axel Lin7cf8c9f2012-09-30 16:23:27 +0800431 break;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200432 case IRQ_TYPE_EDGE_BOTH: {
433 u32 v;
434
435 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
436 readl_relaxed(mvebu_gpioreg_data_in(mvchip));
437
438 /*
439 * set initial polarity based on current input level
440 */
441 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
442 if (v & (1 << pin))
443 u |= 1 << pin; /* falling */
444 else
445 u &= ~(1 << pin); /* rising */
446 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
Axel Lin7cf8c9f2012-09-30 16:23:27 +0800447 break;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200448 }
449 }
450 return 0;
451}
452
453static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
454{
455 struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
Thomas Petazzoni01ca59f2014-02-07 12:29:19 +0100456 struct irq_chip *chip = irq_desc_get_chip(desc);
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200457 u32 cause, type;
458 int i;
459
460 if (mvchip == NULL)
461 return;
462
Thomas Petazzoni01ca59f2014-02-07 12:29:19 +0100463 chained_irq_enter(chip, desc);
464
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200465 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
466 readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
467 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
468 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
469
470 for (i = 0; i < mvchip->chip.ngpio; i++) {
471 int irq;
472
473 irq = mvchip->irqbase + i;
474
475 if (!(cause & (1 << i)))
476 continue;
477
Javier Martinez Canillasfb90c222013-06-14 18:40:44 +0200478 type = irq_get_trigger_type(irq);
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200479 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
480 /* Swap polarity (race with GPIO line) */
481 u32 polarity;
482
483 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
484 polarity ^= 1 << i;
485 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
486 }
Thomas Petazzoni01ca59f2014-02-07 12:29:19 +0100487
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200488 generic_handle_irq(irq);
489 }
Thomas Petazzoni01ca59f2014-02-07 12:29:19 +0100490
491 chained_irq_exit(chip, desc);
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200492}
493
Simon Guinota4ba5e12013-03-24 15:45:29 +0100494#ifdef CONFIG_DEBUG_FS
495#include <linux/seq_file.h>
496
497static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
498{
499 struct mvebu_gpio_chip *mvchip =
500 container_of(chip, struct mvebu_gpio_chip, chip);
501 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
502 int i;
503
504 out = readl_relaxed(mvebu_gpioreg_out(mvchip));
505 io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
506 blink = readl_relaxed(mvebu_gpioreg_blink(mvchip));
507 in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
508 data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip));
509 cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip));
510 edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
511 lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
512
513 for (i = 0; i < chip->ngpio; i++) {
514 const char *label;
515 u32 msk;
516 bool is_out;
517
518 label = gpiochip_is_requested(chip, i);
519 if (!label)
520 continue;
521
522 msk = 1 << i;
523 is_out = !(io_conf & msk);
524
525 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
526
527 if (is_out) {
528 seq_printf(s, " out %s %s\n",
529 out & msk ? "hi" : "lo",
530 blink & msk ? "(blink )" : "");
531 continue;
532 }
533
534 seq_printf(s, " in %s (act %s) - IRQ",
535 (data_in ^ in_pol) & msk ? "hi" : "lo",
536 in_pol & msk ? "lo" : "hi");
537 if (!((edg_msk | lvl_msk) & msk)) {
Andrew Lunna4319a62015-01-10 00:34:47 +0100538 seq_puts(s, " disabled\n");
Simon Guinota4ba5e12013-03-24 15:45:29 +0100539 continue;
540 }
541 if (edg_msk & msk)
Andrew Lunna4319a62015-01-10 00:34:47 +0100542 seq_puts(s, " edge ");
Simon Guinota4ba5e12013-03-24 15:45:29 +0100543 if (lvl_msk & msk)
Andrew Lunna4319a62015-01-10 00:34:47 +0100544 seq_puts(s, " level");
Simon Guinota4ba5e12013-03-24 15:45:29 +0100545 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
546 }
547}
548#else
549#define mvebu_gpio_dbg_show NULL
550#endif
551
Jingoo Han271b17b2014-05-07 18:06:08 +0900552static const struct of_device_id mvebu_gpio_of_match[] = {
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200553 {
554 .compatible = "marvell,orion-gpio",
Andrew Lunna4319a62015-01-10 00:34:47 +0100555 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200556 },
557 {
558 .compatible = "marvell,mv78200-gpio",
Andrew Lunna4319a62015-01-10 00:34:47 +0100559 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200560 },
561 {
562 .compatible = "marvell,armadaxp-gpio",
Andrew Lunna4319a62015-01-10 00:34:47 +0100563 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200564 },
565 {
566 /* sentinel */
567 },
568};
569MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
570
Thomas Petazzonib5b7b482014-10-24 13:59:19 +0200571static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
572{
573 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
574 int i;
575
576 mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip));
577 mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip));
578 mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip));
579 mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip));
580
581 switch (mvchip->soc_variant) {
582 case MVEBU_GPIO_SOC_VARIANT_ORION:
583 mvchip->edge_mask_regs[0] =
584 readl(mvchip->membase + GPIO_EDGE_MASK_OFF);
585 mvchip->level_mask_regs[0] =
586 readl(mvchip->membase + GPIO_LEVEL_MASK_OFF);
587 break;
588 case MVEBU_GPIO_SOC_VARIANT_MV78200:
589 for (i = 0; i < 2; i++) {
590 mvchip->edge_mask_regs[i] =
591 readl(mvchip->membase +
592 GPIO_EDGE_MASK_MV78200_OFF(i));
593 mvchip->level_mask_regs[i] =
594 readl(mvchip->membase +
595 GPIO_LEVEL_MASK_MV78200_OFF(i));
596 }
597 break;
598 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
599 for (i = 0; i < 4; i++) {
600 mvchip->edge_mask_regs[i] =
601 readl(mvchip->membase +
602 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
603 mvchip->level_mask_regs[i] =
604 readl(mvchip->membase +
605 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
606 }
607 break;
608 default:
609 BUG();
610 }
611
612 return 0;
613}
614
615static int mvebu_gpio_resume(struct platform_device *pdev)
616{
617 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
618 int i;
619
620 writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip));
621 writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip));
622 writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip));
623 writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip));
624
625 switch (mvchip->soc_variant) {
626 case MVEBU_GPIO_SOC_VARIANT_ORION:
627 writel(mvchip->edge_mask_regs[0],
628 mvchip->membase + GPIO_EDGE_MASK_OFF);
629 writel(mvchip->level_mask_regs[0],
630 mvchip->membase + GPIO_LEVEL_MASK_OFF);
631 break;
632 case MVEBU_GPIO_SOC_VARIANT_MV78200:
633 for (i = 0; i < 2; i++) {
634 writel(mvchip->edge_mask_regs[i],
635 mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i));
636 writel(mvchip->level_mask_regs[i],
637 mvchip->membase +
638 GPIO_LEVEL_MASK_MV78200_OFF(i));
639 }
640 break;
641 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
642 for (i = 0; i < 4; i++) {
643 writel(mvchip->edge_mask_regs[i],
644 mvchip->membase +
645 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
646 writel(mvchip->level_mask_regs[i],
647 mvchip->membase +
648 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
649 }
650 break;
651 default:
652 BUG();
653 }
654
655 return 0;
656}
657
Bill Pemberton38363092012-11-19 13:22:34 -0500658static int mvebu_gpio_probe(struct platform_device *pdev)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200659{
660 struct mvebu_gpio_chip *mvchip;
661 const struct of_device_id *match;
662 struct device_node *np = pdev->dev.of_node;
663 struct resource *res;
664 struct irq_chip_generic *gc;
665 struct irq_chip_type *ct;
Andrew Lunnde887472013-02-03 11:34:26 +0100666 struct clk *clk;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200667 unsigned int ngpios;
668 int soc_variant;
669 int i, cpu, id;
Andrew Lunnf1d2d082015-01-10 00:34:48 +0100670 int err;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200671
672 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
673 if (match)
674 soc_variant = (int) match->data;
675 else
676 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
677
Andrew Lunna4319a62015-01-10 00:34:47 +0100678 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
679 GFP_KERNEL);
Jingoo Han6c8365f2014-04-29 17:38:21 +0900680 if (!mvchip)
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200681 return -ENOMEM;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200682
Thomas Petazzonib5b7b482014-10-24 13:59:19 +0200683 platform_set_drvdata(pdev, mvchip);
684
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200685 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
686 dev_err(&pdev->dev, "Missing ngpios OF property\n");
687 return -ENODEV;
688 }
689
690 id = of_alias_get_id(pdev->dev.of_node, "gpio");
691 if (id < 0) {
692 dev_err(&pdev->dev, "Couldn't get OF id\n");
693 return id;
694 }
695
Andrew Lunnde887472013-02-03 11:34:26 +0100696 clk = devm_clk_get(&pdev->dev, NULL);
697 /* Not all SoCs require a clock.*/
698 if (!IS_ERR(clk))
699 clk_prepare_enable(clk);
700
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200701 mvchip->soc_variant = soc_variant;
702 mvchip->chip.label = dev_name(&pdev->dev);
703 mvchip->chip.dev = &pdev->dev;
704 mvchip->chip.request = mvebu_gpio_request;
Axel Lin3764bdd2012-11-08 10:27:29 +0800705 mvchip->chip.free = mvebu_gpio_free;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200706 mvchip->chip.direction_input = mvebu_gpio_direction_input;
707 mvchip->chip.get = mvebu_gpio_get;
708 mvchip->chip.direction_output = mvebu_gpio_direction_output;
709 mvchip->chip.set = mvebu_gpio_set;
710 mvchip->chip.to_irq = mvebu_gpio_to_irq;
711 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
712 mvchip->chip.ngpio = ngpios;
Linus Walleij9fb1f392013-12-04 14:42:46 +0100713 mvchip->chip.can_sleep = false;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200714 mvchip->chip.of_node = np;
Simon Guinota4ba5e12013-03-24 15:45:29 +0100715 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200716
717 spin_lock_init(&mvchip->lock);
Julia Lawall08a67a52013-08-14 11:11:07 +0200718 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding641d0342013-01-21 11:09:01 +0100719 mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
Greg Kroah-Hartman422d26b2013-01-25 21:06:30 -0800720 if (IS_ERR(mvchip->membase))
Thierry Reding641d0342013-01-21 11:09:01 +0100721 return PTR_ERR(mvchip->membase);
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200722
723 /* The Armada XP has a second range of registers for the
724 * per-CPU registers */
725 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
726 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Thierry Reding641d0342013-01-21 11:09:01 +0100727 mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
728 res);
Laurent Navetf4dcd2d2013-03-20 13:15:56 +0100729 if (IS_ERR(mvchip->percpu_membase))
Thierry Reding641d0342013-01-21 11:09:01 +0100730 return PTR_ERR(mvchip->percpu_membase);
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200731 }
732
733 /*
734 * Mask and clear GPIO interrupts.
735 */
Laurent Navetf4dcd2d2013-03-20 13:15:56 +0100736 switch (soc_variant) {
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200737 case MVEBU_GPIO_SOC_VARIANT_ORION:
738 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
739 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
740 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
741 break;
742 case MVEBU_GPIO_SOC_VARIANT_MV78200:
743 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
744 for (cpu = 0; cpu < 2; cpu++) {
745 writel_relaxed(0, mvchip->membase +
746 GPIO_EDGE_MASK_MV78200_OFF(cpu));
747 writel_relaxed(0, mvchip->membase +
748 GPIO_LEVEL_MASK_MV78200_OFF(cpu));
749 }
750 break;
751 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
752 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
753 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
754 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
755 for (cpu = 0; cpu < 4; cpu++) {
756 writel_relaxed(0, mvchip->percpu_membase +
757 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
758 writel_relaxed(0, mvchip->percpu_membase +
759 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
760 writel_relaxed(0, mvchip->percpu_membase +
761 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
762 }
763 break;
764 default:
765 BUG();
766 }
767
768 gpiochip_add(&mvchip->chip);
769
770 /* Some gpio controllers do not provide irq support */
771 if (!of_irq_count(np))
772 return 0;
773
774 /* Setup the interrupt handlers. Each chip can have up to 4
775 * interrupt handlers, with each handler dealing with 8 GPIO
776 * pins. */
777 for (i = 0; i < 4; i++) {
Andrew Lunna4319a62015-01-10 00:34:47 +0100778 int irq = platform_get_irq(pdev, i);
779
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200780 if (irq < 0)
781 continue;
782 irq_set_handler_data(irq, mvchip);
783 irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
784 }
785
786 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
787 if (mvchip->irqbase < 0) {
788 dev_err(&pdev->dev, "no irqs\n");
Andrew Lunnf1d2d082015-01-10 00:34:48 +0100789 err = mvchip->irqbase;
790 goto err_gpiochip_add;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200791 }
792
793 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
794 mvchip->membase, handle_level_irq);
Laurent Navetf4dcd2d2013-03-20 13:15:56 +0100795 if (!gc) {
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200796 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
Andrew Lunnf1d2d082015-01-10 00:34:48 +0100797 err = -ENOMEM;
798 goto err_gpiochip_add;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200799 }
800
801 gc->private = mvchip;
802 ct = &gc->chip_types[0];
803 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
804 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
805 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
806 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
807 ct->chip.name = mvchip->chip.label;
808
809 ct = &gc->chip_types[1];
810 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
811 ct->chip.irq_ack = mvebu_gpio_irq_ack;
812 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
813 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
814 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
815 ct->handler = handle_edge_irq;
816 ct->chip.name = mvchip->chip.label;
817
Andrew Lunn8fcff5f2012-10-27 15:28:58 +0200818 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200819 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
820
821 /* Setup irq domain on top of the generic chip. */
Linus Walleijce931f52012-10-16 20:21:04 +0200822 mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio,
823 mvchip->irqbase,
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200824 &irq_domain_simple_ops,
825 mvchip);
826 if (!mvchip->domain) {
827 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
828 mvchip->chip.label);
Andrew Lunnf1d2d082015-01-10 00:34:48 +0100829 err = -ENODEV;
830 goto err_generic_chip;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200831 }
832
833 return 0;
Andrew Lunnf1d2d082015-01-10 00:34:48 +0100834
835err_generic_chip:
836 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
837 IRQ_LEVEL | IRQ_NOPROBE);
838 kfree(gc);
839
840err_gpiochip_add:
841 gpiochip_remove(&mvchip->chip);
842
843 return err;
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200844}
845
846static struct platform_driver mvebu_gpio_driver = {
847 .driver = {
Andrew Lunna4319a62015-01-10 00:34:47 +0100848 .name = "mvebu-gpio",
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200849 .of_match_table = mvebu_gpio_of_match,
850 },
851 .probe = mvebu_gpio_probe,
Thomas Petazzonib5b7b482014-10-24 13:59:19 +0200852 .suspend = mvebu_gpio_suspend,
853 .resume = mvebu_gpio_resume,
Thomas Petazzonifefe7b02012-09-19 22:52:58 +0200854};
Ezequiel Garciadd640032014-04-24 17:54:50 -0300855module_platform_driver(mvebu_gpio_driver);