Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 28 | #include <linux/firmware.h> |
| 29 | #include <linux/platform_device.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 32 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 33 | #include "radeon_asic.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 34 | #include <drm/radeon_drm.h> |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 35 | #include "rv770d.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 36 | #include "atom.h" |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 37 | #include "avivod.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 39 | #define R700_PFP_UCODE_SIZE 848 |
| 40 | #define R700_PM4_UCODE_SIZE 1360 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 42 | static void rv770_gpu_init(struct radeon_device *rdev); |
| 43 | void rv770_fini(struct radeon_device *rdev); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 45 | int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
| 46 | |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 47 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) |
| 48 | { |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 49 | unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 50 | int r; |
| 51 | |
| 52 | /* RV740 uses evergreen uvd clk programming */ |
| 53 | if (rdev->family == CHIP_RV740) |
| 54 | return evergreen_set_uvd_clocks(rdev, vclk, dclk); |
| 55 | |
Christian König | 4ed1083 | 2013-04-18 15:25:58 +0200 | [diff] [blame] | 56 | /* bypass vclk and dclk with bclk */ |
| 57 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
| 58 | VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), |
| 59 | ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); |
| 60 | |
| 61 | if (!vclk || !dclk) { |
| 62 | /* keep the Bypass mode, put PLL to sleep */ |
| 63 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
| 64 | return 0; |
| 65 | } |
| 66 | |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 67 | r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, |
| 68 | 43663, 0x03FFFFFE, 1, 30, ~0, |
| 69 | &fb_div, &vclk_div, &dclk_div); |
| 70 | if (r) |
| 71 | return r; |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 72 | |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 73 | fb_div |= 1; |
| 74 | vclk_div -= 1; |
| 75 | dclk_div -= 1; |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 76 | |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 77 | /* set UPLL_FB_DIV to 0x50000 */ |
| 78 | WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); |
| 79 | |
Christian König | 4ed1083 | 2013-04-18 15:25:58 +0200 | [diff] [blame] | 80 | /* deassert UPLL_RESET and UPLL_SLEEP */ |
| 81 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 82 | |
| 83 | /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ |
| 84 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); |
| 85 | WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); |
| 86 | |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 87 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 88 | if (r) |
| 89 | return r; |
| 90 | |
| 91 | /* assert PLL_RESET */ |
| 92 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); |
| 93 | |
| 94 | /* set the required FB_DIV, REF_DIV, Post divder values */ |
| 95 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); |
| 96 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 97 | UPLL_SW_HILEN(vclk_div >> 1) | |
| 98 | UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | |
| 99 | UPLL_SW_HILEN2(dclk_div >> 1) | |
| 100 | UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 101 | ~UPLL_SW_MASK); |
| 102 | |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 103 | WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 104 | ~UPLL_FB_DIV_MASK); |
| 105 | |
| 106 | /* give the PLL some time to settle */ |
| 107 | mdelay(15); |
| 108 | |
| 109 | /* deassert PLL_RESET */ |
| 110 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); |
| 111 | |
| 112 | mdelay(15); |
| 113 | |
| 114 | /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ |
| 115 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); |
| 116 | WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); |
| 117 | |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 118 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
Christian König | ef0e6e6 | 2013-04-08 12:41:35 +0200 | [diff] [blame] | 119 | if (r) |
| 120 | return r; |
| 121 | |
| 122 | /* switch VCLK and DCLK selection */ |
| 123 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
| 124 | VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), |
| 125 | ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); |
| 126 | |
| 127 | mdelay(100); |
| 128 | |
| 129 | return 0; |
| 130 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 131 | |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 132 | static const u32 r7xx_golden_registers[] = |
| 133 | { |
| 134 | 0x8d00, 0xffffffff, 0x0e0e0074, |
| 135 | 0x8d04, 0xffffffff, 0x013a2b34, |
| 136 | 0x9508, 0xffffffff, 0x00000002, |
| 137 | 0x8b20, 0xffffffff, 0, |
| 138 | 0x88c4, 0xffffffff, 0x000000c2, |
| 139 | 0x28350, 0xffffffff, 0, |
| 140 | 0x9058, 0xffffffff, 0x0fffc40f, |
| 141 | 0x240c, 0xffffffff, 0x00000380, |
| 142 | 0x733c, 0xffffffff, 0x00000002, |
| 143 | 0x2650, 0x00040000, 0, |
| 144 | 0x20bc, 0x00040000, 0, |
| 145 | 0x7300, 0xffffffff, 0x001000f0 |
| 146 | }; |
| 147 | |
| 148 | static const u32 r7xx_golden_dyn_gpr_registers[] = |
| 149 | { |
| 150 | 0x8db0, 0xffffffff, 0x98989898, |
| 151 | 0x8db4, 0xffffffff, 0x98989898, |
| 152 | 0x8db8, 0xffffffff, 0x98989898, |
| 153 | 0x8dbc, 0xffffffff, 0x98989898, |
| 154 | 0x8dc0, 0xffffffff, 0x98989898, |
| 155 | 0x8dc4, 0xffffffff, 0x98989898, |
| 156 | 0x8dc8, 0xffffffff, 0x98989898, |
| 157 | 0x8dcc, 0xffffffff, 0x98989898, |
| 158 | 0x88c4, 0xffffffff, 0x00000082 |
| 159 | }; |
| 160 | |
| 161 | static const u32 rv770_golden_registers[] = |
| 162 | { |
| 163 | 0x562c, 0xffffffff, 0, |
| 164 | 0x3f90, 0xffffffff, 0, |
| 165 | 0x9148, 0xffffffff, 0, |
| 166 | 0x3f94, 0xffffffff, 0, |
| 167 | 0x914c, 0xffffffff, 0, |
| 168 | 0x9698, 0x18000000, 0x18000000 |
| 169 | }; |
| 170 | |
| 171 | static const u32 rv770ce_golden_registers[] = |
| 172 | { |
| 173 | 0x562c, 0xffffffff, 0, |
| 174 | 0x3f90, 0xffffffff, 0x00cc0000, |
| 175 | 0x9148, 0xffffffff, 0x00cc0000, |
| 176 | 0x3f94, 0xffffffff, 0x00cc0000, |
| 177 | 0x914c, 0xffffffff, 0x00cc0000, |
| 178 | 0x9b7c, 0xffffffff, 0x00fa0000, |
| 179 | 0x3f8c, 0xffffffff, 0x00fa0000, |
| 180 | 0x9698, 0x18000000, 0x18000000 |
| 181 | }; |
| 182 | |
| 183 | static const u32 rv770_mgcg_init[] = |
| 184 | { |
| 185 | 0x8bcc, 0xffffffff, 0x130300f9, |
| 186 | 0x5448, 0xffffffff, 0x100, |
| 187 | 0x55e4, 0xffffffff, 0x100, |
| 188 | 0x160c, 0xffffffff, 0x100, |
| 189 | 0x5644, 0xffffffff, 0x100, |
| 190 | 0xc164, 0xffffffff, 0x100, |
| 191 | 0x8a18, 0xffffffff, 0x100, |
| 192 | 0x897c, 0xffffffff, 0x8000100, |
| 193 | 0x8b28, 0xffffffff, 0x3c000100, |
| 194 | 0x9144, 0xffffffff, 0x100, |
| 195 | 0x9a1c, 0xffffffff, 0x10000, |
| 196 | 0x9a50, 0xffffffff, 0x100, |
| 197 | 0x9a1c, 0xffffffff, 0x10001, |
| 198 | 0x9a50, 0xffffffff, 0x100, |
| 199 | 0x9a1c, 0xffffffff, 0x10002, |
| 200 | 0x9a50, 0xffffffff, 0x100, |
| 201 | 0x9a1c, 0xffffffff, 0x10003, |
| 202 | 0x9a50, 0xffffffff, 0x100, |
| 203 | 0x9a1c, 0xffffffff, 0x0, |
| 204 | 0x9870, 0xffffffff, 0x100, |
| 205 | 0x8d58, 0xffffffff, 0x100, |
| 206 | 0x9500, 0xffffffff, 0x0, |
| 207 | 0x9510, 0xffffffff, 0x100, |
| 208 | 0x9500, 0xffffffff, 0x1, |
| 209 | 0x9510, 0xffffffff, 0x100, |
| 210 | 0x9500, 0xffffffff, 0x2, |
| 211 | 0x9510, 0xffffffff, 0x100, |
| 212 | 0x9500, 0xffffffff, 0x3, |
| 213 | 0x9510, 0xffffffff, 0x100, |
| 214 | 0x9500, 0xffffffff, 0x4, |
| 215 | 0x9510, 0xffffffff, 0x100, |
| 216 | 0x9500, 0xffffffff, 0x5, |
| 217 | 0x9510, 0xffffffff, 0x100, |
| 218 | 0x9500, 0xffffffff, 0x6, |
| 219 | 0x9510, 0xffffffff, 0x100, |
| 220 | 0x9500, 0xffffffff, 0x7, |
| 221 | 0x9510, 0xffffffff, 0x100, |
| 222 | 0x9500, 0xffffffff, 0x8, |
| 223 | 0x9510, 0xffffffff, 0x100, |
| 224 | 0x9500, 0xffffffff, 0x9, |
| 225 | 0x9510, 0xffffffff, 0x100, |
| 226 | 0x9500, 0xffffffff, 0x8000, |
| 227 | 0x9490, 0xffffffff, 0x0, |
| 228 | 0x949c, 0xffffffff, 0x100, |
| 229 | 0x9490, 0xffffffff, 0x1, |
| 230 | 0x949c, 0xffffffff, 0x100, |
| 231 | 0x9490, 0xffffffff, 0x2, |
| 232 | 0x949c, 0xffffffff, 0x100, |
| 233 | 0x9490, 0xffffffff, 0x3, |
| 234 | 0x949c, 0xffffffff, 0x100, |
| 235 | 0x9490, 0xffffffff, 0x4, |
| 236 | 0x949c, 0xffffffff, 0x100, |
| 237 | 0x9490, 0xffffffff, 0x5, |
| 238 | 0x949c, 0xffffffff, 0x100, |
| 239 | 0x9490, 0xffffffff, 0x6, |
| 240 | 0x949c, 0xffffffff, 0x100, |
| 241 | 0x9490, 0xffffffff, 0x7, |
| 242 | 0x949c, 0xffffffff, 0x100, |
| 243 | 0x9490, 0xffffffff, 0x8, |
| 244 | 0x949c, 0xffffffff, 0x100, |
| 245 | 0x9490, 0xffffffff, 0x9, |
| 246 | 0x949c, 0xffffffff, 0x100, |
| 247 | 0x9490, 0xffffffff, 0x8000, |
| 248 | 0x9604, 0xffffffff, 0x0, |
| 249 | 0x9654, 0xffffffff, 0x100, |
| 250 | 0x9604, 0xffffffff, 0x1, |
| 251 | 0x9654, 0xffffffff, 0x100, |
| 252 | 0x9604, 0xffffffff, 0x2, |
| 253 | 0x9654, 0xffffffff, 0x100, |
| 254 | 0x9604, 0xffffffff, 0x3, |
| 255 | 0x9654, 0xffffffff, 0x100, |
| 256 | 0x9604, 0xffffffff, 0x4, |
| 257 | 0x9654, 0xffffffff, 0x100, |
| 258 | 0x9604, 0xffffffff, 0x5, |
| 259 | 0x9654, 0xffffffff, 0x100, |
| 260 | 0x9604, 0xffffffff, 0x6, |
| 261 | 0x9654, 0xffffffff, 0x100, |
| 262 | 0x9604, 0xffffffff, 0x7, |
| 263 | 0x9654, 0xffffffff, 0x100, |
| 264 | 0x9604, 0xffffffff, 0x8, |
| 265 | 0x9654, 0xffffffff, 0x100, |
| 266 | 0x9604, 0xffffffff, 0x9, |
| 267 | 0x9654, 0xffffffff, 0x100, |
| 268 | 0x9604, 0xffffffff, 0x80000000, |
| 269 | 0x9030, 0xffffffff, 0x100, |
| 270 | 0x9034, 0xffffffff, 0x100, |
| 271 | 0x9038, 0xffffffff, 0x100, |
| 272 | 0x903c, 0xffffffff, 0x100, |
| 273 | 0x9040, 0xffffffff, 0x100, |
| 274 | 0xa200, 0xffffffff, 0x100, |
| 275 | 0xa204, 0xffffffff, 0x100, |
| 276 | 0xa208, 0xffffffff, 0x100, |
| 277 | 0xa20c, 0xffffffff, 0x100, |
| 278 | 0x971c, 0xffffffff, 0x100, |
| 279 | 0x915c, 0xffffffff, 0x00020001, |
| 280 | 0x9160, 0xffffffff, 0x00040003, |
| 281 | 0x916c, 0xffffffff, 0x00060005, |
| 282 | 0x9170, 0xffffffff, 0x00080007, |
| 283 | 0x9174, 0xffffffff, 0x000a0009, |
| 284 | 0x9178, 0xffffffff, 0x000c000b, |
| 285 | 0x917c, 0xffffffff, 0x000e000d, |
| 286 | 0x9180, 0xffffffff, 0x0010000f, |
| 287 | 0x918c, 0xffffffff, 0x00120011, |
| 288 | 0x9190, 0xffffffff, 0x00140013, |
| 289 | 0x9194, 0xffffffff, 0x00020001, |
| 290 | 0x9198, 0xffffffff, 0x00040003, |
| 291 | 0x919c, 0xffffffff, 0x00060005, |
| 292 | 0x91a8, 0xffffffff, 0x00080007, |
| 293 | 0x91ac, 0xffffffff, 0x000a0009, |
| 294 | 0x91b0, 0xffffffff, 0x000c000b, |
| 295 | 0x91b4, 0xffffffff, 0x000e000d, |
| 296 | 0x91b8, 0xffffffff, 0x0010000f, |
| 297 | 0x91c4, 0xffffffff, 0x00120011, |
| 298 | 0x91c8, 0xffffffff, 0x00140013, |
| 299 | 0x91cc, 0xffffffff, 0x00020001, |
| 300 | 0x91d0, 0xffffffff, 0x00040003, |
| 301 | 0x91d4, 0xffffffff, 0x00060005, |
| 302 | 0x91e0, 0xffffffff, 0x00080007, |
| 303 | 0x91e4, 0xffffffff, 0x000a0009, |
| 304 | 0x91e8, 0xffffffff, 0x000c000b, |
| 305 | 0x91ec, 0xffffffff, 0x00020001, |
| 306 | 0x91f0, 0xffffffff, 0x00040003, |
| 307 | 0x91f4, 0xffffffff, 0x00060005, |
| 308 | 0x9200, 0xffffffff, 0x00080007, |
| 309 | 0x9204, 0xffffffff, 0x000a0009, |
| 310 | 0x9208, 0xffffffff, 0x000c000b, |
| 311 | 0x920c, 0xffffffff, 0x000e000d, |
| 312 | 0x9210, 0xffffffff, 0x0010000f, |
| 313 | 0x921c, 0xffffffff, 0x00120011, |
| 314 | 0x9220, 0xffffffff, 0x00140013, |
| 315 | 0x9224, 0xffffffff, 0x00020001, |
| 316 | 0x9228, 0xffffffff, 0x00040003, |
| 317 | 0x922c, 0xffffffff, 0x00060005, |
| 318 | 0x9238, 0xffffffff, 0x00080007, |
| 319 | 0x923c, 0xffffffff, 0x000a0009, |
| 320 | 0x9240, 0xffffffff, 0x000c000b, |
| 321 | 0x9244, 0xffffffff, 0x000e000d, |
| 322 | 0x9248, 0xffffffff, 0x0010000f, |
| 323 | 0x9254, 0xffffffff, 0x00120011, |
| 324 | 0x9258, 0xffffffff, 0x00140013, |
| 325 | 0x925c, 0xffffffff, 0x00020001, |
| 326 | 0x9260, 0xffffffff, 0x00040003, |
| 327 | 0x9264, 0xffffffff, 0x00060005, |
| 328 | 0x9270, 0xffffffff, 0x00080007, |
| 329 | 0x9274, 0xffffffff, 0x000a0009, |
| 330 | 0x9278, 0xffffffff, 0x000c000b, |
| 331 | 0x927c, 0xffffffff, 0x000e000d, |
| 332 | 0x9280, 0xffffffff, 0x0010000f, |
| 333 | 0x928c, 0xffffffff, 0x00120011, |
| 334 | 0x9290, 0xffffffff, 0x00140013, |
| 335 | 0x9294, 0xffffffff, 0x00020001, |
| 336 | 0x929c, 0xffffffff, 0x00040003, |
| 337 | 0x92a0, 0xffffffff, 0x00060005, |
| 338 | 0x92a4, 0xffffffff, 0x00080007 |
| 339 | }; |
| 340 | |
| 341 | static const u32 rv710_golden_registers[] = |
| 342 | { |
| 343 | 0x3f90, 0x00ff0000, 0x00fc0000, |
| 344 | 0x9148, 0x00ff0000, 0x00fc0000, |
| 345 | 0x3f94, 0x00ff0000, 0x00fc0000, |
| 346 | 0x914c, 0x00ff0000, 0x00fc0000, |
| 347 | 0xb4c, 0x00000020, 0x00000020, |
| 348 | 0xa180, 0xffffffff, 0x00003f3f |
| 349 | }; |
| 350 | |
| 351 | static const u32 rv710_mgcg_init[] = |
| 352 | { |
| 353 | 0x8bcc, 0xffffffff, 0x13030040, |
| 354 | 0x5448, 0xffffffff, 0x100, |
| 355 | 0x55e4, 0xffffffff, 0x100, |
| 356 | 0x160c, 0xffffffff, 0x100, |
| 357 | 0x5644, 0xffffffff, 0x100, |
| 358 | 0xc164, 0xffffffff, 0x100, |
| 359 | 0x8a18, 0xffffffff, 0x100, |
| 360 | 0x897c, 0xffffffff, 0x8000100, |
| 361 | 0x8b28, 0xffffffff, 0x3c000100, |
| 362 | 0x9144, 0xffffffff, 0x100, |
| 363 | 0x9a1c, 0xffffffff, 0x10000, |
| 364 | 0x9a50, 0xffffffff, 0x100, |
| 365 | 0x9a1c, 0xffffffff, 0x0, |
| 366 | 0x9870, 0xffffffff, 0x100, |
| 367 | 0x8d58, 0xffffffff, 0x100, |
| 368 | 0x9500, 0xffffffff, 0x0, |
| 369 | 0x9510, 0xffffffff, 0x100, |
| 370 | 0x9500, 0xffffffff, 0x1, |
| 371 | 0x9510, 0xffffffff, 0x100, |
| 372 | 0x9500, 0xffffffff, 0x8000, |
| 373 | 0x9490, 0xffffffff, 0x0, |
| 374 | 0x949c, 0xffffffff, 0x100, |
| 375 | 0x9490, 0xffffffff, 0x1, |
| 376 | 0x949c, 0xffffffff, 0x100, |
| 377 | 0x9490, 0xffffffff, 0x8000, |
| 378 | 0x9604, 0xffffffff, 0x0, |
| 379 | 0x9654, 0xffffffff, 0x100, |
| 380 | 0x9604, 0xffffffff, 0x1, |
| 381 | 0x9654, 0xffffffff, 0x100, |
| 382 | 0x9604, 0xffffffff, 0x80000000, |
| 383 | 0x9030, 0xffffffff, 0x100, |
| 384 | 0x9034, 0xffffffff, 0x100, |
| 385 | 0x9038, 0xffffffff, 0x100, |
| 386 | 0x903c, 0xffffffff, 0x100, |
| 387 | 0x9040, 0xffffffff, 0x100, |
| 388 | 0xa200, 0xffffffff, 0x100, |
| 389 | 0xa204, 0xffffffff, 0x100, |
| 390 | 0xa208, 0xffffffff, 0x100, |
| 391 | 0xa20c, 0xffffffff, 0x100, |
| 392 | 0x971c, 0xffffffff, 0x100, |
| 393 | 0x915c, 0xffffffff, 0x00020001, |
| 394 | 0x9174, 0xffffffff, 0x00000003, |
| 395 | 0x9178, 0xffffffff, 0x00050001, |
| 396 | 0x917c, 0xffffffff, 0x00030002, |
| 397 | 0x918c, 0xffffffff, 0x00000004, |
| 398 | 0x9190, 0xffffffff, 0x00070006, |
| 399 | 0x9194, 0xffffffff, 0x00050001, |
| 400 | 0x9198, 0xffffffff, 0x00030002, |
| 401 | 0x91a8, 0xffffffff, 0x00000004, |
| 402 | 0x91ac, 0xffffffff, 0x00070006, |
| 403 | 0x91e8, 0xffffffff, 0x00000001, |
| 404 | 0x9294, 0xffffffff, 0x00000001, |
| 405 | 0x929c, 0xffffffff, 0x00000002, |
| 406 | 0x92a0, 0xffffffff, 0x00040003, |
| 407 | 0x9150, 0xffffffff, 0x4d940000 |
| 408 | }; |
| 409 | |
| 410 | static const u32 rv730_golden_registers[] = |
| 411 | { |
| 412 | 0x3f90, 0x00ff0000, 0x00f00000, |
| 413 | 0x9148, 0x00ff0000, 0x00f00000, |
| 414 | 0x3f94, 0x00ff0000, 0x00f00000, |
| 415 | 0x914c, 0x00ff0000, 0x00f00000, |
| 416 | 0x900c, 0xffffffff, 0x003b033f, |
| 417 | 0xb4c, 0x00000020, 0x00000020, |
| 418 | 0xa180, 0xffffffff, 0x00003f3f |
| 419 | }; |
| 420 | |
| 421 | static const u32 rv730_mgcg_init[] = |
| 422 | { |
| 423 | 0x8bcc, 0xffffffff, 0x130300f9, |
| 424 | 0x5448, 0xffffffff, 0x100, |
| 425 | 0x55e4, 0xffffffff, 0x100, |
| 426 | 0x160c, 0xffffffff, 0x100, |
| 427 | 0x5644, 0xffffffff, 0x100, |
| 428 | 0xc164, 0xffffffff, 0x100, |
| 429 | 0x8a18, 0xffffffff, 0x100, |
| 430 | 0x897c, 0xffffffff, 0x8000100, |
| 431 | 0x8b28, 0xffffffff, 0x3c000100, |
| 432 | 0x9144, 0xffffffff, 0x100, |
| 433 | 0x9a1c, 0xffffffff, 0x10000, |
| 434 | 0x9a50, 0xffffffff, 0x100, |
| 435 | 0x9a1c, 0xffffffff, 0x10001, |
| 436 | 0x9a50, 0xffffffff, 0x100, |
| 437 | 0x9a1c, 0xffffffff, 0x0, |
| 438 | 0x9870, 0xffffffff, 0x100, |
| 439 | 0x8d58, 0xffffffff, 0x100, |
| 440 | 0x9500, 0xffffffff, 0x0, |
| 441 | 0x9510, 0xffffffff, 0x100, |
| 442 | 0x9500, 0xffffffff, 0x1, |
| 443 | 0x9510, 0xffffffff, 0x100, |
| 444 | 0x9500, 0xffffffff, 0x2, |
| 445 | 0x9510, 0xffffffff, 0x100, |
| 446 | 0x9500, 0xffffffff, 0x3, |
| 447 | 0x9510, 0xffffffff, 0x100, |
| 448 | 0x9500, 0xffffffff, 0x4, |
| 449 | 0x9510, 0xffffffff, 0x100, |
| 450 | 0x9500, 0xffffffff, 0x5, |
| 451 | 0x9510, 0xffffffff, 0x100, |
| 452 | 0x9500, 0xffffffff, 0x6, |
| 453 | 0x9510, 0xffffffff, 0x100, |
| 454 | 0x9500, 0xffffffff, 0x7, |
| 455 | 0x9510, 0xffffffff, 0x100, |
| 456 | 0x9500, 0xffffffff, 0x8000, |
| 457 | 0x9490, 0xffffffff, 0x0, |
| 458 | 0x949c, 0xffffffff, 0x100, |
| 459 | 0x9490, 0xffffffff, 0x1, |
| 460 | 0x949c, 0xffffffff, 0x100, |
| 461 | 0x9490, 0xffffffff, 0x2, |
| 462 | 0x949c, 0xffffffff, 0x100, |
| 463 | 0x9490, 0xffffffff, 0x3, |
| 464 | 0x949c, 0xffffffff, 0x100, |
| 465 | 0x9490, 0xffffffff, 0x4, |
| 466 | 0x949c, 0xffffffff, 0x100, |
| 467 | 0x9490, 0xffffffff, 0x5, |
| 468 | 0x949c, 0xffffffff, 0x100, |
| 469 | 0x9490, 0xffffffff, 0x6, |
| 470 | 0x949c, 0xffffffff, 0x100, |
| 471 | 0x9490, 0xffffffff, 0x7, |
| 472 | 0x949c, 0xffffffff, 0x100, |
| 473 | 0x9490, 0xffffffff, 0x8000, |
| 474 | 0x9604, 0xffffffff, 0x0, |
| 475 | 0x9654, 0xffffffff, 0x100, |
| 476 | 0x9604, 0xffffffff, 0x1, |
| 477 | 0x9654, 0xffffffff, 0x100, |
| 478 | 0x9604, 0xffffffff, 0x2, |
| 479 | 0x9654, 0xffffffff, 0x100, |
| 480 | 0x9604, 0xffffffff, 0x3, |
| 481 | 0x9654, 0xffffffff, 0x100, |
| 482 | 0x9604, 0xffffffff, 0x4, |
| 483 | 0x9654, 0xffffffff, 0x100, |
| 484 | 0x9604, 0xffffffff, 0x5, |
| 485 | 0x9654, 0xffffffff, 0x100, |
| 486 | 0x9604, 0xffffffff, 0x6, |
| 487 | 0x9654, 0xffffffff, 0x100, |
| 488 | 0x9604, 0xffffffff, 0x7, |
| 489 | 0x9654, 0xffffffff, 0x100, |
| 490 | 0x9604, 0xffffffff, 0x80000000, |
| 491 | 0x9030, 0xffffffff, 0x100, |
| 492 | 0x9034, 0xffffffff, 0x100, |
| 493 | 0x9038, 0xffffffff, 0x100, |
| 494 | 0x903c, 0xffffffff, 0x100, |
| 495 | 0x9040, 0xffffffff, 0x100, |
| 496 | 0xa200, 0xffffffff, 0x100, |
| 497 | 0xa204, 0xffffffff, 0x100, |
| 498 | 0xa208, 0xffffffff, 0x100, |
| 499 | 0xa20c, 0xffffffff, 0x100, |
| 500 | 0x971c, 0xffffffff, 0x100, |
| 501 | 0x915c, 0xffffffff, 0x00020001, |
| 502 | 0x916c, 0xffffffff, 0x00040003, |
| 503 | 0x9170, 0xffffffff, 0x00000005, |
| 504 | 0x9178, 0xffffffff, 0x00050001, |
| 505 | 0x917c, 0xffffffff, 0x00030002, |
| 506 | 0x918c, 0xffffffff, 0x00000004, |
| 507 | 0x9190, 0xffffffff, 0x00070006, |
| 508 | 0x9194, 0xffffffff, 0x00050001, |
| 509 | 0x9198, 0xffffffff, 0x00030002, |
| 510 | 0x91a8, 0xffffffff, 0x00000004, |
| 511 | 0x91ac, 0xffffffff, 0x00070006, |
| 512 | 0x91b0, 0xffffffff, 0x00050001, |
| 513 | 0x91b4, 0xffffffff, 0x00030002, |
| 514 | 0x91c4, 0xffffffff, 0x00000004, |
| 515 | 0x91c8, 0xffffffff, 0x00070006, |
| 516 | 0x91cc, 0xffffffff, 0x00050001, |
| 517 | 0x91d0, 0xffffffff, 0x00030002, |
| 518 | 0x91e0, 0xffffffff, 0x00000004, |
| 519 | 0x91e4, 0xffffffff, 0x00070006, |
| 520 | 0x91e8, 0xffffffff, 0x00000001, |
| 521 | 0x91ec, 0xffffffff, 0x00050001, |
| 522 | 0x91f0, 0xffffffff, 0x00030002, |
| 523 | 0x9200, 0xffffffff, 0x00000004, |
| 524 | 0x9204, 0xffffffff, 0x00070006, |
| 525 | 0x9208, 0xffffffff, 0x00050001, |
| 526 | 0x920c, 0xffffffff, 0x00030002, |
| 527 | 0x921c, 0xffffffff, 0x00000004, |
| 528 | 0x9220, 0xffffffff, 0x00070006, |
| 529 | 0x9224, 0xffffffff, 0x00050001, |
| 530 | 0x9228, 0xffffffff, 0x00030002, |
| 531 | 0x9238, 0xffffffff, 0x00000004, |
| 532 | 0x923c, 0xffffffff, 0x00070006, |
| 533 | 0x9240, 0xffffffff, 0x00050001, |
| 534 | 0x9244, 0xffffffff, 0x00030002, |
| 535 | 0x9254, 0xffffffff, 0x00000004, |
| 536 | 0x9258, 0xffffffff, 0x00070006, |
| 537 | 0x9294, 0xffffffff, 0x00000001, |
| 538 | 0x929c, 0xffffffff, 0x00000002, |
| 539 | 0x92a0, 0xffffffff, 0x00040003, |
| 540 | 0x92a4, 0xffffffff, 0x00000005 |
| 541 | }; |
| 542 | |
| 543 | static const u32 rv740_golden_registers[] = |
| 544 | { |
| 545 | 0x88c4, 0xffffffff, 0x00000082, |
| 546 | 0x28a50, 0xfffffffc, 0x00000004, |
| 547 | 0x2650, 0x00040000, 0, |
| 548 | 0x20bc, 0x00040000, 0, |
| 549 | 0x733c, 0xffffffff, 0x00000002, |
| 550 | 0x7300, 0xffffffff, 0x001000f0, |
| 551 | 0x3f90, 0x00ff0000, 0, |
| 552 | 0x9148, 0x00ff0000, 0, |
| 553 | 0x3f94, 0x00ff0000, 0, |
| 554 | 0x914c, 0x00ff0000, 0, |
| 555 | 0x240c, 0xffffffff, 0x00000380, |
| 556 | 0x8a14, 0x00000007, 0x00000007, |
| 557 | 0x8b24, 0xffffffff, 0x00ff0fff, |
| 558 | 0x28a4c, 0xffffffff, 0x00004000, |
| 559 | 0xa180, 0xffffffff, 0x00003f3f, |
| 560 | 0x8d00, 0xffffffff, 0x0e0e003a, |
| 561 | 0x8d04, 0xffffffff, 0x013a0e2a, |
| 562 | 0x8c00, 0xffffffff, 0xe400000f, |
| 563 | 0x8db0, 0xffffffff, 0x98989898, |
| 564 | 0x8db4, 0xffffffff, 0x98989898, |
| 565 | 0x8db8, 0xffffffff, 0x98989898, |
| 566 | 0x8dbc, 0xffffffff, 0x98989898, |
| 567 | 0x8dc0, 0xffffffff, 0x98989898, |
| 568 | 0x8dc4, 0xffffffff, 0x98989898, |
| 569 | 0x8dc8, 0xffffffff, 0x98989898, |
| 570 | 0x8dcc, 0xffffffff, 0x98989898, |
| 571 | 0x9058, 0xffffffff, 0x0fffc40f, |
| 572 | 0x900c, 0xffffffff, 0x003b033f, |
| 573 | 0x28350, 0xffffffff, 0, |
| 574 | 0x8cf0, 0x1fffffff, 0x08e00420, |
| 575 | 0x9508, 0xffffffff, 0x00000002, |
| 576 | 0x88c4, 0xffffffff, 0x000000c2, |
| 577 | 0x9698, 0x18000000, 0x18000000 |
| 578 | }; |
| 579 | |
| 580 | static const u32 rv740_mgcg_init[] = |
| 581 | { |
| 582 | 0x8bcc, 0xffffffff, 0x13030100, |
| 583 | 0x5448, 0xffffffff, 0x100, |
| 584 | 0x55e4, 0xffffffff, 0x100, |
| 585 | 0x160c, 0xffffffff, 0x100, |
| 586 | 0x5644, 0xffffffff, 0x100, |
| 587 | 0xc164, 0xffffffff, 0x100, |
| 588 | 0x8a18, 0xffffffff, 0x100, |
| 589 | 0x897c, 0xffffffff, 0x100, |
| 590 | 0x8b28, 0xffffffff, 0x100, |
| 591 | 0x9144, 0xffffffff, 0x100, |
| 592 | 0x9a1c, 0xffffffff, 0x10000, |
| 593 | 0x9a50, 0xffffffff, 0x100, |
| 594 | 0x9a1c, 0xffffffff, 0x10001, |
| 595 | 0x9a50, 0xffffffff, 0x100, |
| 596 | 0x9a1c, 0xffffffff, 0x10002, |
| 597 | 0x9a50, 0xffffffff, 0x100, |
| 598 | 0x9a1c, 0xffffffff, 0x10003, |
| 599 | 0x9a50, 0xffffffff, 0x100, |
| 600 | 0x9a1c, 0xffffffff, 0x0, |
| 601 | 0x9870, 0xffffffff, 0x100, |
| 602 | 0x8d58, 0xffffffff, 0x100, |
| 603 | 0x9500, 0xffffffff, 0x0, |
| 604 | 0x9510, 0xffffffff, 0x100, |
| 605 | 0x9500, 0xffffffff, 0x1, |
| 606 | 0x9510, 0xffffffff, 0x100, |
| 607 | 0x9500, 0xffffffff, 0x2, |
| 608 | 0x9510, 0xffffffff, 0x100, |
| 609 | 0x9500, 0xffffffff, 0x3, |
| 610 | 0x9510, 0xffffffff, 0x100, |
| 611 | 0x9500, 0xffffffff, 0x4, |
| 612 | 0x9510, 0xffffffff, 0x100, |
| 613 | 0x9500, 0xffffffff, 0x5, |
| 614 | 0x9510, 0xffffffff, 0x100, |
| 615 | 0x9500, 0xffffffff, 0x6, |
| 616 | 0x9510, 0xffffffff, 0x100, |
| 617 | 0x9500, 0xffffffff, 0x7, |
| 618 | 0x9510, 0xffffffff, 0x100, |
| 619 | 0x9500, 0xffffffff, 0x8000, |
| 620 | 0x9490, 0xffffffff, 0x0, |
| 621 | 0x949c, 0xffffffff, 0x100, |
| 622 | 0x9490, 0xffffffff, 0x1, |
| 623 | 0x949c, 0xffffffff, 0x100, |
| 624 | 0x9490, 0xffffffff, 0x2, |
| 625 | 0x949c, 0xffffffff, 0x100, |
| 626 | 0x9490, 0xffffffff, 0x3, |
| 627 | 0x949c, 0xffffffff, 0x100, |
| 628 | 0x9490, 0xffffffff, 0x4, |
| 629 | 0x949c, 0xffffffff, 0x100, |
| 630 | 0x9490, 0xffffffff, 0x5, |
| 631 | 0x949c, 0xffffffff, 0x100, |
| 632 | 0x9490, 0xffffffff, 0x6, |
| 633 | 0x949c, 0xffffffff, 0x100, |
| 634 | 0x9490, 0xffffffff, 0x7, |
| 635 | 0x949c, 0xffffffff, 0x100, |
| 636 | 0x9490, 0xffffffff, 0x8000, |
| 637 | 0x9604, 0xffffffff, 0x0, |
| 638 | 0x9654, 0xffffffff, 0x100, |
| 639 | 0x9604, 0xffffffff, 0x1, |
| 640 | 0x9654, 0xffffffff, 0x100, |
| 641 | 0x9604, 0xffffffff, 0x2, |
| 642 | 0x9654, 0xffffffff, 0x100, |
| 643 | 0x9604, 0xffffffff, 0x3, |
| 644 | 0x9654, 0xffffffff, 0x100, |
| 645 | 0x9604, 0xffffffff, 0x4, |
| 646 | 0x9654, 0xffffffff, 0x100, |
| 647 | 0x9604, 0xffffffff, 0x5, |
| 648 | 0x9654, 0xffffffff, 0x100, |
| 649 | 0x9604, 0xffffffff, 0x6, |
| 650 | 0x9654, 0xffffffff, 0x100, |
| 651 | 0x9604, 0xffffffff, 0x7, |
| 652 | 0x9654, 0xffffffff, 0x100, |
| 653 | 0x9604, 0xffffffff, 0x80000000, |
| 654 | 0x9030, 0xffffffff, 0x100, |
| 655 | 0x9034, 0xffffffff, 0x100, |
| 656 | 0x9038, 0xffffffff, 0x100, |
| 657 | 0x903c, 0xffffffff, 0x100, |
| 658 | 0x9040, 0xffffffff, 0x100, |
| 659 | 0xa200, 0xffffffff, 0x100, |
| 660 | 0xa204, 0xffffffff, 0x100, |
| 661 | 0xa208, 0xffffffff, 0x100, |
| 662 | 0xa20c, 0xffffffff, 0x100, |
| 663 | 0x971c, 0xffffffff, 0x100, |
| 664 | 0x915c, 0xffffffff, 0x00020001, |
| 665 | 0x9160, 0xffffffff, 0x00040003, |
| 666 | 0x916c, 0xffffffff, 0x00060005, |
| 667 | 0x9170, 0xffffffff, 0x00080007, |
| 668 | 0x9174, 0xffffffff, 0x000a0009, |
| 669 | 0x9178, 0xffffffff, 0x000c000b, |
| 670 | 0x917c, 0xffffffff, 0x000e000d, |
| 671 | 0x9180, 0xffffffff, 0x0010000f, |
| 672 | 0x918c, 0xffffffff, 0x00120011, |
| 673 | 0x9190, 0xffffffff, 0x00140013, |
| 674 | 0x9194, 0xffffffff, 0x00020001, |
| 675 | 0x9198, 0xffffffff, 0x00040003, |
| 676 | 0x919c, 0xffffffff, 0x00060005, |
| 677 | 0x91a8, 0xffffffff, 0x00080007, |
| 678 | 0x91ac, 0xffffffff, 0x000a0009, |
| 679 | 0x91b0, 0xffffffff, 0x000c000b, |
| 680 | 0x91b4, 0xffffffff, 0x000e000d, |
| 681 | 0x91b8, 0xffffffff, 0x0010000f, |
| 682 | 0x91c4, 0xffffffff, 0x00120011, |
| 683 | 0x91c8, 0xffffffff, 0x00140013, |
| 684 | 0x91cc, 0xffffffff, 0x00020001, |
| 685 | 0x91d0, 0xffffffff, 0x00040003, |
| 686 | 0x91d4, 0xffffffff, 0x00060005, |
| 687 | 0x91e0, 0xffffffff, 0x00080007, |
| 688 | 0x91e4, 0xffffffff, 0x000a0009, |
| 689 | 0x91e8, 0xffffffff, 0x000c000b, |
| 690 | 0x91ec, 0xffffffff, 0x00020001, |
| 691 | 0x91f0, 0xffffffff, 0x00040003, |
| 692 | 0x91f4, 0xffffffff, 0x00060005, |
| 693 | 0x9200, 0xffffffff, 0x00080007, |
| 694 | 0x9204, 0xffffffff, 0x000a0009, |
| 695 | 0x9208, 0xffffffff, 0x000c000b, |
| 696 | 0x920c, 0xffffffff, 0x000e000d, |
| 697 | 0x9210, 0xffffffff, 0x0010000f, |
| 698 | 0x921c, 0xffffffff, 0x00120011, |
| 699 | 0x9220, 0xffffffff, 0x00140013, |
| 700 | 0x9224, 0xffffffff, 0x00020001, |
| 701 | 0x9228, 0xffffffff, 0x00040003, |
| 702 | 0x922c, 0xffffffff, 0x00060005, |
| 703 | 0x9238, 0xffffffff, 0x00080007, |
| 704 | 0x923c, 0xffffffff, 0x000a0009, |
| 705 | 0x9240, 0xffffffff, 0x000c000b, |
| 706 | 0x9244, 0xffffffff, 0x000e000d, |
| 707 | 0x9248, 0xffffffff, 0x0010000f, |
| 708 | 0x9254, 0xffffffff, 0x00120011, |
| 709 | 0x9258, 0xffffffff, 0x00140013, |
| 710 | 0x9294, 0xffffffff, 0x00020001, |
| 711 | 0x929c, 0xffffffff, 0x00040003, |
| 712 | 0x92a0, 0xffffffff, 0x00060005, |
| 713 | 0x92a4, 0xffffffff, 0x00080007 |
| 714 | }; |
| 715 | |
| 716 | static void rv770_init_golden_registers(struct radeon_device *rdev) |
| 717 | { |
| 718 | switch (rdev->family) { |
| 719 | case CHIP_RV770: |
| 720 | radeon_program_register_sequence(rdev, |
| 721 | r7xx_golden_registers, |
| 722 | (const u32)ARRAY_SIZE(r7xx_golden_registers)); |
| 723 | radeon_program_register_sequence(rdev, |
| 724 | r7xx_golden_dyn_gpr_registers, |
| 725 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
| 726 | if (rdev->pdev->device == 0x994e) |
| 727 | radeon_program_register_sequence(rdev, |
| 728 | rv770ce_golden_registers, |
| 729 | (const u32)ARRAY_SIZE(rv770ce_golden_registers)); |
| 730 | else |
| 731 | radeon_program_register_sequence(rdev, |
| 732 | rv770_golden_registers, |
| 733 | (const u32)ARRAY_SIZE(rv770_golden_registers)); |
| 734 | radeon_program_register_sequence(rdev, |
| 735 | rv770_mgcg_init, |
| 736 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); |
| 737 | break; |
| 738 | case CHIP_RV730: |
| 739 | radeon_program_register_sequence(rdev, |
| 740 | r7xx_golden_registers, |
| 741 | (const u32)ARRAY_SIZE(r7xx_golden_registers)); |
| 742 | radeon_program_register_sequence(rdev, |
| 743 | r7xx_golden_dyn_gpr_registers, |
| 744 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
| 745 | radeon_program_register_sequence(rdev, |
| 746 | rv730_golden_registers, |
Alex Deucher | 022374c0 | 2013-08-13 15:57:32 -0400 | [diff] [blame] | 747 | (const u32)ARRAY_SIZE(rv730_golden_registers)); |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 748 | radeon_program_register_sequence(rdev, |
| 749 | rv730_mgcg_init, |
Alex Deucher | 022374c0 | 2013-08-13 15:57:32 -0400 | [diff] [blame] | 750 | (const u32)ARRAY_SIZE(rv730_mgcg_init)); |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 751 | break; |
| 752 | case CHIP_RV710: |
| 753 | radeon_program_register_sequence(rdev, |
| 754 | r7xx_golden_registers, |
| 755 | (const u32)ARRAY_SIZE(r7xx_golden_registers)); |
| 756 | radeon_program_register_sequence(rdev, |
| 757 | r7xx_golden_dyn_gpr_registers, |
| 758 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
| 759 | radeon_program_register_sequence(rdev, |
| 760 | rv710_golden_registers, |
Alex Deucher | 022374c0 | 2013-08-13 15:57:32 -0400 | [diff] [blame] | 761 | (const u32)ARRAY_SIZE(rv710_golden_registers)); |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 762 | radeon_program_register_sequence(rdev, |
| 763 | rv710_mgcg_init, |
Alex Deucher | 022374c0 | 2013-08-13 15:57:32 -0400 | [diff] [blame] | 764 | (const u32)ARRAY_SIZE(rv710_mgcg_init)); |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 765 | break; |
| 766 | case CHIP_RV740: |
| 767 | radeon_program_register_sequence(rdev, |
| 768 | rv740_golden_registers, |
Alex Deucher | 022374c0 | 2013-08-13 15:57:32 -0400 | [diff] [blame] | 769 | (const u32)ARRAY_SIZE(rv740_golden_registers)); |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 770 | radeon_program_register_sequence(rdev, |
| 771 | rv740_mgcg_init, |
Alex Deucher | 022374c0 | 2013-08-13 15:57:32 -0400 | [diff] [blame] | 772 | (const u32)ARRAY_SIZE(rv740_mgcg_init)); |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 773 | break; |
| 774 | default: |
| 775 | break; |
| 776 | } |
| 777 | } |
| 778 | |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 779 | #define PCIE_BUS_CLK 10000 |
| 780 | #define TCLK (PCIE_BUS_CLK / 10) |
| 781 | |
| 782 | /** |
| 783 | * rv770_get_xclk - get the xclk |
| 784 | * |
| 785 | * @rdev: radeon_device pointer |
| 786 | * |
| 787 | * Returns the reference clock used by the gfx engine |
| 788 | * (r7xx-cayman). |
| 789 | */ |
| 790 | u32 rv770_get_xclk(struct radeon_device *rdev) |
| 791 | { |
| 792 | u32 reference_clock = rdev->clock.spll.reference_freq; |
| 793 | u32 tmp = RREG32(CG_CLKPIN_CNTL); |
| 794 | |
| 795 | if (tmp & MUX_TCLK_TO_XCLK) |
| 796 | return TCLK; |
| 797 | |
| 798 | if (tmp & XTALIN_DIVIDE) |
| 799 | return reference_clock / 4; |
| 800 | |
| 801 | return reference_clock; |
| 802 | } |
| 803 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 804 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
| 805 | { |
| 806 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
| 807 | u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); |
Alex Deucher | f649647 | 2011-11-28 14:49:26 -0500 | [diff] [blame] | 808 | int i; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 809 | |
| 810 | /* Lock the graphics update lock */ |
| 811 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
| 812 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
| 813 | |
| 814 | /* update the scanout addresses */ |
| 815 | if (radeon_crtc->crtc_id) { |
| 816 | WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
| 817 | WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
| 818 | } else { |
| 819 | WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
| 820 | WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
| 821 | } |
| 822 | WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 823 | (u32)crtc_base); |
| 824 | WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 825 | (u32)crtc_base); |
| 826 | |
| 827 | /* Wait for update_pending to go high. */ |
Alex Deucher | f649647 | 2011-11-28 14:49:26 -0500 | [diff] [blame] | 828 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 829 | if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) |
| 830 | break; |
| 831 | udelay(1); |
| 832 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 833 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
| 834 | |
| 835 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
| 836 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
| 837 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
| 838 | |
| 839 | /* Return current update_pending status: */ |
| 840 | return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; |
| 841 | } |
| 842 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 843 | /* get temperature in millidegrees */ |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 844 | int rv770_get_temp(struct radeon_device *rdev) |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 845 | { |
| 846 | u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> |
| 847 | ASIC_T_SHIFT; |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 848 | int actual_temp; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 849 | |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 850 | if (temp & 0x400) |
| 851 | actual_temp = -256; |
| 852 | else if (temp & 0x200) |
| 853 | actual_temp = 255; |
| 854 | else if (temp & 0x100) { |
| 855 | actual_temp = temp & 0x1ff; |
| 856 | actual_temp |= ~0x1ff; |
| 857 | } else |
| 858 | actual_temp = temp & 0xff; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 859 | |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 860 | return (actual_temp * 1000) / 2; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 861 | } |
| 862 | |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 863 | void rv770_pm_misc(struct radeon_device *rdev) |
| 864 | { |
Rafał Miłecki | a081a9d | 2010-06-07 18:20:25 -0400 | [diff] [blame] | 865 | int req_ps_idx = rdev->pm.requested_power_state_index; |
| 866 | int req_cm_idx = rdev->pm.requested_clock_mode_index; |
| 867 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; |
| 868 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 869 | |
| 870 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
Alex Deucher | a377e18 | 2011-06-20 13:00:31 -0400 | [diff] [blame] | 871 | /* 0xff01 is a flag rather then an actual voltage */ |
| 872 | if (voltage->voltage == 0xff01) |
| 873 | return; |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 874 | if (voltage->voltage != rdev->pm.current_vddc) { |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 875 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 876 | rdev->pm.current_vddc = voltage->voltage; |
Rafał Miłecki | 0fcbe94 | 2010-06-07 18:25:21 -0400 | [diff] [blame] | 877 | DRM_DEBUG("Setting: v: %d\n", voltage->voltage); |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 878 | } |
| 879 | } |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 880 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 881 | |
| 882 | /* |
| 883 | * GART |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 884 | */ |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 885 | static int rv770_pcie_gart_enable(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 886 | { |
| 887 | u32 tmp; |
| 888 | int r, i; |
| 889 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 890 | if (rdev->gart.robj == NULL) { |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 891 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 892 | return -EINVAL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 893 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 894 | r = radeon_gart_table_vram_pin(rdev); |
| 895 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 896 | return r; |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 897 | radeon_gart_restore(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 898 | /* Setup L2 cache */ |
| 899 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 900 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 901 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 902 | WREG32(VM_L2_CNTL2, 0); |
| 903 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
| 904 | /* Setup TLB control */ |
| 905 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| 906 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 907 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
| 908 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
| 909 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
| 910 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
| 911 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
Alex Deucher | 0b8c30b | 2012-05-31 18:54:43 -0400 | [diff] [blame] | 912 | if (rdev->family == CHIP_RV740) |
| 913 | WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 914 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
| 915 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
| 916 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
| 917 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
| 918 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 919 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 920 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
| 921 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
| 922 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
| 923 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
| 924 | (u32)(rdev->dummy_page.addr >> 12)); |
| 925 | for (i = 1; i < 7; i++) |
| 926 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 927 | |
| 928 | r600_pcie_gart_tlb_flush(rdev); |
Tormod Volden | fcf4de5 | 2011-08-31 21:54:07 +0000 | [diff] [blame] | 929 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 930 | (unsigned)(rdev->mc.gtt_size >> 20), |
| 931 | (unsigned long long)rdev->gart.table_addr); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 932 | rdev->gart.ready = true; |
| 933 | return 0; |
| 934 | } |
| 935 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 936 | static void rv770_pcie_gart_disable(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 937 | { |
| 938 | u32 tmp; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 939 | int i; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 940 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 941 | /* Disable all tables */ |
| 942 | for (i = 0; i < 7; i++) |
| 943 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 944 | |
| 945 | /* Setup L2 cache */ |
| 946 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
| 947 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 948 | WREG32(VM_L2_CNTL2, 0); |
| 949 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
| 950 | /* Setup TLB control */ |
| 951 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
| 952 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
| 953 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
| 954 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
| 955 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
| 956 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
| 957 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
| 958 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 959 | radeon_gart_table_vram_unpin(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 960 | } |
| 961 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 962 | static void rv770_pcie_gart_fini(struct radeon_device *rdev) |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 963 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 964 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 965 | rv770_pcie_gart_disable(rdev); |
| 966 | radeon_gart_table_vram_free(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 967 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 968 | |
| 969 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 970 | static void rv770_agp_enable(struct radeon_device *rdev) |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 971 | { |
| 972 | u32 tmp; |
| 973 | int i; |
| 974 | |
| 975 | /* Setup L2 cache */ |
| 976 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 977 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 978 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 979 | WREG32(VM_L2_CNTL2, 0); |
| 980 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
| 981 | /* Setup TLB control */ |
| 982 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| 983 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 984 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
| 985 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
| 986 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
| 987 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
| 988 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
| 989 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
| 990 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
| 991 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
| 992 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
| 993 | for (i = 0; i < 7; i++) |
| 994 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 995 | } |
| 996 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 997 | static void rv770_mc_program(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 998 | { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 999 | struct rv515_mc_save save; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1000 | u32 tmp; |
| 1001 | int i, j; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1002 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1003 | /* Initialize HDP */ |
| 1004 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| 1005 | WREG32((0x2c14 + j), 0x00000000); |
| 1006 | WREG32((0x2c18 + j), 0x00000000); |
| 1007 | WREG32((0x2c1c + j), 0x00000000); |
| 1008 | WREG32((0x2c20 + j), 0x00000000); |
| 1009 | WREG32((0x2c24 + j), 0x00000000); |
| 1010 | } |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 1011 | /* r7xx hw bug. Read from HDP_DEBUG1 rather |
| 1012 | * than writing to HDP_REG_COHERENCY_FLUSH_CNTL |
| 1013 | */ |
| 1014 | tmp = RREG32(HDP_DEBUG1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1015 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1016 | rv515_mc_stop(rdev, &save); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1017 | if (r600_mc_wait_for_idle(rdev)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1018 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1019 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1020 | /* Lockout access through VGA aperture*/ |
| 1021 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1022 | /* Update configuration */ |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1023 | if (rdev->flags & RADEON_IS_AGP) { |
| 1024 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
| 1025 | /* VRAM before AGP */ |
| 1026 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 1027 | rdev->mc.vram_start >> 12); |
| 1028 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 1029 | rdev->mc.gtt_end >> 12); |
| 1030 | } else { |
| 1031 | /* VRAM after AGP */ |
| 1032 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 1033 | rdev->mc.gtt_start >> 12); |
| 1034 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 1035 | rdev->mc.vram_end >> 12); |
| 1036 | } |
| 1037 | } else { |
| 1038 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 1039 | rdev->mc.vram_start >> 12); |
| 1040 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 1041 | rdev->mc.vram_end >> 12); |
| 1042 | } |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1043 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1044 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1045 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
| 1046 | WREG32(MC_VM_FB_LOCATION, tmp); |
| 1047 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
| 1048 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
Jerome Glisse | 46fcd2b | 2010-06-03 19:34:48 +0200 | [diff] [blame] | 1049 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1050 | if (rdev->flags & RADEON_IS_AGP) { |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1051 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1052 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
| 1053 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
| 1054 | } else { |
| 1055 | WREG32(MC_VM_AGP_BASE, 0); |
| 1056 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
| 1057 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
| 1058 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1059 | if (r600_mc_wait_for_idle(rdev)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1060 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1061 | } |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1062 | rv515_mc_resume(rdev, &save); |
Dave Airlie | 698443d | 2009-09-18 14:16:38 +1000 | [diff] [blame] | 1063 | /* we need to own VRAM, so turn off the VGA renderer here |
| 1064 | * to stop it overwriting our objects */ |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1065 | rv515_vga_render_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1066 | } |
| 1067 | |
| 1068 | |
| 1069 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1070 | * CP. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1071 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1072 | void r700_cp_stop(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1073 | { |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 1074 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1075 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1076 | WREG32(SCRATCH_UMSK, 0); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1077 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1078 | } |
| 1079 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1080 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1081 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1082 | const __be32 *fw_data; |
| 1083 | int i; |
| 1084 | |
| 1085 | if (!rdev->me_fw || !rdev->pfp_fw) |
| 1086 | return -EINVAL; |
| 1087 | |
| 1088 | r700_cp_stop(rdev); |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 1089 | WREG32(CP_RB_CNTL, |
| 1090 | #ifdef __BIG_ENDIAN |
| 1091 | BUF_SWAP_32BIT | |
| 1092 | #endif |
| 1093 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1094 | |
| 1095 | /* Reset cp */ |
| 1096 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
| 1097 | RREG32(GRBM_SOFT_RESET); |
| 1098 | mdelay(15); |
| 1099 | WREG32(GRBM_SOFT_RESET, 0); |
| 1100 | |
| 1101 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
| 1102 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 1103 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) |
| 1104 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 1105 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 1106 | |
| 1107 | fw_data = (const __be32 *)rdev->me_fw->data; |
| 1108 | WREG32(CP_ME_RAM_WADDR, 0); |
| 1109 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) |
| 1110 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
| 1111 | |
| 1112 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 1113 | WREG32(CP_ME_RAM_WADDR, 0); |
| 1114 | WREG32(CP_ME_RAM_RADDR, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1115 | return 0; |
| 1116 | } |
| 1117 | |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1118 | void r700_cp_fini(struct radeon_device *rdev) |
| 1119 | { |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 1120 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1121 | r700_cp_stop(rdev); |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 1122 | radeon_ring_fini(rdev, ring); |
| 1123 | radeon_scratch_free(rdev, ring->rptr_save_reg); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1124 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1125 | |
| 1126 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1127 | * Core functions |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1128 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1129 | static void rv770_gpu_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1130 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1131 | int i, j, num_qd_pipes; |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1132 | u32 ta_aux_cntl; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1133 | u32 sx_debug_1; |
| 1134 | u32 smx_dc_ctl0; |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1135 | u32 db_debug3; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1136 | u32 num_gs_verts_per_thread; |
| 1137 | u32 vgt_gs_per_es; |
| 1138 | u32 gs_prim_buffer_depth = 0; |
| 1139 | u32 sq_ms_fifo_sizes; |
| 1140 | u32 sq_config; |
| 1141 | u32 sq_thread_resource_mgmt; |
| 1142 | u32 hdp_host_path_cntl; |
| 1143 | u32 sq_dyn_gpr_size_simd_ab_0; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1144 | u32 gb_tiling_config = 0; |
| 1145 | u32 cc_rb_backend_disable = 0; |
| 1146 | u32 cc_gc_shader_pipe_config = 0; |
| 1147 | u32 mc_arb_ramcfg; |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1148 | u32 db_debug4, tmp; |
| 1149 | u32 inactive_pipes, shader_pipe_config; |
| 1150 | u32 disabled_rb_mask; |
| 1151 | unsigned active_number; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1152 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1153 | /* setup chip specs */ |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1154 | rdev->config.rv770.tiling_group_size = 256; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1155 | switch (rdev->family) { |
| 1156 | case CHIP_RV770: |
| 1157 | rdev->config.rv770.max_pipes = 4; |
| 1158 | rdev->config.rv770.max_tile_pipes = 8; |
| 1159 | rdev->config.rv770.max_simds = 10; |
| 1160 | rdev->config.rv770.max_backends = 4; |
| 1161 | rdev->config.rv770.max_gprs = 256; |
| 1162 | rdev->config.rv770.max_threads = 248; |
| 1163 | rdev->config.rv770.max_stack_entries = 512; |
| 1164 | rdev->config.rv770.max_hw_contexts = 8; |
| 1165 | rdev->config.rv770.max_gs_threads = 16 * 2; |
| 1166 | rdev->config.rv770.sx_max_export_size = 128; |
| 1167 | rdev->config.rv770.sx_max_export_pos_size = 16; |
| 1168 | rdev->config.rv770.sx_max_export_smx_size = 112; |
| 1169 | rdev->config.rv770.sq_num_cf_insts = 2; |
| 1170 | |
| 1171 | rdev->config.rv770.sx_num_of_sets = 7; |
| 1172 | rdev->config.rv770.sc_prim_fifo_size = 0xF9; |
| 1173 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
| 1174 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
| 1175 | break; |
| 1176 | case CHIP_RV730: |
| 1177 | rdev->config.rv770.max_pipes = 2; |
| 1178 | rdev->config.rv770.max_tile_pipes = 4; |
| 1179 | rdev->config.rv770.max_simds = 8; |
| 1180 | rdev->config.rv770.max_backends = 2; |
| 1181 | rdev->config.rv770.max_gprs = 128; |
| 1182 | rdev->config.rv770.max_threads = 248; |
| 1183 | rdev->config.rv770.max_stack_entries = 256; |
| 1184 | rdev->config.rv770.max_hw_contexts = 8; |
| 1185 | rdev->config.rv770.max_gs_threads = 16 * 2; |
| 1186 | rdev->config.rv770.sx_max_export_size = 256; |
| 1187 | rdev->config.rv770.sx_max_export_pos_size = 32; |
| 1188 | rdev->config.rv770.sx_max_export_smx_size = 224; |
| 1189 | rdev->config.rv770.sq_num_cf_insts = 2; |
| 1190 | |
| 1191 | rdev->config.rv770.sx_num_of_sets = 7; |
| 1192 | rdev->config.rv770.sc_prim_fifo_size = 0xf9; |
| 1193 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
| 1194 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
| 1195 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
| 1196 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
| 1197 | rdev->config.rv770.sx_max_export_smx_size += 16; |
| 1198 | } |
| 1199 | break; |
| 1200 | case CHIP_RV710: |
| 1201 | rdev->config.rv770.max_pipes = 2; |
| 1202 | rdev->config.rv770.max_tile_pipes = 2; |
| 1203 | rdev->config.rv770.max_simds = 2; |
| 1204 | rdev->config.rv770.max_backends = 1; |
| 1205 | rdev->config.rv770.max_gprs = 256; |
| 1206 | rdev->config.rv770.max_threads = 192; |
| 1207 | rdev->config.rv770.max_stack_entries = 256; |
| 1208 | rdev->config.rv770.max_hw_contexts = 4; |
| 1209 | rdev->config.rv770.max_gs_threads = 8 * 2; |
| 1210 | rdev->config.rv770.sx_max_export_size = 128; |
| 1211 | rdev->config.rv770.sx_max_export_pos_size = 16; |
| 1212 | rdev->config.rv770.sx_max_export_smx_size = 112; |
| 1213 | rdev->config.rv770.sq_num_cf_insts = 1; |
| 1214 | |
| 1215 | rdev->config.rv770.sx_num_of_sets = 7; |
| 1216 | rdev->config.rv770.sc_prim_fifo_size = 0x40; |
| 1217 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
| 1218 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
| 1219 | break; |
| 1220 | case CHIP_RV740: |
| 1221 | rdev->config.rv770.max_pipes = 4; |
| 1222 | rdev->config.rv770.max_tile_pipes = 4; |
| 1223 | rdev->config.rv770.max_simds = 8; |
| 1224 | rdev->config.rv770.max_backends = 4; |
| 1225 | rdev->config.rv770.max_gprs = 256; |
| 1226 | rdev->config.rv770.max_threads = 248; |
| 1227 | rdev->config.rv770.max_stack_entries = 512; |
| 1228 | rdev->config.rv770.max_hw_contexts = 8; |
| 1229 | rdev->config.rv770.max_gs_threads = 16 * 2; |
| 1230 | rdev->config.rv770.sx_max_export_size = 256; |
| 1231 | rdev->config.rv770.sx_max_export_pos_size = 32; |
| 1232 | rdev->config.rv770.sx_max_export_smx_size = 224; |
| 1233 | rdev->config.rv770.sq_num_cf_insts = 2; |
| 1234 | |
| 1235 | rdev->config.rv770.sx_num_of_sets = 7; |
| 1236 | rdev->config.rv770.sc_prim_fifo_size = 0x100; |
| 1237 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
| 1238 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
| 1239 | |
| 1240 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
| 1241 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
| 1242 | rdev->config.rv770.sx_max_export_smx_size += 16; |
| 1243 | } |
| 1244 | break; |
| 1245 | default: |
| 1246 | break; |
| 1247 | } |
| 1248 | |
| 1249 | /* Initialize HDP */ |
| 1250 | j = 0; |
| 1251 | for (i = 0; i < 32; i++) { |
| 1252 | WREG32((0x2c14 + j), 0x00000000); |
| 1253 | WREG32((0x2c18 + j), 0x00000000); |
| 1254 | WREG32((0x2c1c + j), 0x00000000); |
| 1255 | WREG32((0x2c20 + j), 0x00000000); |
| 1256 | WREG32((0x2c24 + j), 0x00000000); |
| 1257 | j += 0x18; |
| 1258 | } |
| 1259 | |
| 1260 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
| 1261 | |
| 1262 | /* setup tiling, simd, pipe config */ |
| 1263 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
| 1264 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1265 | shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); |
| 1266 | inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT; |
| 1267 | for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) { |
| 1268 | if (!(inactive_pipes & tmp)) { |
| 1269 | active_number++; |
| 1270 | } |
| 1271 | tmp <<= 1; |
| 1272 | } |
| 1273 | if (active_number == 1) { |
| 1274 | WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); |
| 1275 | } else { |
| 1276 | WREG32(SPI_CONFIG_CNTL, 0); |
| 1277 | } |
| 1278 | |
| 1279 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
| 1280 | tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16); |
| 1281 | if (tmp < rdev->config.rv770.max_backends) { |
| 1282 | rdev->config.rv770.max_backends = tmp; |
| 1283 | } |
| 1284 | |
| 1285 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
| 1286 | tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK); |
| 1287 | if (tmp < rdev->config.rv770.max_pipes) { |
| 1288 | rdev->config.rv770.max_pipes = tmp; |
| 1289 | } |
| 1290 | tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK); |
| 1291 | if (tmp < rdev->config.rv770.max_simds) { |
| 1292 | rdev->config.rv770.max_simds = tmp; |
| 1293 | } |
| 1294 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1295 | switch (rdev->config.rv770.max_tile_pipes) { |
| 1296 | case 1: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1297 | default: |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1298 | gb_tiling_config = PIPE_TILING(0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1299 | break; |
| 1300 | case 2: |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1301 | gb_tiling_config = PIPE_TILING(1); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1302 | break; |
| 1303 | case 4: |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1304 | gb_tiling_config = PIPE_TILING(2); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1305 | break; |
| 1306 | case 8: |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1307 | gb_tiling_config = PIPE_TILING(3); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1308 | break; |
| 1309 | } |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1310 | rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1311 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1312 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK; |
| 1313 | tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
| 1314 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, |
| 1315 | R7XX_MAX_BACKENDS, disabled_rb_mask); |
| 1316 | gb_tiling_config |= tmp << 16; |
| 1317 | rdev->config.rv770.backend_map = tmp; |
| 1318 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1319 | if (rdev->family == CHIP_RV770) |
| 1320 | gb_tiling_config |= BANK_TILING(1); |
Alex Deucher | 29d6540 | 2012-05-31 18:53:36 -0400 | [diff] [blame] | 1321 | else { |
| 1322 | if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) |
| 1323 | gb_tiling_config |= BANK_TILING(1); |
| 1324 | else |
| 1325 | gb_tiling_config |= BANK_TILING(0); |
| 1326 | } |
Jerome Glisse | 961fb59 | 2010-02-10 22:30:05 +0000 | [diff] [blame] | 1327 | rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); |
Alex Deucher | 881fe6c | 2010-10-18 23:54:56 -0400 | [diff] [blame] | 1328 | gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 1329 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1330 | gb_tiling_config |= ROW_TILING(3); |
| 1331 | gb_tiling_config |= SAMPLE_SPLIT(3); |
| 1332 | } else { |
| 1333 | gb_tiling_config |= |
| 1334 | ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
| 1335 | gb_tiling_config |= |
| 1336 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
| 1337 | } |
| 1338 | |
| 1339 | gb_tiling_config |= BANK_SWAPS(1); |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1340 | rdev->config.rv770.tile_config = gb_tiling_config; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1341 | |
| 1342 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
| 1343 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| 1344 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1345 | WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| 1346 | WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); |
Christian König | 9a21059 | 2013-04-08 12:41:37 +0200 | [diff] [blame] | 1347 | if (rdev->family == CHIP_RV730) { |
| 1348 | WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| 1349 | WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| 1350 | WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| 1351 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1352 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1353 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
| 1354 | WREG32(CGTS_TCC_DISABLE, 0); |
Alex Deucher | f867c60d | 2010-03-05 14:50:37 -0500 | [diff] [blame] | 1355 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
| 1356 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1357 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1358 | |
| 1359 | num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1360 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
| 1361 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
| 1362 | |
| 1363 | /* set HW defaults for 3D engine */ |
| 1364 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 1365 | ROQ_IB2_START(0x2b))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1366 | |
| 1367 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
| 1368 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1369 | ta_aux_cntl = RREG32(TA_CNTL_AUX); |
| 1370 | WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1371 | |
| 1372 | sx_debug_1 = RREG32(SX_DEBUG_1); |
| 1373 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
| 1374 | WREG32(SX_DEBUG_1, sx_debug_1); |
| 1375 | |
| 1376 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
| 1377 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
| 1378 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
| 1379 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
| 1380 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1381 | if (rdev->family != CHIP_RV740) |
| 1382 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | |
| 1383 | GS_FLUSH_CTL(4) | |
| 1384 | ACK_FLUSH_CTL(3) | |
| 1385 | SYNC_FLUSH_CTL)); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1386 | |
Alex Deucher | b866d13 | 2012-06-14 22:06:36 +0200 | [diff] [blame] | 1387 | if (rdev->family != CHIP_RV770) |
| 1388 | WREG32(SMX_SAR_CTL0, 0x00003f3f); |
| 1389 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1390 | db_debug3 = RREG32(DB_DEBUG3); |
| 1391 | db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); |
| 1392 | switch (rdev->family) { |
| 1393 | case CHIP_RV770: |
| 1394 | case CHIP_RV740: |
| 1395 | db_debug3 |= DB_CLK_OFF_DELAY(0x1f); |
| 1396 | break; |
| 1397 | case CHIP_RV710: |
| 1398 | case CHIP_RV730: |
| 1399 | default: |
| 1400 | db_debug3 |= DB_CLK_OFF_DELAY(2); |
| 1401 | break; |
| 1402 | } |
| 1403 | WREG32(DB_DEBUG3, db_debug3); |
| 1404 | |
| 1405 | if (rdev->family != CHIP_RV770) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1406 | db_debug4 = RREG32(DB_DEBUG4); |
| 1407 | db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; |
| 1408 | WREG32(DB_DEBUG4, db_debug4); |
| 1409 | } |
| 1410 | |
| 1411 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 1412 | POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | |
| 1413 | SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1414 | |
| 1415 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | |
Alex Deucher | e29649d | 2009-11-03 10:04:01 -0500 | [diff] [blame] | 1416 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | |
| 1417 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1418 | |
| 1419 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| 1420 | |
| 1421 | WREG32(VGT_NUM_INSTANCES, 1); |
| 1422 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1423 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
| 1424 | |
| 1425 | WREG32(CP_PERFMON_CNTL, 0); |
| 1426 | |
| 1427 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
| 1428 | DONE_FIFO_HIWATER(0xe0) | |
| 1429 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
| 1430 | switch (rdev->family) { |
| 1431 | case CHIP_RV770: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1432 | case CHIP_RV730: |
| 1433 | case CHIP_RV710: |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1434 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
| 1435 | break; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1436 | case CHIP_RV740: |
| 1437 | default: |
| 1438 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
| 1439 | break; |
| 1440 | } |
| 1441 | WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); |
| 1442 | |
| 1443 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
| 1444 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
| 1445 | */ |
| 1446 | sq_config = RREG32(SQ_CONFIG); |
| 1447 | sq_config &= ~(PS_PRIO(3) | |
| 1448 | VS_PRIO(3) | |
| 1449 | GS_PRIO(3) | |
| 1450 | ES_PRIO(3)); |
| 1451 | sq_config |= (DX9_CONSTS | |
| 1452 | VC_ENABLE | |
| 1453 | EXPORT_SRC_C | |
| 1454 | PS_PRIO(0) | |
| 1455 | VS_PRIO(1) | |
| 1456 | GS_PRIO(2) | |
| 1457 | ES_PRIO(3)); |
| 1458 | if (rdev->family == CHIP_RV710) |
| 1459 | /* no vertex cache */ |
| 1460 | sq_config &= ~VC_ENABLE; |
| 1461 | |
| 1462 | WREG32(SQ_CONFIG, sq_config); |
| 1463 | |
| 1464 | WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 1465 | NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
| 1466 | NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1467 | |
| 1468 | WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 1469 | NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1470 | |
| 1471 | sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | |
| 1472 | NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | |
| 1473 | NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); |
| 1474 | if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) |
| 1475 | sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); |
| 1476 | else |
| 1477 | sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); |
| 1478 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
| 1479 | |
| 1480 | WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
| 1481 | NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
| 1482 | |
| 1483 | WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
| 1484 | NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
| 1485 | |
| 1486 | sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
| 1487 | SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | |
| 1488 | SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
| 1489 | SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); |
| 1490 | |
| 1491 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); |
| 1492 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); |
| 1493 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); |
| 1494 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); |
| 1495 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); |
| 1496 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); |
| 1497 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); |
| 1498 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); |
| 1499 | |
| 1500 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 1501 | FORCE_EOV_MAX_REZ_CNT(255))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1502 | |
| 1503 | if (rdev->family == CHIP_RV710) |
| 1504 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 1505 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1506 | else |
| 1507 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | |
Dave Airlie | fe62e1a | 2009-09-21 14:06:30 +1000 | [diff] [blame] | 1508 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1509 | |
| 1510 | switch (rdev->family) { |
| 1511 | case CHIP_RV770: |
| 1512 | case CHIP_RV730: |
| 1513 | case CHIP_RV740: |
| 1514 | gs_prim_buffer_depth = 384; |
| 1515 | break; |
| 1516 | case CHIP_RV710: |
| 1517 | gs_prim_buffer_depth = 128; |
| 1518 | break; |
| 1519 | default: |
| 1520 | break; |
| 1521 | } |
| 1522 | |
| 1523 | num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; |
| 1524 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; |
| 1525 | /* Max value for this is 256 */ |
| 1526 | if (vgt_gs_per_es > 256) |
| 1527 | vgt_gs_per_es = 256; |
| 1528 | |
| 1529 | WREG32(VGT_ES_PER_GS, 128); |
| 1530 | WREG32(VGT_GS_PER_ES, vgt_gs_per_es); |
| 1531 | WREG32(VGT_GS_PER_VS, 2); |
| 1532 | |
| 1533 | /* more default values. 2D/3D driver should adjust as needed */ |
| 1534 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
| 1535 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
| 1536 | WREG32(VGT_STRMOUT_EN, 0); |
| 1537 | WREG32(SX_MISC, 0); |
| 1538 | WREG32(PA_SC_MODE_CNTL, 0); |
| 1539 | WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); |
| 1540 | WREG32(PA_SC_AA_CONFIG, 0); |
| 1541 | WREG32(PA_SC_CLIPRECT_RULE, 0xffff); |
| 1542 | WREG32(PA_SC_LINE_STIPPLE, 0); |
| 1543 | WREG32(SPI_INPUT_Z, 0); |
| 1544 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
| 1545 | WREG32(CB_COLOR7_FRAG, 0); |
| 1546 | |
| 1547 | /* clear render buffer base addresses */ |
| 1548 | WREG32(CB_COLOR0_BASE, 0); |
| 1549 | WREG32(CB_COLOR1_BASE, 0); |
| 1550 | WREG32(CB_COLOR2_BASE, 0); |
| 1551 | WREG32(CB_COLOR3_BASE, 0); |
| 1552 | WREG32(CB_COLOR4_BASE, 0); |
| 1553 | WREG32(CB_COLOR5_BASE, 0); |
| 1554 | WREG32(CB_COLOR6_BASE, 0); |
| 1555 | WREG32(CB_COLOR7_BASE, 0); |
| 1556 | |
| 1557 | WREG32(TCP_CNTL, 0); |
| 1558 | |
| 1559 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
| 1560 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
| 1561 | |
| 1562 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| 1563 | |
| 1564 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
| 1565 | NUM_CLIP_SEQ(3))); |
Alex Deucher | b866d13 | 2012-06-14 22:06:36 +0200 | [diff] [blame] | 1566 | WREG32(VC_ENHANCE, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1567 | } |
| 1568 | |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1569 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
| 1570 | { |
| 1571 | u64 size_bf, size_af; |
| 1572 | |
| 1573 | if (mc->mc_vram_size > 0xE0000000) { |
| 1574 | /* leave room for at least 512M GTT */ |
| 1575 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1576 | mc->real_vram_size = 0xE0000000; |
| 1577 | mc->mc_vram_size = 0xE0000000; |
| 1578 | } |
| 1579 | if (rdev->flags & RADEON_IS_AGP) { |
| 1580 | size_bf = mc->gtt_start; |
Alex Deucher | 9ed8b1f | 2013-04-08 11:13:01 -0400 | [diff] [blame] | 1581 | size_af = mc->mc_mask - mc->gtt_end; |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1582 | if (size_bf > size_af) { |
| 1583 | if (mc->mc_vram_size > size_bf) { |
| 1584 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1585 | mc->real_vram_size = size_bf; |
| 1586 | mc->mc_vram_size = size_bf; |
| 1587 | } |
| 1588 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; |
| 1589 | } else { |
| 1590 | if (mc->mc_vram_size > size_af) { |
| 1591 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1592 | mc->real_vram_size = size_af; |
| 1593 | mc->mc_vram_size = size_af; |
| 1594 | } |
Jerome Glisse | dfc6ae5 | 2012-04-17 16:51:38 -0400 | [diff] [blame] | 1595 | mc->vram_start = mc->gtt_end + 1; |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1596 | } |
| 1597 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
| 1598 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
| 1599 | mc->mc_vram_size >> 20, mc->vram_start, |
| 1600 | mc->vram_end, mc->real_vram_size >> 20); |
| 1601 | } else { |
Alex Deucher | b4183e3 | 2010-12-15 11:04:10 -0500 | [diff] [blame] | 1602 | radeon_vram_location(rdev, &rdev->mc, 0); |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1603 | rdev->mc.gtt_base_align = 0; |
| 1604 | radeon_gtt_location(rdev, mc); |
| 1605 | } |
| 1606 | } |
| 1607 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 1608 | static int rv770_mc_init(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1609 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1610 | u32 tmp; |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1611 | int chansize, numchan; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1612 | |
| 1613 | /* Get VRAM informations */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1614 | rdev->mc.vram_is_ddr = true; |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1615 | tmp = RREG32(MC_ARB_RAMCFG); |
| 1616 | if (tmp & CHANSIZE_OVERRIDE) { |
| 1617 | chansize = 16; |
| 1618 | } else if (tmp & CHANSIZE_MASK) { |
| 1619 | chansize = 64; |
| 1620 | } else { |
| 1621 | chansize = 32; |
| 1622 | } |
| 1623 | tmp = RREG32(MC_SHARED_CHMAP); |
| 1624 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
| 1625 | case 0: |
| 1626 | default: |
| 1627 | numchan = 1; |
| 1628 | break; |
| 1629 | case 1: |
| 1630 | numchan = 2; |
| 1631 | break; |
| 1632 | case 2: |
| 1633 | numchan = 4; |
| 1634 | break; |
| 1635 | case 3: |
| 1636 | numchan = 8; |
| 1637 | break; |
| 1638 | } |
| 1639 | rdev->mc.vram_width = numchan * chansize; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1640 | /* Could aper size report 0 ? */ |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 1641 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 1642 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1643 | /* Setup GPU memory space */ |
| 1644 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
| 1645 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 1646 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1647 | r700_vram_gtt_location(rdev, &rdev->mc); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1648 | radeon_update_bandwidth_info(rdev); |
| 1649 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1650 | return 0; |
| 1651 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1652 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1653 | static int rv770_startup(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1654 | { |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1655 | struct radeon_ring *ring; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1656 | int r; |
| 1657 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1658 | /* enable pcie gen2 link */ |
| 1659 | rv770_pcie_gen2_enable(rdev); |
| 1660 | |
Alex Deucher | 6fab3feb | 2013-08-04 12:13:17 -0400 | [diff] [blame] | 1661 | rv770_mc_program(rdev); |
| 1662 | |
Alex Deucher | 779720a | 2009-12-09 19:31:44 -0500 | [diff] [blame] | 1663 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
| 1664 | r = r600_init_microcode(rdev); |
| 1665 | if (r) { |
| 1666 | DRM_ERROR("Failed to load firmware!\n"); |
| 1667 | return r; |
| 1668 | } |
| 1669 | } |
| 1670 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1671 | r = r600_vram_scratch_init(rdev); |
| 1672 | if (r) |
| 1673 | return r; |
| 1674 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1675 | if (rdev->flags & RADEON_IS_AGP) { |
| 1676 | rv770_agp_enable(rdev); |
| 1677 | } else { |
| 1678 | r = rv770_pcie_gart_enable(rdev); |
| 1679 | if (r) |
| 1680 | return r; |
| 1681 | } |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1682 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1683 | rv770_gpu_init(rdev); |
Alex Deucher | b70d6bb | 2010-08-06 21:36:58 -0400 | [diff] [blame] | 1684 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1685 | /* allocate wb buffer */ |
| 1686 | r = radeon_wb_init(rdev); |
| 1687 | if (r) |
| 1688 | return r; |
| 1689 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 1690 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 1691 | if (r) { |
| 1692 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| 1693 | return r; |
| 1694 | } |
| 1695 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1696 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
| 1697 | if (r) { |
| 1698 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
| 1699 | return r; |
| 1700 | } |
| 1701 | |
Christian König | e409b12 | 2013-08-13 11:56:53 +0200 | [diff] [blame] | 1702 | r = uvd_v2_2_resume(rdev); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1703 | if (!r) { |
| 1704 | r = radeon_fence_driver_start_ring(rdev, |
| 1705 | R600_RING_TYPE_UVD_INDEX); |
| 1706 | if (r) |
| 1707 | dev_err(rdev->dev, "UVD fences init error (%d).\n", r); |
| 1708 | } |
| 1709 | |
| 1710 | if (r) |
| 1711 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
| 1712 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1713 | /* Enable IRQ */ |
Adis Hamzić | e49f395 | 2013-06-02 16:47:54 +0200 | [diff] [blame] | 1714 | if (!rdev->irq.installed) { |
| 1715 | r = radeon_irq_kms_init(rdev); |
| 1716 | if (r) |
| 1717 | return r; |
| 1718 | } |
| 1719 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1720 | r = r600_irq_init(rdev); |
| 1721 | if (r) { |
| 1722 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| 1723 | radeon_irq_kms_fini(rdev); |
| 1724 | return r; |
| 1725 | } |
| 1726 | r600_irq_set(rdev); |
| 1727 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1728 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1729 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 1730 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
Christian König | 2e1e6da | 2013-08-13 11:56:52 +0200 | [diff] [blame] | 1731 | RADEON_CP_PACKET2); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1732 | if (r) |
| 1733 | return r; |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1734 | |
| 1735 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
| 1736 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
| 1737 | DMA_RB_RPTR, DMA_RB_WPTR, |
Christian König | 2e1e6da | 2013-08-13 11:56:52 +0200 | [diff] [blame] | 1738 | DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1739 | if (r) |
| 1740 | return r; |
| 1741 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1742 | r = rv770_cp_load_microcode(rdev); |
| 1743 | if (r) |
| 1744 | return r; |
| 1745 | r = r600_cp_resume(rdev); |
| 1746 | if (r) |
| 1747 | return r; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1748 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1749 | r = r600_dma_resume(rdev); |
| 1750 | if (r) |
| 1751 | return r; |
| 1752 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1753 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
| 1754 | if (ring->ring_size) { |
Christian König | 02c9f7f | 2013-08-13 11:56:51 +0200 | [diff] [blame] | 1755 | r = radeon_ring_init(rdev, ring, ring->ring_size, 0, |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1756 | UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, |
Christian König | 2e1e6da | 2013-08-13 11:56:52 +0200 | [diff] [blame] | 1757 | RADEON_CP_PACKET2); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1758 | if (!r) |
Christian König | e409b12 | 2013-08-13 11:56:53 +0200 | [diff] [blame] | 1759 | r = uvd_v1_0_init(rdev); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1760 | |
| 1761 | if (r) |
| 1762 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
| 1763 | } |
| 1764 | |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 1765 | r = radeon_ib_pool_init(rdev); |
| 1766 | if (r) { |
| 1767 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 1768 | return r; |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 1769 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 1770 | |
Alex Deucher | d4e30ef | 2012-06-04 17:18:51 -0400 | [diff] [blame] | 1771 | r = r600_audio_init(rdev); |
| 1772 | if (r) { |
| 1773 | DRM_ERROR("radeon: audio init failed\n"); |
| 1774 | return r; |
| 1775 | } |
| 1776 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1777 | return 0; |
| 1778 | } |
| 1779 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1780 | int rv770_resume(struct radeon_device *rdev) |
| 1781 | { |
| 1782 | int r; |
| 1783 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1784 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
| 1785 | * posting will perform necessary task to bring back GPU into good |
| 1786 | * shape. |
| 1787 | */ |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1788 | /* post card */ |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 1789 | atom_asic_init(rdev->mode_info.atom_context); |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1790 | |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 1791 | /* init golden registers */ |
| 1792 | rv770_init_golden_registers(rdev); |
| 1793 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 1794 | rdev->accel_working = true; |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1795 | r = rv770_startup(rdev); |
| 1796 | if (r) { |
| 1797 | DRM_ERROR("r600 startup failed on resume\n"); |
Jerome Glisse | 6b7746e | 2012-02-20 17:57:20 -0500 | [diff] [blame] | 1798 | rdev->accel_working = false; |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1799 | return r; |
| 1800 | } |
| 1801 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1802 | return r; |
| 1803 | |
| 1804 | } |
| 1805 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1806 | int rv770_suspend(struct radeon_device *rdev) |
| 1807 | { |
Rafał Miłecki | 8a8c6e7 | 2010-03-06 13:03:36 +0000 | [diff] [blame] | 1808 | r600_audio_fini(rdev); |
Christian König | e409b12 | 2013-08-13 11:56:53 +0200 | [diff] [blame] | 1809 | uvd_v1_0_fini(rdev); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1810 | radeon_uvd_suspend(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1811 | r700_cp_stop(rdev); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1812 | r600_dma_stop(rdev); |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 1813 | r600_irq_suspend(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1814 | radeon_wb_disable(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1815 | rv770_pcie_gart_disable(rdev); |
Alex Deucher | 6ddddfe | 2011-10-14 10:51:22 -0400 | [diff] [blame] | 1816 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1817 | return 0; |
| 1818 | } |
| 1819 | |
| 1820 | /* Plan is to move initialization in that function and use |
| 1821 | * helper function so that radeon_device_init pretty much |
| 1822 | * do nothing more than calling asic specific function. This |
| 1823 | * should also allow to remove a bunch of callback function |
| 1824 | * like vram_info. |
| 1825 | */ |
| 1826 | int rv770_init(struct radeon_device *rdev) |
| 1827 | { |
| 1828 | int r; |
| 1829 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1830 | /* Read BIOS */ |
| 1831 | if (!radeon_get_bios(rdev)) { |
| 1832 | if (ASIC_IS_AVIVO(rdev)) |
| 1833 | return -EINVAL; |
| 1834 | } |
| 1835 | /* Must be an ATOMBIOS */ |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 1836 | if (!rdev->is_atom_bios) { |
| 1837 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1838 | return -EINVAL; |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 1839 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1840 | r = radeon_atombios_init(rdev); |
| 1841 | if (r) |
| 1842 | return r; |
| 1843 | /* Post card if necessary */ |
Alex Deucher | fd909c3 | 2011-01-11 18:08:59 -0500 | [diff] [blame] | 1844 | if (!radeon_card_posted(rdev)) { |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1845 | if (!rdev->bios) { |
| 1846 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
| 1847 | return -EINVAL; |
| 1848 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1849 | DRM_INFO("GPU not posted. posting now...\n"); |
| 1850 | atom_asic_init(rdev->mode_info.atom_context); |
| 1851 | } |
Alex Deucher | fbb5566 | 2013-02-26 15:59:47 -0500 | [diff] [blame] | 1852 | /* init golden registers */ |
| 1853 | rv770_init_golden_registers(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1854 | /* Initialize scratch registers */ |
| 1855 | r600_scratch_init(rdev); |
| 1856 | /* Initialize surface registers */ |
| 1857 | radeon_surface_init(rdev); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1858 | /* Initialize clocks */ |
Michel Dänzer | 5e6dde7 | 2009-09-17 09:42:28 +0200 | [diff] [blame] | 1859 | radeon_get_clock_info(rdev->ddev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1860 | /* Fence driver */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 1861 | r = radeon_fence_driver_init(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1862 | if (r) |
| 1863 | return r; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1864 | /* initialize AGP */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1865 | if (rdev->flags & RADEON_IS_AGP) { |
| 1866 | r = radeon_agp_init(rdev); |
| 1867 | if (r) |
| 1868 | radeon_agp_disable(rdev); |
| 1869 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1870 | r = rv770_mc_init(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 1871 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1872 | return r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1873 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1874 | r = radeon_bo_init(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1875 | if (r) |
| 1876 | return r; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1877 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1878 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
| 1879 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1880 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1881 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
| 1882 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
| 1883 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1884 | r = radeon_uvd_init(rdev); |
| 1885 | if (!r) { |
| 1886 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; |
| 1887 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], |
| 1888 | 4096); |
| 1889 | } |
| 1890 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1891 | rdev->ih.ring_obj = NULL; |
| 1892 | r600_ih_ring_init(rdev, 64 * 1024); |
| 1893 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1894 | r = r600_pcie_gart_init(rdev); |
| 1895 | if (r) |
| 1896 | return r; |
| 1897 | |
Alex Deucher | 779720a | 2009-12-09 19:31:44 -0500 | [diff] [blame] | 1898 | rdev->accel_working = true; |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 1899 | r = rv770_startup(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1900 | if (r) { |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 1901 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1902 | r700_cp_fini(rdev); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1903 | r600_dma_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 1904 | r600_irq_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1905 | radeon_wb_fini(rdev); |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 1906 | radeon_ib_pool_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 1907 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | 75c8129 | 2009-10-01 18:02:14 +0200 | [diff] [blame] | 1908 | rv770_pcie_gart_fini(rdev); |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1909 | rdev->accel_working = false; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1910 | } |
Rafał Miłecki | 8a8c6e7 | 2010-03-06 13:03:36 +0000 | [diff] [blame] | 1911 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1912 | return 0; |
| 1913 | } |
| 1914 | |
| 1915 | void rv770_fini(struct radeon_device *rdev) |
| 1916 | { |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1917 | r700_cp_fini(rdev); |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1918 | r600_dma_fini(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1919 | r600_irq_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1920 | radeon_wb_fini(rdev); |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 1921 | radeon_ib_pool_fini(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1922 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1923 | rv770_pcie_gart_fini(rdev); |
Christian König | e409b12 | 2013-08-13 11:56:53 +0200 | [diff] [blame] | 1924 | uvd_v1_0_fini(rdev); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1925 | radeon_uvd_fini(rdev); |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1926 | r600_vram_scratch_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1927 | radeon_gem_fini(rdev); |
| 1928 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | d0269ed | 2010-01-07 16:08:32 +0100 | [diff] [blame] | 1929 | radeon_agp_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1930 | radeon_bo_fini(rdev); |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 1931 | radeon_atombios_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1932 | kfree(rdev->bios); |
| 1933 | rdev->bios = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1934 | } |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1935 | |
| 1936 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev) |
| 1937 | { |
| 1938 | u32 link_width_cntl, lanes, speed_cntl, tmp; |
| 1939 | u16 link_cntl2; |
| 1940 | |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 1941 | if (radeon_pcie_gen2 == 0) |
| 1942 | return; |
| 1943 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1944 | if (rdev->flags & RADEON_IS_IGP) |
| 1945 | return; |
| 1946 | |
| 1947 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 1948 | return; |
| 1949 | |
| 1950 | /* x2 cards have a special sequence */ |
| 1951 | if (ASIC_IS_X2(rdev)) |
| 1952 | return; |
| 1953 | |
Kleber Sacilotto de Souza | 7e0e419 | 2013-05-03 19:43:13 -0300 | [diff] [blame] | 1954 | if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && |
| 1955 | (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) |
Dave Airlie | 197bbb3 | 2012-06-27 08:35:54 +0100 | [diff] [blame] | 1956 | return; |
| 1957 | |
| 1958 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
| 1959 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1960 | /* advertise upconfig capability */ |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1961 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1962 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1963 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 1964 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1965 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
| 1966 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
| 1967 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
| 1968 | LC_RECONFIG_ARC_MISSING_ESCAPE); |
| 1969 | link_width_cntl |= lanes | LC_RECONFIG_NOW | |
| 1970 | LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1971 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1972 | } else { |
| 1973 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1974 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1975 | } |
| 1976 | |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1977 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1978 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
| 1979 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
| 1980 | |
| 1981 | tmp = RREG32(0x541c); |
| 1982 | WREG32(0x541c, tmp | 0x8); |
| 1983 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); |
| 1984 | link_cntl2 = RREG16(0x4088); |
| 1985 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; |
| 1986 | link_cntl2 |= 0x2; |
| 1987 | WREG16(0x4088, link_cntl2); |
| 1988 | WREG32(MM_CFGREGS_CNTL, 0); |
| 1989 | |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1990 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1991 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1992 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1993 | |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1994 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1995 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1996 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1997 | |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 1998 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 1999 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 2000 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 2001 | |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 2002 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 2003 | speed_cntl |= LC_GEN2_EN_STRAP; |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 2004 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 2005 | |
| 2006 | } else { |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 2007 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 2008 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
| 2009 | if (1) |
| 2010 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
| 2011 | else |
| 2012 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 2013 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 2014 | } |
| 2015 | } |