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Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001/* bnx2x.h: Broadcom Everest network driver.
2 *
Eilon Greensteind05c26c2009-01-17 23:26:13 -08003 * Copyright (c) 2007-2009 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
Eilon Greenstein24e3fce2008-06-12 14:30:28 -07009 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
Eilon Greenstein34f80b02008-06-23 20:33:01 -070017/* compilation time flags */
18
19/* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21/* #define BNX2X_STOP_ON_ERROR */
22
Eilon Greenstein0c6671b2009-01-14 21:26:51 -080023#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24#define BCM_VLAN 1
25#endif
26
Michael Chan993ac7b2009-10-10 13:46:56 +000027#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
28#define BCM_CNIC 1
29#include "cnic_if.h"
30#endif
Eilon Greenstein0c6671b2009-01-14 21:26:51 -080031
Eilon Greenstein555f6c72009-02-12 08:36:11 +000032#define BNX2X_MULTI_QUEUE
33
34#define BNX2X_NEW_NAPI
35
Eilon Greenstein359d8b12009-02-12 08:38:25 +000036
Eilon Greenstein01cd4522009-08-12 08:23:08 +000037
38#include <linux/mdio.h>
Eilon Greenstein359d8b12009-02-12 08:38:25 +000039#include "bnx2x_reg.h"
40#include "bnx2x_fw_defs.h"
41#include "bnx2x_hsi.h"
42#include "bnx2x_link.h"
43
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020044/* error/debug prints */
45
Eilon Greenstein34f80b02008-06-23 20:33:01 -070046#define DRV_MODULE_NAME "bnx2x"
47#define PFX DRV_MODULE_NAME ": "
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020048
49/* for messages that are currently off */
Eilon Greenstein34f80b02008-06-23 20:33:01 -070050#define BNX2X_MSG_OFF 0
51#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
52#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
53#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
54#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
Eliezer Tamirf1410642008-02-28 11:51:50 -080055#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
56#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020057
Eilon Greenstein34f80b02008-06-23 20:33:01 -070058#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020059
60/* regular debug print */
61#define DP(__mask, __fmt, __args...) do { \
62 if (bp->msglevel & (__mask)) \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070063 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070064 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070065 } while (0)
66
67/* errors debug print */
68#define BNX2X_DBG_ERR(__fmt, __args...) do { \
69 if (bp->msglevel & NETIF_MSG_PROBE) \
70 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070071 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020072 } while (0)
73
74/* for errors (never masked) */
75#define BNX2X_ERR(__fmt, __args...) do { \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070076 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070077 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eliezer Tamirf1410642008-02-28 11:51:50 -080078 } while (0)
79
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020080/* before we have a dev->name use dev_info() */
81#define BNX2X_DEV_INFO(__fmt, __args...) do { \
82 if (bp->msglevel & NETIF_MSG_PROBE) \
83 dev_info(&bp->pdev->dev, __fmt, ##__args); \
84 } while (0)
85
86
87#ifdef BNX2X_STOP_ON_ERROR
88#define bnx2x_panic() do { \
89 bp->panic = 1; \
90 BNX2X_ERR("driver assert\n"); \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070091 bnx2x_int_disable(bp); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020092 bnx2x_panic_dump(bp); \
93 } while (0)
94#else
95#define bnx2x_panic() do { \
Eilon Greensteine3553b22009-08-12 08:23:31 +000096 bp->panic = 1; \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020097 BNX2X_ERR("driver assert\n"); \
98 bnx2x_panic_dump(bp); \
99 } while (0)
100#endif
101
102
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700103#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
104#define U64_HI(x) (u32)(((u64)(x)) >> 32)
105#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200106
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200107
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700108#define REG_ADDR(bp, offset) (bp->regview + offset)
109
110#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
111#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700112
113#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200114#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700115#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200116
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700117#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
118#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200119
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700120#define REG_RD_DMAE(bp, offset, valp, len32) \
121 do { \
122 bnx2x_read_dmae(bp, offset, len32);\
Eilon Greenstein573f2032009-08-12 08:24:14 +0000123 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700124 } while (0)
125
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700126#define REG_WR_DMAE(bp, offset, valp, len32) \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200127 do { \
Eilon Greenstein573f2032009-08-12 08:24:14 +0000128 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200129 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
130 offset, len32); \
131 } while (0)
132
Eilon Greenstein573f2032009-08-12 08:24:14 +0000133#define VIRT_WR_DMAE_LEN(bp, data, addr, len32) \
134 do { \
135 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
136 bnx2x_write_big_buf_wb(bp, addr, len32); \
137 } while (0)
138
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700139#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
140 offsetof(struct shmem_region, field))
141#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
142#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200143
Eilon Greenstein2691d512009-08-12 08:22:08 +0000144#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
145 offsetof(struct shmem2_region, field))
146#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
147#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
148
Eilon Greenstein345b5d52008-08-13 15:58:12 -0700149#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
Eilon Greenstein3196a882008-08-13 15:58:49 -0700150#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200151
152
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700153/* fast path */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200154
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200155struct sw_rx_bd {
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700156 struct sk_buff *skb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200157 DECLARE_PCI_UNMAP_ADDR(mapping)
158};
159
160struct sw_tx_bd {
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700161 struct sk_buff *skb;
162 u16 first_bd;
Eilon Greensteinca003922009-08-12 22:53:28 -0700163 u8 flags;
164/* Set on the first BD descriptor when there is a split BD */
165#define BNX2X_TSO_SPLIT_BD (1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200166};
167
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700168struct sw_rx_page {
169 struct page *page;
170 DECLARE_PCI_UNMAP_ADDR(mapping)
171};
172
Eilon Greensteinca003922009-08-12 22:53:28 -0700173union db_prod {
174 struct doorbell_set_prod data;
175 u32 raw;
176};
177
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700178
179/* MC hsi */
180#define BCM_PAGE_SHIFT 12
181#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
182#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
183#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
184
185#define PAGES_PER_SGE_SHIFT 0
186#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -0800187#define SGE_PAGE_SIZE PAGE_SIZE
188#define SGE_PAGE_SHIFT PAGE_SHIFT
Eilon Greenstein5b6402d2009-07-21 05:47:51 +0000189#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700190
191/* SGE ring related macros */
192#define NUM_RX_SGE_PAGES 2
193#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
194#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
Eilon Greenstein33471622008-08-13 15:59:08 -0700195/* RX_SGE_CNT is promised to be a power of 2 */
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700196#define RX_SGE_MASK (RX_SGE_CNT - 1)
197#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
198#define MAX_RX_SGE (NUM_RX_SGE - 1)
199#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
200 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
201#define RX_SGE(x) ((x) & MAX_RX_SGE)
202
203/* SGE producer mask related macros */
204/* Number of bits in one sge_mask array element */
205#define RX_SGE_MASK_ELEM_SZ 64
206#define RX_SGE_MASK_ELEM_SHIFT 6
207#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
208
209/* Creates a bitmask of all ones in less significant bits.
210 idx - index of the most significant bit in the created mask */
211#define RX_SGE_ONES_MASK(idx) \
212 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
213#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
214
215/* Number of u64 elements in SGE mask array */
216#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
217 RX_SGE_MASK_ELEM_SZ)
218#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
219#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
220
221
Eilon Greensteinde832a52009-02-12 08:36:33 +0000222struct bnx2x_eth_q_stats {
223 u32 total_bytes_received_hi;
224 u32 total_bytes_received_lo;
225 u32 total_bytes_transmitted_hi;
226 u32 total_bytes_transmitted_lo;
227 u32 total_unicast_packets_received_hi;
228 u32 total_unicast_packets_received_lo;
229 u32 total_multicast_packets_received_hi;
230 u32 total_multicast_packets_received_lo;
231 u32 total_broadcast_packets_received_hi;
232 u32 total_broadcast_packets_received_lo;
233 u32 total_unicast_packets_transmitted_hi;
234 u32 total_unicast_packets_transmitted_lo;
235 u32 total_multicast_packets_transmitted_hi;
236 u32 total_multicast_packets_transmitted_lo;
237 u32 total_broadcast_packets_transmitted_hi;
238 u32 total_broadcast_packets_transmitted_lo;
239 u32 valid_bytes_received_hi;
240 u32 valid_bytes_received_lo;
241
242 u32 error_bytes_received_hi;
243 u32 error_bytes_received_lo;
244 u32 etherstatsoverrsizepkts_hi;
245 u32 etherstatsoverrsizepkts_lo;
246 u32 no_buff_discard_hi;
247 u32 no_buff_discard_lo;
248
249 u32 driver_xoff;
250 u32 rx_err_discard_pkt;
251 u32 rx_skb_alloc_failed;
252 u32 hw_csum_err;
253};
254
255#define BNX2X_NUM_Q_STATS 11
256#define Q_STATS_OFFSET32(stat_name) \
257 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
258
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200259struct bnx2x_fastpath {
260
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700261 struct napi_struct napi;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200262
Eilon Greensteinca003922009-08-12 22:53:28 -0700263 u8 is_rx_queue;
264
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200265 struct host_status_block *status_blk;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700266 dma_addr_t status_blk_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200267
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700268 struct sw_tx_bd *tx_buf_ring;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200269
Eilon Greensteinca003922009-08-12 22:53:28 -0700270 union eth_tx_bd_types *tx_desc_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700271 dma_addr_t tx_desc_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200272
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700273 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
274 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200275
276 struct eth_rx_bd *rx_desc_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700277 dma_addr_t rx_desc_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200278
279 union eth_rx_cqe *rx_comp_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700280 dma_addr_t rx_comp_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200281
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700282 /* SGE ring */
283 struct eth_rx_sge *rx_sge_ring;
284 dma_addr_t rx_sge_mapping;
285
286 u64 sge_mask[RX_SGE_MASK_LEN];
287
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700288 int state;
289#define BNX2X_FP_STATE_CLOSED 0
290#define BNX2X_FP_STATE_IRQ 0x80000
291#define BNX2X_FP_STATE_OPENING 0x90000
292#define BNX2X_FP_STATE_OPEN 0xa0000
293#define BNX2X_FP_STATE_HALTING 0xb0000
294#define BNX2X_FP_STATE_HALTED 0xc0000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200295
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700296 u8 index; /* number in fp array */
297 u8 cl_id; /* eth client id */
298 u8 sb_id; /* status block number in HW */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200299
Eilon Greensteinca003922009-08-12 22:53:28 -0700300 union db_prod tx_db;
301
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700302 u16 tx_pkt_prod;
303 u16 tx_pkt_cons;
304 u16 tx_bd_prod;
305 u16 tx_bd_cons;
Eilon Greenstein4781bfa2009-02-12 08:38:17 +0000306 __le16 *tx_cons_sb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200307
Eilon Greenstein4781bfa2009-02-12 08:38:17 +0000308 __le16 fp_c_idx;
309 __le16 fp_u_idx;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200310
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700311 u16 rx_bd_prod;
312 u16 rx_bd_cons;
313 u16 rx_comp_prod;
314 u16 rx_comp_cons;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700315 u16 rx_sge_prod;
316 /* The last maximal completed SGE */
317 u16 last_max_sge;
Eilon Greenstein4781bfa2009-02-12 08:38:17 +0000318 __le16 *rx_cons_sb;
319 __le16 *rx_bd_cons_sb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200320
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +0000321
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700322 unsigned long tx_pkt,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200323 rx_pkt,
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700324 rx_calls;
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +0000325
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700326 /* TPA related */
327 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
328 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
329#define BNX2X_TPA_START 1
330#define BNX2X_TPA_STOP 2
331 u8 disable_tpa;
332#ifdef BNX2X_STOP_ON_ERROR
333 u64 tpa_queue_used;
334#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200335
Eilon Greensteinde832a52009-02-12 08:36:33 +0000336 struct tstorm_per_client_stats old_tclient;
337 struct ustorm_per_client_stats old_uclient;
338 struct xstorm_per_client_stats old_xclient;
339 struct bnx2x_eth_q_stats eth_q_stats;
340
Eilon Greensteinca003922009-08-12 22:53:28 -0700341 /* The size is calculated using the following:
342 sizeof name field from netdev structure +
343 4 ('-Xx-' string) +
344 4 (for the digits and to make it DWORD aligned) */
345#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
346 char name[FP_NAME_SIZE];
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700347 struct bnx2x *bp; /* parent */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200348};
349
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700350#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700351
352
353/* MC hsi */
354#define MAX_FETCH_BD 13 /* HW max BDs per packet */
355#define RX_COPY_THRESH 92
356
357#define NUM_TX_RINGS 16
Eilon Greensteinca003922009-08-12 22:53:28 -0700358#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700359#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
360#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
361#define MAX_TX_BD (NUM_TX_BD - 1)
362#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
363#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
364 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
365#define TX_BD(x) ((x) & MAX_TX_BD)
366#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
367
368/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
369#define NUM_RX_RINGS 8
370#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
371#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
372#define RX_DESC_MASK (RX_DESC_CNT - 1)
373#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
374#define MAX_RX_BD (NUM_RX_BD - 1)
375#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
376#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
377 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
378#define RX_BD(x) ((x) & MAX_RX_BD)
379
380/* As long as CQE is 4 times bigger than BD entry we have to allocate
381 4 times more pages for CQ ring in order to keep it balanced with
382 BD ring */
383#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
384#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
385#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
386#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
387#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
388#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
389#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
390 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
391#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
392
393
Eilon Greenstein33471622008-08-13 15:59:08 -0700394/* This is needed for determining of last_max */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700395#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
396
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700397#define __SGE_MASK_SET_BIT(el, bit) \
398 do { \
399 el = ((el) | ((u64)0x1 << (bit))); \
400 } while (0)
401
402#define __SGE_MASK_CLEAR_BIT(el, bit) \
403 do { \
404 el = ((el) & (~((u64)0x1 << (bit)))); \
405 } while (0)
406
407#define SGE_MASK_SET_BIT(fp, idx) \
408 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
409 ((idx) & RX_SGE_MASK_ELEM_MASK))
410
411#define SGE_MASK_CLEAR_BIT(fp, idx) \
412 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
413 ((idx) & RX_SGE_MASK_ELEM_MASK))
414
415
416/* used on a CID received from the HW */
417#define SW_CID(x) (le32_to_cpu(x) & \
418 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
419#define CQE_CMD(x) (le32_to_cpu(x) >> \
420 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
421
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700422#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
423 le32_to_cpu((bd)->addr_lo))
424#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
425
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700426
427#define DPM_TRIGER_TYPE 0x40
428#define DOORBELL(bp, cid, val) \
429 do { \
Eilon Greensteinca003922009-08-12 22:53:28 -0700430 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700431 DPM_TRIGER_TYPE); \
432 } while (0)
433
434
435/* TX CSUM helpers */
436#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
437 skb->csum_offset)
438#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
439 skb->csum_offset))
440
441#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
442
443#define XMIT_PLAIN 0
444#define XMIT_CSUM_V4 0x1
445#define XMIT_CSUM_V6 0x2
446#define XMIT_CSUM_TCP 0x4
447#define XMIT_GSO_V4 0x8
448#define XMIT_GSO_V6 0x10
449
450#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
451#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
452
453
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700454/* stuff added to make the code fit 80Col */
455
456#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
457
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700458#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
459#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
460#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
461 (TPA_TYPE_START | TPA_TYPE_END))
462
Eilon Greenstein1adcd8b2008-08-13 15:48:29 -0700463#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
464
465#define BNX2X_IP_CSUM_ERR(cqe) \
466 (!((cqe)->fast_path_cqe.status_flags & \
467 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
468 ((cqe)->fast_path_cqe.type_error_flags & \
469 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
470
471#define BNX2X_L4_CSUM_ERR(cqe) \
472 (!((cqe)->fast_path_cqe.status_flags & \
473 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
474 ((cqe)->fast_path_cqe.type_error_flags & \
475 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
476
477#define BNX2X_RX_CSUM_OK(cqe) \
478 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700479
Eilon Greenstein052a38e2009-02-12 08:37:16 +0000480#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
481 (((le16_to_cpu(flags) & \
482 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
483 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
484 == PRS_FLAG_OVERETH_IPV4)
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700485#define BNX2X_RX_SUM_FIX(cqe) \
Eilon Greenstein052a38e2009-02-12 08:37:16 +0000486 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700487
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200488
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700489#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
490#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
491
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700492#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
493#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
494#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200495
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700496#define BNX2X_RX_SB_INDEX \
497 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200498
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700499#define BNX2X_RX_SB_BD_INDEX \
500 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200501
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700502#define BNX2X_RX_SB_INDEX_NUM \
503 (((U_SB_ETH_RX_CQ_INDEX << \
504 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
505 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
506 ((U_SB_ETH_RX_BD_INDEX << \
507 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
508 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200509
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700510#define BNX2X_TX_SB_INDEX \
511 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200512
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700513
514/* end of fast path */
515
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700516/* common */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200517
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700518struct bnx2x_common {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200519
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700520 u32 chip_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200521/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700522#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200523
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700524#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700525#define CHIP_NUM_57710 0x164e
526#define CHIP_NUM_57711 0x164f
527#define CHIP_NUM_57711E 0x1650
528#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
529#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
530#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
531#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
532 CHIP_IS_57711E(bp))
533#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200534
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700535#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700536#define CHIP_REV_Ax 0x00000000
537/* assume maximum 5 revisions */
538#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
539/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
540#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
541 !(CHIP_REV(bp) & 0x00001000))
542/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
543#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
544 (CHIP_REV(bp) & 0x00001000))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200545
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700546#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
547 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
548
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700549#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
550#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200551
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700552 int flash_size;
553#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
554#define NVRAM_TIMEOUT_COUNT 30000
555#define NVRAM_PAGE_SIZE 256
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200556
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700557 u32 shmem_base;
Eilon Greenstein2691d512009-08-12 08:22:08 +0000558 u32 shmem2_base;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700559
560 u32 hw_config;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200561
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700562 u32 bc_ver;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700563};
564
565
566/* end of common */
567
568/* port */
569
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700570struct nig_stats {
571 u32 brb_discard;
572 u32 brb_packet;
573 u32 brb_truncate;
574 u32 flow_ctrl_discard;
575 u32 flow_ctrl_octets;
576 u32 flow_ctrl_packet;
577 u32 mng_discard;
578 u32 mng_octet_inp;
579 u32 mng_octet_out;
580 u32 mng_packet_inp;
581 u32 mng_packet_out;
582 u32 pbf_octets;
583 u32 pbf_packet;
584 u32 safc_inp;
585 u32 egress_mac_pkt0_lo;
586 u32 egress_mac_pkt0_hi;
587 u32 egress_mac_pkt1_lo;
588 u32 egress_mac_pkt1_hi;
589};
590
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700591struct bnx2x_port {
592 u32 pmf;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200593
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700594 u32 link_config;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200595
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700596 u32 supported;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200597/* link settings - missing defines */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700598#define SUPPORTED_2500baseX_Full (1 << 15)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200599
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700600 u32 advertising;
601/* link settings - missing defines */
602#define ADVERTISED_2500baseX_Full (1 << 15)
603
604 u32 phy_addr;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700605
606 /* used to synchronize phy accesses */
607 struct mutex phy_mutex;
Eilon Greenstein46c6a672009-02-12 08:36:58 +0000608 int need_hw_lock;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700609
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700610 u32 port_stx;
611
612 struct nig_stats old_nig_stats;
613};
614
615/* end of port */
616
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700617
618enum bnx2x_stats_event {
619 STATS_EVENT_PMF = 0,
620 STATS_EVENT_LINK_UP,
621 STATS_EVENT_UPDATE,
622 STATS_EVENT_STOP,
623 STATS_EVENT_MAX
624};
625
626enum bnx2x_stats_state {
627 STATS_STATE_DISABLED = 0,
628 STATS_STATE_ENABLED,
629 STATS_STATE_MAX
630};
631
632struct bnx2x_eth_stats {
633 u32 total_bytes_received_hi;
634 u32 total_bytes_received_lo;
635 u32 total_bytes_transmitted_hi;
636 u32 total_bytes_transmitted_lo;
637 u32 total_unicast_packets_received_hi;
638 u32 total_unicast_packets_received_lo;
639 u32 total_multicast_packets_received_hi;
640 u32 total_multicast_packets_received_lo;
641 u32 total_broadcast_packets_received_hi;
642 u32 total_broadcast_packets_received_lo;
643 u32 total_unicast_packets_transmitted_hi;
644 u32 total_unicast_packets_transmitted_lo;
645 u32 total_multicast_packets_transmitted_hi;
646 u32 total_multicast_packets_transmitted_lo;
647 u32 total_broadcast_packets_transmitted_hi;
648 u32 total_broadcast_packets_transmitted_lo;
649 u32 valid_bytes_received_hi;
650 u32 valid_bytes_received_lo;
651
652 u32 error_bytes_received_hi;
653 u32 error_bytes_received_lo;
Eilon Greensteinde832a52009-02-12 08:36:33 +0000654 u32 etherstatsoverrsizepkts_hi;
655 u32 etherstatsoverrsizepkts_lo;
656 u32 no_buff_discard_hi;
657 u32 no_buff_discard_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700658
659 u32 rx_stat_ifhcinbadoctets_hi;
660 u32 rx_stat_ifhcinbadoctets_lo;
661 u32 tx_stat_ifhcoutbadoctets_hi;
662 u32 tx_stat_ifhcoutbadoctets_lo;
663 u32 rx_stat_dot3statsfcserrors_hi;
664 u32 rx_stat_dot3statsfcserrors_lo;
665 u32 rx_stat_dot3statsalignmenterrors_hi;
666 u32 rx_stat_dot3statsalignmenterrors_lo;
667 u32 rx_stat_dot3statscarriersenseerrors_hi;
668 u32 rx_stat_dot3statscarriersenseerrors_lo;
669 u32 rx_stat_falsecarriererrors_hi;
670 u32 rx_stat_falsecarriererrors_lo;
671 u32 rx_stat_etherstatsundersizepkts_hi;
672 u32 rx_stat_etherstatsundersizepkts_lo;
673 u32 rx_stat_dot3statsframestoolong_hi;
674 u32 rx_stat_dot3statsframestoolong_lo;
675 u32 rx_stat_etherstatsfragments_hi;
676 u32 rx_stat_etherstatsfragments_lo;
677 u32 rx_stat_etherstatsjabbers_hi;
678 u32 rx_stat_etherstatsjabbers_lo;
679 u32 rx_stat_maccontrolframesreceived_hi;
680 u32 rx_stat_maccontrolframesreceived_lo;
681 u32 rx_stat_bmac_xpf_hi;
682 u32 rx_stat_bmac_xpf_lo;
683 u32 rx_stat_bmac_xcf_hi;
684 u32 rx_stat_bmac_xcf_lo;
685 u32 rx_stat_xoffstateentered_hi;
686 u32 rx_stat_xoffstateentered_lo;
687 u32 rx_stat_xonpauseframesreceived_hi;
688 u32 rx_stat_xonpauseframesreceived_lo;
689 u32 rx_stat_xoffpauseframesreceived_hi;
690 u32 rx_stat_xoffpauseframesreceived_lo;
691 u32 tx_stat_outxonsent_hi;
692 u32 tx_stat_outxonsent_lo;
693 u32 tx_stat_outxoffsent_hi;
694 u32 tx_stat_outxoffsent_lo;
695 u32 tx_stat_flowcontroldone_hi;
696 u32 tx_stat_flowcontroldone_lo;
697 u32 tx_stat_etherstatscollisions_hi;
698 u32 tx_stat_etherstatscollisions_lo;
699 u32 tx_stat_dot3statssinglecollisionframes_hi;
700 u32 tx_stat_dot3statssinglecollisionframes_lo;
701 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
702 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
703 u32 tx_stat_dot3statsdeferredtransmissions_hi;
704 u32 tx_stat_dot3statsdeferredtransmissions_lo;
705 u32 tx_stat_dot3statsexcessivecollisions_hi;
706 u32 tx_stat_dot3statsexcessivecollisions_lo;
707 u32 tx_stat_dot3statslatecollisions_hi;
708 u32 tx_stat_dot3statslatecollisions_lo;
709 u32 tx_stat_etherstatspkts64octets_hi;
710 u32 tx_stat_etherstatspkts64octets_lo;
711 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
712 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
713 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
714 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
715 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
716 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
717 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
718 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
719 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
720 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
721 u32 tx_stat_etherstatspktsover1522octets_hi;
722 u32 tx_stat_etherstatspktsover1522octets_lo;
723 u32 tx_stat_bmac_2047_hi;
724 u32 tx_stat_bmac_2047_lo;
725 u32 tx_stat_bmac_4095_hi;
726 u32 tx_stat_bmac_4095_lo;
727 u32 tx_stat_bmac_9216_hi;
728 u32 tx_stat_bmac_9216_lo;
729 u32 tx_stat_bmac_16383_hi;
730 u32 tx_stat_bmac_16383_lo;
731 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
732 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
733 u32 tx_stat_bmac_ufl_hi;
734 u32 tx_stat_bmac_ufl_lo;
735
Eilon Greensteinde832a52009-02-12 08:36:33 +0000736 u32 pause_frames_received_hi;
737 u32 pause_frames_received_lo;
738 u32 pause_frames_sent_hi;
739 u32 pause_frames_sent_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700740
741 u32 etherstatspkts1024octetsto1522octets_hi;
742 u32 etherstatspkts1024octetsto1522octets_lo;
743 u32 etherstatspktsover1522octets_hi;
744 u32 etherstatspktsover1522octets_lo;
745
Eilon Greensteinde832a52009-02-12 08:36:33 +0000746 u32 brb_drop_hi;
747 u32 brb_drop_lo;
748 u32 brb_truncate_hi;
749 u32 brb_truncate_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700750
751 u32 mac_filter_discard;
752 u32 xxoverflow_discard;
753 u32 brb_truncate_discard;
754 u32 mac_discard;
755
756 u32 driver_xoff;
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700757 u32 rx_err_discard_pkt;
758 u32 rx_skb_alloc_failed;
759 u32 hw_csum_err;
Eilon Greensteinde832a52009-02-12 08:36:33 +0000760
761 u32 nig_timer_max;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700762};
763
Eilon Greensteinde832a52009-02-12 08:36:33 +0000764#define BNX2X_NUM_STATS 41
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700765#define STATS_OFFSET32(stat_name) \
766 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
767
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700768
Michael Chan37b091b2009-10-10 13:46:55 +0000769#ifdef BCM_CNIC
770#define MAX_CONTEXT 15
771#else
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700772#define MAX_CONTEXT 16
Michael Chan37b091b2009-10-10 13:46:55 +0000773#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700774
775union cdu_context {
776 struct eth_context eth;
777 char pad[1024];
778};
779
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700780#define MAX_DMAE_C 8
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700781
782/* DMA memory not used in fastpath */
783struct bnx2x_slowpath {
784 union cdu_context context[MAX_CONTEXT];
785 struct eth_stats_query fw_stats;
786 struct mac_configuration_cmd mac_config;
787 struct mac_configuration_cmd mcast_config;
788
789 /* used by dmae command executer */
790 struct dmae_command dmae[MAX_DMAE_C];
791
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700792 u32 stats_comp;
793 union mac_stats mac_stats;
794 struct nig_stats nig_stats;
795 struct host_port_stats port_stats;
796 struct host_func_stats func_stats;
Eilon Greenstein6fe49bb2009-08-12 08:23:17 +0000797 struct host_func_stats func_stats_base;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700798
799 u32 wb_comp;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700800 u32 wb_data[4];
801};
802
803#define bnx2x_sp(bp, var) (&bp->slowpath->var)
804#define bnx2x_sp_mapping(bp, var) \
805 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200806
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200807
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700808/* attn group wiring */
809#define MAX_DYNAMIC_ATTN_GRPS 8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200810
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700811struct attn_route {
812 u32 sig[4];
813};
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200814
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700815struct bnx2x {
816 /* Fields used in the tx and intr/napi performance paths
817 * are grouped together in the beginning of the structure
818 */
819 struct bnx2x_fastpath fp[MAX_CONTEXT];
820 void __iomem *regview;
821 void __iomem *doorbells;
Michael Chan37b091b2009-10-10 13:46:55 +0000822#ifdef BCM_CNIC
823#define BNX2X_DB_SIZE (18*BCM_PAGE_SIZE)
824#else
Eilon Greensteina5f67a042009-01-14 21:28:13 -0800825#define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
Michael Chan37b091b2009-10-10 13:46:55 +0000826#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200827
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700828 struct net_device *dev;
829 struct pci_dev *pdev;
830
831 atomic_t intr_sem;
Michael Chan37b091b2009-10-10 13:46:55 +0000832#ifdef BCM_CNIC
833 struct msix_entry msix_table[MAX_CONTEXT+2];
834#else
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700835 struct msix_entry msix_table[MAX_CONTEXT+1];
Michael Chan37b091b2009-10-10 13:46:55 +0000836#endif
Eilon Greenstein8badd272009-02-12 08:36:15 +0000837#define INT_MODE_INTx 1
838#define INT_MODE_MSI 2
839#define INT_MODE_MSIX 3
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700840
841 int tx_ring_size;
842
843#ifdef BCM_VLAN
844 struct vlan_group *vlgrp;
845#endif
846
847 u32 rx_csum;
Eilon Greenstein437cf2f2008-09-03 14:38:00 -0700848 u32 rx_buf_size;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700849#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
850#define ETH_MIN_PACKET_SIZE 60
851#define ETH_MAX_PACKET_SIZE 1500
852#define ETH_MAX_JUMBO_PACKET_SIZE 9600
853
Eilon Greenstein0f008462009-02-12 08:36:18 +0000854 /* Max supported alignment is 256 (8 shift) */
855#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
856 L1_CACHE_SHIFT : 8)
857#define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
858
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700859 struct host_def_status_block *def_status_blk;
860#define DEF_SB_ID 16
Eilon Greenstein4781bfa2009-02-12 08:38:17 +0000861 __le16 def_c_idx;
862 __le16 def_u_idx;
863 __le16 def_x_idx;
864 __le16 def_t_idx;
865 __le16 def_att_idx;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700866 u32 attn_state;
867 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700868
869 /* slow path ring */
870 struct eth_spe *spq;
871 dma_addr_t spq_mapping;
872 u16 spq_prod_idx;
873 struct eth_spe *spq_prod_bd;
874 struct eth_spe *spq_last_bd;
Eilon Greenstein4781bfa2009-02-12 08:38:17 +0000875 __le16 *dsb_sp_prod;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700876 u16 spq_left; /* serialize spq */
877 /* used to synchronize spq accesses */
878 spinlock_t spq_lock;
879
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700880 /* Flags for marking that there is a STAT_QUERY or
881 SET_MAC ramrod pending */
Michael Chane665bfd2009-10-10 13:46:54 +0000882 int stats_pending;
883 int set_mac_pending;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700884
Eilon Greenstein33471622008-08-13 15:59:08 -0700885 /* End of fields used in the performance code paths */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700886
887 int panic;
888 int msglevel;
889
890 u32 flags;
891#define PCIX_FLAG 1
892#define PCI_32BIT_FLAG 2
Eilon Greenstein1c063282009-02-12 08:36:43 +0000893#define ONE_PORT_FLAG 4
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700894#define NO_WOL_FLAG 8
895#define USING_DAC_FLAG 0x10
896#define USING_MSIX_FLAG 0x20
Eilon Greenstein8badd272009-02-12 08:36:15 +0000897#define USING_MSI_FLAG 0x40
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700898#define TPA_ENABLE_FLAG 0x80
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700899#define NO_MCP_FLAG 0x100
900#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
Eilon Greenstein0c6671b2009-01-14 21:26:51 -0800901#define HW_VLAN_TX_FLAG 0x400
902#define HW_VLAN_RX_FLAG 0x800
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700903
904 int func;
905#define BP_PORT(bp) (bp->func % PORT_MAX)
906#define BP_FUNC(bp) (bp->func)
907#define BP_E1HVN(bp) (bp->func >> 1)
908#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700909
Michael Chan37b091b2009-10-10 13:46:55 +0000910#ifdef BCM_CNIC
911#define BCM_CNIC_CID_START 16
912#define BCM_ISCSI_ETH_CL_ID 17
913#endif
914
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700915 int pm_cap;
916 int pcie_cap;
Eilon Greenstein8d5726c2009-02-12 08:37:19 +0000917 int mrrs;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700918
Eilon Greenstein1cf167f2009-01-14 21:22:18 -0800919 struct delayed_work sp_task;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700920 struct work_struct reset_task;
921
922 struct timer_list timer;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700923 int current_interval;
924
925 u16 fw_seq;
926 u16 fw_drv_pulse_wr_seq;
927 u32 func_stx;
928
929 struct link_params link_params;
930 struct link_vars link_vars;
Eilon Greenstein01cd4522009-08-12 08:23:08 +0000931 struct mdio_if_info mdio;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700932
933 struct bnx2x_common common;
934 struct bnx2x_port port;
935
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +0000936 struct cmng_struct_per_port cmng;
937 u32 vn_weight_sum;
938
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700939 u32 mf_config;
940 u16 e1hov;
941 u8 e1hmf;
Eilon Greenstein3196a882008-08-13 15:58:49 -0700942#define IS_E1HMF(bp) (bp->e1hmf != 0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200943
Eliezer Tamirf1410642008-02-28 11:51:50 -0800944 u8 wol;
945
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700946 int rx_ring_size;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200947
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700948 u16 tx_quick_cons_trip_int;
949 u16 tx_quick_cons_trip;
950 u16 tx_ticks_int;
951 u16 tx_ticks;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200952
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700953 u16 rx_quick_cons_trip_int;
954 u16 rx_quick_cons_trip;
955 u16 rx_ticks_int;
956 u16 rx_ticks;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200957
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700958 u32 lin_cnt;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200959
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700960 int state;
Eilon Greenstein356e2382009-02-12 08:38:32 +0000961#define BNX2X_STATE_CLOSED 0
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700962#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
963#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200964#define BNX2X_STATE_OPEN 0x3000
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700965#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200966#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
967#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700968#define BNX2X_STATE_DISABLED 0xd000
969#define BNX2X_STATE_DIAG 0xe000
970#define BNX2X_STATE_ERROR 0xf000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200971
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000972 int multi_mode;
973 int num_rx_queues;
974 int num_tx_queues;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200975
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700976 u32 rx_mode;
977#define BNX2X_RX_MODE_NONE 0
978#define BNX2X_RX_MODE_NORMAL 1
979#define BNX2X_RX_MODE_ALLMULTI 2
980#define BNX2X_RX_MODE_PROMISC 3
981#define BNX2X_MAX_MULTICAST 64
982#define BNX2X_MAX_EMUL_MULTI 16
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200983
Michael Chan37b091b2009-10-10 13:46:55 +0000984 u32 rx_mode_cl_mask;
985
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700986 dma_addr_t def_status_blk_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200987
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700988 struct bnx2x_slowpath *slowpath;
989 dma_addr_t slowpath_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200990
Eilon Greensteina18f5122009-08-12 08:23:26 +0000991 int dropless_fc;
992
Michael Chan37b091b2009-10-10 13:46:55 +0000993#ifdef BCM_CNIC
994 u32 cnic_flags;
995#define BNX2X_CNIC_FLAG_MAC_SET 1
996
997 void *t1;
998 dma_addr_t t1_mapping;
999 void *t2;
1000 dma_addr_t t2_mapping;
1001 void *timers;
1002 dma_addr_t timers_mapping;
1003 void *qm;
1004 dma_addr_t qm_mapping;
1005 struct cnic_ops *cnic_ops;
1006 void *cnic_data;
1007 u32 cnic_tag;
1008 struct cnic_eth_dev cnic_eth_dev;
1009 struct host_status_block *cnic_sb;
1010 dma_addr_t cnic_sb_mapping;
1011#define CNIC_SB_ID(bp) BP_L_ID(bp)
1012 struct eth_spe *cnic_kwq;
1013 struct eth_spe *cnic_kwq_prod;
1014 struct eth_spe *cnic_kwq_cons;
1015 struct eth_spe *cnic_kwq_last;
1016 u16 cnic_kwq_pending;
1017 u16 cnic_spq_pending;
1018 struct mutex cnic_mutex;
1019 u8 iscsi_mac[6];
1020#endif
1021
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001022 int dmae_ready;
1023 /* used to synchronize dmae accesses */
1024 struct mutex dmae_mutex;
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001025
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001026 /* used to synchronize stats collecting */
1027 int stats_state;
1028 /* used by dmae command loader */
1029 struct dmae_command stats_dmae;
1030 int executer_idx;
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001031
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001032 u16 stats_counter;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001033 struct bnx2x_eth_stats eth_stats;
1034
1035 struct z_stream_s *strm;
1036 void *gunzip_buf;
1037 dma_addr_t gunzip_mapping;
1038 int gunzip_outlen;
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001039#define FW_BUF_SIZE 0x8000
Eilon Greenstein573f2032009-08-12 08:24:14 +00001040#define GUNZIP_BUF(bp) (bp->gunzip_buf)
1041#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1042#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001043
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001044 struct raw_op *init_ops;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07001045 /* Init blocks offsets inside init_ops */
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001046 u16 *init_ops_offsets;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07001047 /* Data blob - has 32 bit granularity */
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001048 u32 *init_data;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07001049 /* Zipped PRAM blobs - raw data */
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001050 const u8 *tsem_int_table_data;
1051 const u8 *tsem_pram_data;
1052 const u8 *usem_int_table_data;
1053 const u8 *usem_pram_data;
1054 const u8 *xsem_int_table_data;
1055 const u8 *xsem_pram_data;
1056 const u8 *csem_int_table_data;
1057 const u8 *csem_pram_data;
Eilon Greenstein573f2032009-08-12 08:24:14 +00001058#define INIT_OPS(bp) (bp->init_ops)
1059#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1060#define INIT_DATA(bp) (bp->init_data)
1061#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1062#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1063#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1064#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1065#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1066#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1067#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1068#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1069
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001070 const struct firmware *firmware;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001071};
1072
1073
Eilon Greensteinca003922009-08-12 22:53:28 -07001074#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
1075 : (MAX_CONTEXT/2))
1076#define BNX2X_NUM_QUEUES(bp) (bp->num_rx_queues + bp->num_tx_queues)
1077#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 2)
Eilon Greenstein3196a882008-08-13 15:58:49 -07001078
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001079#define for_each_rx_queue(bp, var) \
1080 for (var = 0; var < bp->num_rx_queues; var++)
1081#define for_each_tx_queue(bp, var) \
Eilon Greensteinca003922009-08-12 22:53:28 -07001082 for (var = bp->num_rx_queues; \
1083 var < BNX2X_NUM_QUEUES(bp); var++)
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001084#define for_each_queue(bp, var) \
1085 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
Eilon Greenstein3196a882008-08-13 15:58:49 -07001086#define for_each_nondefault_queue(bp, var) \
Eilon Greensteinca003922009-08-12 22:53:28 -07001087 for (var = 1; var < bp->num_rx_queues; var++)
Eilon Greenstein3196a882008-08-13 15:58:49 -07001088
1089
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001090void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1091void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1092 u32 len32);
Eilon Greenstein4acac6a2009-02-12 08:36:52 +00001093int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
Eilon Greenstein17de50b2008-08-13 15:56:59 -07001094int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
Eilon Greenstein4acac6a2009-02-12 08:36:52 +00001095int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
Eilon Greenstein4d295db2009-07-21 05:47:47 +00001096u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
Eilon Greenstein573f2032009-08-12 08:24:14 +00001097void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1098void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1099 u32 addr, u32 len);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001100
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001101static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1102 int wait)
1103{
1104 u32 val;
1105
1106 do {
1107 val = REG_RD(bp, reg);
1108 if (val == expected)
1109 break;
1110 ms -= wait;
1111 msleep(wait);
1112
1113 } while (ms > 0);
1114
1115 return val;
1116}
1117
1118
1119/* load/unload mode */
1120#define LOAD_NORMAL 0
1121#define LOAD_OPEN 1
1122#define LOAD_DIAG 2
1123#define UNLOAD_NORMAL 0
1124#define UNLOAD_CLOSE 1
1125
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001126
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001127/* DMAE command defines */
1128#define DMAE_CMD_SRC_PCI 0
1129#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1130
1131#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1132#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1133
1134#define DMAE_CMD_C_DST_PCI 0
1135#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1136
1137#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1138
1139#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1140#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1141#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1142#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1143
1144#define DMAE_CMD_PORT_0 0
1145#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1146
1147#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1148#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1149#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1150
1151#define DMAE_LEN32_RD_MAX 0x80
1152#define DMAE_LEN32_WR_MAX 0x400
1153
1154#define DMAE_COMP_VAL 0xe0d0d0ae
1155
1156#define MAX_DMAE_C_PER_PORT 8
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001157#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001158 BP_E1HVN(bp))
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001159#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001160 E1HVN_MAX)
1161
1162
Eliezer Tamir25047952008-02-28 11:50:16 -08001163/* PCIE link and speed */
1164#define PCICFG_LINK_WIDTH 0x1f00000
1165#define PCICFG_LINK_WIDTH_SHIFT 20
1166#define PCICFG_LINK_SPEED 0xf0000
1167#define PCICFG_LINK_SPEED_SHIFT 16
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001168
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001169
Eilon Greensteind3d4f492009-02-12 08:36:27 +00001170#define BNX2X_NUM_TESTS 7
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001171
Eilon Greensteinb5bf9062009-02-12 08:38:08 +00001172#define BNX2X_PHY_LOOPBACK 0
1173#define BNX2X_MAC_LOOPBACK 1
1174#define BNX2X_PHY_LOOPBACK_FAILED 1
1175#define BNX2X_MAC_LOOPBACK_FAILED 2
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001176#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1177 BNX2X_PHY_LOOPBACK_FAILED)
Eliezer Tamir96fc1782008-02-28 11:57:55 -08001178
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001179
1180#define STROM_ASSERT_ARRAY_SIZE 50
1181
Eliezer Tamir96fc1782008-02-28 11:57:55 -08001182
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001183/* must be used on a CID before placing it on a HW ring */
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001184#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1185 (BP_E1HVN(bp) << 17) | (x))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001186
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001187#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1188#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1189
1190
1191#define BNX2X_BTR 3
1192#define MAX_SPQ_PENDING 8
1193
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001194
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001195/* CMNG constants
1196 derived from lab experiments, and not from system spec calculations !!! */
1197#define DEF_MIN_RATE 100
1198/* resolution of the rate shaping timer - 100 usec */
1199#define RS_PERIODIC_TIMEOUT_USEC 100
1200/* resolution of fairness algorithm in usecs -
Eilon Greenstein33471622008-08-13 15:59:08 -07001201 coefficient for calculating the actual t fair */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001202#define T_FAIR_COEF 10000000
1203/* number of bytes in single QM arbitration cycle -
Eilon Greenstein33471622008-08-13 15:59:08 -07001204 coefficient for calculating the fairness timer */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001205#define QM_ARB_BYTES 40000
1206#define FAIR_MEM 2
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001207
1208
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001209#define ATTN_NIG_FOR_FUNC (1L << 8)
1210#define ATTN_SW_TIMER_4_FUNC (1L << 9)
1211#define GPIO_2_FUNC (1L << 10)
1212#define GPIO_3_FUNC (1L << 11)
1213#define GPIO_4_FUNC (1L << 12)
1214#define ATTN_GENERAL_ATTN_1 (1L << 13)
1215#define ATTN_GENERAL_ATTN_2 (1L << 14)
1216#define ATTN_GENERAL_ATTN_3 (1L << 15)
1217#define ATTN_GENERAL_ATTN_4 (1L << 13)
1218#define ATTN_GENERAL_ATTN_5 (1L << 14)
1219#define ATTN_GENERAL_ATTN_6 (1L << 15)
1220
1221#define ATTN_HARD_WIRED_MASK 0xff00
1222#define ATTENTION_ID 4
1223
1224
1225/* stuff added to make the code fit 80Col */
1226
1227#define BNX2X_PMF_LINK_ASSERT \
1228 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1229
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001230#define BNX2X_MC_ASSERT_BITS \
1231 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1232 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1233 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1234 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1235
1236#define BNX2X_MCP_ASSERT \
1237 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1238
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001239#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1240#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1241 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1242 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1243 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1244 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1245 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1246
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001247#define HW_INTERRUT_ASSERT_SET_0 \
1248 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1249 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1250 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1251 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001252#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001253 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1254 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1255 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1256 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1257#define HW_INTERRUT_ASSERT_SET_1 \
1258 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1259 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1260 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1261 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1262 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1263 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1264 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1265 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1266 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1267 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1268 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001269#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001270 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1271 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1272 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001273 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1274 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001275 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1276 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1277 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1278 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1279 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1280#define HW_INTERRUT_ASSERT_SET_2 \
1281 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1282 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1283 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1284 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1285 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001286#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001287 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1288 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1289 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1290 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1291 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1292 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1293
1294
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001295#define MULTI_FLAGS(bp) \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001296 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1297 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1298 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1299 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001300 (bp->multi_mode << \
1301 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001302#define MULTI_MASK 0x7f
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001303
1304
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001305#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1306#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1307#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1308#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001309
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001310#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001311
1312#define BNX2X_SP_DSB_INDEX \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001313(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001314
1315
1316#define CAM_IS_INVALID(x) \
1317(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1318
1319#define CAM_INVALIDATE(x) \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001320 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001321
1322
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001323/* Number of u32 elements in MC hash array */
1324#define MC_HASH_SIZE 8
1325#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1326 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1327
1328
1329#ifndef PXP2_REG_PXP2_INT_STS
1330#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1331#endif
1332
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001333/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1334
1335#endif /* bnx2x.h */